AD AD9821 Complete 12-bit 40 msps imaging signal processor Datasheet

Complete 12-Bit 40 MSPS
Imaging Signal Processor
AD9821
FEATURES
Differential Sensor Input with 1 V p-p Input Range
0 dB to 36 dB 10-Bit Variable Gain Amplifier (VGA)
Low Noise Optical Black Clamp Circuit
Analog Preblanking Function
12-Bit 40 MSPS A/D Converter (ADC)
3-Wire Serial Digital Interface
3 V Single-Supply Operation
Low Power: 150 mW @ 3 V Supply
48-Lead LQFP Package
GENERAL DESCRIPTION
The AD9821 is a complete analog signal processor for imaging
applications that do not require Correlated Double Sampling
(CDS). It features a 40 MHz single-channel architecture designed
to sample and condition the outputs of CMOS imagers and CCD
arrays already containing on-chip CDS. The AD9821’s signal
chain consists of a differential input sample-and-hold amplifier
(SHA), digitally controlled variable gain amplifier (VGA), black
level clamp, and a 12-bit ADC.
The internal registers are programmed through a 3-wire serial
digital interface. Programmable features include gain adjustment, black level adjustment, and power-down modes.
APPLICATIONS
Digital Still Cameras Using CMOS Imagers
Industrial/Scientific Imaging
The AD9821 operates from a single 3 V power supply, typically
dissipates 150 mW, and is packaged in a 48-lead LQFP.
FUNCTIONAL BLOCK DIAGRAM
AVDD
AVSS
VRT
VRB
PBLK
DRVDD
BAND GAP
REFERENCE
AD9821
DRVSS
0dB ~ 36dB
VIN+
VIN–
+
SHA
–
12-BIT
ADC
VGA
BYP1
12
DOUT
CLP
10
CLPOB
8
INTERNAL
REGISTERS
BLK CLAMP
LEVEL
DVDD
DIGITAL
INTERFACE
SL
SCK
DVSS
SDATA
DATACLK
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2002
AD9821–SPECIFICATIONS
GENERAL SPECIFICATIONS
(TMIN to TMAX, AVDD = DVDD = 3.0 V, fDATACLK = 40 MHz, unless otherwise noted.)
Parameter
Min
TEMPERATURE RANGE
Operating
Storage
POWER SUPPLY VOLTAGE
Analog, Digital, Digital Driver
POWER CONSUMPTION
Normal Operation
Power-Down Modes
Standby
Total Power-Down
Typ
Max
Unit
–20
–65
+85
+150
°C
°C
2.7
3.6
V
(Specified under Each Mode of Operation)
5
1
MAXIMUM CLOCK RATE
mW
mW
40
A/D CONVERTER
Resolution
Differential Nonlinearity (DNL)
No Missing Codes
Full-Scale Input Voltage
Data Output Coding
MHz
12
Bits
LSB
Bits Guaranteed
V
± 0.5
12
2.0
Straight Binary
VOLTAGE REFERENCE
Reference Top Voltage (VRT)
Reference Bottom Voltage (VRB)
2.0
1.0
V
V
Specifications subject to change without notice.
DIGITAL SPECIFICATIONS (DRVDD = 2.7 V, C = 20 pF, unless otherwise noted.)
L
Parameter
Symbol
Min
LOGIC INPUTS
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Capacitance
VIH
VIL
IIH
IIL
CIN
2.1
LOGIC OUTPUTS
High Level Output Voltage, IOH = 2 mA
Low Level Output Voltage, IOL = 2 mA
VOH
VOL
2.2
Typ
Max
0.6
10
10
10
0.5
Unit
V
V
µA
µA
pF
V
V
Specifications subject to change without notice.
–2–
REV. 0
AD9821
IMAGER-MODE SPECIFICATIONS (T
Parameter
MIN
Min
POWER CONSUMPTION
to TMAX, AVDD = DVDD = 3.0 V, fDATACLK = 40 MHz, unless otherwise noted.)
Typ
Max
150
MAXIMUM CLOCK RATE
40
ANALOG INPUTS (VIN+, VIN–)
Input Common-Mode Range*
Max Input Amplitude*
Max Optical Black Pixel Amplitude*
0
1.0
1.8
V
V p-p
mV
1024
Guaranteed
Steps
0
36
dB
dB
256
Steps
0
255
LSB
LSB
–1
34.5
0
35.5
0.3
0.5
40
+1
36.5
dB
dB
%
LSB rms
dB
12 dB Gain Applied
AC Grounded Input, 6 dB Gain Applied
Measured with Step Change on Supply
Normal Clock Signals Applied
1
3
10
ms
ms
ms
*Input Signal Characteristics defined as follows:
+1.8V
INPUT
CM RANGE
Specifications subject to change without notice.
REV. 0
Linear operating range for VIN+, VIN–
Defined as VIN+ minus VIN–
For stable Clamp at max VGA gain
Specifications Include Entire Signal Chain
POWER-UP RECOVERY TIME
Reference Standby Mode
Total Power-Down Mode
Power-Off Condition
VIN+
VIN–
GND
See TPC 1 for Power vs. Sample Rate
Measured at ADC Output
SYSTEM PERFORMANCE
Gain Accuracy
Min Gain
Max Gain
Peak Nonlinearity, 500 mV Input
Total Output Noise
Power Supply Rejection (PSR)
ⴞ30mV MAX
OB PIXEL
mW
See Figure 11 for VGA Gain Curve
BLACK LEVEL CLAMP
Clamp Level Resolution
Clamp Level
Min Clamp Level
Max Clamp Level
1V p-p MAX
INPUT SIGNAL RANGE
Notes
MHz
± 30
VARIABLE GAIN AMPLIFIER (VGA)
Gain Control Resolution
Gain Monotonicity
Gain Range
Min Gain (VGA Gain Code 00)
Max Gain (VGA Gain Code 1023)
Unit
–3–
AD9821
TIMING SPECIFICATIONS (C = 20 pF, f
L
SAMP
= 40 MHz, Imager-Mode Timing in Figures 5 and 6, Serial Timing in Figures 7–9)
Parameter
Symbol
Min
Typ
SAMPLE CLOCKS
DATACLK Clock Period
DATACLK Hi/Low Pulsewidth
CLPOB Pulsewidth*
Internal Clock Delay
tCONV
tADC
tCOB
tID
25
11
2
25
12.5
20
3.0
DATA OUTPUTS
Output Delay
Output Hold Time
Pipeline Delay
SERIAL INTERFACE
Maximum SCK Frequency
SL to SCK Setup Time
SCK to SL Hold Time
SDATA Valid to SCK Rising Edge Setup
SCK Falling Edge to SDATA Valid Hold
SCK Falling Edge to SDATA Valid Read
tOD
tH
7.0
fSCLK
tLS
tLH
tDS
tDH
tDV
10
10
10
10
10
10
13
7.6
9
Max
Unit
ns
ns
Pixels
ns
16
ns
ns
Cycles
MHz
ns
ns
ns
ns
ns
*Minimum CLPOB pulsewidth is for functional operation only. Wider typical pulses are recommended to achieve low noise clamp performance.
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS
Parameter
AVDD1, AVDD2
DVDD1, DVDD2
DRVDD
Digital Outputs
DATACLK
CLPOB, PBLK
SCK, SL, SDATA
VRT, VRB
BYP1, VIN
Junction Temperature
Lead Temperature
(10 sec)
ORDERING GUIDE
With
Respect
To
Min
Max
Unit
AVSS
DVSS
DRVSS
DRVSS
DVSS
DVSS
DVSS
AVSS
AVSS
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
+3.9
+3.9
+3.9
DRVDD + 0.3
DVDD + 0.3
DVDD + 0.3
DVDD + 0.3
AVDD + 0.3
AVDD + 0.3
150
300
V
V
V
V
V
V
V
V
V
°C
°C
Model
Temperature
Range
Package
Description
Package
Option
AD9821KST
–20°C to +85°C
Thin Plastic
Quad Flatpack
(LQFP)
ST-48
THERMAL CHARACTERISTICS
Thermal Resistance
48-Lead LQFP Package
θJA = 56°C/W
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD9821 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.
–4–
REV. 0
AD9821
NC
VRT
VRB
DVDD2
DVSS
NC
STBY
SL
SDATA
SCK
NC
NC
PIN CONFIGURATION
48 47 46 45 44 43 42 41 40 39 38 37
(LSB) D0 1
36
TEST
35
AVSS
D2 3
34
TEST
4
33
AVDD2
D4 5
32
BYP1
31
VIN–
PIN 1
IDENTIFIER
D1 2
D3
AD9821
D5 6
TOP VIEW
(Not to Scale)
D6 7
30
VIN+
29
TEST
D8 9
28
TEST
D9 10
27
AVDD1
D10 11
26
AVSS
(MSB) D11 12
25
AVSS
D7 8
NC
TEST
TEST
TEST
CLPOB
PBLK
NC
DVDD1
DATACLK
DVSS
DRVSS
DRVDD
NC = NO CONNECT
13 14 15 16 17 18 19 20 21 22 23 24
PIN FUNCTION DESCRIPTIONS
Pin Number
Mnemonic
Type
Description
1–12
13
14
15, 41
16
17
18, 24, 37, 42, 47, 48
19
20
21–23
25, 26, 35
27
28, 29
30
31
32
33
34, 36
38
39
40
43
44
45
46
D0–D11
DRVDD
DRVSS
DVSS
DATACLK
DVDD1
NC
PBLK
CLPOB
TEST
AVSS
AVDD1
TEST
VIN+
VIN–
BYP1
AVDD2
TEST
VRT
VRB
DVDD2
STBY
SL
SDATA
SCK
DO
P
P
P
DI
P
NC
DI
DI
DI
P
P
AO
AI
AI
AO
P
AI
AO
AO
P
DI
DI
DI
DI
Digital Data Outputs
Digital Output Driver Supply
Digital Output Driver Ground
Digital Ground
Digital Data Output Latch Clock
Digital Supply
Internally Not Connected. May be Tied High or Low.
Preblanking Clock Input
Black Level Clamp Clock Input
Test Use Only. Tie to VDD or VSS.
Analog Ground
Analog Supply
Test Use Only. Tie to VDD or VSS.
Positive Analog Input for Imager Signal
Negative Analog Input for Imager Signal
Internal Bias Level Decoupling
Analog Supply
Test Use Only. Tie to VDD or VSS.
ADC Top Reference Voltage Decoupling
ADC Bottom Reference Voltage Decoupling
Digital Supply
Standby Mode, Active High. Same as Total Power-Down Mode.
Serial Digital Interface Load Pulse
Serial Digital Interface Data
Serial Digital Interface Clock
TYPE: AI = Analog Input, AO = Analog Output, DI = Digital Input, DO = Digital Output, P = Power.
REV. 0
–5–
AD9821
DEFINITIONS OF SPECIFICATIONS
Total Output Noise
Differential Nonlinearity (DNL)
The rms output noise is measured using histogram techniques.
The standard deviation of the ADC output codes is calculated
in LSB and represents the rms noise level of the total signal
chain at the specified gain setting. The output noise can be
converted to an equivalent voltage using the relationship 1 LSB =
(ADC Full Scale/2N codes) when N is the bit resolution of the ADC.
For the AD9821, 1 LSB is 500 µV.
An ideal ADC exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. Thus, every
code must have a finite width. No missing codes guaranteed to
12-bit resolution indicates that all 4096 codes, respectively,
must be present over all operating conditions.
Peak Nonlinearity
Power Supply Rejection (PSR)
Peak nonlinearity, a full signal chain specification, refers to the
peak deviation of the output of the AD9821 from a true straight
line. The point used as “zero scale” occurs 1/2 LSB before the
first code transition. “Positive full scale” is defined as a Level 1,
1/2 LSB beyond the last code transition. The deviation is measured from the middle of each particular output code to the true
straight line. The error is then expressed as a percentage of the
2 V ADC full-scale signal. The input signal is always appropriately
gained up to fill the ADC’s full-scale range.
The PSR is measured with a step change applied to the supply
pins. This represents a very high frequency disturbance on the
AD9821’s power supply. The PSR specification is calculated
from the change in the data outputs for a given step change in
the supply voltage.
Internal Delay for SHA
The internal delay (also called aperture delay) is the time delay
that occurs from when the sampling edge is applied to the AD9821
until the actual sample of the input signal is held. The DATACLK
samples the input signal during the transition from low to high,
so the internal delay is measured from each clock’s rising edge
to the instant the actual internal sample is taken.
EQUIVALENT INPUT CIRCUITS
DVDD
AVDD
330⍀
60⍀
ACVSS
DVSS
Figure 1. Digital Inputs— DATACLK, CLPOB, PBLK, SCK, SL
DVDD
ACVSS
Figure 3. VIN+ and VIN– (Pins 30 and 31)
DRVDD
DATA
DVDD
DVDD
DATA IN
THREESTATE
DOUT
330⍀
DATA OUT
RNW
DVSS
DVSS
DRVSS
DVSS
Figure 2. Data Outputs—D0–D11
DVSS
Figure 4. SDATA (Pin 47)
–6–
REV. 0
Typical Performance Characteristics–AD9821
160
15.0
13.5
12.0
OUTPUT NOISE – LSB
POWER DISSIPATION – mW
150
140
VDD = 3.0V
130
120
10.5
9.0
7.5
6.0
4.5
3.0
110
1.5
100
20
30
SAMPLE RATE – MHz
0
40
0.5
0
–0.5
–1.0
1000
1500
2000
2500
3000
35000
4000
TPC 2. Typical DNL Performance
REV. 0
511
767
TPC 3. Output Noise vs. VGA Gain
1.0
500
255
VGA GAIN CODE – LSB
TPC 1. Power vs. Sample Rate
0
0
–7–
1023
AD9821
IMAGER MODE AND AUX MODE TIMING
N+9
N
N+1
N+8
N+2
VIN+
tID
VIN–
tCONV
DATACLK
tOD
OUTPUT
DATA
tH
N–10
N–9
N–8
N–1
N
NOTES:
1. VIN+ AND VIN– SIGNALS ARE SAMPLED AT DATACLK RISING EDGES (CAN BE INVERTED USING THE CONTROL REGISTER).
2. INTERNAL SAMPLING DELAY (APERTURE) tID IS TYPICALLY 3 ns.
3. OUTPUT DATA LATENCY IS NINE DATACLK CYCLES.
Figure 5. Imager Mode Timing
EFFECTIVE PIXELS
OPTICAL BLACK PIXELS
HORIZONTAL
BLANKING
EFFECTIVE PIXELS
IMAGER
SIGNAL
CLPOB
PBLK
OUTPUT
DATA
EFFECTIVE PIXEL DATA
OB PIXEL DATA
EFFECTIVE DATA
NOTES:
1. CLPOB WILL OVERWRITE PBLK. PBLK WILL NOT AFFECT CLAMP OPERATION IF OVERLAPPING CLPOB.
2. PBLK SIGNAL IS OPTIONAL.
3. DIGITAL OUTPUT DATA WILL BE ALL ZEROS DURING PBLK. OUTPUT DATA LATENCY IS NINE DATACLK CYCLES.
Figure 6. Typical Imager Mode Line Clamp Timing
–8–
REV. 0
AD9821
INTERNAL REGISTER MAP AND SERIAL INTERFACE TIMING
Table I. Internal Register Map
Register
Name
Address
A0 A1 A2
D0 D1 D2
Operation
000
Input Mode
Selection
VGA Gain
100
LSB
Clamp Level
010
LSB
Control
110
0
Data Bits
D4
D5
D3
Power-Down
Modes
D6
D7
Software OB Clamp
Reset
On/Off
0
1
D8
D9
2
1
1
0
1
0
1
0
1
0
1
Clock Polarity Select for
CLP/DATA
0
01
01
MSB
X
X
X
X
1
1
X
0
MSB
1
1
D10
0
0
NOTES
1
Internal use only. Must be set to 0.
2
Must be set to 1.
RNW
TEST BIT
0
SDATA
A0
tDS
A1
A2
0
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
tDH
SCK
tLS
tLH
SL
NOTES:
1. SDATA BITS ARE INTERNALLY LATCHED ON THE RISING EDGES OF SCK.
2. RNW = READ-NOT WRITE. SET LOW FOR WRITE OPERATION.
3. TEST BITS = INTERNAL USE ONLY. MUST BE SET LOW.
4. SYSTEM UPDATE OF LOADED REGISTERS OCCURS ON SL RISING EDGE.
Figure 7. Serial Write Operation
RNW
TEST BIT
1
SDATA
A0
tDS
A1
0
0
D0
tDH
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
tDV
SCK
tLS
tLH
SL
NOTES:
1. RNW = READ-NOT WRITE. SET HIGH FOR READ OPERATION.
2. TEST BITS = INTERNAL USE ONLY. MUST BE SET LOW.
3. SERIAL DATA FROM THE SELECTED REGISTER IS VALID STARTING AFTER THE FIFTH SCK FALLING EDGE, AND IS UPDATED ON
SCK FALLING EDGES.
Figure 8. Serial Readback Operation
RNW A0 A1
SDATA
0
0
0
11 BITS
OPERATION
A2
0
0
D0
D1
D2
D3
...
D10 D0
D1
D2
D3
1
2
3
4
5
6
7
8
9
...
D9
D0
D1
D2
D3
...
...
SCK
8 BITS
CLAMP LEVEL
10 BITS
VGA GAIN
16
17
18
19
20
...
10 BITS
CONTROL
D7
D0
D1
D2
D3
27
28
29
30
D9
...
...
26
...
34
35
36
37
38
44
SL
...
NOTES:
1. ANY NUMBER OF ADJACENT REGISTERS MAY BE LOADED SEQUENTIALLY, BEGINNING WITH THE LOWEST ADDRESS AND INCREMENTING ONE ADDRESS AT A TIME.
2. WHEN SEQUENTIALLY LOADING MULTIPLE REGISTERS, THE EXACT REGISTER LENGTH (SHOWN ABOVE) MUST BE USED FOR EACH REGISTER.
3. ALL LOADED REGISTERS WILL BE SIMULTANEOUSLY UPDATED WITH THE RISING EDGE OF SL.
Figure 9. Continuous Serial Write Operation to All Registers
REV. 0
–9–
AD9821
REGISTER DETAILS
Table II. Operation Register Contents (Default Value x000)
D10 D9
D8
D7
D6
01
01
12
01
01
Optical Black Clamp
D5
Reset
D4
Power-Down Modes
D3 D2
Channel Selection
D1 D0
0 Enable Clamping
1 Disable Clamping
0 Normal
1 Reset All Registers
to Default
0
0
1
1
0
0
1
1
0
1
0
1
Normal Power
Test Only
Ref-Standby
Total Power-Down
0
1
0
1
Test Only
Test Only
Test Only
Imager Mode
NOTES
1
Must be set to 0.
2
Set to 1.
Table III. VGA Gain Register Contents (Default Value x000)
D10
MSB
D9
D8
D7
D6
D5
D4
D3
D2
D1
LSB
D0
X
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
•
•
•
1
1
1
1
1
1
1
1
1
1
0
1
Gain (dB)
0.0
•
•
•
35.965
36.0
Table IV. Clamp Level Register Contents (Default Value x080)
D10
D9
D8
X
X
X
MSB
D7
D6
D5
D4
D3
D2
D1
LSB
D0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
1
1
1
0
0
1
2
•
•
•
254
1
1
1
1
255
1
1
1
0
0
0
•
•
•
1
1
1
1
1
Clamp Level (LSB)
Table V. Control Register Contents (Default Value x000)
D10
D9
D8
D7
X
0*
0*
0*
DATACLK Polarity
D6
CLPOB/PBLK Polarity
D5
0 Sample on Rising Edge
1 Sample on Falling Edge
0 Active Low
1 Active High
D4
D3
D2
D1
D0
0*
0*
0*
0*
0*
*Must be set to 0.
–10–
REV. 0
AD9821
CIRCUIT DESCRIPTION AND OPERATION
negative clipping will occur. A small amount of offset between
the VIN+ and VIN– signals is allowable and can be corrected by
the Optical Black Clamp, up to ± 30 mV.
The AD9821 signal processing chain is shown in Figure 10.
Each processing step is essential in achieving a high quality
image from the raw imager pixel data.
Note that the VIN+ and VIN– inputs do not contain any dc
restoration or bias circuitry. Therefore, dc-coupling is recommended when driving the AD9821 analog inputs. If ac-coupling is
used, external biasing circuitry must be provided for the VIN+
and VIN– inputs to keep them in the acceptable common-mode
voltage range of 0 V to 1.8 V.
Differential Input SHA
The differential input SHA circuit is designed to accommodate
a variety of different image sensor output voltages. The timing
shown in Figure 8 illustrates how the DATACLK signal is used to
sample both the VIN+ and VIN– signals simultaneously. The
imager signal is sampled on the rising edges of DATACLK.
Placement of this clock signal is critical in achieving the best
performance from the imager. An internal DATACLK delay (tID)
of 3 ns is caused by internal propagation delays.
Table VI. Example Input Voltage Configurations
VIN+ Range (V) VIN– Range (V) SHA Output Range (V)
Black White
Black White
Black White
The differential input can be used in a variety of single-ended
and differential configurations, as shown in Table VI. The
allowable voltage range for both VIN+ or VIN– is from 0 V
to 1.8 V. Signal levels outside this range will result in severely
degraded performance. Regardless of the input configuration,
the voltage sampled by the SHA is always equal to VIN+ minus
VIN–. VIN+ must always be equal to or greater than VIN– or
0
0.5
1.0
0.5
1.0
1.0
1.5
1.5
1.0
1.0
0
0.5
1.0
0.5
1.0
0
0.5
0.5
0
0
0
0
0
0
0
1.0
1.0
1.0
1.0
1.0
1.0␮F 1.0␮F
DATACLK
REFB
REFT
1.0V
2.0V
INTERNAL
VREF
PBLK
0dB TO 36dB
VIN+
SHA
BYP1
0.1␮F
0.45V
10
12
12-BIT
ADC
VGA
VIN–
8-BIT
DAC
INTERNAL
BIAS
DOUT
CLPOB
OPTICAL BLACK
CLAMP
DIGITAL
FILTERING
VGA GAIN
REGISTER
8
CLAMP LEVEL
REGISTER
Figure 10. Internal Block Diagram
REV. 0
–11–
AD9821
Variable Gain Amplifier
The VGA stage provides a gain range of 0 dB to 36 dB, programmable with 10-bit resolution through the serial digital interface. A
minimum gain of 6 dB is needed to match a 1 V input signal with
the ADC full-scale range of 2 V. When compared to 1 V full-scale
systems, the equivalent gain range is –6 dB to +30 dB.
The VGA gain curve follows a “linear-in-dB” characteristic.
The exact VGA gain can be calculated for any Gain Register
value by using the equation:
Gain ( dB ) = (0.0351 × Code)
where the code range is 0 to 1023.
Horizontal timing is shown in Figure 9. The CLPOB pulse
should be placed during the CCD’s optical black pixels. It is
recommended that the CLPOB pulse duration be at least 20
pixels wide. Shorter pulsewidths may be used, but the ability to
track low frequency variations in the black level will be reduced.
36
VGA GAIN – dB
30
24
18
12
6
0
0
127
255
383
511
639
767
VGA GAIN REGISTER CODE
programmed using the 8-bit Clamp Level Register. The resulting
error signal is filtered to reduce noise, and the correction value is
applied to the ADC input through a D/A converter. Normally, the
optical black clamp loop is turned on once per horizontal line, but
this loop can be updated more slowly to suit a particular
application. If external digital clamping is used during the postprocessing, the AD9821 optical black clamping may be disabled
using Bit D5 in the Operation Register (see Internal Register
Map and Serial Interface Timing section). When the loop is
disabled, the Clamp Level Register may still be used to provide
programmable offset adjustment.
895
1023
Figure 11. VGA Gain Curve
Optical Black Clamp
The optical black clamp loop is used to remove residual offsets
in the signal chain, and to track low frequency variations in the
CCD’s black level. During the optical black (shielded) pixel
interval on each line, the ADC output is compared with a fixed
black level reference selected by the user in the Clamp Level
Register. Any value between 0 LSB and 255 LSB may be
As discussed in the Differential Input SHA section, the CLPOB
loop is capable of correcting for an offset difference between the
VIN+ and VIN– inputs. Because the clamp is located after the
VGA gain stage, the clamp will be most limited when the VGA
gain is at its maximum value. Under these conditions, the OB
clamp loop correction range is restricted to ± 30 mV offset
between the VIN+ and VIN– inputs. At minimum VGA gain,
the offset correction range increases to ± 250 mV of offset. If the
OB clamp loop’s correction range is exceeded, then the black
level at the output of the AD9821 will increase and further
correction will be necessary. As mentioned previously, it is also
possible to disable the AD9821’s OB clamp loop.
A/D Converter (ADC)
The AD9821 uses high performance ADC architecture, optimized for high speed and low power. Differential nonlinearity
(DNL) performance is typically better than 0.5 LSB, as shown in
TPC 2. Instead of the 1 V full-scale range used by the earlier
AD9801 and AD9803 products from Analog Devices, the
AD9821’s ADC uses a 2 V input range. Better noise performance
results from using a larger ADC full-scale range (see TPC 3).
–12–
REV. 0
AD9821
AD9821’s digital output data is then processed by the image
processing ASIC. The internal registers of the AD9821—used
to control gain, offset level, and other functions—are
programmed by the ASIC or microprocessor through a 3-wire
serial digital interface. A system timing generator provides the
clock signals for both the imager and the AFE.
APPLICATIONS INFORMATION
The AD9821 is a complete Analog Front End (AFE) product
for a variety of imager applications using CMOS image sensors
and CCDs with on-chip CDS. As shown in Figure 10, the imager
output is generally buffered and sent to the AD9821’s analog
inputs, either as a differential or single-ended signal. The AD9821
performs the sample-and-hold operation, gain adjustment,
black level correction, and analog-to-digital conversion. The
CMOS
OR
CCD
IMAGER
AD9821
OUT+
VIN+
ADCOUT
OUT–
VIN–
REGISTERDATA
BUFFER
OR
LEVEL SHIFT
DIGITAL
OUTPUTS
DIGITAL IMAGE
PROCESSING
ASIC
SERIAL
INTERFACE
(MAY ALSO
INCLUDE TG)
DATACLK/CLAMP
TIMING
V-DRIVE
(CCD)
IMAGER
TIMING
TIMING
GENERATOR
Figure 12. System Applications Diagram
3V
ANALOG SUPPLY
0.1␮F
1.0␮F
3
NC
VRT
DVDD2
VRB
DVSS
NC
SL
STBY
SDATA
NC
1.0␮F
NC
SCK
SERIAL
INTERFACE
48 47 46 45 44 43 42 41 40 39 38 37
D0 1
D1 2
36
PIN 1
IDENTIFIER
D2 3
D3
35
34
4
D4
33
5
D8
D9
D10
(MSB) D11
8
30
29
9
28
10
27
11
26
12
25
12
AVSS
0.1␮F
TEST
AVDD2
0.1␮F
3V
ANALOG SUPPLY
BYP1
VIN-
IMAGER INPUT, NEGATIVE/REFERENCE
VIN+
IMAGER INPUT, POSITIVE
TEST
TEST
AVDD1
AVSS
AVSS
0.1␮F
3V
ANALOG SUPPLY
NC
TEST
TEST
TEST
PBLK
CLPOB
NC
DVDD1
DVSS
DATACLK
3V
DRIVER
SUPPLY
DRVSS
13 14 15 16 17 18 19 20 21 22 23 24
DRVDD
DATA
OUTPUTS
31
TOP VIEW
(Not to Scale)
7
D7
32
AD9821
D5
6
D6
TEST
NC = INTERNALLY NOT CONNECTED
0.1␮F
3
CLOCK
INPUTS
0.1␮F
3V
ANALOG SUPPLY
Figure 13. Recommended Circuit Configuration
REV. 0
–13–
AD9821
Internal Power-On Reset Circuitry
After power-on, the AD9821 will automatically reset all internal
registers and perform internal calibration procedures. This takes
approximately 1 ms to complete. During this time, normal clock
signals and serial write operations may occur. However, serial
register writes will be ignored until the internal reset operation
is completed.
Grounding and Decoupling Recommendations
As shown in Figure 13, a single ground plane is recommended
for the AD9821. This ground plane should be as continuous as
possible, particularly around Pins 25 through 39. This will ensure
that all analog decoupling capacitors provide the lowest possible
impedance path between the power and bypass pins and their
respective ground pins. All decoupling capacitors should be
located as close as possible to the package pins. A single clean
power supply is recommended for the AD9821, but a separate
digital driver supply may be used for DRVDD (Pin 13). DRVDD
should always be decoupled to DRVSS (Pin 14), which should
be connected to the analog ground plane. Advantages of using a
separate digital driver supply include using a lower voltage (2.7 V)
to match levels with a 2.7 V ASIC, reducing digital power
dissipation, and reducing potential noise coupling. If the
digital outputs (Pins 1–12) must drive a load larger than 20 pF,
buffering is recommended to reduce digital code transition noise.
Alternatively, placing series resistors close to the digital output
pins may also help reduce noise.
–14–
REV. 0
AD9821
OUTLINE DIMENSIONS
48-Lead Plastic Quad Flatpack [LQFP]
1.4 mm Thick
(ST-48)
Dimensions shown in millimeters
1.60 MAX
0.75
0.60
0.45
PIN 1
INDICATOR
9.00 BSC
37
48
36
1
1.45
1.40
1.35
0.15
0.05
0.20
0.09
SEATING
PLANE
SEATING
PLANE
7ⴗ
3.5ⴗ
0ⴗ
0.08 MAX
COPLANARITY
VIEW A
25
12
13
0.50
BSC
VIEW A
ROTATED 90ⴗ CCW
COMPLIANT TO JEDEC STANDARDS MS-026BBC
REV. 0
7.00
BSC
TOP VIEW
(PINS DOWN)
–15–
24
0.27
0.22
0.17
–16–
PRINTED IN U.S.A.
C03223–0–11/02(0)