M82510 ASYNCHRONOUS SERIAL CONTROLLER Military Y Y Y Asynchronous Operation Ð 5- to 9-Bit Character Format Ð Baud Rate DC to 288k Ð Complete Error Detection Y MCSÉ-51 9-Bit Protocol Support Y Control Character Recognition Y CHMOS III with Power Down Mode Multiple Sampling Windows Y Interrupts Maskable at Two Levels Two, Independent, Four-Byte Transmit and Receive FIFOs Ð Programmable Threshold Y Auto Echo and Loopback Modes Y Seven I/O Pins, Dedicated and General Purpose Y Available in 28-Lead CERDIP and 28-Pad LCC Packages Y Military Temperature Range: b 55§ C to a 125§ C (TC) Y Two, 16-bit Baud Rate Generators/ Timers Y System Clock Options Ð On-Chip Crystal Oscillator Ð External Clocks The Intel CHMOS M82510 is designed to increase system efficiency in asynchronous environments such as modems, serial portsÐincluding expanding performance areas: MCSÉ-51 9-bit format and high speed async. The functional support provided in the M82510 is unparalleledÐ2 baud rate generators/timers provide independent data rates or protocol timeouts; a crystal oscillator and smart modem I/O simplify system logic. New features, dual FIFOs and Control Character Recognition (CCR), dramatically reduce CPU interrupts and increase software efficiency. The M82510’s software versatility allows emulation of the INS 8250A/16450 for IBM PC AT* compatibility or a high performance mode, configured by 35 control registers. All interrupts are maskable at 2 levels. The multi-personality I/O pins are configurable as desired. A DPLL and multiple sampling of serial data improve data reliability for high speed asynchronous communication. The compact 28-pin M82510 is fabricated in CHMOS III technology and includes a software powerdown option. *IBM and PC AT are registered trademarks of IBM Corporation. 271072 – 1 Figure 1. Block Diagram *Other brands and names are the property of their respective owners. Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products. Intel retains the right to make changes to these specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata. COPYRIGHT © INTEL CORPORATION, 1996 March 1996 Order Number: 271072-007 M82510 28-Pin Cerdip 28-Pad LCC 271072 – 2 271072 – 55 Figure 2. Package Pinouts M82510 PINOUT DEFINITION Pin No. Type RESET 17 I RESET: A high on this input pin resets the M82510 to the Default Wake-up mode. CS 18 I CHIP SELECT: A low on this input pin enables the M82510 and allows read or write operations. A2–A0 2422 I ADDRESS PINS: These inputs interface with three bits of the System Address Bus to select one of the internal registers for read or write. D7–D0 4* 25 I/O RD 20 I READ: A low on this input pin allows the CPU to read Data or Status bytes from the M82510. WR 19 I WRITE: A low on this input allows the CPU to write Data or Control bytes to the M82510. INT 5 O INTERRUPT: A high on this output pin signals an interrupt request to the CPU. The CPU may determine the particular source and cause of the interrupt by reading the M82510 Status registers. CLK/X1 9 I MULTIFUNCTION: This input pin serves as a source for the internal system clock. The clock may be asynchronous to the serial clocks and to the processor clock. This pin may be used in one of two modes: CLK Ð in this mode an externally generated TTL compatible clock should be used to drive this input pin; X1 Ð in this mode the clock is internally generated by an on-chip crystal oscillator. This mode requires a crystal to be connected between this pin (X1) and the X2 pin. (See System Clock Generation.) OUT2/X2 8 O MULTIFUNCTION: This is a dual function pin which may be configured to one of the following functions: OUT2 Ð a general purpose output pin controlled by the CPU, only available when CLK/X1 pin is driven by an externally generated clock; X2 - this pin serves as an output pin for the crystal oscillator. Note : The configuration of the pin is done only during hardware reset. For more details refer to the System Clock Generation. Symbol *Pins 28 – 25 and Pins 4–1. 2 Name and Description DATA BUS: Bidirectional, three state, eight-bit Data Bus. These pins allow transfer of bytes between the CPU and the M82510. M82510 M82510 PINOUT DEFINITION (Continued) Pin No. Type TXD 6 O TRANSMIT DATA: Serial data is transmitted via this output pin starting at the Least Significant bit. RXD 13 I RECEIVE DATA: Serial data is received on this input pin starting at the Least Significant bit. RI/SCLK 10 I MULTIFUNCTION: This is a dual function pin which can be configured to one of the following functions. RI - Ring Indicator - Input, active low. This is a general purpose input pin accessible by the CPU. SCLK - This input pin may serve as a source for the internal serial clock(s), RxClk and/or TxClk. See Figure 12, BRG sources and outputs. DTR/TB 15 O MULTIFUNCTION: This is a dual function pin which may be configured to one of the following functions. DTR - Data Terminal Ready. Output, active low. This is a general purpose output pin controlled by the CPU. TB - This pin outputs the BRGB output signal when configured as either a clock generator or as a timer. When BRGB is configured as a timer this pin outputs a ‘‘timer expired pulse.’’ When BRGB is configured as a clock generator it outputs the BRGB output clock. DSR/TA/ OUT0 11 I/O MULTIFUNCTION: This is a multifunction pin which may be configured to one of the following functions. DSR - Data Set Ready. Input, active low. This is a general purpose input pin accessible by the CPU. TA - This pin is similar in function to pin TB except it outputs the signals from BRGA instead of BRGB. OUT0 - Output pin. This is a general purpose output pin controlled by the CPU. RTS 16 O REQUEST TO SEND: Output pin, active low. This is a general purpose output pin controlled by the CPU. In addition, in automatic transmission mode this pin, along with CTS, controls the transmission of data. (See Transmit modes for further detail.) During hardware reset this pin is an input. It is used to determine the System Clock Mode. (See System Clock Generation for further detail.) CTS 14 I CLEAR TO SEND: Input pin, active low. In automatic transmission mode it directly controls the Transmit Machine. (See transmission mode for further details.) This pin can be used as a General Purpose Input. DCD/ICLK/ OUT1 12 I/O VSS 7 P Ground VCC 21 P Power: a 5V Supply Symbol Name and Description MULTIFUNCTION: This is a multifunction pin which may be configured to one of the following functions. DCD - Data Carrier Detected. Input pin, active low. This is a general purpose input pin accessible by the CPU. ICLK - This pin is the output of the internal system clock. OUT1 - General purpose output pin. Controlled by the CPU. Table 1. Multifunction Pins Pin Ý I/O Timing Modem 8 *OUT2 X2 Ð 9 Ð *CLK/X1 Ð 10 Ð SCLK *RI 11 OUT0 TA *DSR 12 OUT1 ICLK *DCD 14 Ð Ð *CTS 15 Ð TB *DTR 16 Ð Ð *RTS *Default 3 M82510 GENERAL DESCRIPTION The M82510 can be functionally divided into seven major blocks (See Fig 1): Bus Interface Unit, Timing Unit, Modem Module, Tx FIFO, Rx FIFO, Tx Machine, and Rx Machine. Six of these blocks (all except Bus Interface Unit) can generate block interrupts. Three of these blocks can generate secondlevel interrupts which reflect errors/status within the block (Receive Machine, Timing Unit, and the Modem Module). Its register set can be used in 8250A/16450 compatibility or High Performance modes. The 8250A/ 16450 mode is the default wake-up mode in which only the 8250A/16450 compatible registers are accessible. The remaining registers are default configured to support 8250A/16450 emulation. Software Interface The Bus interface unit allows the M82510 to interface with the rest of the system. It controls access to device registers as well as generation of interrupts to the external world. The FIFOs buffer the CPU from the Serial Machines and reduce the interrupt overhead normally required for serial operations. The threshold (level of occupancy in the FIFO which will generate an interrupt) is programmable for each FIFO. The timing unit controls generation of the system clock through either its on-chip crystal oscillator, or an externally generated clock. It also provides two Baud Rate Generators/Timers with various options and modes to support serial communication. FUNCTIONAL DESCRIPTION 271072 – 3 Figure 3. M82510 Register Architecture CPU Interface The M82510 has a simple demultiplexed Bus Interface, which consists of a bidirectional three-state eight-bit, data bus and a three-bit address bus. An Interrupt pin along with the Read, Write and Chip Select are the remaining signals used to interface with the CPU. The three address lines along with the Bank Pointer register are used to select the registers. The M82510 is designed to interface to all Intel microprocessor and microcontroller families. Like most other I/O based peripherals it is programmed through its registers to support a variety of functions. The M82510 is configured and controlled through its 35 registers which are divided into four banks. Only one bank is accessible at any one time. The bank switching is done by changing the contents of the bank pointer (GIR/BANK – BANK0, BANK1). The banks are logically grouped into 8250A/16450 compatible (0), General Work Bank (1), General Configuration (2), and Modem Configuration (3). The 8250A/16450 compatible bank (Bank 0) is the default bank upon power up. The M82510 registers can be categorized under the following: Table 2. M82510 Register/Block Functions 4 Status Enable Configuration Command Data FIFO MODEM RX TX TIMER FLR MSR RST, RXF LSR TMST Ð MIE RIE LSR TMIE Ð MCR RCM TCM TMCR DEVICE 8250 GSR, GIR LSR, MSR, GIR GER GER FMD PMD RMD TMD CLCF, BACF, BBCF IMD LCR, MCR Ð Ð RXD, RXF TXD, TXF BBL, BBH BAL, BAH Ð TXD, RXD BAL, BAH ICM MCR M82510 8250 Compatibility Upon power up or reset, the M82510 comes up in the default wake up mode. The 8250A/16450 compatible bank, bank zero, is the accessible bank and all the other registers are configured via their default values to support this mode. Table 3. 8250A/16450 Compatible Registers M82510 Registers (Bank 0) Address Read 8250A Registers Write Read Write 00 (DLAB e 0) RxD TxD RBR THR 01 (DLAB e 0) GER GER IER IER 00 (DLAB e 1) BAL BAL DLL DLL 01 (DLAB e 1) BAH BAH DLM DLM 02 GIR/BANK BANK IIR Ð 03 LCR LCR LCR LCR 04 MCR MCR MCR MCR 05 LSR LSR LSR LSR 06 MSR MSR MSR MSR 07 ACR0 ACR0 SCR SCR Table 4. Default Wake-Up Mode RxD Ð ACR1 00H RxF TxD Ð RIE 1EH TxF BAL 02H RMD 00H TMST BAH 00H CLCF 00H TMCR GER 00H BACF 04H FLR Ð Ð 30H Ð 00H GIR/BANK 01H BBCF 84H RCM Ð LCR 00H PMD FCH TCM Ð MCR 00H MIE 0FH GSR 12H LSR 60H TMIE 00H ICM Ð MSR 00H BBL 05H FMD 00H ACR0 00H BBH 00H RST 00H TMD 00H IMD 0CH 5 M82510 271072 – 4 Figure 4. Interrupt Structure Interrupts There are two levels of interrupt/status reporting within the M82510. The first level is the block level interrupts such as RX FIFO, Tx FIFO, Rx Machine, Tx Machine, Timing unit, and Modem Module. The status of these blocks is reported in the General Status and General Interrupt Registers. The second level is the various sources within each block; only three of the blocks generate second level interrupts (Rx Machine, Timing Unit, and Modem Module). Interrupt requests are maskable at both the block level and at the individual source level within the module. If more than one unmasked block requests interrupt service an on-chip interrupt controller will resolve contention on a priority basis (each block has a fixed priority). An interrupt request from a particular block is activated if one of the unmasked status bits within the status register for the block is set. A CPU service operation, e.g., reading the appropriate status register, will reset the status bits. ACKNOWLEDGE MODES The interrupt logic will assert the INT pin when an interrupt is coded into the General Interrupt register. The INT pin is forced low upon acknowledgment. The M82510 has two modes of interrupt acknowledgment: 1. Manual Acknowledge 6 The CPU must issue an explicit Interrupt Acknowledge command via the Interrupt Acknowledge bit of the Internal Command register. As a result the INT pin is forced low for two clocks and then updated. 2. Automatic Acknowledge As opposed to the Manual Acknowledge mode, when the CPU must issue an explicit interrupt acknowledge command, an interrupt service operation is considered as an automatic acknowledgment. This forces the INT pin low for two clock cycles. After two cycles the INT pin is updated, i.e., if there is still an active non-masked interrupt request the INT pin is set HIGH. INTERRUPT SERVICE A service operation is an operation performed by the CPU, which causes the source of the M82510 interrupt to be reset (it will reset the particular status bit causing the interrupt). An interrupt request within the M82510 will not reset until the interrupt source has been serviced. Each source can be serviced in two or three different ways; one general way is to disable the particular status bit causing the interrupt, via the corresponding block enable register. Setting the appropriate bit of the enable register to zero will mask off the corresponding bit in the status register, thus causing an edge on the input line to the interrupt logic. The same effect can be achieved by masking M82510 off the particular block interrupt request in GSR via the General Enable Register. Another method, which is applicable to all sources, is to issue the Status Clear command from the Internal Command Register. The detailed service requirements for each source are given below: The M82510 has an on-chip oscillator to generate its system clock. The oscillator will take the inputs from a crystal attached to the X1 and X2 pins. This mode is configured via a hardware strapping option on RTS. Table 5. Service Procedures Interrupt Status Bits Interrupt Source & Registers Masking Timers Specific Service TMST (1–0) TMIE (1–0) Read TMST GSR (5) GER (5) Tx GSR (4) Machine LSR (6) GER (4) Write Character to tX FIFO Rx LSR (4–1) Machine RST (7–1) GSR (2) RIE (7–1) GER (2) Read RST or LSR Write 0 to bit in RST/LSR Rx FIFO RST/LSR (0) GER (0) GSR (0) Write 0 to LSR/RST Bit zero. Read Character Tx FIFO LSR (5) GSR (1) GER (1) Write to FIFO Read GIR(1) Modem MIE (3-0) GER (3) Read MSR write 0 into the appropriate bits of MSR (3– 0). MSR (3-0) GSR (3) 271072 – 6 Figure 6. Strapping Option During hardware reset the RTS pin is an input; it is weakly pulled high from within and then checked. If it is driven low externally then the M82510 is configured for the Crystal Oscillator; otherwise an external clock is expected. EXTERNALLY GENERATED SYSTEM CLOCK 271072 – 7 NOTE: 1. Only if pending interrupt is Tx FIFO. Figure 7. External Clock System Clock Generation The M82510 has two modes of System Clock Operation. It can accept an externally generated clock, or it can use a crystal to internally generate its system clock. This is the default configuration. Under normal conditions the system clock is divided by two; however, the user may disable divide by two via a hardware strapping option on the DTR pin. The Hardware strapping option is similar to the one used on the RTS pin. It is forbidden to strap both DTR and RTS. Transmit CRYSTAL OSCILLATOR Parallel Resonant Crystal The two major blocks involved in transmission are the Transmit FIFO and the Transmit Machine. The Tx FIFO acts as a buffer between the CPU and the Tx Machine. Whenever a data character is written to the Transmit Data register, it, along with the Transmit Flags (if applicable), is loaded into the Tx FIFO. 271072 – 5 Figure 5. Crystal Oscillator 7 M82510 TX FIFO TRANSMIT CLOCKS There are two modes of transmission clocking, 1X and 16X. In the 1X mode the transmitted data is synchronous to the transmit clock as supplied by the SCLK pin. In this mode stop-bit length is restricted to one or two bits only. In the 16X mode the data is not required to be synchronous to the clock. (Note: The Tx clock can be generated by the BRGs or from the SCLK pin.) MODEM HANDSHAKING The transmitter has three modes of handshaking. 271072 – 8 Figure 8. Tx FIFO The Tx FIFO can hold up to four, eleven-bit characters (nine-bits data, parity, and address flag). It has separate read and write mechanisms. The read and write pointers are incremented after every operation to allow data transfer to occur in a First In First Out fashion. The Tx FIFO will generate a maskable interrupt when the level in the FIFO is below, or equal to, the Threshold. The threshold is user programmable. For example, if the threshold equals two, and the number of characters in the Tx FIFO decreases from three to two, the FIFO will generate an interrupt. The threshold should be selected with regard to the system’s interrupt service latency. NOTE: There is a one character transmission delay between FIFO empty and Transmitter Idle, so a threshold of zero may be selected without getting an underrun condition. Also if more than four characters are written to the FIFO an overrun will occur and the extra character will not be written to the Tx FIFO. This error will not be reported to the CPU. TX MACHINE The Tx Machine reads characters from the Tx FIFO, serializes the bits, and transmits them over the TXD pin according to the timing signals provided for transmission. It will also generate parity, transmit break (upon CPU request), and manage the modem handshaking signals (CTS and RTS) if configured so. The Tx machine can be enabled or disabled through the Transmit Command register or CTS. If the transmitter is disabled in the middle of a character transmission the transmission will continue until the end of the character; only then will it enter the disable state. 8 Manual ModeÐIn this mode the CTS and RTS pins are not used by the Tx Machine (transmission is started regardless of the CTS state, and RTS is not forced low). The CPU may manage the handshake itself, by accessing the CTS and RTS signals through the MODEM CONTROL and MODEM STATUS registers. Semi-Automatic ModeÐIn this mode the RTS pin is activated whenever the transmitter is enabled. The CTS pin’s state controls transmission. Transmission is enabled only if CTS is active. If CTS becomes inactive during transmission, the Tx Machine will complete transmission of the current character and then go to the inactive state until CTS becomes active again. Automatic ModeÐThis mode is similar to the semiautomatic mode, except that RTS will be activated as long as the transmitter is enabled and there are more characters to transmit. The CPU need only fill the FIFO, the handshake is done by the Tx Machine. When both the shift register and the FIFO are empty RTS automatically goes inactive. (Note: The RTS pin can be forced to the active state by the CPU, regardless of the handshaking mode, via the MODEM CONTROL register.) Receive The M82510 reception mechanism involves two major blocks; the Rx Machine and the Rx FIFO. The Rx Machine will assemble the incoming character and its associated flags and then LOAD them on to the Rx FIFO. The top of the FIFO may be read by reading the Receive Data register and the Receive Flags Register. The receive operation can be done in two modes. In the normal mode the characters are received in the standard Asynchronous format and only control characters are recognized. In the ulan mode, the nine bit protocol of the MCS-51 family is supported and the ulan Address characters, rather than Control Characters are recognized. M82510 Manual ModeÐIn this mode the Rx Machine does not control the FIFO automatically; however, the user may UNLOCK/LOCK the FIFO by using the RECEIVE COMMAND register. RX FIFO RX MACHINE 271072 – 9 Figure 9. Rx FIFO The Rx FIFO is very similar in structure and basic operation to the Tx FIFO. It will generate a maskable interrupt when the FIFO level is above, the threshold. The Rx FIFO can also be configured to operate as a one-byte buffer. This mode is used for 8250 compatible software drivers. An overrun will occur when the FIFO is full and the Rx Machine has a new character for the FIFO. In this situation the oldest character is discarded and the new character is loaded from the Rx Machine. An Overrun error bit will also be set in the RECEIVE STATUS and LINE STATUS registers. The user has the option to disable the loading of incoming characters on to the Rx FIFO by using the UNLOCK/LOCK FIFO commands. (See RECEIVE COMMAND register.) When the Rx FIFO is locked, it will ignore load requests from the Rx Machine, and thus the received characters will not be loaded into the FIFO and may be lost (if another character is received). These two commands are useful when the CPU is not willing to receive characters, or is waiting for specific Control/Address characters. In uLAN mode there are three options of address recognition, each of these options varies in the amount of CPU offload, and degree of FIFO control through OPEN/LOCK FIFO commands. Automatic ModeÐIn this mode the Rx Machine will open the FIFO whenever an Address Match occurs; it will LOCK the FIFO if an address mismatch occurs. Semi-Automatic ModeÐIn this mode the Rx Machine will open the FIFO whenever an address character is received. It will not lock the FIFO if the Address does not match. The user is responsible for locking the Rx FIFO. The RX Machine has two modes of clocking the incoming dataÐ16X or 1X. In 16X synchronization is done internally; in the 1X mode the data must be synchronous to the SCLK pin input. The Rx Machine synchronizes the data, passes it through a digital filter to filter out the spikes, and then uses the voting counter to generate the data bit (multiple sampling of input RXD). Bit polarity decisions are made on the basis of majority voting; i.e., if the majority of the samples are ‘‘1’’ the result is a ‘‘1’’ bit. If all samples are not in agreement then the bit is also reported as a noisy bit in the RECEIVE FLAGS register. The sampling window is programmable for either 3/16 or 7/16 samples. The 3/16 mode is useful for high frequency transmissions, or when serious RC delays are expected on the channel. The 7/16 is best suited for noisy media. The Rx machine also has a DPLL to overcome frequency shift problems; however, using it in a very noisy environment may increase the error, so the user can disable the DPLL via the Receive Mode register. The Rx Machine will generate the parity and the address marker as well as any framing error indications. Start Bit DetectionÐThe falling edge of the Start bit resets the DPLL counter and the Rx Machine starts sampling the input line (the number of samples is determined by the configuration of the sampling window mode). The Start bit verification can be done through either a majority voting system or an absolute voting system. The absolute voting requires that all the samples be in agreement. If one of the samples does not agree then a false Start bit is determined and the Rx Machine returns to the Start Bit search Mode. Once a Start bit is detected the Rx Machine will use the majority voting sampling window to receive the data bits. Break DetectionÐIf the input is low for the entire character frame including the stop Bit, then the Rx Machine will set Break Detected as well as Framing Error in the RECEIVE STATUS and LINE STATUS registers. It will push a NULL character onto the Rx FIFO with a framing-error and Break flag (As part of the Receive Flags). The Rx Machine then enters the Idle state. When it sees a mark it will set Break Terminated in RECEIVE STATUS and LINE STATUS registers and resume normal operation. 9 M82510 271072 – 10 Figure 10. Sampling Windows Control CharactersÐThe Rx machine can generate a maskable interrupt upon reception of standard ASCII or EBCDIC control characters, or an Address marker is received in the uLAN mode. The Rx machine can also generate a maskable interrupt upon a match with programmed characters in the Address/ Control Character 0 or Address/Control Character 1 registers. optionally output to external devices via the TA, TB pins (see Figure 11. BRG Sources and Outputs). SOFTWARE CONTROLLED GATE SYS CLK XTAL CLK SCLK SOURCE OUT Rx CLK Tx CLK BRGB SOURCE OUT Rx CLK Tx CLK -A- Table 6. Control Character Recognition SOFTWARE CONTROLLED CONTROL CHARACTER RECOGNITION AÓ STANDARD SET X ASCII: 000X XXXX a 0111 1111 (ASCII DEL) (00 - 1FH a 7 FH) OR X BÓ EBCDIC: 00XX XXXX (00 - 3FH) User Programmed X ACR0, ACR1 XXXX XXXX REGISTERS Baud-Rate Generators/Timers The M82510 has two-on-chip, 16-bit baud-rate generators. Each BRG can also be configured as a Timer, and is completely independent of the other. This can be used when the Transmit and Receive baud rates are different. The mode, the output, and the source of each BRG is configurable, and can also be 10 SCLK SYS CLK XTAL CLK BRGA OUTPUT GATE SOURCE -B- Figure 11. BRG Sources and Outputs BAUD RATE GENERATION The Baud Rate is generated by dividing the source clock with the divisor count (from the Divisor count registers). The count is loaded from the divisor count registers into a count down register. A 50% duty cycle is generated by counting down in steps of two. When the count is down to 2 the entire count is reloaded and the output clock is toggled. Optionally the two BRGs may be cascaded to provide a larger divisor. f0 e fin./Divisor where f in is the input clock frequency and Divisor is the count loaded into the appropriate count registers. M82510 Table 7. Standard Baud Rates 16x Divisor % Error 110 5236 (1474h) .007% 300 1,920 (780h) Ð 1200 480 (1E0h) Ð 2400 240 (F0h) Ð 9600 60 (3Ch) Ð 19,200 30 (1Eh) Ð 38,400 15 (0Fh) Ð 56,000 10 (0Ah) 2.8% 288,000 2 (02h) Bit Rate Ð Source CLK e Internal Sys. Clk e 18.432 MHz/2 e 9.216 MHz The BRG counts down in increments of two and then is divided by two to generate a 50% duty cycle; however, for odd divisors it will count down the first time by one. All subsequent countdowns will then continue in steps of two. In those cases the duty cycle is no longer exactly 50%. The deviation is given by the following equation: deviation e 1/(2 X divisor) The BRG can operate with any divisor between 1 and 65,535; however, for divisors between 1 and 3 the duty cycle is as follows: To start counting, the Timer has to be triggered via the Start Timer Command. To restart the Timer after terminal count or while counting, the software has to issue the trigger command again. While counting the Timer can be enabled or disabled by using a software controlled Gate. It is also possible to output a pulse generated upon terminal count through the TA or TB pins. In 1X clock mode the only clock source available is the SCLK pin. The serial machines (both Tx Machine and Rx Machine) can independently use one of two clock modes, either 1X or 16X. Also no configuration changes are allowed during operation as each write in the BRG configuration registers causes a reset signal to be sent to the BRG logic. The mode or source clocks may be changed only after a Hardware or Software reset. The Divisor (or count, depending upon the mode) may be updated during operation unless the particular BRG machine is being used as a clock source for one of the serial machines, and the particular serial machine is in operation at the time. Loading the count registers with ‘‘0’’ is forbidden in all cases, and loading it with a ‘‘1’’ is forbidden in the Timer Mode only. SERIAL DIAGNOSTICS The M82510 supports two modes of Loopback operation, Local Loopback and Remote Loopback as well as an Echo mode for diagnostics and improved throughput. LOCAL LOOPBACK Table 8. Duty Cycles Divisor Duty Cycle 3 33% 2 50% 1 Same as Source 0 FORBIDDEN Timer Mode Each of the M82510 BRGs can be used as Timers. The Timer is used to generate time delays by counting the internal system clock. When enabled the Timer uses the count from the Divisor/Count registers to count down to 1. Upon terminal count a maskable Timer Expired interrupt is generated. The delay between the trigger and the terminal count is given by the following equation: 271072 – 11 Figure 12. Local Loopback The Tx Machine output and Rx Machine input are shorted internally, TXD pin output is held at Mark. This feature allows simulation of Transmission/Reception of characters and checks the Tx FIFO, Tx Machine, Rx Machine, and Rx FIFO along with the software without any external side effects. The modem outputs OUT1, OUT2, DTR and RTS are internally shorted to RI, DCD, DSR and CTS respectively. OUT0 is held at a mark state. Delay e Count X (System Clock Period) 11 M82510 The M82510 powers down when the power down command is issued via the Internal Command Register (ICM). There are two modes of power down, Sleep and Idle. REMOTE LOOPBACK 271072 – 12 Figure 13. Remote Loopback The TXD pin and RXD pin are shorted internally (the data is not sent on to the RX Machine). This feature allows the user to check the communications channel as well as the Tx and Rx pin circuits not checked in the Local Loopback mode. AUTO ECHO 271072 – 13 Figure 14. Auto Echo In Echo Mode the received characters are automatically transmitted back. When the characters are read from the Rx FIFO they are automatically pushed back onto the Tx FIFO (the flags are also included). The Rx Machine baud rate must be equal to, or less than, the Tx Machine baud rate or some of the characters may be lost. The user has an option of preventing echo of special characters; Control Characters and characters with Errors. Power Down Mode The M82510 has a ‘‘power down’’ mode to reduce power consumption when the device is not in use. 12 In Sleep mode, even the system clock of the M82510 is shut down. The system clock source of the M82510 can either be the Crystal Oscillator or an external clock source. If the Crystal Oscillator is being used and the power down command is issued, then the M82510 will automatically enter the Sleep mode. If an external clock is being used, then the user must disable the external clock in addition to issuing the Power Down command, to enter the Sleep mode. The benefit of this mode is the increased savings in power consumption (typical power consumption in the Sleep mode is in the ranges of 100s of microAmps). However, upon wake up, the user must reprogram the device. To exit this mode the user can either issue a Hardware reset, or read the FIFO Level Register (FLR) and then issue a software reset. In either case the contents of the M82510 registers are not preserved and the device must be reprogrammed prior to operation. If the Crystal Oscillator is being used then the user must allow enough time for the oscillator to wake up before issuing the software reset. The M82510 is in the idle mode when the Power Down command is issued and the system clock is still running (i. e. the system clock is generated externally and not disabled by the user). In this mode the contents of all registers and memory cells are preserved, however, the power consumption in this mode is greater than in the Sleep mode. Reading FLR will take the M82510 out of this mode. NOTE: The data read from FLR when exiting Power Down is invalid and should be ignored. M82510 DETAILED REGISTER DESCRIPTION Table 9. Register Map Bank Read Register Address 0 (NAS) 8250A/16450 0 (DLAB 1 (DLAB 0 (DLAB 1 (DLAB 2 3 4 5 6 7 RXD GER BAL BAH GIR/BANK LCR MCR LSR MSR ACR0 TXD GER BAL BAH BANK LCR MCR LSR MSR ACR0 1 (WORK) 0 1 2 3 4 5 6 7 RXD RXF GIR/BANK TMST FLR RST MSR GSR TXD TXF BANK TMCR MCR RCM TCM ICM 2 (GENERAL CONF) 0 1 2 3 4 5 6 7 Ð FMD GIR/BANK TMD IMD ACR1 RIE RMD Ð FMD BANK TMD IMD ACR1 RIE RMD 3 (MODEM CONF) 0 (DLAB 1 (DLAB 0 (DLAB 1 (DLAB 2 3 4 5 6 7 CLCF BACF BBL BBH GIR/BANK BBCF PMD MIE TMIE Ð CLCF BACF BBL BBH BANK BBCF PMD MIE TMIE Ð e e e e e e e e 0) 0) 1) 1) Write Register 0) 0) 1) 1) (1) ACRO is used in INS8250 as a Scratch-Pad Register (2) DLAB e LCR Bit Ý7 The M82510 has thirty-five registers which are divided into four banks of register banks. Only one bank is accessible at any one time. The bank is selected through the BANK1-0 bits in the GIR/BANK register. The individual registers within a bank are selected by the three address lines (A2 – 0). The M82510 registers can be grouped into the following categories. 13 M82510 BANK ZERO 8250A/16450ÐCOMPATIBLE BANK Register 7 6 5 4 3 2 1 0 Address Default TxD (33) Tx Data bit 7 Tx Data Tx Data bit 6 bit 5 Tx Data bit 4 Tx Data bit 3 Tx Data bit 2 Tx Data bit 1 Tx Data bit 0 0 Ð RxD (35) Rx Data bit 7 Rx Data Rx Data bit 6 bit 5 Rx Data bit 4 Rx Data bit 3 Rx Data bit 2 Rx Data bit 1 Rx Data bit 0 0 Ð BAL (11) BRGA LSB Divide Count (DLAB e 1) 0 02H BAH (12) BRGA MSB Divide Count (DLAB e 1) 1 00H GER (16) 0 GIR/BANK (21) 0 LCR (2) 0 Tx Machine Modem Interrupt Interrupt Enable Enable BANK BANK Pointer Pointer bit 1 bit 0 DLAB Set Divisor Break Latch Access bit MCR (32) 0 0 LSR (22) 0 TxM Idle MSR (27) Timer Interrupt Enable Parity Mode bit 2 0 Parity Mode bit 1 Rx Machine Interrupt Enable Tx FIFO Interrupt Enable Rx FIFO Interrupt Enable 1 00H Active Block Int bit 2 Active Block Int bit 1 Active Block Int bit 0 Interrupt Pending 2 01H Parity Mode bit 0 Stop bit Length bit 0 Character Length bit 1 Character Length bit 0 3 00H OUT 0 Loopback OUT 2 OUT 1 Complement Control bit Complement Complement RTS DTR Complement Complement 4 00H Tx FIFO Interrupt Overrun Error Rx FIFO Int Req 5 60H State (H x L) State Change Change in RI in DSR State Change in CTS 6 00H 7 00H DCD Input RI Input DSR Input Inverted Inverted Inverted ACR0 (5) Break Detected Framing Error CTS Input State Inverted Change in DCD Parity Error Address or Control Character Zero BANK ONEÐGENERAL WORK BANK Register 7 6 5 4 3 2 1 0 Address Default TxD (33) Tx Data bit 7 Tx Data Tx Data bit 6 bit 5 Tx Data bit 4 Tx Data bit 3 Tx Data bit 2 Tx Data bit 1 Tx Data bit 0 0 Ð RxD (35) Rx Data bit 7 Rx Data Rx Data bit 6 bit 5 Rx Data bit 4 Rx Data bit 3 Rx Data bit 2 Rx Data bit 1 Rx Data bit 0 0 Ð Rx Char Rx Char OK Noisy Rx Char Parity Error Address or Control Character Break Flag Rx Char Framing Error Ninth Data bit of Rx Char 1 Ð 1 Ð RxF (24) TxF (34) Ð Address Software Ninth bit Marker bit Parity bit of Data Char BANK Pointer bit 1 BANK Pointer bit 0 0 0 0 Active Block Int bit 2 0 Active Block Int bit 1 0 0 GIR/BANK (21) 0 Active Block Int bit 0 Interrupt Pending 2 01H TMST (26) Ð Ð Gate B State Gate A State Ð Ð Timer B Expired Timer A Expired 3 30H TMCR (31) 0 0 Trigger Gate B Trigger Gate A 0 0 Start Timer B Start Timer A 3 Ð MCR (32) 0 0 OUT 0 Loopback OUT 2 OUT 1 RTS DTR Complement Control bit Complement Complement Complement Complement 4 00H NOTE: The register number is provided as a reference number for the register description. 14 M82510 BANK ONEÐGENERAL WORK BANK (Continued) Register 7 FLR (25) Ð 6 5 4 3 Rx FIFO Level 2 1 Ð 4 00H 00H 5 Ð State State State Change Change Change in RI in DSR in CTS 6 00H Flush Tx Machine Flush Tx Tx FIFO Enable 6 Ð Modem Interrupt RxM Tx FIFO Rx FIFO Interrupt Interrupt Interrupt 7 12H 7 Ð Address/ Break Break Framing Control Terminated Detected Error Character Match Parity Error RCM (30) Rx Enable Rx Disable Open Rx FIFO TCM (29) 0 0 GSR (20) Ð Ð ICM (28) 0 0 Flush RxM Flush Rx FIFO DSR Input Inverted CTS Input State Inverted Change in DCD 0 Lock Rx FIFO 0 Timer Interrupt 0 TxM Interrupt Address Default 5 RST (23) Address/ Control Character Received MSR (27) DCD RI Input Complement Inverted 0 Tx FIFO Level Software Manual Int Status Reset Acknowledge Clear Command Overrun Rx FIFO Error Interrupt Requested 0 0 Tx Disable Power Down Mode 0 BANK TWOÐGENERAL CONFIGURATION Register 7 6 FMD (4) 0 0 GIR/BANK (21) 0 BANK Pointer bit 1 TMD (3) IMD (1) Error Echo Disable 5 BANK Pointer bit 0 RMD (7) 0 Control 9-bit Character Character Echo Disable Length 0 0 3 2 0 0 Active Block Int bit 2 Transmit Mode 0 ACR1 (6) RIE (17) 4 Rx FIFO Threshold 0 1 0 Address Default Tx FIFO Threshold 1 00H Active Active Interrupt Block Int Block Int Pending bit 1 bit 0 2 01H Software Parity Mode 3 00H Loopback or Echo Mode of Operation 4 0CH Stop Bit Length Interrupt Rx FIFO ulan Acknowledge Depth Mode Mode Select Address or Control Character 1 Address/ Control Character Recognition Interrupt Enable Address/ Control Character Match Interrupt Enable Address/Control Character Mode Break Terminate Interrupt Enable Break Detect Interrupt Enable Framing Error Interrupt Enable Disable DPLL Sampling Start bit Window Sampling Mode Mode 5 00H Parity Error Interrupt Enable Overrun Error Interrupt Enable 0 6 1EH 0 0 0 7 00H BANK THREEÐMODEM CONFIGURATION Register 7 6 5 4 3 2 1 0 Address Default CLCF (8) Rx Clock Mode Rx Clock Source Tx Clock Mode Tx Clock Source 0 0 0 0 0 00H BACF (9) 0 0 0 0 BRGA Mode 0 0 1 04H BRGA Clock Source BBL (13) BRGB LSB Divide Count (DLAB e 1) 0 05H BBH (14) BRGB MSB Divide Count (DLAB e 1) 1 00H 15 M82510 BANK THREEÐMODEM CONFIGURATION (Continued) Register 7 6 GIR/BANK (21) 0 BANK Pointer bit 1 BBCF (10) PMD (15) BRGB Clock Source 5 4 BANK Pointer bit 0 0 0 0 3 Active Block Int bit 2 0 DCD/ICLK/ DCD/ICLK/ DSR/TA/ DSR/TA/ RI/SCLK OUT 1 OUT 1 OUT 0 OUT 0 Function Direction Function Direction Function MIE (19) 0 0 0 0 TMIE (18) 0 0 0 0 2 Active Block Int bit 1 1 Active Block Int bit 0 0 Interrupt Pending Address Default 2 01H BRGB Mode 0 0 3 84H DTR/TB Function 0 0 4 FCH 5 0FH 6 00H DCD State RI State DSR State CTS State Change Int Change Int Change Int Change Int Enable Enable Enable Enable 0 0 Timer B Interrupt Enable Timer A Interrupt Enable CONFIGURATION These read/write registers are used to configure the device. They may be read at anytime; however, they may be written to only when the device is idle. Typically they are written to only once after system power up. They are set to default values upon Hardware or Software Reset (Default Wake-Up Mode). The default values are chosen so as to allow the M82510 to be fully software compatible with the IBM PC Async Adapter (INS 8250A/16450) when in the default wakeup mode. The M82510 can operate in the High Performance mode by programming the configuration registers as necessary. The configuration options available to the user are listed below. Table 11. Configuration Options Interrupt Acknowledge Mode # Automatic # Manual Receive # Sampling Window Size # Start Bit Detection Mode # DPLL Disable/Enable mLAN (8051) Address Recognition # Manual, Semi-Automatic, Automatic Diagnostics # Loopback # Remote # Local # Echo # Yes/No # Disable Error Echo # Disable Control/Address Char. Echo 16 FIFO # RX FIFO Depth # RX, TX Threshold Clock Options # RX, TX Clock Mode # 1X # 16X # RX, TX Clock Source # BRGA # BRGB # BRGA/B Operation Mode # Timer # BRG # BRGA/B Divide Count # BRGA/B Source # Sys Clock # SCLK Pin # BRGA Output (BRGB Only) Control Character Recognition # None # Standard # ASCII # EBCDIC # Two User Programmed TX Operation # RTS/CTS Control Manual, Semi-Automatic, Automatic # Parity Mode # Stop Bit Length # Character Size I/O Pins # Select Function for Each Multifunction Pin # Select Direction for Multifunction Pin (If Applicable) M82510 1. IMDÐINTERNAL MODE REGISTER IMDÐInternal Mode Register 271072 – 14 This register defines the general device mode of operation. The bit functions are as follows: 7–4: Reserved IAM: Interrupt Acknowledge Mode Bit 0 Ð Manual acknowledgement of pending interrupts 1 Ð Automatic acknowledgement of pending interrupts (upon CPU service) This bit, when set, configures the M82510 for the automatic acknowledge mode. This causes the M82510 INT line to go low for two clock cycles upon service of the interrupt. After two clock cycles it is then updated. It is useful in the edge triggered mode. In manual acknowledgement mode the CPU must explicitly issue a command to clear the INT pin. (The INT pin then goes low for a minimum of two clock cycles until another enabled status register bit is set.) RFD: ULM: uLAN Mode 0 Ð Normal Mode 1 Ð uLAN Mode This bit, enables the M82510 to recognize and/or match address using the 9-bit MCS-51 asynchronous protocol. LEM: Loopback/Echo Mode Select This bit selects the mode of loopback operation, or the mode of echo operation; depending upon which operation mode is selected by the Modem Control register bit LC. In loopback mode (Modem Control register bit LC e 1) it selects between local and remote loopback. 0 Ð Local Loopback 1 Ð Remote Loopback In echo mode (Modem Control register bit LC e 0) it selects between echo or non-echo operation. Receive FIFO Depth 0 Ð Four Bytes 1 Ð One Byte 0 Ð No Echo 1 Ð Echo Operation This bit configures the depth of the Rx FIFO. With a FIFO depth of one, the FIFO will act as a 1-byte buffer to emulate the 8250A. 17 M82510 2. LCRÐLINE CONFIGURE REGISTER LCRÐLine Configure Register 271072 – 15 This register defines the basic configuration of the serial link. DLABÐDivisor Latch Access BitÐThis bit, when set, allows access to the Divisor Count registers BAL,BAH;BBL,BBH registers. SBKÐSet Break BitÐThis bit will force the TxD pin low. The TxD pin will remain low (regardless of all activities) until this bit is reset. PM2ÐPM0ÐParity Mode BitsÐThese three bits combine with the SPF bit of the Transmit Mode register to define the various parity modes. See Table 12. Table 12. Parity Modes PM0 SPF PM2 PM1 Function 0 1 1 1 1 1 X 0 0 0 0 1 X 0 0 1 1 0 X 0 1 0 1 0 No Parity Odd Parity Even Parity High Parity Low Parity Software Parity SBLOÐStop Bit LengthÐThis bit, together with SBL1 and SBL2 bits of the Transmit Mode register, defines the Stop-bit lengths for transmission. The Rx machine can identify 3/4 stop bit or more. See Table 13. 18 Table 13. Stop Bit Length SBL2 SBL1 SBL0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Stop Bit Length 16X 1X 4/4 6/4 or 8/4* 3/4 4/4 5/4 6/4 7/4 8/4 Ð Ð 1 1 1 1 1 2 *6/4 if character length is 5 bits; else 8/4 CL0ÐCL1ÐCharacter Length BitsÐThese bits, together with the Transmit Mode register bit NBCL, define the character length. See Table 14. Table 14. Character Length NBCL CL1 CL0 Character Length 0 0 0 0 1 0 0 1 1 0 0 1 0 1 0 5 BITS 6 BITS 7 BITS 8 BITS 9 BITS M82510 3. TMDÐTransmit Machine Mode Register TMDÐTransmit Machine Mode Register 271072 – 16 This register together with the Line Configure Register defines the Tx machine mode of operation. 01ÐReserved EEDÐError Echo DisableÐDisables Echo of characters received with errors (valid in echo mode only). 10ÐSemi-Automatic ModeÐIn this mode the M82510 transmits only when CTS input is active. The M82510 activates the RTS output as long as transmission is enabled. CEDÐControl Character Echo DisableÐDisables Echo of characters recognized as control characters (or address characters in uLAN mode). Valid in echo mode only. 11ÐAutomatic ModeÐIn this mode the M82510 transmits only when CTS input is active. The RTS output is activated only when transmission is enabled and there is more data to transmit. NBCLÐNine-Bit LengthÐThis bit, coupled with LCR (CL0, CL1), selects Transmit/Receive character length of nine bits. See Table 14. SPFÐSoftware Parity ForceÐThis bit defines the parity modes along with the PM0, PM1, and PM2 bits of the LCR register. When software parity is enabled the software must determine the parity bit through the TxF register on transmission, or check the parity bit in RxF upon reception. See Table 12. TM1ÐTM0ÐTransmit ModeÐThese bits select one of three modes of control over the CTS and RTS lines. 00ÐManual ModeÐIn this mode the CPU has full control of the Transmit operation. The CPU has to explicitly enable/disable transmission, and activate/ check the RTS/CTS pins. SBL2ÐSBL1ÐStop Bit LengthÐThese bits, together with the SBL0 bit of the LCR register define the stop bit length. See Table 13. 19 M82510 4. FMDÐFIFO MODE REGISTER FMDÐFIFO Mode Register 271072 – 17 This register configures the Tx and Rx FIFO’s threshold levelsÐthe occupancy levels that can cause an interrupt. cated by these bits the Rx FIFO Interrupt is activated. 3Ð2ÐReserved 7Ð6ÐReserved RFT1ÐRFT0ÐReceive FIFO ThresholdÐWhen the Rx FIFO occupancy is greater than the level indi- TFT1ÐTFT0ÐTransmit FIFO ThresholdÐWhen the TX FIFO occupancy is less than or equal to the level indicated by these bits the Tx FIFO Interrupt is activated. 5. ACR0ÐADDRESS/CONTROL CHARACTER REGISTER 0 ARC0ÐAddress/Control Character Register 0 271072 – 18 This register contains a byte which is compared to each received character. The exact function depends on the configuration of the IMD register. In normal mode this register may be used to program a special control character; a matched character will be reported in the RECEIVE STATUS register. The maximum length of the control characters is eight bits. If the length is less than eight bits then the character must be right justified and the leading bits be filled with zeros. In uLAN mode this register contains the eight-bit station address for recognition. In this mode only incoming address characters (i.e., characters with address bit set) will be compared to these register. The PCRF bit in the RECEIVE STATUS register will be set when an Address or Control Character match occurs. 6. ACR1ÐADDRESS/CONTROL CHARACTER REGISTER 1 ARC1ÐAddress/Control Character Register 1 271072 – 19 NOTE: This register is identical in function to ACR0. 20 M82510 7. RMDÐRECEIVE MACHINE MODE REGISTER RMDÐReceive Machine Mode Register 271072 – 20 This register defines the Rx Machine mode of operation. uCM0, uCM1ÐuLAN/Control Character Recognition ModeÐIn normal mode it defines the Control Character recognition mode. In ulan mode they define modes of address recognition. In uLAN mode: selects the mode of address recognition. 11ÐReserved In normal Mode: selects the mode of Standard Set Control Character Recognition (programmed control characters are always recognized). 00Ð No Standard Set Control Characters Recognized. 01Ð ASCII Control Characters (00HÐ1 FH a 7FH). 10Ð Reserved. 00ÐManual ModeÐRx Machine reports reception of any address character, via CRF bit of RECEIVE STATUS register, and writes it to the Rx FIFO. 01ÐSemi-Automatic ModeÐOperates the same as Manual Mode but, in addition, the Rx Machine OPENS (unlocks) the Rx FIFO upon reception of any address characters. Subsequent received characters will be written into the FIFO. (Note: it is the user’s responsibility to LOCK the FIFO if the address character does not match the station’s address.) 10ÐAutomatic ModeÐThe Rx Machine will OPEN (unlock) the Rx FIFO upon Address Match. In addition the Rx Machine LOCKs the Rx FIFO upon recognition of address mismatch; i.e., it controls the flow of characters into the Rx FIFO depending upon the results of the address comparison. If a match occurs it will allow characters to be sent to the FIFO; if a mismatch occurs it will keep the characters out of the FIFO by LOCKING it. 11Ð EBCDIC Control Character Recognized (00H b 3FH). DPDÐDisable Digital Phase Locked LoopÐWhen set, disables the DPLL machine. (Note: using the DPLL in a very noisy media, may increase the error rate.) SWMÐSampling Window ModeÐThis bit controls the mode of data sampling: 0ÐSmall Window, 3/16 sampling. 1ÐLarge Window, 7/16 sampling. SSMÐStart Bit Sampling ModeÐThis bit controls the mode of Start Bit sampling. 0Ð Majority Voting for start bit. In this mode a majority of the samples determines the bit. 1Ð In this mode if one of the bit samples is not ‘0’, the start bit will not be detected. 21 M82510 8. CLCFÐCLOCKS CONFIGURE REGISTER CLCFÐClocks Configure Register 271072 – 21 This register defines the Transmit and Receive Code modes and sources. TxCMÐTransmit Clock ModeÐThis bit selects the mode of the Transmit Data Clock, which is used to clock out the Transmit Data. RxCMÐRx Clock ModeÐThis bit selects the mode of the receive clock which is used to sample the received data. 0Ð 16X Mode 1Ð 1X Mode. In this mode the Transmit data is synchronous to the Serial Clock; supplied via the SCLK pin. 0Ð 16X Mode. 1Ð 1X Mode. In this mode the receive data must be synchronous to the Rx Clock; supplied via the SCLK pin. RxCSÐRx Clock SourceÐThis bit selects the source of the internal receive clock in the case of 16X mode (as programmed by the RxCM bit above). TxCSÐTransmit Clock SourceÐSelects the source of internal Transmit Clock in case of 16X mode. 0ÐBRGB Output. 1ÐBRGA Output. 0ÐBRGB Output 1ÐBRGA Output 9. BACFÐBRGA CONFIGURATION REGISTER BACFÐBRGA Configuration Register 271072 – 22 This register defines the BRGA clock sources and the mode of operation. BACSÐBRGA Clock SourceÐSelects the input clock source for Baud Rate Generator A. 0ÐSystem Clock 1ÐSCLK Pin This bit has no effect if BRGA is configured as a timer. 22 BAMÐBRGA Mode of OperationÐSelects between the Timer mode or the Baud Rate Generator Mode. 0Ð Timer Mode (in this mode the input clock source is always the system clock). 1Ð Baud Rate Generator Mode M82510 10. BBCFÐBRGB CONFIGURATION REGISTER BBCFÐBRGB Configuration Register 271072 – 23 This register defines the BRGB clock sources and mode of operation. (Note: BRGB can also take its Input Clock from the output of BRGA.) BBCS1, BBCS0ÐThese two bits together define the input Clock Sources for BRGB. These bits have no effect when in the timer mode. 00Ð System Clock 01Ð SCLK Pin 10Ð BRGA Output 11Ð Reserved BBMÐBRGB Mode of Operation. 0Ð Timer Mode (In this mode the input clock source is always the system clock.) 1Ð BRG Mode 11. BALÐBRGA DIVIDE COUNT LEAST SIGNIFICANT BYTE BALÐBRGA Divide Count Low Byte 271072 – 24 This register contains the least significant byte of the BRGA divisor/count. 12. BAHÐBRGA DIVIDE COUNT MOST SIGNIFICANT BYTE BAHÐBRGA Divide Count High Byte 271072 – 25 This register contains the most significant byte of the BRGA divisor/count. 13. BBLÐBRGB DIVIDE COUNT LEAST SIGNIFICANT BYTE BBLÐBRGB Divide Count Low Byte 271072 – 26 This register contains the least significant byte of the BRGB divisor/count. 23 M82510 14. BBHÐBRGB DIVIDE COUNT MOST SIGNIFICANT BYTE BBHÐBRGB Divide Count High Byte 271072 – 27 This register contains the most significant byte of the BRGB divisor/count. 15. PMDÐI/O PIN MODE REGISTER PMDÐI/O Pin Mode Register 271072 – 28 This register is used to configure the direction and function of the multifunction pins. The following options are available on each pin. 1. Direction: Input or Output Pin. 0Ð Defines the Pin as an output pin (general purpose or special function). 1Ð Defines the pin as an input pin. 2. Function: General purpose or special purpose pin (no effect if the pin is programmed as an Input). 0Ð special function output pin. 1Ð general purpose output pin. DIODÐDCD/ICLK/OUT1 Direction. 0Ð Output: ICLK or OUT1 (depending on bit DIOF) 1Ð Input: DCD. DIOFÐDCD/ICLK/OUT1 Function (output mode only). 24 0Ð ICLK (Output of the Internal System Clock). 1Ð OUT1 general purpose output, Controlled by MODEM CONTROL Register DTADÐDSR/TA/OUT0 Direction. 0Ð Output: TA or OUT0 (Dependent upon DTAF). 1Ð Input: DSR. DTAFÐDSR/TA/OUT0 Direction (output mode only). 0Ð TA (BRGA Output or Timer A Termination Pulse). 1Ð OUT0 (general purpose output, controlled by MODEM CONTROL). RRFÐRI/SCLK Function 0Ð SCLK (Receive and/or Transmit Clock) 1Ð RI DTFÐDTR/TB Function 0Ð TB (BRGB Output Clock on Timer B termination pulse depending upon the mode of BRGB). 1Ð DTR M82510 INTERRUPT/STATUS REGISTERS Interrupt Masking The M82510 uses a two layer approach to handle interrupt and status generation. Device level registers show the status of the major M82510 functional block (MODEM, FIFO, Tx MACHINE, Rx MACHINE, TIMERS, etc.). Each block may be examined by reading its individual block level registers. Also each block has interrupt enable/generation logic which may generate a request to the built-in interrupt controller, the interrupt requests are then resolved on a priority basis. The M82510 has a device enable register, GER, which can be used to enable or mask-out any block interrupt request. Some of the blocks (Rx Machine, Modem, Timer) have an enable register associated with their status register which can be used to mask out the individual sources within the block. Interrupts are enabled when programmed high. 16. GERÐGENERAL ENABLE REGISTER GERÐGeneral Enable Register 271072 – 29 This register enables or disables the bits of the GSR register from being reflected in the GIR register. It serves as the device enable register and is used to mask the interrupt requests from any of the M82510 block (See Figure 1). TIEÐTimers Interrupt Enable MIEÐModem Interrupt Enable. RxIEÐRx Machine Interrupt Enable. TFIEÐTransmit FIFO Interrupt Enable. RFIEÐReceive FIFO Interrupt Enable. TxIEÐTransmit Machine Interrupt Enable. 17. RIEÐRECEIVE INTERRUPT ENABLE REGISTER RIEÐReceive Interrupt Enable Register 271072 – 30 This register enables interrupts from the Rx Machine. It is used to mask out interrupt requests generated by the status bits of the RST register. CREÐControl/uLAN Address Character Recognition Interrupt Enable.ÐEnables Interrupt when CRF bit of RST register is set. PCREÐProgrammable Control/Address Character Match Interrupt Enable.ÐEnables Interrupt on PCRF bit of RST. BkDEÐBreak Detection Interrupt EnableÐEnable Interrupt on BkD bit of RST. FEEÐFraming Error EnableÐEnable Interrupt on FE bit of RST. PEEÐParity Error EnableÐEnable Interrupt on PE bit of RST. OEEÐOverrun Error EnableÐEnable Interrupt on OE bit of RST. BkTeÐBreak Termination Interrupt Enable. 25 M82510 18. TMIEÐTIMER INTERRUPT ENABLE REGISTER TMIEÐTimers/Interrupt Enable Register 271072 – 31 This is the enable register for the Timer Block. It is used to mask out interrupt requests generated by the status bits of the TMST register. TBIEÐTimer B Expired Interrupt EnableÐEnables Interrupt on TBEx bit of TMST. TAIEÐTimer A Expired Interrupt EnableÐEnables Interrupt on TAEx bit of TMST. 19. MIEÐMODEM INTERRUPT ENABLE REGISTER MIEÐModem Interrupt Enable Register 271072 – 32 This register enables interrupts from the Modem Block. It is used to mask out interrupt requests generated by the status bits of the MODEM STATUS register. CTSEÐDelta CTS Interrupt EnableÐEnables Interrupt on DCTS bits of MODEM STATUS. STATUS/INTERRUPT DCDEÐDelta DCD Interrupt EnableÐEnables Interrupt on DDCD bit of MODEM STATUS. RIEÐDelta RI Interrupt EnableÐEnables Interrupt on DRI bit of MODEM STATUS. DSREÐDelta DSR Interrupt EnableÐEnables Interrupt on DSR bit of MODEM STATUS. 26 The M82510 has two device status registers, which reflect the overall status of the device, and five block status registers. The two device status registers, GSR and GIR, and supplementary in function. GSR reflects the interrupt status of all blocks, whereas GIR depicts the highest priority interrupt only. GIR is updated after the GSR register; the delay is of approximately two clock cycles. M82510 20. GSRÐGENERAL STATUS REGISTER GSRÐGeneral Status Register 271072 – 33 This register reflects all the pending block-level Interrupt requests. Each bit in GSR reflects the status of a block and may be individually enabled by GER. GER masks-out interrupts from GIR; it does not have any effect on the bits in GSR. The only way that the bits can be masked out in GSR (i.e., not appear in GSR) is if they are masked out at the lower level. TIRÐTimers Interrupt RequestÐThis bit indicates that one of the timers has expired. (See TMST) MIRÐModem Interrupt RequestÐThis bit, if set, indicates an interrupt from the Modem Module. (As reflected in MODEM STATUS.) RxIRÐReceive Machine Interrupt RequestÐ(As reflected in RST.) TFIRÐTransmit FIFO Interrupt RequestÐTx FIFO occupancy is below or equal to threshold. RFIRÐReceive FIFO Interrupt RequestÐRx FIFO Occupancy is above threshold. TxIRÐTransmit Machine Interrupt RequestÐIndicates that the Transmit Machine is either empty or disabled (Idle). 21. GIR/BANKÐGENERAL INTERRUPT REGISTER/BANK REGISTER General Interrupt Register/Bank Register 271072 – 34 This register holds the highest priority enabled pending interrupt from GSR. In addition it holds a pointer to the current register segment. Writing into this register will update only the BANK bits. BANK1, BANK0ÐBank Pointer BitsÐThese two bits point to the currently accessible register bank. The user can read and write to these bits. The address of this register is always two within all four register banks. BI2, BI1, BI0,ÐInterrupt Bits 0–2ÐThese three bits reflect the highest priority enabled pending interrupt from GSR. 101: 100: 011: 010: 001: 000: Timer Interrupt (highest priority) Tx Machine Interrupt Rx Machine Interrupt Rx FIFO Interrupt Tx FIFO Interrupt Modem Interrupt (lowest priority) IPNÐInterrupt PendingÐThis bit is active low. It indicates that there is an interrupt pending. The interrupt logic asserts the INT pin as soon as this bit goes active. (Note: the GIR register is continuously updated; so that, while the user is serving one interrupt source, a new interrupt with higher priority may enter GIR and replace the older interrupt.) 27 M82510 22. LSRÐLINE STATUS REGISTER LSRÐLine Status Register 271072 – 35 This register holds the status of the serial link. It shares five of its bits with the RST register (BkD, FE, PE, OE, and RFIR). When this register is read, the RST register (BITS 1–7) and LSR register (BITS 1 – 4) are cleared. This register is provided for compatibility with the INS8250A. TFIR bit of GSR by writing a character to Tx FIFO, or drop TFIE bit of GER (Disable Tx FIFO). TxStÐTransmit Machine Status BitÐSame as TxIR bit of GSR register. If high it indicates that the Transmit Machine is in Idle State. (Note: Idle may indicate that the TxM is either empty or disabled. FEÐFraming Error DetectedÐSee FE bit in RST register for a full explanation. The FE bit in RST register is the same as this bit. TFStÐTransmit FIFO StatusÐSame as TFIR bit of GSR. It indicates that the Transmit FIFO level is equal to or below the Transmit FIFO Threshold. There are two ways to disable the transmit FIFO status from being reflected in GIR: 1. Writing a ‘‘0’’ to the TFIE bit of the GER register 2. Dynamically by using the Tx FIFO HOLD INTERRUPT logic. When the Tx FIFO is in the Hold State, no interrupts are generated regardless of the TFIR and TFIE bits. The Transmit FIFO enters the Hold State when the CPU reads the GIR register and the source of the interrupt is Tx FIFO. To Exit, the CPU must drop the 28 BkdÐBreak DetectedÐSee Bkd bit in RST register for full explanation. The BkD bit in RST register is the same as this bit. PEÐParity Error DetectedÐSee PE bit in RST register for full explanation. The PE bit in RST register is the same as this bit. OEÐOverrun ErrorÐSee OE bit in RST register for full explanation. The OE bit in RST register is the same as this bit. RFIRÐReceive FIFO Interrupt RequestÐThis bit is identical to RFIR bit of GSR. It indicates that the RX FIFO level is above the Rx FIFO Threshold. This bit is forced LOW during any READ from the Rx FIFO. A zero written to this bit will acknowledge an Rx FIFO interrupt. M82510 23. RSTÐRECEIVE MACHINE STATUS REGISTER RSTÐReceive Machine Status Register 271072 – 36 This register displays the status of the Receive Machine. It reports events that have occurred since the RST was cleared. This register is cleared when it is read except for BIT0, Rx FIFO interrupt. Each bit in this register, when set, can cause an interrupt. Five bits of this register are shared with the LSR register. CRFÐControl/Address Character ReceivedÐ When enabled, this bit can cause an interrupt if a control character or address character is received. In uLAN Mode: indicates that an address character has been received. In normal Mode: indicates that a standard control character (either ASCII or EBCDIC) has been received. PCRFÐProgrammed Control/Address Character ReceivedÐThis bit, when enabled, will cause an interrupt when an address or control character match occurs. In uLAN Mode: indicates that an address character equal to one of the registers ACR0 or ACR1 has been received. In normal Mode: indicates that a character which matches the registers ACR0 or ACR1 has been received. BkTÐBreak TerminatedÐThis bit indicates that a break condition has been terminated. BkDÐBreak DetectedÐThis bit indicates that a Break Condition has been detected, i.e., RxD input was held low for one character frame plus a stop BIT. FEÐFraming ErrorÐThis bit indicates that a received character did not have a valid stop bit. PEÐParity ErrorÐIndicates that a received character had a parity error. OEÐOverrun ErrorÐIndicates that a received character was lost because the Rx FIFO was full. RFIRÐReceive FIFO Interrupt RequestÐSame as the RFIR bit of LSR register. 29 M82510 24. RXFÐRECEIVED CHARACTER FLAGS RxFÐReceive Flags Register 271072 – 37 This register contains additional information about the character in the RXD register. It is loaded by the Rx Machine simultaneously with the RXD register. ROKÐReceived Character OKÐThis bit indicates that the character in RXD no parity or framing error. The parity error is not included in the s/w parity mode. RxNÐReceived Character NoisyÐThe character in RXD was noisy. This bit, valid only in 16X sampling mode, indicates that the received character had non-identical samples for at least one of its bits. RPEÐReceive Character Parity ErrorÐThis bit indicates that the RxD character had a Parity Error. However, in S/W Parity mode it holds the received parity bit as is. A control CharacterÐin normal Mode. An Address Character in uLAN Mode. RFEÐReceive Character Framing ErrorÐIndicates that no Stop bit was found for the character in RXD. NOTE: A Framing Error will be generated for the first character of the Break sequence. RNDÐNinth Bit of Received CharacterÐThe most significant bit of the character in RXD is written into this bit. This bit is zero for characters with less than nine bits. BKFÐBreak FlagÐIndicates that the character is part of a ‘‘break’’ sequence. ACRÐAddress/Control Character MarkerÐThis bit indicates that the character in RXD is either: 25. FLRÐFIFO LEVEL REGISTER FLRÐFIFO Level Register 271072 – 38 This register holds the current Receive and Transmit FIFO occupancy levels. pancy of the Rx FIFO. The valid range is zero (000) to four (100). RFL2, RFL1, RFL0ÐReceive FIFO Level of OccupancyÐThese three bits indicate the level of Occu- TFL2, TFL1, TFL0ÐTransmit FIFO Level of OccupancyÐThese three bits indicate the level of occupancy in the transmit FIFO. The valid range is zero (000) to four (100). 30 M82510 26. TMSTÐTIMER STATUS REGISTER TMSTÐTimer Status Register 271072 – 39 This register holds the status of the timers. Bits TBEx and TAEx generate interrupts which are reflected in bit TIR of GSR. Bits GBS and GAS just display the counting status, they do not generate interrupts. GASÐGateÐA StateÐThis bit does not generate an interrupt. It reflects the state of the software gate of Timer A, as written through the TMCR register. GBSÐGate B StateÐThis bit does not generate an interrupt. It indicates the counting state of the software gate of Timer B, as written through the TMCR register. 0Ðcounting disabled 1Ðcounting enabled TBExÐTimer B ExpiredÐWhen Set generates an interrupt through TIR bit of GSR. Indicates that Timer B count has expired. This bit is set via the terminal count pulse generated by the timer when it terminates counting. 0Ðcounting disabled 1Ðcounting enabled TAExÐTimer A ExpiredÐSame as TBEx except it refers to Timer A. 27. MSRÐMODEM/I/O PINS REGISTER MSRÐModem/I/O Pins Status Register 271072 – 40 This register holds the status of the Modem input pins (CTS, DCD, DSR, RI). It is the source of interrupts (MSR 0–3) for the MIR bit of GSR. If any of the above inputs change levels the appropriate bit in MODEM STATUS is set. Reading MODEM STATUS will clear the status bits. DCDCÐDCD ComplementÐHolds the complement of the DCD input pin if programmed as an input in PMD. DRIÐDelta RIÐIndicates that there was a high-tolow transition on the RI input pin since the register was last read. DDSRÐDelta DSRÐIndicates that the DSR input pin has changed state since this register was last read. DCTSÐDelta CTSÐIndicates that the CTS input pin has changed state since this register was last read. DRICÐHolds the complement of the RI input pin if programmed as an input in PMD. COMMAND REGISTERS DSRCÐDSR ComplementÐHolds the complement of the DSR input pin if configured as an input in PMD. CTSCÐCTS ComplementÐHolds the complement of the CTS pin. The command registers are write only; they are used to trigger an operation by the device. Once the operation is started the register is automatically reset. There is a device level register as well as four block command registers. It is recommended that only one command be issued during a write cycle. DDCDÐDelta DCDÐIndicates that the DCD input pin has changed state since this register was last read. 31 M82510 28. ICMÐINTERNAL COMMAND REGISTER ICMÐInternal Command Register 271072 – 41 This register activates the device’s general functions. SRSTÐDevice Software RESETÐCauses a total device reset; the effect is identical to the hardware reset (except for strapping options). The reset lasts four clocks and puts the device into the Default Wake-up Mode. INTAÐInterrupt AcknowledgeÐThis command is an explicit acknowledgement of the M82510’s interrupt request. It forces the INT pin inactive for two clocks; afterwards, the INT pin may again go active if other enabled interrupts are pending. This command is provided for the Manual Acknowledge mode of the M82510. StCÐStatus ClearÐClears the following status registers: RST, MSR, and TMST. PDMÐPower DownÐThis command forces the device into the power-down mode. Refer to the functional description for details. 29. TCMÐTRANSMIT COMMAND REGISTER TCMÐTransmit Command Register 271072 – 42 This register controls the operation of the Transmit Machine. TxENÐTransmit EnableÐEnables Transmission by the Transmit Machine. FTMÐFlush Transmit MachineÐResets the Transmit Machine logic (but not the registers or FIFO) and enables transmission. TxDiÐTransmit DisableÐDisables transmission. If transmission is occurring when this command is issued the Tx Machine will complete transmission of the current character before disabling transmission. FTFÐFlush Transmit FIFOÐClears the Tx FIFO. 32 M82510 30. RCMÐRECEIVE COMMAND REGISTER RCMÐReceive Command Register 271072 – 43 This register controls the operation of the Rx machine. RxEÐReceive EnableÐEnables the reception of characters. RxDiÐReceive DisableÐDisables reception of data on RXD pin. FRMÐFlush Receive MachineÐResets the Rx Machine logic (but not registers and FIFOs), enables reception, and unlocks the receive FIFO. FRFÐFlush Receive FIFOÐClears the Rx FIFO. LRFÐLocks Rx FIFOÐDisables the write mechanism of the Rx FIFO so that characters subsequently received are not written to the Rx FIFO but are lost. However, reception is not disabled and complete status/event reporting continues. (This command may be used in the uLAN mode to disable loading of characters into the Rx FIFO until an address match is detected.) ORFÐOpen (Unlock) Rx FIFOÐThis command enables or unlocks the write mechanism of the Rx FIFO. 31. TMCRÐTIMER CONTROL REGISTER TMCRÐTimer Control Register 271072 – 44 This register controls the operation of the two M82510 timers. It has no effect when the timers are configured as baudÐrate generators. TGA and TGB are not reset after command execution. TGBÐTimer-B GateÐThis bit serves as a gate for Timer B operation: 1Ðenables counting 0Ðdisables counting 1Ðenables counting 0Ðdisables counting STBÐStart Timer BÐThis command triggers timer B. At terminal count a status bit is set in TMST (TBEx). STAÐStart Timer AÐThis command triggers timer A. At terminal count a status bit is set in TMST (TAEx). TGAÐTimer-A GateÐThis bit serves as a gate for Timer-A operation: 33 M82510 32. MCRÐMODEM CONTROL REGISTER MCRÐModem Control Register 271072 – 45 This register controls the modem output pins. With multi-function pins it affects only the pins configured as general purpose output pins. All the output pins invert the data, i.e. their output will be the complement of the data written into this register. OUT0ÐOUT0 Output BitÐThis bit controls the OUT0 pin. The output signal is the complement of this bit. LCB Loopback Control BitÐThis bit puts the M82510 into loopback mode. The particular type of loopback is selected via the IMD register. OUT2ÐOUT2 Output BitÐThis bit controls the OUT2 pin. The output signal is the complement of this bit. OUT1ÐOUT1 Output BitÐThis bit controls the OUT1 pin. The output signal is the complement of this bit. RTSÐRTS Output BitÐThis bit controls the RTS pin. The output signal is the complement of this bit. DTRÐDTR Output BitÐThis bit controls the DTR pin. The output signal is the complement of this bit. DATA REGISTERS The data registers hold data or other information and may be accessed at any time. 33. TXDÐTRANSMIT DATA REGISTER TXDÐTransmit Data Register 271072 – 46 This register holds the next data byte to be pushed into the Transmit FIFO. For character formats with more than eight bits of data, or with additional components (S/W Parity, Address Marker Bit) the additional data bits should be written into the TxF regis- 34 ter. When a byte is written to this register its contents, along with the contents of the TxF register, are pushed to the top of the Transmit FIFO. This register is write only. M82510 34. TXFÐTRANSMIT FLAGS REGISTER TxFÐTransmit Flags Register 271072 – 47 This register holds some additional components of the next character to be pushed into the Tx FIFO. The contents of this register are pushed into the Tx FIFO with the Transmit Data register whenever the TxD register is written to by the CPU. SPÐSoftware Parity BitÐThis bit is transmitted in S/W parity mode as the character’s parity bit. D8ÐNinth Bit of DataÐIn nine-bit character length mode this bit is transmitted as the MSB (D8) bit. uLANÐuLAN Address Marker BitÐThis bit is transmitted in uLAN mode as the address marker bit. 35. RXDÐRECEIVE DATA REGISTER RXDÐReceive Data Register 271072 – 48 This register holds the earliest received character in the Rx FIFO. The character is right justified and leading bits are zeroed. This register is loaded by the Rx Machine with the first received character. Reading the register causes the next register from the Rx FIFO to be loaded into RxD and RxF registers. 35 M82510 SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS NOTICE: This is a production data sheet. The specifications are subject to change without notice. Case Temperature under Bias ÀÀÀ b 55§ C to a 125§ C *WARNING: Stressing the device beyond the ‘‘Absolute Maximum Ratings’’ may cause permanent damage. These are stress ratings only. Operation beyond the ‘‘Operating Conditions’’ is not recommended and extended exposure beyond the ‘‘Operating Conditions’’ may affect device reliability. Voltage on any Pin (w.r.t. VSS) b 0.5V to VCC a 0.5V Storage Temperature ÀÀÀÀÀÀÀÀÀÀÀÀ b 65§ to a 150§ C Voltage on VCC Pin (w.r.t. VSS)ÀÀÀÀÀÀ b 0.5V to a 7V Power Dissipation ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ250 mW Operating Conditions Description Min Max Units TC Symbol Case Temperature (Instant On) b 55 a 125 §C VCC Digital Supply Voltage 4.50 5.50 V DC SPECIFICATIONS DC CHARACTERISTICS Symbol (Over Specified Operating Conditions) Parameter Notes Min Max Units (1) b 0.5 0.8 V 2.4 VCC a 0.5 V 2.6 VCC a 0.5 V 0.45 V VIL Input Low Voltage VIH1 Input High Voltage-Cerdip (1) VIH2 Input High Voltage-LCC (2) VOL Output Low Voltage (2), (8) VOH Output High Voltage (3), (8) ILI Input Leakage Current (4) g 10 mA ILO 3-State Leakage Current (5) g 10 mA ICC Power Supply Current (6) 3.8 mA/MHz ISTBY Standby Supply Current (9) 500 mA IOHR RTS, DTR Strapping Current (10) 0.4 mA IOLR RTS, DTR Strapping Current (11) CIN Input Capacitance (7) 10 pF CIO I/O Capacitance (7) 10 pF CXTAL X1, X2 Load 10 pF 2.4 V 11 mA NOTES: 1. Does not apply to CLK/X1 pin, when configured as crystal oscillator input (X1). 2. @ IOL e 2 mA. 3. @ IOH e b0.4 mA. 4. 0 k VIN k VCC. 5. 0.45V k VOUT k (VCC b 0.45). 6. VCC e 5.5V; VIL e 0.5V (max); VIH e VCC b 0.5V (min); Typical value e 2.5 mA/MHz (Not Tested); Ext 1X CLK; IOL e IOH e 0. 7. Freq e 1 MHz. 8. Does not apply to OUT2/X2 pin, when configured as crystal oscillator output (X2). 9. Same as 7, but input clock not running. 10. Applies only during hardware reset for clock configuration options. Strapping current for logic HIGH. 11. Applies only during hardware reset for clock configuration. Strapping current for logic LOW. 36 M82510 AC SPECIFICATIONS SYSTEM CLOCK SPECIFICATIONS (Over Specified Operating Conditions) Symbol Parameter Min Max Notes 250 (2) DIVIDE BY TWO OPTIONÐACTIVE Testing Conditions: # All AC output parameters are under output load TCY/2 CLK Period 54 of 20 to 100 pF, unless otherwise specified. # AC testing inputs are driven at 2.4V for logic ‘1’ on CERDIP, 2.7V on LCC, and 0.45V for logic ‘0’. Output timing measurements are made at 1.5V for both a logical ‘0’ and ‘1’. TCLCH CLK Low Time 25 TCHCL CLK High Time 25 TCH1CH2 CLK Rise Time 10 (1) TCL2CL1 CLK Fall Time 10 (1) # In the following tables, the units are ns, unless FXTAL External Crystal Frequency Rating otherwise specified. 4.0 18.432 MHz DIVIDE BY TWO OPTIONÐINACTIVE System Interface SpecificationÐSystem Clock Specification: TCY CLK Period TCLCH CLK Low Tme 54 The M82510 system clock is supplied via the CLK pin or generated by an on-chip crystal oscillator. The clock is optionally divided by two. The CLK parameters are given separately for internal divide-by-two option ACTIVE and INACTIVE. TCHCL CLK High Time 44 TCH1CH2 CLK Rise Time 15 (1) TCL2CL1 CLK Fall Time 15 (1) The system clock (after division by two, if active) must be at least 16X the Tx or Rx baud rate (the faster of the two). 108 250 NOTES: 1. Rise/fall times are measured between 0.8 and 2.0V. 2. Tcy in ACTIVE divide by two option is TWICE the input clock period. RESET SPECIFICATION Symbol Parameter Min TRSHL Reset WidthÐCLK/X1 Configured to CLK 8 TCY TTLRSL RTS/DTR LOW Setup to Reset Inactive 6 TCY TRSLTX RTS/DTR Low Hold after Reset Inactive 0 Max Notes (1) (2) TCY b 20 (2) 271072 – 49 NOTES: 1. In case of CLK/X1 configured as X1, 1 Ms is required to guarantee crystal oscillator wake-up. 2. RTS/DTR are internally driven HIGH during RESET active time. The pin should be either left OPEN or externally driven LOW during RESET according to the required configuration of the system clock. These parameters specify the timing requirements on these pins, in case they are externally driven LOW during RESET. The maximum spec on TRSLTX requires that the RTS/DTR pins not be forced later than TRSLTX maximum. 37 M82510 READ CYCLE SPECIFICATIONS Symbol Parameter Min TRLRH RD Active Width TAVRL Address/CS Setup Time to RD Active 7 TRHAX Address/CS Hold Time after RD Inactive 0 TRLDV Data Out Valid Delay after RD Active TCIAD Command Inactive to Active Delay TRHDZ Data Out Float Delay after RD Inactive Max Notes 2 Tcy a 65 2 Tcy a 65 Tcy a 15 (1) 40 NOTE: 1. Command refers to either Read or Write signals. 271072 – 50 WRITE CYCLE SPECIFICATION Symbol Parameter Min TWLWH WR Active Width TAVWL Address CS Setup Time to WR Active 7 TWHAX Address and CS Hold Time after WR 0 TDVWH Data in Setup Time to WR Inactive 90 TWHDX Data in Hold Time after WR Inactive 12 Max Notes 2 Tcy a 15 271072 – 51 NOTE: Many of the serial interface pins have more than one function; sometimes the different functions have different timings. In such a case, the timing of each function of a pin is given separately. 38 M82510 SCLK PIN SPECIFICATIONÐ16x CLOCKING MODE Symbol Parameter Min Max Notes TXCY SCLK Period 216 TXLXH SCLK Low Time 93 TXHXL SCLK High Time 93 TXH1XH2 SCLK Rise Time 15 (1) TXL2XL1 SCLK Fall Time 15 (1) Max Notes NOTE: 1. Rise/fall times are measured between 0.8V and 2.0V. SCLK PIN SPECIFICATIONÐ1x CLOCK MODE Symbol Parameter Min TXCY SCLK Period 3500 TXLXH SCLK Low Time 1650 TXHXL SCLK High Time 1650 TXH1XH2 SCLK Rise Time 15 (1) TXL2XL1 SCLK Fall Time 15 (1) NOTE: 1. Rise/fall times are measured between 0.8V and 2.0V. RXD SPECIFICATION (1x MODE) Symbol Parameter Min TRPW RXD Setup Time to SCLK High 250 TRPD RXD Hold Time After SCLK High 250 Max Notes 271072 – 52 TXD SPECIFICATION (1x MODE) Symbol Parameter Min Max TSCLKTXD TXD Valid Delay after SCLK Low Ð 170 Notes REMOTE LOOPBACK SPECIFICATION Symbol Parameter Min Max TRXDTXD TXD Delay after RXD Ð 170 Notes 39 M82510 Receive Logic Diagram 271072 – 53 Transmit Logic Diagram 271072 – 54 INTEL CORPORATION, 2200 Mission College Blvd., Santa Clara, CA 95052; Tel. (408) 765-8080 INTEL CORPORATION (U.K.) Ltd., Swindon, United Kingdom; Tel. (0793) 696 000 INTEL JAPAN k.k., Ibaraki-ken; Tel. 029747-8511 Printed in U.S.A./xxxx/0896/B10M/xx xx