PRELIMINARY Integrated Circuit Systems, Inc. ICS844256 FEMTOCLOCKS™CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER GENERAL DESCRIPTION FEATURES The ICS844256 is a Crystal-to-LVDS Clock Synthesizer/Fanout Buffer designed for SONET HiPerClockS™ and Gigabit Ethernet applications and is a member of the HiperClockS™ family of High Performance Clock Solutions from ICS. The output frequency can be set using the frequency select pins and a 25MHz crystal for Ethernet frequencies, or a 19.44MHz crystal for SONET. The low phase noise characteristics of the ICS844256 make it an ideal clock for these demanding applications. • Six LVDS outputs ICS • Crystal oscillator interface • Output frequency range: 62.5MHz to 622.08MHz • Crystal input frequency range: 15.625MHz to 25.5MHz • RMS phase jitter at 125MHz, using a 25MHz crystal (1.875MHz to 20MHz): 0.48ps (typical) • Full 3.3V or 3.3V core, 2.5V output supply mode • 0°C to 70°C ambient operating temperature • Industrial temperature information available upon request • Available in both standard and lead-free RoHS-compliant packages SELECT FUNCTION TABLE Inputs Function FB_SEL N_SEL1 N_SEL0 M Divide N Divide M/N 0 0 0 25 1 25 0 0 1 25 2 12.5 0 1 0 25 4 6.25 0 1 1 25 5 5 1 0 0 32 1 32 1 0 1 32 2 16 1 1 0 32 4 8 1 1 1 32 8 4 BLOCK DIAGRAM PIN ASSIGNMENT Q0 nQ0 PLL_BYPASS Pullup Q1 1 XTAL_IN OSC PLL Output Divider 0 XTAL_OUT nQ1 Q2 nQ2 Q3 Feedback Divider nQ3 FB_SEL Pulldown Q4 N_SEL1 Pullup nQ4 N_SEL0 Pullup Q5 nQ5 VDDO VDDO nQ2 Q2 nQ1 Q1 nQ0 Q0 PLL_BYPASS V DDA VDD FB_SEL 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 Q3 nQ3 Q4 nQ4 Q5 nQ5 N_SEL1 GND GND N_SEL0 XTAL_OUT XTAL_IN ICS844256 24-Lead, 300-MIL SOIC 7.5mm x 15.33mm x 2.3mm body package M Package Top View 24-Lead TSSOP 4.40mm x 7.8mm x 0.92mm body package G Package Top View The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice. 844256AM www.icst.com/products/hiperclocks.html REV. A NOVEMBER 29, 2005 1 PRELIMINARY Integrated Circuit Systems, Inc. ICS844256 FEMTOCLOCKS™CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER TABLE 1. PIN DESCRIPTIONS Number Name 1, 2 VDDO 3, 4 5, 6 Type Description Power Output supply pins. nQ2, Q2 Output Differential output pair. LVDS interface levels. nQ1, Q1 Output Differential output pair. LVDS interface levels. 7, 8 nQ0, Q0 Output 9 PLL_BYPASS Input 10 VDDA Power Differential output pair. LVDS interface levels. Selects between the PLL and cr ystal inputs as the input to the dividers. When LOW, selects PLL. When HIGH, selects XTAL_IN, XTAL_OUT. LVCMOS / LVTTL interface levels. Analog supply pin. 11 VDD Power Core supply pin. 12 13, 14 15, 18 16, 17 FB_SEL XTAL_IN, XTAL_OUT N_SEL0 N_SEL1 GND Input 19, 20 nQ5, Q5 Output Differential output pair. LVDS interface levels. 21, 22 nQ4, Q4 Output Differential output pair. LVDS interface levels. 23, 24 nQ3, Q3 Output Differential output pair. LVDS interface levels. Input Input Pullup Pulldown Feedback frequency select pin. LVCMOS/LVTTL interface levels. Cr ystal oscillator interface. XTAL_IN is the input. XTAL_OUT is the output. Pullup Output frequency select pin. LVCMOS/LVTTL interface levels. Power supply ground. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter CIN Input Capacitance 4 pF RPULLUP Input Pullup Resistor 51 kΩ RPULLDOWN Input Pulldown Resistor 51 kΩ 844256AM Test Conditions www.icst.com/products/hiperclocks.html 2 Minimum Typical Maximum Units REV. A NOVEMBER 29, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS844256 FEMTOCLOCKS™CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER TABLE 3. CRYSTAL FUNCTION TABLE Inputs XTAL (MHz) FB_SEL Function N_SEL1 N_SEL0 M VCO (MHz) N Output (MHz) 20 0 0 0 25 500 1 500 20 0 0 1 25 500 2 250 20 0 1 0 25 500 4 125 20 0 1 1 25 500 5 100 21.25 0 1 1 25 531.25 5 106.25 24 0 0 0 25 600 1 600 24 0 0 1 25 600 2 300 24 0 1 0 25 60 0 4 150 24 0 1 1 25 60 0 5 12 0 25 0 0 0 25 625 1 625 25 0 0 1 25 625 2 312.5 25 0 1 0 25 625 4 156.25 25 0 1 1 25 625 5 12 5 25.5 0 1 0 25 637.5 4 159.375 15.625 1 1 1 32 500 8 62.5 18.5625 1 1 1 32 594 8 74.25 18.75 1 0 0 32 600 1 600 18.75 1 0 1 32 600 2 300 18.75 1 1 0 32 600 4 150 18.75 1 1 1 32 600 8 75 19.44 1 0 0 32 622.08 1 622.08 19.44 1 0 1 32 622.08 2 311.04 19.44 1 1 0 32 622.08 4 155.52 19.44 1 1 1 32 622.08 8 77.76 19.53125 1 0 0 32 625 1 625 19.53125 1 0 1 32 625 2 312.5 19.53125 1 1 0 32 625 4 156.25 19.53125 1 1 1 32 62 5 8 78.125 20 1 1 1 32 640 8 80 844256AM www.icst.com/products/hiperclocks.html 3 REV. A NOVEMBER 29, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS844256 FEMTOCLOCKS™CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5V Outputs, IO Continuous Current Surge Current 10mA 15mA Package Thermal Impedance, θJA 24 Lead SOIC 24 Lead TSSOP 50°C/W (0 lfpm) 70°C/W (0 mps) Storage Temperature, TSTG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter VDD Core Supply Voltage Test Conditions Minimum Typical Maximum Units 3.135 3.3 3.465 V VDDA Analog Supply Voltage 3.135 3.3 3.465 V VDDO Output Supply Voltage 3.135 3.3 3.465 V IDD Power Supply Current TBD mA IDDA Analog Supply Current TBD mA IDDO Output Supply Current TBD mA TABLE 4B. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = 3.3V±5%, VDDO = 2.5V±5%, TA = 0°C TO 70°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VDD Core Supply Voltage 3.135 3.3 3.465 V VDDA Analog Supply Voltage 3.135 3.3 3.465 V VDDO Output Supply Voltage 2.375 2.5 2.625 V IDD Power Supply Current TBD mA IDDA Analog Supply Current TBD mA IDDO Output Supply Current TBD mA TABLE 4C. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = VDDA = 3.3V±5%, VDDO = 3.3V±5% OR 2.5V±5%, TA = 0°C TO 70°C Symbol Parameter Maximum Units VIH Input High Voltage 2 VDD + 0.3 V VIL Input Low Voltage -0.3 0.8 V VDD = VIN = 3.465V 150 µA IIH Input High Current VDD = VIN = 3.465V 5 µA IIL Input Low Current 844256AM Test Conditions FB_SEL PLL_BYPASS, N_SEL0, N_SEL1 FB_SEL PLL_BYPASS, N_SEL0, N_SEL1 Minimum Typical VDD = 3.465V, VIN = 0V -5 µA VDD = 3.465V, VIN = 0V -150 µA www.icst.com/products/hiperclocks.html 4 REV. A NOVEMBER 29, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS844256 FEMTOCLOCKS™CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER TABLE 4D. LVDS DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5% TA = 0°C TO 70°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VOD Differential Output Voltage 350 mV Δ VOD VOD Magnitude Change 40 mV VOS Offset Voltage Δ VOS VOS Magnitude Change 1.25 V 50 mV NOTE: Please refer to Parameter Measurement Information for output information. TABLE 4E. LVDS DC CHARACTERISTICS, VDD = VDDA = 3.3V±5%, VDDO = 2.5V±5%, TA = 0°C TO 70°C Symbol Parameter VOD Differential Output Voltage Test Conditions Minimum Typical TBD Maximum Units mV Δ VOD VOD Magnitude Change TBD mV VOS Offset Voltage TBD V Δ VOS VOS Magnitude Change TBD mV TABLE 5. CRYSTAL CHARACTERISTICS Parameter Test Conditions Minimum Mode of Oscillation Typical Maximum Units Fundamental Frequency 15.625 25.5 MHz Equivalent Series Resistance (ESR) 50 Ω Shunt Capacitance 7 pF Drive Level 1 mW NOTE: Characterized using an 18pF parallel resonant cr ystal. 844256AM www.icst.com/products/hiperclocks.html 5 REV. A NOVEMBER 29, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS844256 FEMTOCLOCKS™CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER TABLE 6A. AC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter FOUT Output Frequency t jit(Ø) RMS Phase Jitter (Random) t sk(o) Output Skew; NOTE 1, 2 tR / tF Output Rise/Fall Time odc Output Duty Cycle Test Conditions Minimum Typical 53.125 Maximum Units 333.33 MHz 125MHz, Integration Range: 1.875MHz - 20MHz 0.48 TBD ps 20% to 80% TBD ps ps 50 PLL Lock Time tLOCK See Parameter Measurement Information section. NOTE 1: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential crossing points. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. % 1 ms Maximum Units 333.33 MHz TABLE 6B. AC CHARACTERISTICS, VDD = VDDA = 3.3V±5%, VDDO = 2.5V±5%, TA = 0°C TO 70°C Symbol Parameter FOUT Test Conditions Minimum Output Frequency t jit(Ø) RMS Phase Jitter (Random) t sk(o) Output Skew; NOTE 1, 2 tR / tF Output Rise/Fall Time odc Output Duty Cycle Typical 53.125 125MHz, Integration Range: 1.875MHz - 20MHz 20% to 80% 0.44 ps TBD ps TBD ps 50 PLL Lock Time tLOCK See Parameter Measurement Information section. NOTE 1: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential crossing points. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. 844256AM www.icst.com/products/hiperclocks.html 6 % 1 ms REV. A NOVEMBER 29, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS844256 FEMTOCLOCKS™CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER TYPICAL PHASE NOISE AT 125MHZ @ 3.3V 0 ➤ -10 -20 -30 Gb Ethernet Filter -50 -60 -70 125MHz RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.48ps (typical) -80 Raw Phase Noise Data -90 -100 -110 -120 -130 -140 -150 ➤ NOISE POWER dBc Hz -40 ➤ -160 -170 -180 -190 -200 Phase Noise Result by adding Gb Ethernet Filter to raw data 10 100 1k 10k 100k 1M 10M 100M OFFSET FREQUENCY (HZ) TYPICAL PHASE NOISE 125MHZ @ 3.3V/2.5V ➤ -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 AT Gb Ethernet Filter 125MHz RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.44ps (typical) Raw Phase Noise Data -110 -120 ➤ -130 -140 -150 -160 -170 -180 -190 -200 ➤ NOISE POWER dBc Hz 0 Phase Noise Result by adding Gb Ethernet Filter to raw data 10 100 1k 10k 100k 1M 10M 100M OFFSET FREQUENCY (HZ) 844256AM www.icst.com/products/hiperclocks.html 7 REV. A NOVEMBER 29, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS844256 FEMTOCLOCKS™CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER PARAMETER MEASUREMENT INFORMATION 3.3V 2.5V Qx 3.3V±5% POWER SUPPLY + Float GND - SCOPE SCOPE Qx + + LVDS LVDS nQx nQx 3.3V OUTPUT LOAD AC TEST CIRCUIT 3.3V/2.5V OUTPUT LOAD AC TEST CIRCUIT nQx nQ0:nQ5 Qx Q0:Q5 t PW t nQy Qy odc = tsk(o) PERIOD t PW x 100% t PERIOD OUTPUT SKEW OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD VDD out 80% DC Input VSW I N G Clock Outputs LVDS ➤ 80% 20% 20% tR ➤ out tF VOS/Δ VOS ➤ OFFSET VOLTAGE SETUP OUTPUT RISE/FALL TIME VDD ➤ out ➤ LVDS 100 VOD/Δ VOD out ➤ DC Input DIFFERENTIAL OUTPUT VOLTAGE SETUP 844256AM www.icst.com/products/hiperclocks.html 8 – POWER SUPPLY Float GND REV. A NOVEMBER 29, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS844256 FEMTOCLOCKS™CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER APPLICATION INFORMATION POWER SUPPLY FILTERING TECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS844256 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD, VDDA and VDDO should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 10Ω resistor along with a 10μF and a .01μF bypass capacitor should be connected to each VDDA pin. The 10Ω resistor can also be replaced by a ferrite bead. 3.3V VDD .01μF 10Ω V DDA .01μF 10μF FIGURE 1. POWER SUPPLY FILTERING CRYSTAL INPUT INTERFACE below were determined using an 18pF parallel resonant crystal and were chosen to minimize the ppm error. The ICS844256 has been characterized with 18pF parallel resonant crystals. The capacitor values shown in Figure 2 XTAL_IN C1 18p X1 18pF Parallel Crystal XTAL_OUT C2 22p Figure 2. CRYSTAL INPUt INTERFACE 844256AM www.icst.com/products/hiperclocks.html 9 REV. A NOVEMBER 29, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS844256 FEMTOCLOCKS™CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS INPUTS: OUTPUTS: LVCMOS CONTROL PINS: All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. LVDS All unused LVDS output pairs can be either left floating or terminated with 100Ω across. If they are left floating, we recommend that there is no trace attached. 3.3V, 2.5V LVDS DRIVER TERMINATION require a matched load termination of 100Ω across near the receiver input. A general LVDS interface is shown in Figure 3. In a 100Ω differential transmission line environment, LVDS drivers 2.5V or 3.3V VDD LVDS_Driv er + R1 100 - 100 Ohm Differential Transmission Line FIGURE 3. TYPICAL LVDS DRIVER TERMINATION 844256AM www.icst.com/products/hiperclocks.html 10 REV. A NOVEMBER 29, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS844256 FEMTOCLOCKS™CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER RELIABILITY INFORMATION TABLE 7A. θJAVS. AIR FLOW TABLE FOR 24 LEAD SOIC θJA by Velocity (Linear Feet per Minute) Multi-Layer PCB, JEDEC Standard Test Boards 0 200 50°C/W 43°C/W 500 38°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TABLE 7B. θJAVS. AIR FLOW TABLE FOR 24 LEAD TSSOP θJA by Velocity (Meters per Second) Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2.5 70°C/W 65°C/W 62°C/W TRANSISTOR COUNT The transistor count for ICS844256 is: 3887 844256AM www.icst.com/products/hiperclocks.html 11 REV. A NOVEMBER 29, 2005 PRELIMINARY Integrated Circuit Systems, Inc. PACKAGE OUTLINE - M SUFFIX FEMTOCLOCKS™CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER FOR 24 LEAD SOIC PACKAGE OUTLINE - G SUFFIX FOR Millimeters SYMBOL Minimum N 24 LEAD TSSOP TABLE 8B. PACKAGE DIMENSIONS TABLE 8A. PACKAGE DIMENSIONS SYMBOL Maximum Millimeters Minimum N 24 Maximum 24 A -- 2.65 A -- 1.20 A1 0.10 -- A1 0.05 0.15 A2 2.05 2.55 A2 0.80 1.05 B 0.33 0.51 b 0.19 0.30 C 0.18 0.32 c 0.09 0.20 D 15.20 15.85 D 7.70 7.90 E 7.40 7.60 E e H 1.27 BASIC E1 10.00 10.65 6.40 BASIC 4.30 e 4.50 0.65 BASIC h 0.25 0.75 L 0.45 0.75 L 0.40 1.27 α 0° 8° α 0° 8° aaa -- 0.10 Reference Document: JEDEC Publication 95, MS-013, MO-119 844256AM ICS844256 Reference Document: JEDEC Publication 95, MO-153 www.icst.com/products/hiperclocks.html 12 REV. A NOVEMBER 29, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS844256 FEMTOCLOCKS™CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER TABLE 9. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature ICS844256AM TBD 24 Lead SOIC tube 0°C to 70°C ICS844256AMT TB D 24 Lead SOIC 1000 tape & reel 0°C to 70°C ICS844256AMLF TBD 24 Lead "Lead-Free" SOIC tube 0°C to 70°C ICS844256AMLFT TBD 24 Lead "Lead-Free" SOIC 1000 tape & reel 0°C to 70°C ICS844256AG ICS844256AG 24 Lead TSSOP tube 0°C to 70°C ICS844256AGT ICS844256AG 24 Lead TSSOP 2500 tape & reel 0°C to 70°C ICS844256AGLF TBD 24 Lead "Lead-Free" TSSOP tube 0°C to 70°C ICS844256AGLFT TBD 24 Lead "Lead-Free" TSSOP 2500 tape & reel 0°C to 70°C NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant. The aforementioned trademarks, HiPerClockS and FEMTOCLOCKS are trademarks of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 844256AM www.icst.com/products/hiperclocks.html 13 REV. A NOVEMBER 29, 2005