Anpec APA2065JI-TRL Stereo 2.7-w audio power amplifier (with dc volume control) Datasheet

APA2065
Stereo 2.7-W Audio Power Amplifier (with DC_Volume Control)
Features
General Description
•
•
•
APA2065 is a monolithic integrated circuit, which
provides precise DC volume control, and a stereo
bridged audio power amplifiers capable of producing
2.7W(2.0W) into 3Ω with less than 10%(1.0%) THD+N.
The attenuator range of the volume control in APA2065
is from 20dB (DC_Vol=0V) to -80dB (DC_Vol=3.54V)
with 32 steps. The advantage of internal gain setting
can be less components and PCB area. Both of the
depop circuitry and the thermal shutdown protection
circuitry are integrated in APA2065, that reduce pops
and clicks noise during power up or shutdown mode
operation. It also improves the power off pop noise
and protects the chip from being destroyed by over
temperature and short current failure. To simplify the
audio system design, APA2065 combines a stereo
bridge-tied loads (BTL) mode for speaker drive and a
stereo single-end (SE) mode for headphone drive into
a single chip, where both modes are easily switched
by the SE/BTL input control pin signal.
Low Operating Current with 14mA
Improved Depop Circuitry to Eliminate
Turn-on and Turn-off Transients in Outputs
High PSRR
•
32 Steps Volume Adjustable by DC Voltage
with Hysteresis
•
2W per Channel Output Power into 4Ω Load
at 5V, BTL Mode
•
Two Output Modes Allowable with BTL
and SE Modes Selected by SE/BTL pin
•
Low Current Consumption in Shutdown Mode
(50µA)
•
•
•
•
Short Circuit Protection
Power Off Depop Circuit Integration
PDIP-16 & SOP-16 Packages Available
Lead Free Available (RoHS Compliant)
Applications
•
•
NoteBook PC
LCD Monitor or TV
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise
customers to obtain the latest version of relevant information to verify before placing orders.
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Aug., 2005
1
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APA2065
Ordering and Marking Information
Package Code
J : PDIP-16
K : SOP-16
Temp. Range
I : - 40 to 85 °C
Handling Code
TU : Tube
TR : Tape & Reel
TY : Tray
Lead Free Code
L : Lead Free Device
Blank : Original Device
APA2065
Lead Free Code
Handling Code
Temp. Range
Package Code
APA2065
XXXXX
APA2065 J :
XXXXX - Date Code
APA2065
XXXXX
APA2065 K :
XXXXX - Date Code
Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate
termination finish; which are fully compliant with RoHS and compatible with both SnPb and lead-free soldiering
operations. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J STD-020C
for MSL classification at lead-free peak reflow temperature.
Block Diagram
LOUT+
LIN-
RINLOUT-
Volume
Control
BYPASS
BYPASS
ROUT+
VOLUME
SE/BTL
SE/BTL
ROUTSHUTDOWN
Shutdown
ckt
VDD
POW ER and
Depop circuit
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Aug., 2005
2
GND
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APA2065
Absolute Maximum Ratings
(Over operating free-air temperature range unless otherwise noted.)
Symbol
VDD
VIN
TA
TJ
TSTG
TS
VESD
PD
Parameter
Supply Voltage Range
Input Voltage Range, SE/BTL,
SHUTDOWN
Operating Ambient Temperature Range
Maximum Junction Temperature
Rating
Unit
-0.3 to 6
V
-0.3 to VDD+0.3
V
°C
-40 to 85
Intermal Limited*
Storage Temperature Range
Soldering Temperature,10 seconds
Electrostatic Discharge
Power Dissipation
°C
1
-65 to +150
°C
260
-3000 to 3000*2
-200 to 200*3
°C
V
Intermal Limited
Note:
1.APA2065 integrated internal thermal shutdown protection when junction temperature ramp up to 150°C
2.Human body model: C=100pF, R=1500Ω, 3 positives pulse plus 3 negative pulses
3.Machine model: C=200pF, L=0.5µF, 3 positive pulses plus 3 negative pulses
Recommended Operating Conditions
Supply Voltage, VDD
High level threshold voltage, VIH
Low level threshold voltage, VIL
SHUTDOWN
Min.
Max.
Unit
4.5
2
5.5
V
V
4
SE/BTL
1.0
SHUTDOWN
3
SE/BTL
Common mode input voltage, VICM
VDD-1.0
V
V
Thermal Characteristics
Symbol
Parameter
R THJA
Thermal Resistance from Junction to Ambient in Free Air
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Aug., 2005
Value
Unit
PDIP-16
45
K/W
SOP-16
60
K/W
3
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APA2065
Electrical Characteristics
VDD=5V, -20°C<TA<85°C (unless otherwise noted)
Symbol
VDD
Parameter
Supply Voltage
IDD
Supply Current
ISD
Supply Current in Shutdown
Mode
IIH
IIL
VOS
Test Condition
SE/BTL=0V
SE/BTL=5V
APA2065
Min. Typ. Max.
4.5
5.5
14
25
8.0
15
SE/BTL=5V
SHUTDOWN=0V
High input Current
Low Input Current
Output Differential Voltage
Unit
V
mA
50
µA
900
900
5
nA
nA
mV
Operating Characteristics, BTL mode VDD=5V,TA=25°C,RL=4Ω, Gain=2V/V (unless otherwise noted)
Symbol
PO
Parameter
Maximum Output Power
THD+N Total Harmonic Distortion Plus
Noise
PSRR Power Ripple Rejection Ratio
Xtalk
S/N
Channel Separation
Signal to Noise Ratio
Test Condition
THD=10%, RL=3Ω, Fin=1kHz
THD=10%, RL=4Ω, Fin=1kHz
THD=10%, RL=8Ω, Fin=1kHz
THD=1%, RL=3Ω, Fin=1kHz
THD=1%, RL=4Ω, Fin=1kHz
THD=0.5%, RL=8Ω, Fin=1kHz
PO=1.5W, RL=4Ω, Fin=1kHz
PO=1W, RL=8Ω, Fin=1kHz
VIN=0.1Vrms, RL=8Ω, CB=1µF,
Fin=120Hz
CB=1µF, RL=8Ω, Fin=1kHz
PO=1.1W, RL=8Ω, A_wieght
APA2065
Unit
Min. Typ. Max.
2.7
2.3
1.5
W
2.0
1.9
1
1.1
0.05
%
0.07
60
dB
90
95
dB
dB
Operating Characteristics, SE mode VDD=5V,TA=25°C,RL=4Ω, Gain=1V/V (unless otherwise noted)
Symbol
PO
Parameter
Maximum Output Power
THD+N Total Harmonic Distortion Plus
Noise
PSRR Power Ripple Rejection Ratio
Xtalk
S/N
Channel Separation
Signal to Noise Ratio
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Aug., 2005
Test Condition
THD=10%, RL=8Ω, Fin=1kHz
THD=10%, RL=32Ω, Fin=1kHz
THD=1%, RL=8Ω, Fin=1kHz
THD=1%, RL=32Ω, Fin=1kHz
PO=250mW, RL=8Ω, Fin=1kHz
PO=75mW, RL=32Ω, Fin=1kHz
VIN=0.1Vrms, RL=8Ω, CB=1µF,
Fin=120Hz
CB=1µF, RL=32Ω, Fin=1kHz
PO=75mW, SE, RL=32Ω, A_wieght
4
APA2065
Unit
Min. Typ. Max.
400
110
mW
320
90
0.08
%
0.08
48
dB
100
100
dB
dB
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APA2065
Pin Description
ROUT+ 1
16 VDD
SHUTDOWN 2
15 ROUT-
GND 1
VOLUME 2
RIN- 3
14 SE/BTL
LOUT+ 3
GND 4
APA2065
PDIP-16
GND 5
VOLUME 6
13 GND
LIN- 4
12 GND
1 1 B Y PASS
V DD 5
10 LOUT-
LOUT+ 7
9
LIN- 8
16 GND
15 RIN14 SHUTDOWN
APA2065
SOP-16
13 ROUT+
12 VDD
LOUT- 6
11 ROUT-
BYPASS 7
10 SE/BTL
VDD
GND 8
9 GND
Pin Function Description
Pin Name
Config.
GND
Description
Ground connection, Connected to thermal pad.
VOLUME
LOUT+
LINLOUTBYPASS
I/P
O/P
I/P
O/P
SE/BTL
I/P
ROUT-
O/P
VDD
ROUT+
SHUTDOWN
RIN-
O/P
I/P
I/P
Input signal for internal volume gain setting.
Left channel positive output in BTL mode and SE mode.
Left channel input terminal
Left channel negative output in BTL mode and high impedance in SE mode.
Bias voltage generator
Output mode control input, high for SE output mode and low for BTL mode.
Right channel negative output in BTL mode and high impedance in SE
mode.
Supply voltage for internal circuit excepting power amplifier.
Right channel positive output in BTL mode and SE mode.
It will be into shutdown mode when pull low.
Right channel input terminal
Control Input Table
SE/BTL
X
L
H
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Aug., 2005
SHUTDOWN
L
H
H
5
Operating mode
Shutdown mode
BTL out
SE out
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APA2065
Typical Application Circuit
VDD
0.1µ F
VDD
GND
LOUT+
1µ F
L-Ch
input
100µ F
LIN-
220 µ F
1kΩ
1µ F
RIN-
R-Ch
input
VDD
4Ω
LOUT-
Volume
Control
2.2µ F
50kΩ
Control
Pin
Ring
SE/BTL
BYPASS
BYPASS
Tip
Sleeve
Headphone Jack
ROUT+
VOLUME
V DD
220µ F
1kΩ
100kΩ
SE/BTL
SE/BTL
4Ω
100kΩ
Shutdow n
Signal
SHUTDOWN
ROUTShutdown
ckt
Volume Control Table_BTL Mode
Supply Voltage Vdd=5V
Gain(dB)
20
18
16
14
12
10
8
6
4
2
0
-2
-4
-6
-8
High(V)
0.12
0.23
0.34
0.46
0.57
0.69
0.80
0.91
1.03
1.14
1.25
1.37
1.48
1.59
1.71
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Aug., 2005
Low(V)
0.00
0.17
0.28
0.39
0.51
0.62
0.73
0.84
0.96
1.07
1.18
1.29
1.41
1.52
1.63
Hysteresis(mV)
52
51
50
49
47
46
45
44
43
41
40
39
38
37
6
Recommended Voltage(V)
0
0.20
0.31
0.43
0.54
0.65
0.77
0.88
0.99
1.10
1.22
1.33
1.44
1.56
1.67
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APA2065
Volume Control Table_BTL Mode (Cont.)
Supply Voltage Vdd=5V
Gain(dB)
-10
-12
-14
-16
-18
-20
-22
-24
-26
-28
-30
-32
-34
-36
-38
-40
-80
High(V)
1.82
1.93
2.05
2.16
2.28
2.39
2.50
2.62
2.73
2.84
2.96
3.07
3.18
3.30
3.41
3.52
5.00
Low(V)
1.74
1.85
1.97
2.08
2.19
2.30
2.42
2.53
2.64
2.75
2.87
2.98
3.09
3.20
3.32
3.43
3.54
Hysteresis(mV)
35
34
33
32
30
29
28
27
26
24
23
22
21
20
18
17
16
Recommended Voltage(V)
1.78
1.89
2.01
2.12
2.23
2.35
2.46
2.57
2.69
2.80
2.91
3.02
3.14
3.25
3.36
3.48
5
Typical Characteristics
THD+N vs. Frequency
THD+N vs. Output Power
10
10
VDD=5V
RL=3Ω
AV=2
BTL
1
0.1
THD+N (%)
THD+N (%)
VDD=5V
RL=3Ω
Po=1.75W
BTL
AV=10 AV=2
1
0.1
f=20kHz
f=1kHz
AV=5
f=20Hz
0.01
20
100
1k
0.01
10m
20k
Rev. A.4 - Aug., 2005
1
2 3
Output Power (W)
Frequency (Hz)
Copyright  ANPEC Electronics Corp.
100m
7
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APA2065
Typical Characteristics
THD+N vs. Frequency
THD+N vs. Output Power
10
10
1
0.1
THD+N (%)
THD+N (%)
VDD=5V
RL=4Ω
Po=1.5W
BTL
AV=2
VDD=5V
RL=4Ω
AV=2
BTL
1
f=20kHz
0.1
f=1kHz
AV=5
f=20Hz
AV=10
0.01
20
5 0 100 200
500 1 k
2k
5k
0.01
100m
20k
200m
Frequency (W)
10
1
THD+N (%)
THD+N (%)
VDD=5V
RL=8Ω
Po=1.0W
BTL
AV=2
f=20kHz
0.1
AV=10
f=20Hz
0.01
10m
20k
Frequency (Hz)
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Aug., 2005
2
1
f=1kHz
1k
1
VDD=5V
RL=8Ω
AV=2
BTL
AV=5
100
3
THD+N vs. Output Power
10
0.01
20
2
Output Power (W)
THD+N vs. Frequency
0.1
500m 800m
100m
Output Power (W)
8
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APA2065
Typical Characteristics (Cont.)
THD+N vs. Output Power
THD+N vs. Frequency
10
VDD=5V
RL=8Ω
Po=250mW
SE
VDD=5V
RL=8Ω
AV=2
BTL
1
1
THD+N (%)
THD+N (%)
10
AV=1 AV=5
0.1
f=20kHz
0.1
f=20Hz
AV=2.5
0.01
20
100
f=1kHz
1k
0.01
10m
20k
100m
Frequency (Hz)
Output Power (W)
THD+N vs. Frequency
THD+N vs. Output Power
10
10
VDD=5V
RL=16Ω
AV=1
BTL
1
AV=2
THD+N (%)
THD+N (%)
VDD=5V
RL=16Ω
Po=100mW
SE
0.1
AV=1
1
f=20Hz
f=1kHz
5 0 100 2 0 0
500 1k
2k
5k
0.01
10m
20k
Frequency (Hz)
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Aug., 2005
f=20kHz
0.1
AV=2.5
0.01
20
500m
100m
300m
Output Power (W)
9
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APA2065
Typical Characteristics (Cont.)
THD+N vs. Output Power
THD+N vs. Frequency
10
10
5
1
THD+N (%)
THD+N (%)
VDD=5V
RL=32Ω
Po=75mW
SE
AV=2.5 AV=1
0.1
VDD=5V
RL=32Ω
AV=1
BTL
f=20kHz
1
f=20Hz
0.1
f=1kHz
AV=5
0.01
20
100
1k
0.01
10m
20k
Output Power (W)
THD+N vs. Frequency
THD+N vs. Output Swing
200m
10
VDD=5V
RL=10Ω
AV=1
SE
VDD=5V
RL=10Ω
Vo=1VRMS
SE
1
AV=2.5
THD+N (%)
THD+N (%)
100m
Frequency (Hz)
10
0.1
50m
AV=1
1
0.1
f=20kHz
f=1kHz
f=20Hz
AV=5
0.01
20
100
1k
0.01
100m
20k
Frequency (Hz)
Copyright  ANPEC Electronics Corp.
500m
1
2
3
Output Swing (VRMS)
10
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Rev. A.4 - Aug., 2005
Note:Dropout voltage definition:VIN-VOUT when VOUT is 2% below the value of VOUT for VIN= VOUT+1V
APA2065
Typical Characteristics (Cont.)
Crosstalk vs. Frequency
Crosstalk vs. Frequency
+0
+0
VDD=5V
RL=32Ω
-20 Po=75mW
AV=1
SE
Crosstalk (dB)
VDD=5V
RL=8Ω
-20 Po=1.0W
AV=2
BTL
Crosstalk (dB)
-40
-60
-80
R-ch to L-ch
-120
20
100
1k
-60
-80
R-ch to L-ch
L-ch to R-ch
L-ch to R-ch
-100
-40
-100
-120
20
20k
100
Frequency (Hz)
Noise Floor vs. Frequency
100u
100u
VDD=5V
RL=32Ω
50u AV=1
50u
SE
No Filter
Noise Floor (µVRMS)
Noise Floor (µVRMS)
20k
Frequency (Hz)
Noise Floor vs. Frequency
20u
A-Weight
10u
5u
VDD=5V
RL=8Ω
AV=2
BTL
2u
1u
20
1k
100
1k
Rev. A.4 - Aug., 2005
No Filter
10u
A-Weight
5u
2u
1u
20
20k
100
1k
20k
Frequency (Hz)
Frequency (Hz)
Copyright  ANPEC Electronics Corp.
20u
11
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APA2065
Typical Characteristics (Cont.)
Noise Floor vs. Frequency
Power Dissipation vs. Output Power
0.2
VDD=5V
RL=10KΩ
5 0 u AV=1
SE
0.18
Power Dissipation (W)
Noise Floor (µVRMS)
100u
No Filter
20u
10u
A-Weight
5u
2u
0.16
0.14
RL=8Ω
0.12
0.1
RL=16Ω
0.08
0.06
RL=32Ω
0.04
VDD=5V
AV=1
SE
0.02
1u
20
0
100
1k
20k
0
Frequency (Hz)
Output Power (W)
Power Dissipation vs. Output Power
Supply Current vs. Supply Voltage
20
1.8
1.6
17.5
RL=3Ω
1.4
Suuply Current (mA)
Power Dissipation (W)
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4
1.2
RL=4Ω
1
0.8
0.6
RL=8Ω
0.4
VDD=5V
AV=2
BTL
0.2
15
BTL
12.5
10
SE
7.5
5
2.5
No Load
0
0
0.5
1
1.5
2
2.5
1
Output Power (W)
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Aug., 2005
1.5
2
2.5
3
3.5
4
4.5
5 5.5
Supply Voltage (V)
12
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APA2065
Typical Characteristics (Cont.)
Output Power vs. Supply Voltage
1.8
Output Power (W)
1.6
160
RL=8Ω
AV=2
BTL
140
Output Power (mW)
2.0
Output Power vs. Supply Voltage
1.4
THD+N=10%
1.2
1.0
0.8
THD+N=1%
0.6
RL=32Ω
AV=1
SE
120
100
THD+N=10%
80
60
THD+N=1%
40
0.4
20
0.2
0
0
2.5
Output Power (W)
2.5
3.5
4
4.5
5
2.5
5.5
3.5
4
4.5
5
5.5
Supply Voltage (V)
Output Power vs. Load Resistance
Output Power vs. Load Resistance
0.7
VDD=5V
AV=2
BTL
0.6
2
1.5
1
THD+N=10%
0.5
3
Supply Voltage (V)
Output Power (W)
3
3
0.5
0.4
0.3
0.2
0.1
THD+N=1%
0
VDD=5V
AV=1
SE
THD+N=10%
THD+N=1%
0
4 8 12 16 20 24 28 32 36 40 44 48 52 56 60 64
4 8 12 16 20 24 28 32 36 40 44 48 52 56 6064
Load Resistance (Ω)
Load Resistance (Ω)
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Aug., 2005
13
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APA2065
Typical Characteristics (Cont.)
Close Loop Response
Close Loop Response
+12
+6
+4
Loop Gain (dB)
Loop Gain (dB)
VDD=5V
RL=8Ω
+10 AV=2
BTL
CO=330µF
+8
+6
AV=2
AV=5
AV=10
+4
+2
-0
20
VDD=5V
RL=32Ω
AV=1
SE
CO=330µF
+2
+0
AV=1
AV=2.5
AV=5
-2
-4
100
1k
-6
20
20k
Frequency (Hz)
100
1k
20k
Frequency (Hz)
PSRR vs. Frequency
Ripple Rejection Ratio (dB)
+0
-20
TT
VDD=5V
Vin=100mVRMS
RL=8Ω
Cbypass=2.2µF
BTL
-40
SE
-60
-80
20
100
1k
20k
Frequency (Hz)
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Aug., 2005
14
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APA2065
Application Descriptions
BTL Operation
Four times the output power same conditions. A BTL
The APA2065 output stage (power amplifier) has two
pairs of operational amplifiers internally, allowed for
different amplifier configurations.
configuration, such as the one used in APA2065, also
creates a second advantage over SE amplifiers. Since
the differential outputs, ROUT+, ROUT-, LOUT+, and
LOUT-, are biased at half-supply, no need DC voltage
exists across the load. This eliminates the need for an
output coupling capacitor which is required in a single
supply, SE configuration.
OUT+
Volume Control
amplifier output
signal
OP1
Single-Ended Operation
RL
Consider the single-supply SE configuration shown
Application Circuit. A coupling capacitor is required to
block the DC offset voltage from reaching the load.
These capacitors can be quite large (approximately
33µF to 1000µF) so they tend to be expensive, occupy
valuable PCB area, and have the additional drawback
of limiting low-frequency performance of the system
(refer to the Output Coupling Capacitor). The rules
described still hold with the addition of the following
relationship:
1
(1)
≤ 1 << 1
Cbypass x 125kΩ
RiCi
RLCC
OUT-
Vbias
Circuit
OP2
Figure 1: APA2065 internal configuration
(each channel)
The power amplifier’s OP1 gain is setting by internal
unity-gain and input audio signal is come from internal
volume control amplifier, while the second amplifier
OP2 is internally fixed in a unity-gain, inverting
configuration. Figure 1 shows that the output of OP1
is connected to the input to OP2, which results in the
output signals of with both amplifiers with identical in
magnitude, but out of phase 180°. Consequently, the
differential gain for each channel is 2 x (Gain of SE
mode).
Output SE/BTL Operation
The ability of the APA2065 to easily switch between
BTL and SE modes is one of its most important costs
saving features. This feature eliminates the requirement
for an additional headphone amplifier in applications
where internal stereo speakers are driven in BTL mode
but external headphone or speakers must be
accommodated.
By driving the load differentially through outputs OUT+
and OUT-, an amplifier configuration commonly referred
to as bridged mode is established. BTL mode operation
is different from the classical single-ended SE amplifier
configuration where one side of its load is connected
Internal to the APA2065, two separate amplifiers drive
OUT+ and OUT- (see Figure 1). The SE/BTL input
controls the operation of the follower amplifier that drives
LOUT- and ROUT-.
to ground.
A BTL amplifier design has a few distinct advantages
over the SE configuration, as it provides differential
drive to the load, thus doubling the output swing for a
specified supply voltage.
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Aug., 2005
• When SE/BTL is held low, the OP2 is turn on and
the APA2065 is in the BTL mode.
15
www.anpec.com.tw
APA2065
Application Descriptions (Cont.)
VOLUME input pin. The APA2065 volume control
consists of 32 steps that are individually selected by
a variable DC voltage level on the VOLUME control
pin. The range of the steps, controlled by the DC
voltage, are from 20dB to -80dB. Each gain step
corresponds to a specific input voltage range, as shown
in table. To minimize the effect of noise on the volume
control pin, which can affect the selected gain level,
hysteresis and clock delay are implemented. The
amount of hysteresis corresponds to half of the step
width, as shown in volume control graph.
Output SE/BTL Operation (Cont.)
• When SE/BTL is held high, the OP2 is in a high
output impedance state, which configures the
APA2065 as SE driver from OUT+. IDD is reduced by
approximately one-half in SE mode.
Control of the SE/BTL input can be a logic-level TTL
source or a resistor divider network or the stereo headphone jack with switch pin as shown in Application
Circuit.
1kΩ
Gan
i _BTLmode
VDD
100k Ω
APA2021volumecontrolcurve
Forward
Backward
20
Control
Pin
16
Ring
12
8
SE/BTL
4
0
Tip
-4
Sleeve
-8
Headphone Jack
-12
-16
Figure 2: SE/BTL input selection by phonejack plug
-20
-24
In Figure 2, input SE/BTL operates as follows :
-28
-32
When the phonejack plug is inserted, the 1kΩ resistor
is disconnected and the SE/BTL input is pulled high
and enables the SE mode. When the input goes high,
the OUT- amplifier is shutdown causing the speaker to
mute. The OUT+ amplifier then drives through the
output capacitor (CC) into the headphone jack. When
there is no headphone plugged into the system, the
contact pin of the headphone jack is connected from
-36
-40
-44
0
0.6
0.8
1
1.2
1.4
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6 3.8
(V)
For highest accuracy, the voltage shown in the
‘recommended voltage’column of the table is used
to select a desired gain. This recommended voltage
is exactly halfway between the two nearest transitions.
The gain levels are 2dB/step from 20dB to -40dB in
100kΩ and 1kΩ.
BTL mode, and the last step at -80dB as mute mode.
Resistor 1kΩ then pulls low the SE/BTL pin, enabling
the BTL function.
Input Resistance, Ri
The gain for each audio input of the APA2065 is set by
the internal resistors (Ri and Rf) of volume control
amplifier in inverting configuration.
Volume Control Function
APA2065 has an internal stereo volume control whose
setting is a function of the DC voltage applied to the
Rev. A.4 - Aug., 2005
0.4
Figure 3: Gain setting vs VOLUME pin voltage
the signalpin, the voltage divider set up by resistors
Copyright  ANPEC Electronics Corp.
0.2
16
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APA2065
Application Descriptions (Cont.)
Input Resistance, Ri (Cont.)
RF
SE Gain = AV = Ri
R
F
BTL Gain = -2 x
Ri
The value of Ci is important to consider as it directly
affects the low frequency performance of the circuit.
Consider the example where Ri is 10kΩ and the
specification calls for a flat bass response down to
100Hz. Equation is reconfigured as follow :
(2)
(3)
BTL mode operation brings the factor of 2 in the gain
equation due to the inverting amplifier mirroring the
voltage swing across the load. For the varying gain
setting, APA2065 generates each input resistance
on figure 4. The input resistance will affect the low
frequency performance of audio signal. The minmum
input resistance is 10kΩ when gain setting is 20dB
and the resistance will ramp up when close loop gain
below 20dB. The input resistance has wide variation
(+/-10%) caused by process variation.
Ci=
(5)
Consider to input resistance variation, the Ci is 0.16µF
so one would likely choose a value in the range
of 0.22µF to 1.0µF.
A further consideration for this capacitor is the leakage
path from the input source through the input network
(Ri+Rf, Ci) to the load. This leakage current creates a
DC offset voltage at the input to the amplifier that
reduces useful headroom, especially in high gain
applications. For this reason a low-leakage tantalum
or ceramic capacitor is the best choice. When polarized
capacitors are used, the positive side of the capacitor
should face the amplifier input in most applications as
the DC level there is held at VDD/2, which is likely higher
that the source DC level. Please note that it is important
to confirm the capacitor polarity in the application.
Ri vs Gain(BTL)
Ri(kΩ)
120
1
2πx10kΩxf C
100
80
60
40
20
Effective Bypass Capacitor, Cbypass
0
-40
-30
-20
-10
0
10
As other power amplifiers, proper supply bypassing is
critical for low noise performance and high power
supply rejection.
20
Gain(dB)
Figure 4: Input resistance vs Gain setting
The capacitors located on both the bypass and power
supply pins should be as close to the device as
possible. The effect of a larger bypass capacitor will
improve PSRR due to increased supply stability.
Typical applications employ a 5V regulator with 1.0µF
and a 0.1µF bypass capacitor as supply filtering. This
does not eliminate the need for bypassing the supply
nodes of the APA2065. The selection of bypass
capacitors, especially Cbypass, is thus dependent
upon desired PSRR requirements, click and pop
performance.
Input Capacitor, Ci
In the typical application an input capacitor, Ci, is
required to allow the amplifier to bias the input signal to
the proper DC level for optimum operation. In this case,
Ci and the minimum input impedance Ri (10kΩ) form a
high-pass filter with the corner frequency determined in
the follow equation:
FC(highpass)=
1
2πx10kΩxCi
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Aug., 2005
(4)
17
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APA2065
Application Descriptions (Cont.)
for power amplifier only and VDD is used for volume
control amplifier and internal circuit excepting power
amplifier. The APA2065 is a high-performance
CMOS audio amplifier that requires adequate power
supply decoupling to ensure the output total harmonic
distortion (THD) is as low as possible. Power supply
decoupling also prevents the oscillations causing by
long lead length between the amplifier and the speaker.
The optimum decoupling is achieved by using two
different type capacitors that target on different type
of noise on the power supply leads.
Effective Bypass Capacitor, Cbypass (Cont.)
To avoid start-up pop noise occurred, the bypass
voltage should rise slower than the input bias voltage
and the relationship shown in equation (6) should be
maintained.
1
1
<<
(6)
Cbypass x 125kΩ
100kΩ x Ci
The bypass capacitor is fed thru from a 125kΩ resistor
inside the amplifier and the 100kΩ is maximum input
resistance of (Ri+ Rf). Bypass capacitor, Cb, values of
3.3µF to 10µF ceramic or tantalum low-ESR capacitors
are recommended for the best THD and noise
performance.
For higher frequency transients, spikes, or digital hash
on the line, a good low equivalent-series-resistance
(ESR) ceramic capacitor, typically 0.1µF placed as
close as possible to the device VDD lead works best.
For filtering lower-frequency noise signals, a large
aluminum electrolytic capacitor of 10µF or greater
placed near the audio power amplifier is recommended.
The bypass capacitance also effects to the start up
time. It is determined in the following equation:
Tstart up = 5 x (Cbypass x 125KΩ)
(7)
Output Coupling Capacitor, Cc
Optimizing Depop Circuitry
In the typical single-supply SE configuration, an output
coupling capacitor (Cc) is required to block the DC
bias at the output of the amplifier thus preventing DC
currents in the load. As with the input coupling capacitor,
the output coupling capacitor and impedance of the
load form a high-pass filter governed by equation.
FC(highpass)=
1
2πRLCC
Circuitry has been included in the APA2065 to minimize
the amount of popping noise at power-up and when
coming out of shutdown mode. Popping occurs
whenever a voltage step is applied to the speaker. In
order to eliminate clicks and pops, all capacitors must
be fully discharged before turn-on. Rapid on/off
switching of the device or the shutdown function will
cause the click and pop circuitry.
(8)
For example, a 330µF capacitor with an 8Ω speaker
The value of Ci will also affect turn-on pops (Refer to
Effective Bypass Capacitance). The bypass voltage
ramp up should be slower than input bias voltage.
Although the bypass pin current source cannot be
modified, the size of Cbypass can be changed to alter
the device turn-on time and the amount of clicks and
pops. By increasing the value of Cbypass, turn-on pop
can be reduced. However, the tradeoff for using a larger
bypass capacitor is to increase the turn-on time for
this device. There is a linear relationship between the
would attenuate low frequencies below 60.6Hz.The
main disadvantage, from a performance standpoint, is
the load impedance is typically small, which drives
the low-frequency corner higher degrading the bass
response. Large values of CC are required to pass low
frequencies into the load.
Power Supply Decoupling, Cs
The APA2065 provides two independent power inputs
for right channel and left channel used. PVDD is used
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Aug., 2005
18
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APA2065
Application Descriptions (Cont.)
Optimizing Depop Circuitry (Cont.)
volume control function abnormal when VOLUME
control signal with spike or noise. APA2065 changes
each step of volume gain after four clock cycles to
make sure control signal ready.
size of Cbypass and the turn-on time. In a SE
configuration, the output coupling capacitor, CC, is of
particular concern.
BTL Amplifier Efficiency
This capacitor discharges through the internal 10kΩ
resistors. Depending on the size of CC, the time
constant can be relatively large. To reduce transients
in SE mode, an external 1kΩ resistor can be placed in
parallel with the internal 10kΩ resistor. The tradeoff
for using this resistor is an increase in quiescent current.
In the most cases, choosing a small value of Ci in the
range of 0.33µF to 1µF, Cb being equal to 4.7µF and
an external 1kΩ resistor should be placed in parallel
with the internal 10kΩ resistor should produce a
virtually clickless and popless turn-on.
An easy-to-use equation to calculate efficiency starts
out as being equal to the ratio of power from the power
supply to the power delivered to the load.
The following equations are the basis for calculating
amplifier efficiency.
Efficiency =
PO = VORMS x VORMS = VPxVP
RL
2RL
VORMS =
VP
√2
(10)
PSUP = VDD x IDDAVG = VDD x 2VP
πRL
Shutdown Function
(11)
Efficiency of a BTL configuration :
In order to reduce power consumption while not in use,
the APA2065 contains a shutdown pin to externally
turn off the amplifier bias circuitry. This shutdown
feature turns the amplifier off when a logic low is placed
on the SHUTDOWN pin. The trigger point between a
logic high and logic low level is typically 2.0V. It is
best to switch between ground and the supply VDD
PO
VPxVP ) / (VDD x 2VP ) = πVP
=(
4VDD
PSUP
πRL
2RL
(12)
Note that the efficiency of the amplifier is quite low for
lower power levels and rises sharply as power to the
load is increased resulting in a nearly flat internal power
dissipation over the normal operating range. Note that
the internal dissipation at full output power is less than
in the half power range. Calculating the efficiency for a
specific system is the key to proper power supply
design. For a stereo 1W audio system with 8Ω loads
and a 5V supply, the maximum draw on the power
supply is almost 3W.
to provide maximum device performance.
By switching the SHUTDOWN pin to low, the amplifier
enters a low-current state, I DD<50µA. On normal
operating, SHUTDOWN pin pull to high level to keeping
the IC out of the shutdown mode. The SHUTDOWN
pin should be tied to a definite voltage to avoid unwanted
state changes.
A final point to remember about linear amplifiers (either
SE or BTL) is how to manipulate the terms in the
efficiency equation to utmost advantage when
possible. Note that in equation, V DD is in the
Clock Generator
APA2065 integrates a clock block 130kHz to avoid
Rev. A.4 - Aug., 2005
(9)
Where :
A high gain amplifier intensifies the problem as the
small delta in voltage is multiplied by the gain. So it is
advantageous to use low-gain configurations.
Copyright  ANPEC Electronics Corp.
PO
PSUP
19
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APA2065
Application Descriptions (Cont.)
assuming a 5V-power supply and an 8Ω load, must
not be greater than the power dissipation that results
from the equation15:
BTL Amplifier Efficiency (Cont.)
denominator. This indicates that as VDD goes down,
efficiency goes up. In other words, use the efficiency
analysis to choose the correct supply voltage and
speaker impedance for the application.
PD,MAX=
31.25
0.16
2.00
0.55
0.50
47.62
0.21
2.83
0.55
1.00
66.67
0.30
4.00
0.5
1.25
78.13
0.32
4.47
0.35
(15)
For DIP-16 package with thermal pad, the thermal
resistance (θJA) is equal to 45οC/W.
Po (W) Efficiency (%) IDD(A) VPP(V) PD (W)
0.25
TJ,MAX - TA
θJA
Since the maximum junction temperature (TJ,MAX) of
APA2065 is 150οC and the ambient temperature (TA)
is defined by the power system design, the maximum
power dissipation which the IC package is able to
handle can be obtained from equation15.
Once the power dissipation is greater than the
maximum limit (PD,MAX), either the supply voltage
(VDD) must be decreased, the load impedance (RL)
must be increased or the ambient temperature
should be reduced.
**High peak voltages cause the THD to increase.
Table 1. Efficiency Vs Output Power in 5-V/8Ω BTL
Systems
Power Dissipation
Whether the power amplifier is operated in BTL or SE
modes, power dissipation is a major concern. In
equation13 states the maximum power dissipation
point for a SE mode operating at a given supply
voltage and driving a specified load.
VDD2
(13)
SE mode : PD,MAX= 2
2π RL
In BTL mode operation, the output voltage swing is
doubled as in SE mode. Thus the maximum power
dissipation point for a BTL mode operating at the same
given conditions is 4 times as in SE mode.
BTL mode : PD,MAX=
4VDD2
2π2RL
(14)
Since the APA2065 is a dual channel power amplifier,
the maximum internal power dissipation is 2 times
that both of equations depending on the mode of
operation. Even with this substantial increase in power
dissipation, the APA2065 does not require extra
heatsink. The power dissipation from equation14,
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Aug., 2005
20
www.anpec.com.tw
APA2065
Packaging Information
PDIP-16 pin ( Reference JEDEC Registration MS-001)
D
E
c
E1
α
eB
s
Q1
A2
A
A1
A3
e
b2
Dim
A
A1
A2
A3
b
b2
b3
c
D
E
E1
e
eB
Q1
s
α
Millimeters
Min.
0.38
3.17
2.92
0.36
1.14
0.76
0.20
18.632
Inches
Max.
5.32
3.42
3.80
0.56
1.78
1.14
0.36
19.646
Min.
0.015
0.125
0.115
0.014
0.045
0.030
0.008
0.735
6.477
0.245
7.605BSC
6.223
8.492
1.397
0.58
3°
Max.
0.210
0.135
0.150
0.022
0.070
0.045
0.014
0.775
0.300BSC
2.54BSC
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Aug., 2005
b3
b
0.255
0.100BSC
9.506
1.651
0.84
8°
21
0.335
0.055
0.023
3°
0.375
0.065
0.033
8°
www.anpec.com.tw
APA2065
Package Information
SO – 300mil ( Reference JEDEC Registration MS-013)
D
N
H
GAUGE
PLANE
E
1 2 3
A
Millimeters
1
A1
B
e
L
Variations- D
Inches
Variations- D
Dim
Min.
Max.
Variations
Min.
Max.
Dim
Min.
Max.
Variations
Min.
Max.
A
2.35
2.65
SO-16
10.10
10.50
A
0.093
0.1043
SO-16
0.398
0.413
A1
0.10
0.30
SO-18
11.35
11.76
A1
0.004
0.0120
SO-18
0.447
0.463
B
0.33
0.51
SO-20
12.60
13
B
0.013
0.020
SO-20
0.496
0.512
D
See variations
SO-24
15.20
15.60
D
See variations
SO-24
0.599
0.614
E
7.40
SO-28
17.70
18.11
E
SO-28
0.697
0.713
SO-14
8.80
9.20
e
SO-14
0.347
0.362
e
7.60
1.27BSC
0.2914
0.2992
0.050BSC
H
10
10.65
H
0.394
0.419
L
0.40
1.27
L
0.016
0.050
N
See variations
N
See variations
0°
φ1
φ1
8°
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Aug., 2005
22
0°
8°
www.anpec.com.tw
APA2065
Physical Specifications
Terminal Material
Lead Solderability
Solder-Plated Copper (Solder Material : 90/10 or 63/37 SnPb), 100%Sn
Meets EIA Specification RSI86-91, ANSI/J-STD-002 Category 3.
Reflow Condition
(IR/Convection or VPR Reflow)
tp
TP
Critical Zone
T L to T P
Temperature
Ramp-up
TL
tL
Tsmax
Tsmin
Ramp-down
ts
Preheat
25
t 25 °C to Peak
Time
Classificatin Reflow Profiles
Profile Feature
Average ramp-up rate
(TL to TP)
Preheat
- Temperature Min (Tsmin)
- Temperature Max (Tsmax)
- Time (min to max) (ts)
Time maintained above:
- Temperature (T L)
- Time (tL)
Peak/Classificatioon Temperature (Tp)
Time within 5°C of actual
Peak Temperature (tp)
Ramp-down Rate
Sn-Pb Eutectic Assembly
Pb-Free Assembly
3°C/second max.
3°C/second max.
100°C
150°C
60-120 seconds
150°C
200°C
60-180 seconds
183°C
60-150 seconds
217°C
60-150 seconds
See table 1
See table 2
10-30 seconds
20-40 seconds
6°C/second max.
6°C/second max.
6 minutes max.
8 minutes max.
Time 25°C to Peak Temperature
Notes: All temperatures refer to topside of the package .Measured on the body surface.
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Aug., 2005
23
www.anpec.com.tw
APA2065
Classificatin Reflow Profiles(Cont.)
Table 1. SnPb Entectic Process – Package Peak Reflow Temperature s
Package Thickness
Volume mm 3
Volume mm 3
<350
≥350
<2.5 mm
240 +0/-5°C
225 +0/-5°C
≥2.5 mm
225 +0/-5°C
225 +0/-5°C
Table 2. Pb-free Process – Package Classification Reflow Temperatures
Package Thickness
Volume mm 3
Volume mm 3
Volume mm 3
<350
350-2000
>2000
<1.6 mm
260 +0°C*
260 +0°C*
260 +0°C*
1.6 mm – 2.5 mm
260 +0°C*
250 +0°C*
245 +0°C*
≥2.5 mm
250 +0°C*
245 +0°C*
245 +0°C*
*Tolerance: The device manufacturer/supplier shall assure process compatibility up to and
including the stated classification temperature (this means Peak reflow temperature +0°C.
For example 260°C+0°C) at the rated MSL level.
Reliability Test Program
Test item
SOLDERABILITY
HOLT
PCT
TST
ESD
Latch-Up
Method
MIL-STD-883D-2003
MIL-STD-883D-1005.7
JESD-22-B,A102
MIL-STD-883D-1011.9
MIL-STD-883D-3015.7
JESD 78
Description
245°C, 5 SEC
1000 Hrs Bias @125°C
168 Hrs, 100%RH, 121°C
-65°C~150°C, 200 Cycles
VHBM > 2KV, VMM > 200V
10ms, 1 tr > 100mA
Carrier Tape & Reel Dimensions
t
E
W
D
P
Po
P1
Bo
F
Ao
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Aug., 2005
D1
24
Ko
www.anpec.com.tw
APA2065
Carrier Tape & Reel Dimensions(Cont.)
T2
J
C
A
B
T1
Application
SOP- 16
A
B
C
J
330 ± 1
100 +2
13+ 0.5
2 ± 0.5
F
D
D1
Po
7.5± 0.1
1.5 +0.1
T1
T2
16.4 +0.3 2.5 ± 0.5
-0.2
P1
1.5+ 0.25 4.0 ± 0.1
Ao
W
P
E
16± 0.2
12± 0.1
1.75±0.1
Bo
Ko
t
2.0 ± 0.1 10.9 ± 0.1 10.8± 0. 1 3.0± 0.1 0.3±0.013
(mm)
Cover Tape Dimensions
Application
SOP- 16
Carrier Width
24
Cover Tape Width
21.3
Devices Per Reel
1000
Customer Service
Anpec Electronics Corp.
Head Office :
5F, No. 2 Li-Hsin Road, SBIP,
Hsin-Chu, Taiwan, R.O.C.
Tel : 886-3-5642000
Fax : 886-3-5642050
Taipei Branch :
7F, No. 137, Lane 235, Pac Chiao Rd.,
Hsin Tien City, Taipei Hsien, Taiwan, R. O. C.
Tel : 886-2-89191368
Fax : 886-2-89191369
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Aug., 2005
25
www.anpec.com.tw