E2B0026-27-Y2 ¡ Semiconductor MSM6779 ¡ Semiconductor This version: Nov. 1997 MSM6779 Previous version: Mar. 1996 160-DOT SEGMENT DRIVER (TCP) GENERAL DESCRIPTION The MSM6779 is a LCD dot matrix segment driver. Fabricated in CMOS technology, the device consists of 160-bit latches I and II, a 160-bit level shifter, and a 4-level driver. The MSM6779 latches the 4-bit parallel display data sent from a microcontroller or a LCD controller to generate a LCD driving signal. This MSM6779 has a power-save function that sets all the drivers except one to the low supply current status (IDD SBY). This driver's 3V-operation allows significant reduction in current consumption, suitable for battery-driving. The bias voltage to specify a drive level can be supplied externally. The MSM6779 can be used for various types of LCD panels. FEATURES • Logic supply voltage : 2.7 V to 5.5 V • LCD drive voltage : A wide range from 14 V to 28 V • Applicable LCD duty : 1/64 to 1/256 • The bias voltage can be supplied externally. • LCD outputs : 160 • A power-save function to reduce power consumption in a large-screen LCD panel. • A 4-bit parallel data transfer to reduces its transfer speed to 1/4 of conventional serial transfer, providing low power consumption. • Data transfer clock frequency : 6.5 MHz (VDD=4.5 V) 4.0 MHz (VDD=2.7 V) • 35mm-wide-film TCP Tin-plating User area : 8 mm 1/9 ¡ Semiconductor MSM6779 BLOCK DIAGRAM O1 O2 O3 V1L V3L V4L VEEL O158 O159 O160 V1R V3R V4R VEER 160-DOT 4-LEVEL DRIVER ´ VDD VEE 160-bit LEVEL SHIFTER VDD ´ DF DISPOFF VSS LOAD D0 D1 D2 D3 160-bit LATCH (II) DATA CONTROL 160-bit LATCH (I) (4X40) SHL CP EIO1 20-bit SHIFT REGISTER CONTROL CIRCUIT EIO2 VDD VSS 2/9 ¡ Semiconductor MSM6779 PIN CONFIGURATION (TOP VIEW) O160 O159 O158 V1R V3R V4R VEER VDDR SHL VSS EIO2 D0 D1 D2 D3 CP LOAD DF DISPOFF EIO1 VDDL VEEL V4L V3L V1L O3 O2 O1 Note: The drawing shown does not specify the exact outline of the TCP; it only specifies the pin layout. 3/9 ¡ Semiconductor MSM6779 ABSOLUTE MAXIMUM RATINGS Parameter Symbol Condition Rating Unit Supply Voltage (1) VDD Ta=25˚C –0.3 to 6.5 V Supply Voltage (2) VDD–VEE*1 Ta=25˚C 0 to 30 V VI Ta=25˚C –0.3 to VDD+0.3 V TSTG — –30 to +85 ˚C Input Voltage Storage Temperature *1 V1>V3>V4>VEE, VDD≥V1>V3≥VDD–10 V, VEE+10 V≥V4>VEE V1=V1L=V1R, V3=V3L=V3R, V4=V4L=V4R, VEE=VEEL=VEER RECOMMENDED OPERATING CONDITIONS Parameter Symbol Condition Range Unit Supply Voltage (1) VDD — 2.7 to 5.5 V Supply Voltage (2) VDD–VEE*1 — 14 to 28 V Top — –20 to +75 ˚C Operating Temperature *1 V1>V3>V4>VEE, VDD≥V1>V3≥VDD–7 V, VEE+7 V≥V4>VEE V1=V1L=V1R, V3=V3L=V3R, V4=V4L=V4R, VEE=VEEL=VEER Note: Unlike mold packages, TCP has a low light resistance. Therefore, they are protected from light. 4/9 ¡ Semiconductor MSM6779 ELECTRICAL CHARACTERISTICS DC Characteristics (VDD=2.7 V to 5.5 V, Ta=–20 to +75˚C) Symbol Condition Min. Typ. Max. Unit "H" level Input Voltage Parameter VIH —*1 0.8 VDD — — V "L" level Input Voltage VIL —*1 — — 0.2 VDD V "H" level Input Current IIH VI=VDD, VDD=5.5 V *1 — — 1 mA "L" level Input Current IIL VI=0 V, VDD=5.5 V *1 — — –1 mA "H" level output Voltage VOH IO=–0.2 mA, VDD=2.7 V *2 "L" level output Voltage VOL ON Resistance RON IO=0.2 mA, VDD=2.7 V *2 VDD–VEE=25 V, VDD–0.4 — — V — — 0.4 V — 1.5 3.0 kW — — 300 mA — — 1.5 mA — — 2.0 mA — — ±200 mA — 5 — pF VDD=2.7 V, Stand-by Current Consumption Current Consumption (1) IDD SBY IDD I VN–VO I=0.25 V *3 *4 fCP=4.0 MHz, VDD=3.0 V VDD–VEE=25 V, No load *5 fCP=4.0 MHz, VDD=3.0 V VDD–VEE=25 V, No load *6 Current Consumption (2) IEE fCP=4.0 MHz, VDD=3.0 V VDD–VEE=25 V, No load *7 Current Consumption (3) IV fCP=4.0 MHz, VDD=3.0 V VDD–VEE=25 V, No load *8 Input Capacitance CI f=1 MHz Applicable to LOAD, CP, D0~D3, EIO1, EIO2, SHL, DF, DISPOFF pins Applicable to EIO1, EIO2 pins VN=VDD–VEE, V4=14/16 (VDD–VEE), V3=2/16 (VDD–VEE), VDD=V1 Applicable to O1~O160 pins Display data 1010.....fDF = 45 Hz, Current from VDD to VSS when the display data is not fetching. *6 Display data 1010.....fDF = 45 Hz, Current from VDD to VSS when the display data is fetching. *7 Display data 1010.....fDF = 45 Hz, Current from VDD to VEE *8 Display data 1010.....fDF = 45 Hz, Current on V1, V3, and V4 pins. *1 *2 *3 *4 *5 V1=VIL=VIR, V3=V3L=V3R, V4=V4L=V4R, VEE=VEEL=VEER Note: The above values are quaranteed when TCP is protected from light. 5/9 ¡ Semiconductor MSM6779 Switching Characteristics (2.7£VDD<4.5 V, Ta=–20 to +75˚C) Symbol Condition Min. Typ. Max. Unit Clock Frequency Parameter fCP DUTY=50%, VDD=2.7 V — — 4.0 MHz Clock Pulse Width tW1 — 90 — — ns Load Pulse Width tW2 — 110 — — ns Clock Pulse Rise/Fall Time tr, tf — — — 20 ns Data Set-up Time tDSU — 80 — — ns Data Hold Time tDHD — 65 — — ns Clock Load Time 1 tCL1 — 0 — — ns Clock Load Time 2 tCL2 — 100 — — ns Load Clock Time 1 tLC1 — 100 — — ns Load Clock Time 2 tLC2 — 100 — — ns Propagation Delay Time tPHL — — 380 ns EIO1, EIO2 Set-up Time tESU CL=15 pF — 80 — — ns EIO1, EIO2 Hold Time tEHD — 80 — — ns Note: The above values are quaranteed when TCP is protected from light. tf tr tW1 CP tW1 0.8 VDD tW1 0.8 VDD 0.8 VDD 0.2 VDD tDSU 0.8 VDD 0.2 VDD tDHD 0.8 VDD D0~D3 0.2 VDD tLC2 tCL2 tCL1 tLC1 0.8 VDD LOAD 0.8 VDD 0.2 VDD 0.2 VDD tW2 tr tf 0.8 VDD CP 1 2 38 39 40 0.2VDD 41 0.2 VDD LOAD tPHL EIO1, EIO2 (Output) 0.2 VDD tESU EIO1, EIO2 (Input) 0.2 VDD tEHD 0.2 VDD 6/9 ¡ Semiconductor MSM6779 Switching Characteristics (4.5£VDD£5.5 V, Ta=–20 to +75˚C) Symbol Condition Min. Typ. Max. Unit Clock Frequency Parameter fCP DUTY=50%, VDD=4.5 V — — 6.5 MHz Clock Pulse Width tW1 — 56 — — ns Load Pulse Width tW2 — 70 — — ns Clock Pulse Rise/Fall Time tr, tf — — — 20 ns Data Set-up Time tDSU — 50 — — ns Data Hold Time tDHD — 40 — — ns Clock Load Time 1 tCL1 — 0 — — ns Clock Load Time 2 tCL2 — 65 — — ns Load Clock Time 1 tLC1 — 65 — — ns Load Clock Time 2 tLC2 — 65 — — ns Propagation Delay Time tPHL — — 236 ns EIO1, EIO2 Set-up Time tESU CL=15 pF — 50 — — ns EIO1, EIO2 Hold Time tEHD — 50 — — ns Note: The above values are quaranteed when TCP is protected from light. tf tr tW1 CP tW1 0.8 VDD tW1 0.8 VDD 0.8 VDD 0.2 VDD tDSU 0.8 VDD 0.2 VDD tDHD 0.8 VDD D0~D3 0.2 VDD tLC2 tCL2 tCL1 tLC1 0.8 VDD LOAD 0.8 VDD 0.2 VDD 0.2 VDD tW2 tr tf 0.8 VDD CP 1 2 38 39 40 0.2 VDD 41 0.2 VDD LOAD tPHL EIO1, EIO2 (Output) 0.2 VDD tESU EIO1, EIO2 (Input) 0.2 VDD tEHD 0.2 VDD 7/9 ¡ Semiconductor MSM6779 FUNCTIONAL DESCRIPTION Pin Descriptions VDD, VSS Power supply for the device. VDD is set to 2.7 V to 5.5 V. VSS is set to 0 V. V1L, V1R, V3L, V3R, V4L, V4R, VEEL, VEER Bias power supply for the LCD drive voltages. Power supply should be VDD≥V1>V3>V4>VEE. DISPOFF Input for controlling the output level of O1 to O160. The V1 level is output from O1 to O160 pins during "L" level input. Refer to Truth Table. DF Input for LCD drive wave form AC synchronization. O1~O160 LCD drive outputs that correspond to each bit of the latch (II). Depending on the combination of the contents of the latch (display data) and DF signal, one of 4 levels (V1, V3, V4, VEE) is output. Refer to Truth Table. CP Clock pulse input for display data reading. Data is taken into the latch (I) at the falling edge of the clock pulse. Use an even number for the clock number per line (the number of the clock pulses during the period from Load input to the next Load input). EIO1, EIO2 Chip Select Signal Input/Output. Input/Output are controlled by the SHL input. If the SHL input at "L"level,EIO1 is output and EIO2 is input. If the SHL input is at "H" level,EIO1 is input and EIO2 is output. If the SHL is at "L" level, the first EIO2 is fixed to "L"level,and the following EIO2 is connected to the preceding EIO1. If the SHL is at "H"level,the first EIO1 is fixed to "L" level, and the following EIO1 is connected to the preceding EIO2 as shown below. When SHL is at "L" level Start data O160 EIO2 End data O1 EIO1 EIO2 EIO1 EIO2 When SHL is at "H" level End data Start data O160 EIO1 EIO2 EIO1 EIO2 O1 EIO1 8/9 ¡ Semiconductor MSM6779 D0, D1, D2, D3 These are display data inputs that input data with clock synchronization. The table below shows the relationship between the LCD output for the display data and DFs and the LCD. Display Data DF LCD drive output LCD L L Non-selection level (V3) OFF H L Selection level (V1) ON L H Non-selection level (V4) OFF H H Selection level (VEE) ON LOAD This is an input to simultaneously output the display data of one line stored in the latch (I). At the falling edge, the data in the latch (I) is transferred to the latch (II) end is output. SHL Input to select for display data reading direction. Input of "L" level at Vss level fetches data in the direction from O160 to O1 sequentially, while input of "H" level at VDD fetches data in the direction from O1 to O160. The table below shows the relationship between read data and driver outputs (O1 to O160). SHL L H EIO1 EIO2 Outputs Inputs Inputs Outputs Numbers of the clock pulse Data input 40 clocks 39 clocks 38 clocks ... 3 clocks 2 clocks ... D0 O1 O5 O9 O153 O149 ... D1 O2 O6 O10 O154 O150 1 clocks O157 O158 D2 O3 O7 O11 ... O151 O155 O159 D3 O4 O8 O12 ... O152 O156 O160 D0 O160 O156 O152 ... O12 O8 O4 D1 O159 O155 O151 ... O11 O7 O3 D2 O158 O154 O150 ... O10 O6 O2 O149 ... O9 O5 O1 D3 O157 O153 TRUTH TABLE Display Data DISPOFF Driver output (01~0160) L L H V3 L H H V1 H L H V4 H H H VEE X X L V1 DF X : don't care NOTES ON USAGE (when turning the power ON or OFF) If a high voltage is applied to a LCD drive system while the logic supply is floating, over-current may destroy the device, because the voltage over the LCD drive system is high. Follow the sequence below when turning the power ON or OFF. Power ON : Logic system ON Æ LCD drive system ON, or both ON Power OFF : LCD drive system OFF Æ logic system OFF, or both OFF 9/9