Keysight M3102A PXIe Digitizers with Optional Real-Time Sequencing and FPGA Programming 500 MSa/s, 14 Bits, 2/4 Channels Data Sheet 02 | Keysight | M3102A PXIe Digitizer with Optional Real-Time Sequencing and FPGA Programming - Data Sheet Improve Your Measurement Fidelity, Signal Integrity and Measurement Throughput The M3102A are high-performance, high-bandwidth digitizers with an advanced data acquisition system (DAQ). Performance meets simplicity thanks to easy-to-use programming libraries, real-time sequencing technology (Hard Virtual Instrumentation or HVI), and graphical FPGA programming technology. Features 500 MSa/s simultaneous sampling, 14 bits, 2/4 channels, 200 MHz BW Advanced data acquisition system (DAQ) –– Flexible triggering (HW trigger, HVI trigger, SW trigger) –– Programmable cycles and data bursts to avoid PC saturation Optional HW programming for high-performance applications –– Real-time sequencing (HVI technology) –– FPGA programming –– Xilinx Kintex-7, 325T or 410T FPGA Up to 2 GB of onboard RAM (~ 1 Gsamples) Mechanical/interface –– 1 slot 3U (PXIe) –– Up to 200 MB/s transfer BW with P2P capabilities –– Independent DMA channels for fast and efficient data transfer Applications General purpose digitizer BB electronics designs and manufacturing in wireless devices R&D/scientific research equipment Aerospace & defense (A/D), angle of arrival (AoA) 03 | Keysight | M3102A PXIe Digitizer with Optional Real-Time Sequencing and FPGA Programming - Data Sheet Programming Technology and Software Tools Software programming –– Easy-to-use native programming libraries for most common languages: C, C++, Visual Studio, LabVIEW, MATLAB, Python, and more Hardware programming (optional) –– Real-time sequencing ((Hard Virtual Instrumentation or HVI technology)) –– Graphical flowchart-style M3601A design environment (-HV1 option required on HW) –– Ultra-fast, fully-parallelized hard real-time execution –– Ultra-fast, time-deterministic decision-making –– Off-the-shelf inter-module synchronization & data exchange –– FPGA programming –– Graphical M3602A FPGA design environment (-FP1 option required on HW) –– No FPGA know-how required –– Include high-level to low-level design elements: off-the-shelf DSP blocks, MATLAB/Simulink designs, Xilinx CORE Generator IP cores, Xilinx VIVADO/ISE projects, VHDL or Verilog code –– Ultra-fast, one-click compiling and on-the-fly programming No programming –– Ready-to-use SD1 SPF (software front panels) PXIe Arbitrary Waveform Generators, Digitizers and Combination Modules Outputs (AWGs) Inputs (Digitizers) Product Type Speed (MSa/s) Bits Ch BW (MHz) M3202A AWG 1000 14 2/4 400 M3201A AWG 500 16 2/4 200 M3102A Speed (MSa/s) Bits Ch BW (MHz) Digitizer 500 14 2/4 DC-200 M3100A Digitizer 100 14 4/8 DC-100 M3302A Combo 500 16 2 200 500 14 2 DC-200 M3300A Combo 500 16 2/4 200 100 14 4/8 DC-100 04 | Keysight | M3102A PXIe Digitizer with Optional Real-Time Sequencing and FPGA Programming - Data Sheet Functional Block Diagram Channel 1 Channel 1 output Channel x Input settings Full scale, Z, coupling (as available) Channel x output Prescaler ÷ Data acquisition (DAQx) Analog trigger Channel n Channel n output Figure 1. M3102A input functional block diagram, all channels have identical input structure Ordering Information 1 Product Description M3102A PXIe digitizer: 500 MSa/s, 14 Bits Options Description M3102A-CH2 / -CH4 Two channels 2 / four channels M3102A-CLV / -CLF Variable sampling clock / Fixed sampling clock, low jitter 2 M3102A-M01 / -M12 / -M20 Memory 16 MB, 8 MSamples 2 / 128 MB, 60 MSamples / 2 GB, 1 GSamples HW programming options Description M3102A-HVI Enabled HVI programming, requires an HVI design environment license (M3601A) M3102A-FP1 Enabled FPGA programming, requires -K32 or -K41 option and an FPGA design environment license (M3602A) M3102A-K32 / -K41 FPGA, Xilinx 7K325T / 7K410T, required for -FP1 option only (needs memory option -M20) Related software Description M3601A HVI design environment M3602A FPGA design environment 1. All options must be selected at time of purchase and are not upgradable 2. These options represent the standard configuration 05 | Keysight | M3102A PXIe Digitizer with Optional Real-Time Sequencing and FPGA Programming - Data Sheet Technical Specifications and Characteristics General characteristics M3102A-CH2 Parameter Min Typ Max M3102A-CH4 Min Typ Max Units Comments Inputs and outputs Channels Reference clock 1 Reference clock 2 2 4 Out 1 1 Out 1 1 In 1, 3 1 1 In/out Reconfigurable Triggers/markers 2, 3 8 8 In/out Reconfigurable Sampling rate 4 500 500 MSa/s Voltage resolution 14 14 Bits Triggers/markers Input channels overview Input frequency 0 200 0 200 MHz Real-time BW 200 200 MHz Time skew < 50 < 50 ps Input conditioning blocks 2 4 1 per channel Analog trigger processors 2 4 1 per channel Data acquisition blocks 2 4 1 per channel Between channels Built-in functionalities Onboard memory RAM memory 1. 2. 3. 4. 16 2048 At front panel At backplane Markers available from firmware version v3.0 or later 100 to 500 MSa/s (-CLV) option with variable sampling clock 16 2048 MBytes 06 | Keysight | M3102A PXIe Digitizer with Optional Real-Time Sequencing and FPGA Programming - Data Sheet I/O specifications Analog input characteristics Number of channels CH2 or CH4 Sampling rate 500 MSa/s option CLF (Table 4) variable rate option CLV (Table 4) Configurable inputs: impedance 50Ω or 1MΩ (HiZ) Configurable inputs: Coupling AC or DC Input voltage range (50Ω) 125 mVpp to 8Vpp (7 scales: 0.125, 0.25, 0,5, 1, 2, 4, 8 Vpp) Input voltage range (HiZ) 200 mVpp to 16Vpp (7 scales: 0.2, 0.4, 0.8, 2, 4, 8, 16 Vpp) Bandwidth limit filters 200 MHz Effective number of bits (ENOB)1 10.6 bits @ 95 MHz (typical) Noise floor1 -146 dBm/Hz SINAD1 66 dB @ 95 MHz (typical) Spurious free dynamic range (SFDR) + Total Harmonic Distorsion1 71 dBc @ 95 MHz (typical) 1. Measured at -1 DBFS input signal with 1 Vpp 50Ω M3102A Parameter Min Typ Max Units Comments 10 to 12.52 MHz Generated from the internal clock. User selectable Voltage 800 mVpp On a 50 Ω load Power 2 dBm On a 50 Ω load Source impedance 50 Ω AC coupled Reference clock output Frequency External I/O trigger/marker VIH 2 5 V VIL 0 0.8 V VOH 2.4 3.3 V On a high Z load VOL 0 0.25 V On a high Z load Input impedance 10 KΩ Source impedance TTL – Speed 100 MHz 2. CLF option is set to 10 MHz while with CLV option varies from 12.5 MHz to 10 MHz 07 | Keysight | M3102A PXIe Digitizer with Optional Real-Time Sequencing and FPGA Programming - Data Sheet Data acquisition blocks (DAQs) specifications M3102A-CH2 Parameter Min Typ Max M3102A-CH4 Min Typ Max Units Comments General specifications DAQs 2 Aggregated speed 1 per channel 1000 Acquisition burst multiple Acquisition RAM capacity 4 2000 5 15 Acquisition RAM capacity effic. Trigger 5 957M 15 957M 93.5 93.5 Selec. Selec. MSa/s For all onboard DAQs combined Samples Burst length must be a multiple of this value Samples Maximum depends on onboard RAM % Effic. = waveform size / waveform size in RAM Hardware trigger (analog channels, input trigger, backplane triggers), software trigger DAQ specifications Speed Resolution 500 500 14 14 MSa/s Per DAQ Bits Clock system specifications M3102A Parameter Min Max Units Comments Clock frequency (-CLF) 500 500 MHz Fixed clock Clock frequency (-CLV) 100 500 MHz Variable clock General specifications 08 | Keysight | M3102A PXIe Digitizer with Optional Real-Time Sequencing and FPGA Programming - Data Sheet System Specifications Environmental specifications (PXI Express) M3102A-CH2 Parameter Min Typ M3102A-CH4 Max Min Typ Max Units Comments Slot PXI Express (CompactPCI Express compatible) – Automatic gen negotiation, chassis dependent Lanes Automatic lane negotiation, chassis dependent System bus Slots 1 1 PCI Express type Gen 1 Gen 2 Gen 1 Gen 2 PCI Express link 1 4 1 4 Power dissipation 3.3V PXIe power supply 1.5 1.5 A ~5W 12V PXIe power supply 2 2 A ~ 24 W Environmental 1 Temperature range Operating Non-operating 0 to +55°C (10,000 feet) -40 to +70°C (up to 15,000 feet) Max operative altitude 4000 m (10,000 feet) Operating Humidity range (%RH) 10 to 95% at 40°C Non-operating Humidity range (%RH): 5 to 95 5 to 95% Calibration interval 1 year EMC Complies with European EMC Directive – IEC/EN 61326-1 – CISPR Pub 11 Group 1, class A This ISM device is in compliance with Canadian ICES-001 Cet appareil ISM est conforme à la norme NMB-001 du Canada. This ISM device is in compliance with Australian and New Zealand RCM This ISM device is in compliance with South Korea EMC KCC 1. Samples of this product have been type tested in accordance with the Keysight Environmental Test Manual and verified to be robust against the environmental stresses of Storage, Transportation and End-use; those stresses include but are not limited to temperature, humidity, shock, vibration, altitude and power line conditions. Test Methods are aligned with IEC 60068-2 and levels are similar to MIL-PRF-28800F Class 3. 09 | Keysight | M3102A PXIe Digitizer with Optional Real-Time Sequencing and FPGA Programming - Data Sheet Evolving Since 1939 Our unique combination of hardware, software, services, and people can help you reach your next breakthrough. We are unlocking the future of technology. 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DEKRA Certified ISO 9001:2015 Quality Management System This information is subject to change without notice. © Keysight Technologies, 2017 - 2018 Published in USA, February 20, 2018 5992-1805EN www.keysight.com