Micronas MAS3539F Mas 35x9f mpeg layer 2/3, aac audio decoder, g.729 annex a codec Datasheet

DATA SHEET
MICRONAS
June 30, 2004
6251-505-1DS
MAS 35x9F
MPEG Layer 2/3,
AAC Audio Decoder,
G.729 Annex A Codec
MICRONAS
MAS 35x9F
DATA SHEET
Contents
Page
Section
Title
5
6
6
7
1.
1.1.
1.2.
1.3.
Introduction
Features
Features of the MAS 35x9F Family
Application Overview
8
8
8
8
9
9
9
9
10
10
10
10
10
10
10
11
11
11
11
11
12
12
12
13
15
15
15
15
15
15
15
15
16
17
17
18
18
18
18
18
18
19
2.
2.1.
2.2.
2.3.
2.3.1.
2.3.2.
2.3.2.1.
2.3.2.2.
2.4.
2.4.1.
2.4.2.
2.4.2.1.
2.4.2.2.
2.4.2.3.
2.4.2.4.
2.4.3.
2.4.4.
2.5.
2.5.1.
2.5.2.
2.6.
2.6.1.
2.6.2.
2.6.3.
2.7.
2.8.
2.8.1.
2.8.2.
2.8.3.
2.8.4.
2.8.5.
2.8.6.
2.9.
2.10.
2.10.1.
2.10.2.
2.10.2.1.
2.10.2.2.
2.11.
2.11.1.
2.11.2.
2.11.2.1.
Functional Description
Overview
Architecture of the MAS 35x9F
DSP Core
RAM and Registers
Firmware and Software
Internal Program ROM and Firmware, MPEG-Decoding
Program Download Feature
Audio Codec
A/D Converter and Microphone Amplifier
Baseband Processing
Bass, Treble, and Loudness
Micronas Bass (MB)
Automatic Volume Control (AVC)
Balance and Volume
D/A Converters
Output Amplifiers
Clock Management
DSP Clock
Clock Output At CLKO
Power Supply Concept
Power Supply Regions
DC/DC Converters
Power Supply Configurations
Battery Voltage Supervision
Interfaces
I2C Control Interface
S/PDIF Input Interface
S/PDIF Output
Multiline Serial Audio Input (SDI, SDIB)
Multiline Serial Output (SDO)
Parallel Input/Output Interface (PIO)
MPEG Synchronization Output
MP3 Block Input Mode
Functional Description of the MP3 Block Input Mode
Setup
Resync Timeout
Detailed Setup
Default Operation
Stand-by Functions
Power-Up of the DC/DC Converters and Reset
Important Advice for Turn-on and Operating Voltage
2
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Micronas
MAS 35x9F
DATA SHEET
Contents, continued
Page
Section
Title
20
21
21
21
2.11.3.
2.11.4.
2.11.5.
2.11.6.
Reset Signal Specification
Control of the Signal Processing
Start-up of the Audio Codec
Power-Down
22
22
22
22
22
22
23
23
27
27
28
28
28
28
29
29
29
29
29
30
30
30
31
31
31
32
32
43
43
44
44
45
45
45
46
52
3.
3.1.
3.1.1.
3.1.2.
3.1.3.
3.2.
3.2.1.
3.2.2.
3.3.
3.3.1.
3.3.2.
3.3.2.1.
3.3.2.2.
3.3.2.3.
3.3.2.4.
3.3.2.5.
3.3.2.6.
3.3.2.7.
3.3.2.8.
3.3.2.9.
3.3.2.10.
3.3.2.11.
3.3.2.12.
3.3.3.
3.3.4.
3.3.4.1.
3.3.4.2.
3.3.5.
3.3.6.
3.3.7.
3.3.8.
3.4.
3.4.1.
3.4.2.
3.4.3.
3.4.4.
Controlling
I2C Interface
Device Address
I2C Registers and Subaddresses
Naming Convention
Direct Configuration Registers
Write Direct Configuration Registers
Read Direct Configuration Register
DSP Core
Access Protocol
Data Formats
Run and Freeze (Codes 0hex to 3hex)
Read Register (Code Ahex)
Write Register (Code Bhex)
Read Memory (Codes Chex and Dhex)
Short Read Memory (Codes C4hex and D4hex)
Write Memory (Codes Ehex and Fhex)
Short Write Memory (Codes E4hex and F4hex)
Clear SYNC Signal (Code 5hex)
Default Read
Fast Program Download (Code 6hex)
Serial Program Download
Read IC Version (Code 7hex)
List of DSP Registers
List of DSP Memory Cells
Application Selection and Application Running
Application Specific Control
Ancillary Data
Reading of the Memory Cells “Number of Bits in Ancillary Data” and “Ancillary Data”
DSP Volume Control
Explanation of the G.729A Data Format
Audio Codec Access Protocol
Write Codec Register
Read Codec Register
Codec Registers
Basic MB Configuration
Micronas
June 30, 2004; 6251-505-1DS
3
MAS 35x9F
DATA SHEET
Contents, continued
Page
Section
Title
54
54
57
60
60
60
60
60
60
60
61
61
61
61
61
61
61
61
62
62
63
64
65
65
67
71
72
73
74
76
77
77
79
4.
4.1.
4.2.
4.3.
4.3.1.
4.3.2.
4.3.3.
4.3.4.
4.3.5.
4.3.6.
4.3.6.1.
4.3.7.
4.3.8.
4.3.9.
4.3.10.
4.3.11.
4.3.12.
4.3.13.
4.3.14.
4.4.
4.5.
4.5.1.
4.6.
4.6.1.
4.6.1.1.
4.6.2.
4.6.2.1.
4.6.2.2.
4.6.2.3.
4.6.2.4.
4.6.2.5.
4.6.2.6.
4.6.2.7.
80
81
84
86
4.6.2.8.
4.6.3.
4.6.4.
4.6.5.
Specifications
Outline Dimensions
Pin Connections and Short Descriptions
Pin Descriptions
Power Supply Pins
Analog Reference Pins
DC/DC Converters and Battery Voltage Supervision
Oscillator Pins and Clocking
Control Lines
Parallel Interface Lines
PIO Handshake Lines
Serial Input Interface (SDI)
Serial Input Interface B (SDIB)
Serial Output Interface (SDO)
S/PDIF Input Interface
S/PDIF Output Interface
Analog Input Interfaces
Analog Output Interfaces
Miscellaneous
Pin Configuration
Internal Pin Circuits
Reset Pin Configuration for MAS 3529F and MAS 3539F
Electrical Characteristics
Absolute Maximum Ratings
Recommended Operating Conditions
Digital Characteristics
I2C Characteristics
Serial (I2S) Input Interface Characteristics (SDI, SDIB)
Serial Output Interface Characteristics (SDO)
S/PDIF Input Characteristics
S/PDIF Output Characteristics
PIO as Parallel Input Interface: DMA Mode
PIO as Parallel Input Interface:
Program Download Mode
PIO as Parallel Output Interface
Analog Characteristics
DC/DC Converter Characteristics
Typical Performance Characteristics
89
89
90
5.
5.1.
5.2.
Application
Typical Application in a Portable Player
Recommended DC/DC Converter Application Circuit
92
6.
Data Sheet History
4
June 30, 2004; 6251-505-1DS
Micronas
MAS 35x9F
DATA SHEET
MPEG Layer 2/3, AAC Audio Decoder,
G.729 Annex A Codec
Release Note: Revision bars indicate significant
changes to the previous edition. This data sheet
applies to the MAS 35x9F version B4.
1. Introduction
The MAS 35x9F is a single-chip, low-power MPEG
layer 2/3 and MPEG2-AAC audio stereo decoder. It
also contains the G.729 Annex A speech compression
and decompression technology for use in memorybased or broadcast applications. Additional functionality is achievable via download software (e.g., CELP
voice decoder, Micronas SC4 (ADPCM) encoder/
decoder).
The MAS 35x9F decoding block accepts compressed
digital data streams as serial bit streams or in parallel
format, and provides serial PCM and S/PDIF output of
decompressed audio. In addition to the signal processing function, the IC incorporates a high-performance
stereo D/A converter, headphone amplifiers, a stereo
A/D converter, a microphone amplifier, and two DC/DC
converters.
In MPEG 1 (ISO 11172-3), three hierarchical layers of
compression have been standardized. The most
sophisticated and complex, layer 3, allows compression rates of approximately 12:1 for mono and stereo
signals while still maintaining CD audio quality. Layer 2
(widely used, e.g., in DVD) achieves a compression of
8:1 without significant losses in audio quality.
The MAS 35x9F supports the “Advanced Audio Coding” (AAC) that is defined as a part of MPEG 2. AAC
provides compression rates up to 16:1. It defines several profiles for different applications. This IC decodes
the “low complexity profile” that is especially optimized
for portable applications.
The MAS 35x9F also implements a voice encoder and
decoder that is compliant to the ITU Standard G.729
Annex A.
SC4 is a proprietary Micronas speech codec technology that can be downloaded to the MAS 35x9F, to
allow recording and playing back speech at various
sampling rates.
Thus, the MAS 35x9F provides a true “all-in-one”
solution that is ideally suited for highly optimized memory-based portable music players with integrated
speech recording and playback function.
Micronas
June 30, 2004; 6251-505-1DS
5
MAS 35x9F
DATA SHEET
1.1. Features
Hardware Features
Firmware
– Two independent embedded DC/DC converters,
(e.g., for DSP and flash RAM supply)
– MPEG 1/2 layer 2 and layer 3 decoder
– Low DC/DC converter start-up voltage (0.9 V)
– Extension to MPEG 2 layer 3 for low sampling rates
(“MPEG 2.5”)
– DC converter efficiency up to 95%
– Battery voltage monitor
– Extraction of MPEG Ancillary Data
– MPEG 2 AAC decoder (low-complexity profile)
– Micronas G.729 Annex A speech compression and
decompression
– Low supply voltage down to 2.2 V
– Low power dissipation, e.g., 87 mW
(128kBit/s, 44.1 kHz, Headphone playback)
– High-performance RISC DSP core
– Master or slave clock operation
– On-chip crystal oscillator
– Adaptive bit rates (bit rate switching)
– Intelligent power management (processor clock is
dependent on sampling frequencies)
– Hardware power management and power-off functions
– Microphone amplifier
– SDMI-compliant security technology
– Stereo A/D converter for FM/AM-radio and speech
input
– Stereo channel mixer
– Bass, treble, and loudness function
– CD quality stereo D/A converter
– Micronas Bass (MB)
– Headphone amplifier
– Automatic Volume Control (AVC)
– Noise and power-optimized volume
Interfaces
– External clock or crystal frequency of 13...28 MHz
– Two serial asynchronous interfaces for bit streams
and uncompressed digital audio
– Standby current < 10 µA
– Parallel handshake bit stream input
– Serial audio output via I2S and related formats
– S/PDIF data input and output
– Controlling via I2C interface
1.2. Features of the MAS 35x9F Family
Feature
6
3509
3519
3529
3539
Layer 3 Decoder
X
X
X
X
G.729 Encoder/Decoder
X
X
AAC Decoder
X
June 30, 2004; 6251-505-1DS
3549
3559
X
X
X
Micronas
MAS 35x9F
DATA SHEET
1.3. Application Overview
The following block diagram shows an example application for the MAS 35x9F in a portable audio player
device. Besides a simple controller and the external
flash memories, all required components are integrated in the MAS 35x9F. The MAS 35x9F supports
both speech and radio quality audio encoding, as well
as compressed-audio decoding tasks.
Fig. 1–1 depicts a portable power-optimized audio
application. The two embedded DC/DC converters of
the MAS 35x9F generate optimum power supply voltages for the DSP core and also for state-of-the art
flash memories that typically require 2.7 to 3.3 V supply. The performance of the DC/DC converters
reaches efficiencies of up to 95%.
Portable Digital Music Player
MAS 35x9F
optional
line in
Audio
baseband
features
A/D
D/A
DSP Core
MP3
AAC
G.729
Headphone
amplifier
Optional
SC4
Downloads
Volume
Microphone
amplifier
optional
digital in
digital out
S/PDIF and serial
Battery
Voltage
Monitor
I2C
I2C Control
System clock
DC/DC1
e.g. 1.0 V e.g. 2.2 V
I 2C
Display
Keyboard
DC/DC2
e.g. 3.0 V
Flash RAM
Crystal
Osc./PLL
Parallel I/O Bus
S/PDIF
or
serial
Headphone
µC
PC Connector
Fig. 1–1: Example of an application for the MAS 35x9F in a portable audio player device
Micronas
June 30, 2004; 6251-505-1DS
7
MAS 35x9F
DATA SHEET
2. Functional Description
2.2. Architecture of the MAS 35x9F
2.1. Overview
The hardware of the MAS 35x9F consists of a highperformance RISC Digital Signal Processor (DSP),
and appropriate interfaces. A hardware overview of the
IC is shown in Fig. 2–1.
The MAS 35x9F is intended for use in portable consumer audio applications. It receives parallel or serial
data streams and decodes MPEG Layer 2 and 3
(including the low sampling frequency extensions) and
MPEG 2 AAC. A low bit-rate speech codec, compliant
to the ITU Standard G.729 Annex A, is integrated.
Additional downloadable software modules (SDMI,
other audio/speech encoders/decoders) are available
on request.
Mic. Input
(incl. Bias)
2.3. DSP Core
The internal processor is a dedicated DSP for
advanced audio applications.
Audio Codec
1
2
Line Input
2
A/D
MIX
Audio
Proc.
2
Audio
Output
D/A
DSP Core
S/PDIF Input 1
ALU
Serial
Audio
MAC
S/PDIF Input 2
(I2S, SDO)
Accumulators
Serial Audio
S/PDIF
Output
Input Select
(I S, SDI)
Serial Audio
(stream, SDIB)
V1
V2
Xtal
18.432 MHz
Volt.
Mon.
DC/DC 2 DC/DC 1
VBAT
ROM
D0
D1
Output Select
2
Registers
Control
DCCF
DCFR
DSP
Codec
2
I C
Interface
Div.
Parallel
I/O Bus
(PIO)
Div.
Osc.
PLL
Synth.
Synthesizer
Clock
I 2C
control
Scaler
÷2
CLKO
Fig. 2–1: The MAS 35x9F architecture
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Micronas
MAS 35x9F
DATA SHEET
2.3.1. RAM and Registers
selected, the Layer 2, Layer 3 or AAC bit stream is recognized and decoded automatically.
The DSP core has access to two RAM banks denoted
D0 and D1. All RAM addresses can be accessed in a
20-bit or a 16-bit mode via I2C bus. For fast access of
internal DSP states the processor core has an address
space of 256 data registers which also can be
accessed via I2C bus. For more details, please refer to
Section 3.3. on page 27.
2.3.2. Firmware and Software
2.3.2.1. Internal Program ROM and Firmware,
MPEG-Decoding
The firmware implemented in the program ROM of the
MAS 35x9F provides MPEG 1/2 Layer 2, MPEG 1/2/
2.5 Layer 3 and MPEG 2 AAC-decoding as well as a
G.729 encoder and decoder.
The DSP operating system starts the firmware in the
“Application Selection Mode”. By setting the appropriate bit in the Application Select memory cell (see
Table 3–8 on page 32), the MPEG audio decoder or
the G.729 Codec can be activated.
To add/remove MPEG layers while running in MPEG
decoding mode (e.g. Layer 2, Layer 3 (0x0c) to
Layer 2, Layer 3, AAC (0x1c)), the application selection has to be reset before writing the new value.
For general control purposes, the operation system
provides a set of I2C instructions that give access to
internal DSP registers and memory areas.
An auxiliary digital volume control and mixer matrix is
applied to the digital stereo audio data. This matrix is
capable of performing the balance control and a simple kind of stereo basewidth enhancement. All four
factors LL, LR, RL, and RR are adjustable, please
refer to Fig. 3–3 on page 44.
2.3.2.2. Program Download Feature
The standard functions of the MAS 35x9F can be
extended or substituted by downloading up to
4 kWords (1 Word = 20 bits) of program code and
additionally up to 4 kWords of coefficients into the
internal RAM.
The MPEG decoder provides an automatic standard
detection mode. If all MPEG audio decoders are
SDI
PIO
Encoder
LINE IN
MIC IN
MIX
A/D
Audio
Proc.
D/A
OUT
Fig. 2–2: Encoder signal flow
PIO
Decoder
DSP
Volume
Matrix
S/PDIF
SDO
SDIB
LINE IN
MIC IN
A/D
MIX
Audio
Proc.
D/A
OUT
Fig. 2–3: Decoder signal flow
Micronas
June 30, 2004; 6251-505-1DS
9
MAS 35x9F
DATA SHEET
2.4. Audio Codec
2.4.2.2. Micronas Bass (MB)
A sophisticated set of audio converters and sound features has been implemented to comply with various
kinds of operating environments that range up to highend equipment (see Fig. 2–4).
The Micronas Bass system (MB) was developed to
extend the frequency range of loudspeakers or headphones below the cutoff frequency of the speakers.
Apart from dynamically amplifying the low-frequency
bass signals, the MB exploits the psycho-acoustic phenomenon of the ‘missing fundamental’. Adding harmonics of the frequency components below the cutoff
frequency gives the impression of actually hearing the
low frequency fundamental, while at the same time
retaining the loudness of the original signal. Due to the
parametric implementation of the MB, it can be customized to create different bass effects and adapted to
various
loudspeaker
characteristics
(see
Section 3.4.4. and Table 3–16).
Mic-In
D
Line-In
A
D
DSP
Mono
A
Deemphasis
50µs / 75µs
Mic-Amplifier incl. Bias
Mixer
Q-peak
Mono/Stereo
Q-peak
2.4.2.3. Automatic Volume Control (AVC)
AVC
In a collection of tracks from different sources fairly
often the average volume level varies. Especially in a
noisy listening environment the user must adjust the
volume to comfortably enjoy listening. The Automatic
Volume Correction (AVC) solves this problem by
equalizing the volume level.
Bass/Treble
Headphone
Amplifier
Audio
Codec
Output
D
MB
Right invert
D
A
Loudness
Volume
Balance
A
Fig. 2–4: Signal flow block diagram of Audio Codec
2.4.1. A/D Converter and Microphone Amplifier
A pair of A/D converters is provided for recording or
loop-through purposes. In addition, a microphone
amplifier including voltage supply function for an electret type microphone has been integrated.
2.4.2. Baseband Processing
To prevent clipping, the AVC's gain decreases quickly
in dynamic boost conditions. To suppress oscillation
effects, the gain increases rather slowly for low level
inputs. The decay time is programmable by means of
the AVC register (see Table 3–16 on page 46).
For input levels of -18 dBr to 0 dBr, the AVC maintains
a fixed output level of -9 dBr. Fig. 2–5 shows the AVC
output level versus its input level. For volume and
baseband registers set to 0 dB, a level of 0 dBr corresponds to full scale input/output.
AVCon
−9
The several baseband functions are applied to the digital audio signal immediately before D/A conversion.
AVCoff
output level
dBr
−15
−21
2.4.2.1. Bass, Treble, and Loudness
Standard baseband functions such as bass, treble,
and loudness are provided (refer to Table 3–16 for
details).
−30
−24
−18
−12
−6
0
+6
input level
dBr
Fig. 2–5: Simplified AVC characteristics
2.4.2.4. Balance and Volume
To minimize quantization noise, the main volume control is automatically split into a digital and an analog
part. The volume range is −114...+12 dB with an additional mute position. A balance function is provided.
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Micronas
MAS 35x9F
DATA SHEET
2.4.3. D/A Converters
2.5.1. DSP Clock
One pair of Micronas’ unique multibit sigma-delta D/A
converters is used to convert the audio data with high
linearity and a superior S/N. In order to attenuate highfrequency noise caused by noise-shaping, internal
low-pass filters are included. They require additional
external capacitors between pins FILTx and OUTx
(see Section 5.1. on page 89).
The DSP clock has a separate divider. In order to
reduce the power consumption, it is set to the lowest
acceptable rate of the synthesizer clock which is capable to allow the processor core to perform all tasks.
2.4.4. Output Amplifiers
The integrated output amplifiers are capable of directly
driving stereo headphones or loudspeakers of 16 to
32 Ω impedance via 22 Ω series resistors. If more output power is required, the right output signal can be
inverted and a single loudspeaker can be connected
as a bridge between pins OUTL and OUTR. In this
case, the source should be set to mono for optimized
power.
DAC
OUTL
OUTR
If the DSP or audio codec functions are enabled
(bits[11] or [10] in the Control Register at I2C subaddress 6Ahex), the reference clock at pin CLKO is
derived from the synthesizer clock.
Dependent on the sample rate of the decoded signal a
scaler is applied which automatically divides the clockout by 1, 2, or 4, as shown in Table 2–1. An additional
division by 2 may be selected by setting bit[17] of the
OutClkConfig memory cell (see Table 3–8 on
page 32). The scaler can be disabled by setting bit[8]
of this cell.
The controlling at OutClkConfig is only possible as
long as the DSP is operational (bit[10] of the Control
Register). Settings remain valid if the DSP is disabled
by clearing bit[10].
MASF
DAC
2.5.2. Clock Output At CLKO
R ≥ 32 Ω
Table 2–1: Settings of bits[8] and [17] in OutClkConfig
and resulting CLKO output frequencies
Fig. 2–6: Bridge operation mode
Output Frequency at CLKO/MHz
2.5. Clock Management
The MAS 35x9F is driven by a single crystal-controlled
clock with a frequency of 18.432 MHz. It is possible to
drive the MAS 35x9F with other reference clocks. In
this case, the nominal crystal frequency must be written into memory location D0:348. The crystal clock
acts as a reference for the embedded synthesizer that
generates the internal clock.
For compressed audio data reception, the MAS 35x9F
may act either as the clock master (Demand Mode) or
as a slave (Broadcast Mode) as defined by bit[1] in
IOControlMain memory cell (see Table 3–8 on
page 32). In both modes, the output of the clock synthesizer depends on the sample rate of the decoded
data stream as shown in Table 2–1.
In the BROADCAST MODE (PLL on), the incoming
audio data controls the clock synthesizer via a PLL.
fs/kHz
Synth.
Scaler On
Scaler Plus
Clock bit[8]=0, bit[17]=0
Extra Division
bit[8]=1
bit[8]=0, bit[17]=1
48
24.576
24.576
44.1
22.5792
32
24.576
22.5792
768⋅fs
24.576
11.2896
384⋅fs
12.288
24
22.5792
16
24.576
6.144
11.2896
768⋅fs
12.288
5.6448
384⋅fs
6.144
12
22.5792
8
24.576
3.072
5.6448
768⋅fs
6.144
256⋅fs
512⋅fs
11.025
12.288
256⋅fs
512⋅fs
22.05
12.288
256⋅fs
512⋅fs
6.144
2.8224
384⋅fs
3.072
In the DEMAND MODE (PLL off) the MAS 35x9F acts
as the system master clock. The data transfer is triggered by a demand signal at pin EOD.
Micronas
June 30, 2004; 6251-505-1DS
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MAS 35x9F
DATA SHEET
2.6. Power Supply Concept
The MAS 35x9F was designed for minimal power dissipation. In order to optimize the battery management
in portable players, two DC/DC converters were implemented to supply the complete portable audio player
with regulated voltages.
2.6.1. Power Supply Regions
The MAS 35x9F has five power supply regions.
The VDD/VSS pin pair supplies all digital parts including the DSP core, the XVDD/XVSS pin pair is connected to the digital signal pin output buffers, the
AVDD0/AVSS0 supply is for the analog output amplifiers, AVDD1/AVSS1 for all other analog circuits like
clock oscillator, PLL circuits, system clock synthesizer
and A/D and D/A converters. The I2C interface has an
own supply region via pin I2CVDD. Connecting this to
the microcontroller supply assures that the I2C bus
always works as long as the microcontroller is alive so
that the operating modes can be selected.
Beside these regions, the DC/DC converters have
start-up circuits of their own which get their power via
pin VSENSx.
2.6.2. DC/DC Converters
The MAS 35x9F has two embedded high-performance
step-up DC/DC converters with synchronous rectifiers
to supply both the DSP core itself and external circuitry
such as a controller or flash memory at two different
voltage levels. An overview is given in Fig. 2–7 on
page 13.
The DC/DC converters are designed to generate an
output voltage between 2.0 V and 3.5 V which can be
programmed separately for each converter via the I2C
interface (see table 3.3). Both converters are of bootstrapped type allowing to start up from a voltage down
to 0.9 V for use with a single battery or NiCd/NiMH cell.
The default output voltages are 3.0 V. Both converters
are enabled with a high level at pin DCEN and
enabled/disabled by the I2C interface.
When the audio codec is enabled, the switching frequency of the converters is synchronised to the audio
codec clock to avoid interferences into the audio band.
The actual switching frequency can be selected via the
I2C-interface between 300 kHz and 580 kHz (for
details see DCFR Register in Table 3–3 on page 24).
In the PFM operation mode, the switching frequency is
controlled by the converters themselves. It will be just
high enough to service the output load, thus resulting
in the best possible efficiency at low current loads. The
PFM mode does not need a clock signal from the crystal oscillator. If both converters do not use the PWMmode, the crystal clock will be shut down as long it is
not needed by other internal blocks.
The synchronous rectifier bypasses the external
Schottky diode to reduce losses caused by the diode
forward voltage providing up to 5% efficiency improvement. By default, the P-channel synchronous rectifier
switch is turned on when the voltage at pin(s) DCSOn
exceeds the converter’s output voltage at pin(s)
VSENSn, and is turned off when the inductor current
drops below a threshold. If one or both converters are
disabled, the corresponding P-channel switch will be
turned on, connecting the battery voltage to the DC/
DC converters output voltage at pin VSENSn. However, it is possible to individually disable both synchronous rectifier switches by setting the corresponding
bits (bit[8] and [0] in DCCF-register).
If both DC/DC-converters are off, a high signal may be
applied at pin DCEN. This will start the converters in
their default mode (PWM with 3.0 V output voltage).
The PUP signal will change from low to high when
both converters have reached their nominal output
voltage and will return to low when both converters
output voltages have dropped 200 mV below their programmed output voltage. The signal at pin PUP can be
used to control the reset of an external microcontroller
(see Section 2.11.2. on page 18 for details on the startup procedure).
If only DC/DC-converter 1 is used, the output of the
unused converter 2 (VSENS2) must be connected to
the output of converter 1 (VSENS1) to make the PUP
signal work properly. Also, if a DC/DC-converter is not
used (no inductor connected), the pin DCSO must be
left vacant.
The MAS 35x9F DC/DC converters feature a constantfrequency, low noise pulse width modulation (PWM)
mode and a low quiescent current, pulse frequency
modulation (PFM) mode for improved efficiencies at
low current loads. Both modes – PWM or PFM – can
be selected independently for each converter via I2C
interface. The default mode is PWM.
In PWM mode the switching frequency of the powerMOSFET-switches is derived from the crystal oscillator. Switching harmonics generated by constant frequency operation are consistent and predictable.
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MAS 35x9F
DATA SHEET
2.6.3. Power Supply Configurations
If DC/DC converter 1 is used, it must supply the analog
circuits (pins AVDD0, AVDD1) of the MAS 35x9F.
One of the following supply configurations may be
used:
– Power-optimized solution (recommended operation). DC/DC 1 (e.g. 2.2 V) drives the MAS 35x9F
DSP and the audio circuitry, DC/DC 2 (e.g. 2.7 V)
supplies controller and flash (see Fig. 2–8 on
page 14)
If only one DC/DC converter is required, DC/DC1 must
be used. Pin DCSO2 must be left vacant, pin VSENS2
should be connected to pin VSENS1.
If the DC/DC converters are not used, pin DCEN must
be connected to VSS, DCSOx must be left vacant.
– Volume-optimized solution. DC/DC 1 (e.g. 2.7 V)
supplies controller, flash and MAS 35x9F audio
parts, DC/DC 2 generates e.g. 2.2 V for the
MAS 35x9F DSP (see Fig. 2–9 on page 14).
– Minimized external components. DC/DC 1 operates
on, e.g., 2.7 V and feeds all components, DC/DC 2
remains off (see Fig. 2–10 on page 14).
– External power supply. All components are powered
by an external source, no DC/DC converter is used
(see Fig. 2–11 on page 14).
battery
voltage
monitor
VBAT
I2CVDD
to I2C interface
output 1
DCCF (76hex)
15
supply
L1
DCSO2
8
22 µH
DC/DC
converter 2
DCSG2
D1
VSENS2
set voltage
+
−
voltage
monitor
PUP2
DCEN
S
system
or crystal
clock
frequency
divider
3
C1
330 µF
Start
+
PUP
Vin
−
R
+
−
factor
voltage
monitor
0
DCFR (77hex)
DC/DC
converter 1
DCCF (76hex)
7
0
VSS
Fig. 2–7: DC/DC converter overview. The DCEN input must be connected to pin I2CVDD via start-up push button.
Micronas
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13
MAS 35x9F
Flash
VSENS1
DATA SHEET
DC/DC 1
Flash
on
VSENS1
DC/DC1
on
e.g. 2.7 V
µC
I2CVDD
I2CVDD
µC
I 2C
XVDD
I 2C
XVDD
DSP
DSP
VDD
VSENS2
VDD
VSENS2
DC/DC 2
on
AVDD0/1
DC/DC2
off
Analog
Parts
AVDD0/1
Analog
Parts
e.g. 2.7 V
e.g. 2.2 V
Fig. 2–8: Solution 1: Power-optimized
Flash
µC
VSENS1
Fig. 2–10: Solution 3: Minimized components
DC/DC1
Flash
on
I2CVDD
XVDD
I2C
XVDD
DSP
VDD
VSENS2
DC/DC1
off
I2CVDD
µC
I2C
VSENS1
DSP
VDD
VSENS2
DC/DC2
on
DC/DC2
off
External
Supply
AVDD0/1
e.g. 2.7 V
e.g. 2.2 V
Analog
Parts
Fig. 2–9: Solution 2: Volume-optimized
14
AVDD0/1
e.g. 2.7 V
Analog
Parts
Fig. 2–11: Solution 4: External power supply
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MAS 35x9F
DATA SHEET
2.7. Battery Voltage Supervision
2.8.4. Multiline Serial Audio Input (SDI, SDIB)
Independent of the DC/DC converters, a battery voltage supervision circuit (at pin VBAT) is provided. It can
be programmed to supervise one or two battery cells.
The voltage is measured by subsequently setting a
series of voltage thresholds and checking the respective comparison result in register 77hex.
There are two multiline serial audio input interfaces
(SDI, SDIB) each consisting of the three pins SI(B)C,
SI(B)I, and SI(B)D. The standard firmware only supports SDIB for bit-stream signals, while PCM-inputs
should be routed to SDI.
2.8. Interfaces
The MAS 35x9F uses an I2C control interface, a serial
input interface for MPEG bit streams, and digital audio
output interfaces for the decoded audio data (I2S and
S/PDIF). S/PDIF input is available after Software
download. A parallel I/O interface (PIO) may be used
for fast data exchange.
2.8.1. I2C Control Interface
For controlling and program download purposes, a
standard I2C slave interface is implemented. A
detailed description of all functions can be found in
Section 3.
2.8.2. S/PDIF Input Interface
If the download software (refer to Download Software
Supplement I2SPDIF (6251-505-1PDS)) is used, the
interface acts as an I2S-type with SI(B)I as a wordstrobe for PCM data.
For the Demand Mode (see Section 2.5.), the signal
clock coming from the data source must be higher than
the nominal data transmission rate (e.g. 128 kbit/s).
Pin EOD is used to interrupt the data flow whenever
the input buffer of the MAS 35x9F is filled.
For controlling details, please refer to Table 3–8 on
page 32.
2.8.5. Multiline Serial Output (SDO)
The S/PDIF interface receives a one-wire serial bus
signal. In addition to the signal input pin SPDI1/SPDI2,
a reference pin SPDIR is provided to support balanced
signal sources or twisted pair transmission lines.
The synchronization time on the input signal is
< 50 ms.
S/PDIF input is not supported for MPEG 1/2 Layer 2/3
and MPEG 2 AAC.
Micronas has developed a download software for flexible usage of the S/PDIF I/O and SDI/SDO interfaces. It
is described in Download Software Supplement
I2SPDIF (6251-505-1PDS).
2.8.3. S/PDIF Output
The S/PDIF output of the baseband audio signals is
implemented at pin SPDO since version B4.
The channel status bits can be set as described in
Table 3–8.
Micronas
The interfaces can be configured as continuous bitstream or word-oriented inputs. For the MPEG bit
streams, the word strobe pin SIBI must always be connected to VSS; bits must be sent MSB first as created
by the encoder.
The serial audio output interface of the MAS 35x9F is
a standard I2S-like interface consisting of the data
lines SOD, the word strobe SOI and the clock signal
SOC. It is possible to choose between two standard
interface configurations (16-bit data words with word
strobe time offset or 32-bit data words with inverted
SOI signal).
If the serial output generates 32 bits per audio sample,
only the first 20 bits will carry valid audio data. The
12 trailing bits are set to zero by default.
2.8.6. Parallel Input/Output Interface (PIO)
The parallel interface of the MAS 35x9F consists of the
8 data lines PI12...PI19 (MSB) and the control lines
PCS, PR, PRTR, PRTW, and EOD. It can be used for
data exchange with an external memory, for fast program download and for other special purposes as
defined by the DSP software.
For MPEG data input, the PIO interface is activated by
setting bits[9] and [8] in D0:346 to 01. For the handshake protocol, please refer to Section 4.6.2.8. on
page 80.
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MAS 35x9F
DATA SHEET
2.9. MPEG Synchronization Output
The signal at pin SYNC is set to ‘1’ after the internal
decoding for the MPEG header has been finished for
one frame. The rising edge of this signal can be used
as an interrupt input for the controller that triggers the
read out of the control information and ancillary data.
As soon as the MAS 35x9F has received the SYNC
reset command (see Section 4.6.2.6. on page 77), the
SYNC signal is cleared. If the controller does not issue
a reset command, the SYNC signal returns to ‘0’ as
soon as the decoding of the next MPEG frame is
started. MPEG status and ancillary data become
invalid until the frame is completely decoded and the
signal at pin SYNC rises again. The controller must
have finished reading all MPEG information before it
becomes invalid. The MPEG Layer 2/3 frame lengths
are given in Table 2–2. AAC has no fixed frame length.
tframe = 24...72 ms
Vh
tread
Vl
Fig. 2–12: Schematic timing of the signal at pin SYNC.
The signal is cleared at tread when the controller has
issued a Clear SYNC Signal command (see
Section 4.6.2.6. on page 77). If no command is
issued, the signal returns to ‘0’ just before the
decoding of the next MPEG frame.
Table 2–2: Frame length in MPEG Layer 2/3
fs/kHz
Frame Length
Layer 2
Frame Length
Layer 3
48
24 ms
24 ms
44.1
26.12 ms
26.12 ms
32
36 ms
36 ms
24
24 ms
24 ms
22.05
26.12 ms
26.12 ms
16
36 ms
36 ms
12
not available
48 ms
11.025
not available
52.24 ms
8
not available
72 ms
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DATA SHEET
2.10.MP3 Block Input Mode
Table 2–3: MP3 bit rate vs. number of interrupts
A new so-called MP3 block input mode is now available which improves the input timing behavior of the
MAS 35x9F MPEG 1/2/2.5 Layer 3 decoder. The following sections provide a detailed description of this
new mode.
Bit Rate
[kbit/s]
Number of Interrupts
[1/s]
320
20
2.10.1.Functional Description of the MP3 Block
Input Mode
256
16
224
14
192
12
160
10
128
8
112
7
96
6
80
5
64
4
In MP3 block input, the MAS 35x9F generates a
demand for new input data each time one of its two
input buffers becomes available. The controller then
has to send one block of input data via the serial interface SDIB. The block size is 2048 byte. The demand is
signalized via a pulse on the EOD pin.
Fig. 2–13 shows that the number of interrupts per second does not depend on the data rate at the serial
interface. The maximum input data bit clock rate supported by the MAS 35x9F for all MPEG audio sampling
rates is 1.4 MHz.
Table 2–3 shows the average number of interrupts per
second for several typical MP3 bit rates.
The time period between two interrupts may vary
slightly even for fixed bit rate input streams due to the
MP3 specific bit reservoir.
Interrupt
a)
SIC
b)
SIC
Interrupt
Data blocks in a) and b) contain the same number of bytes.
Data block a) is sent with a lower data rate than data block b).
t
Fig. 2–13: Data Block Timing Diagram
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MAS 35x9F
DATA SHEET
2.10.2.Setup
2.11.Default Operation
Table 3–10 on page 39 lists the new bits, UIC cells,
and registers to setup the MP3 block input mode.
This sections refers to the standard operation mode
“power-optimized solution” (see Section 2.6.3.).
2.10.2.1.Resync Timeout
2.11.1. Stand-by Functions
In case the MP3 decoder loses the synchronization
(e.g. due to corrupted input data), the output is softly
muted and a resync loop is entered where the
MAS 35x9F can be accessed via I2C. The loop is left
and the re-synchronization procedure continues in any
of the following cases:
After applying the battery voltage, the system will
remain stand-by, as long as the DCEN pin level is kept
low. Due to the low stand-by current of CMOS circuits,
the battery may remain connected to DCSOn/VSENSn
at all times.
– the last input data block is fully sent,
2.11.2.Power-Up of the DC/DC Converters
and Reset
– the Validate bit of IOControlMain is set
(D0:346, bit[0]),
– the timeout is reached (ResyncTimeout in
Table 3–10), the end bit is set (this bit will be reset
by the MAS 35x9F).
2.10.2.2.Detailed Setup
After the MPEG audio decoder application has been
selected, the following settings enable the MP3 block
decoding process.
Play MP3
The battery voltage must be applied to pin DCSOn via
the 22 µH inductor and, furthermore, to the sense pin
VSENSn via a Schottky diode (see Fig. 2–7 on
page 13).
For start-up, the pin DCEN must be connected via an
external “start” push button to the I2CVDD supply,
which is equivalent to the battery supply voltage
(> 0.9 V) at start-up.
The supply at DCEN must be applied until the DC/DC
converters have started up (signal at pin PUP) and
then removed for normal operation.
1. Write 0x318 into SerialInConfig.
2. Write IOControlMain with bit[2] and bit[0] equal one.
3. Write IOControlMain with bit[2] equals zero and
bit[0] equals one.
4. Write 0x0 into ResyncTimeout.
5. Write 0x0 into SoftMute.
6. Enable EODQ interrupt for sending data in controller.
7. Set StartBit in MP3BlockConfig.
8. Send data block of 2048 byte when EODQ goes
high.
As soon as the output voltage at VSENSn reaches the
default voltage monitor reset level of 3.0 V, the respective internal PUPn bit will be set. When both PUPn bits
are set, the signal at pin PUP will go high and can be
used to start and reset the microcontroller.
Before transmitting any I2C commands, the controller
must issue a power-on reset to pin POR. The separate
supply pin I2CVDD ensures that the I2C interface
works independently from the DSP or the audio codec.
Now the desired supply voltage can be programmed at
I2C subaddress 76hex.
Stop/Pause MP3
1. Write 0x1 into SoftMute.
2. Clear start bit in MP3BlockConfig.
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DATA SHEET
2.11.2.1.Important Advice for Turn-on and Operating Voltage
Before the 2.2 V are programmed at the DCDC converter, DSP+Codec must be enabled.
Operating and Turn-Off is possible down to 2.2 V.
The sequence should be similar to the following:
1. Start DCDC
2. Set DCDC to 2.5 V
Turn on DSP+Codec
Write App-Select memory cell
Read App-Running Mem cell
If okay: Set DCDC to 2.2 V
Set other mem cells
Set other codec registers
.....
3. Demute...send data
4. Mute...stop data.....loop "3)" "4)"...
5. Turn off DSP+Codec
goto "2)"
etc.....
The signal at pin PUP will return to low only when both
PUPn flags (I2C subaddress 76hex) have returned to
zero. Care must be taken when changing both DC/DC
output voltages to higher values. In this case, both output voltages are momentarily insufficient to keep the
PUPn flags up; the resulting dip in the signal at the
PUP pin may, in turn, reset the microcontroller. To
avoid this condition, only one DC/DC output voltage
should be changed at a time. Before modifying the
second voltage, the microcontroller must wait for the
PUPn flag of the first voltage to be set again.
If only DC/DC converter 1 is used, the reference voltage of the second, unused converter should be set to
a lower value than that of converter 1, and its pin
VSENS2 should be connected to VDD.
The operating mode pulse width modulation, or pulse
frequency modulation, are controlled at I2C subaddress 76hex, the operating frequency at I2C subaddress 77hex.
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MAS 35x9F
DATA SHEET
2.11.3. Reset Signal Specification
After power-up, a reset signal should be applied to the pin POR by the microcontroller as follows:
VDD 2.2 V min.
VDD
POR 2.2 V min.
POR
see Note 1
I2C access works without
additional delay from this point
0.5 µs min. delay
time
Fig. 2–14: Reset signal at pin POR
Note: The slew rate of POR should be as high as possible, but must be glitch-free in any case.
Slew rate typ.: 1 µs for 10% to 90% level transition,
Slew rate max.: 20 µs for 10% to 90% level transition.
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DATA SHEET
2.11.4.Control of the Signal Processing
2.11.5.Start-up of the Audio Codec
Before starting the DSP, the controller should check
for a sufficient voltage supply (respective flag PUPn at
I2C subaddress 76hex). The DSP is enabled by setting
the appropriate bit in the Control register (I2C subaddress 6Ahex). The nominal frequency of the crystal
oscillator must be written into D0:348. After an initialization phase of 5 ms, the DSP data registers can be
accessed via I2C.
Before enabling the audio codec, the controller should
check for a sufficient voltage supply (respective flag
PUPn at I2C subaddress 76hex).
Input and output control is performed via memory location D0:346 and D0:347. The serial input interface
SDIB is the default. The decoded audio can be routed
to either the S/PDIF, the SDO and the analog outputs.
The output clock signal at pin CLKO is defined in
D0:349.
All changes in the D0 memory cells become effective
synchronously upon setting the LSB of Main I/O Control (see Table 3–8 on page 32). Therefore, this cell
should always be written last.
The digital volume control (see Table 3–8 on page 32)
is applied to the output signal of the DSP. The
decoded audio data will be available at the SPDO output interface in the next version.
The DSP does not have to be started if its functions
are not required, e.g., for routing audio through the
codec part of the IC via the A/D and the D/A converters.
The audio codec is enabled by setting the appropriate
bit at the Control register (I2C subaddress 6Ahex). After
an initialization phase of 5 ms, the DSP data registers
can be accessed via I2C. The A/D and the D/A converters must be switched on explicitly (register
00 00hex at I2C subaddress 6Chex). The D/A converters may either accept data from the A/D converters or
the output of the DSP, or a mix of both1) (register
00 06hex and 00 07hex at I2C subaddress 6Chex).
Finally, an appropriate output volume (register
00 10hex at I2C subaddress 6Chex) must be selected.
2.11.6.Power-Down
All analog outputs should be muted and the A/D and
the D/A converters must be switched off (register
00 10hex and 00 00hex at I2C subaddress 6Chex). The
DSP and the audio codec must be disabled (clear
DSP_EN and CODEC_EN bits in the Control register,
I2C subaddress 6Ahex). By clearing both DC/DC
enable flags in the Control register (I2C subaddress
6Ahex), the microcontroller can power down the complete system.
1) mixer available in version A2 and later; in version
A1, please use selector 00 0Fhex.
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MAS 35x9F
DATA SHEET
3. Controlling
nibble.
3.1. I2C Interface
– Data values in nibbles are always shown in hexadecimal notation.
Controlling between the MAS 35x9F and the external
controller is done via an I2C slave interface.
– A hexadecimal 20-bit number d is written, e.g. as
d = 17C63hex, its five nibbles are
d0 = 3hex, d1 = 6hex, d2 = Chex, d3 = 7hex, and
d4 = 1hex.
3.1.1. Device Address
The device addresses are 3C/3Ehex (device write
“DW”) and 3D/3Fhex (device read, “DR”) as shown in
Table 3–1. The device address pair 3C/3Dhex applies if
the DVS pin is connected to VSS, the device address
pair 3E/3Fhex applies if the DVS pin is connected to
I2CVDD.
Table 3–1: I2C device address
A7
A6
A5
A4
A3
A2
A1
W/R
0
0
1
1
1
1
DVS
0/1
I2C clock synchronization is used to slow down the
interface if required.
– Variables used in the following descriptions:
I²C address:
DW3C/3EhexI2C device write
DR3D/3FhexI2C device read
DSP core:
data_write68hexDSP data write
data_read69hexDSP data read
Codec:
codec_write6Chexcodec write
codec_read6Dhexcodec read
– Bus signals
S Start
P Stop
A ACK =
N NAK =
W Wait =
3.1.2. I2C Registers and Subaddresses
The interface uses one level of subaddresses. The
MAS 35x9F interface has 7 subaddresses allocated
for the corresponding I2C registers. The registers can
be divided into three categories as shown in Table 3–
2.
The address 6Ahex is used for basic control, i.e. reset
and task select. The other addresses are used for data
transfer from/to the MAS 35x9F.
The I2C registers of the MAS 35x9F are 16 bits wide,
the MSB is denoted as bit[15]. Transmissions via I2C
bus have to take place in 16-bit words (two byte transfers, MSB sent first); thus, for each register access,
two 8-bit data words must be sent/received via I2C
bus.
3.1.3. Naming Convention
The description of the various controller commands
uses the following formalism:
– Abbreviations used in the following descriptions:
a address
d data value
n count value
o offset value
r register number
x don’t care
– Memory addresses, like D1:89f, are always in hexadecimal notation.
Acknowledge
Not acknowledge
I2C clock line is held low
while the MAS 35x9F is processing
the current I2C command
– Symbols in the telegram examples
<
Start Condition
>
Stop
dd
data bytes
xx
ignore
All telegram numbers are hexadecimal, data originating from the MAS 35x9F are represented as gray
letters.
Example:
<DW 68 dd dd >
write data to DSP
<DW 69 <DR dd dd > read data from DSP
Fig. 3–1 shows I2C bus protocols for write and read
operations of the interface; the read operations require
an extra start condition and repetition of the chip
address with the device read command (DR). Fields
with signals/data originating from the MAS 35x9F are
marked by a gray background.
Note: In some cases the data reading process must
be concluded by a NAK condition.
3.2. Direct Configuration Registers
The task selection of the DSP and the DC/DC converters are controlled in the direct configuration registers
CONTROL, DCCF, and DCFR.
– A data value is split into 4-bit nibbles which are
numbered beginning with 0 for the least significant
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MAS 35x9F
DATA SHEET
Table 3–2: I2C subaddresses
Subaddress
(hex)
I2CRegister
Name
3.2.1. Write Direct Configuration Registers
Function
S
76
77
W
A
subaddr.
A
d3,d2
A
d1,d0
A
P
The write protocol for the direct configuration registers
only consists of device address, subaddress and one
16-bit data word.
Direct Configuration
6A
DW
CONTROL
Controller writes to
MAS 35x9F CONTROL
register
DCCF
3.2.2. Read Direct Configuration Register
S
Controller writes to first
DC/DC configuration register
DCFR
DW
W
A
subaddr.
A
S
d3,d2
DR
A
W
A
d1,d0
N
P
To check the PUP1 and PUP2 power-up flags, it is
necessary to read back the content of the direct configuration registers.
Controller writes to
second DC/DC configuration register
DSP Core Access
68
data_write
Controller writes to
MAS 35x9F DSP
69
data_read
Controller reads from
MAS 35x9F DSP
Codec Access
6C
codec_write
Controller writes to
MAS 35x9F codec register
6D
codec_read
Controller reads from
MAS 35x9F codec register
Example: I2C write access
S
DW
W
A
subaddress
A
high byte data
A
subaddress
A
S
A
low byte data
W
A
N
P
P
Example: I2C read access
S
DW
W
DR
high byte data
SDA
SCL
S
1
0
P
A
W
A
low byte data
W
W = Wait
A = Acknowledge (Ack)
N = Not Acknowledge (NAK)
S = Start
P = Stop
Fig. 3–1: Example of an I2C bus protocol for the MAS 35x9F (MSB first; data must be stable while clock is high)
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MAS 35x9F
DATA SHEET
Table 3–3: Direct configuration registers
I2C Subaddress
(hex)
Function
Name
6A
Control Register (reset value = 3000hex)
CONTROL
bit[15:14]
Analog supply voltage range
Code
00
01
10
11
AGNDC
1.1 V
1.3 V
1.6 V
reserved
recommended for voltage range of AVDD
2.0 ... 2.4 V (reset)
2.4 ... 3.0 V
3.0 ... 3.6 V
reserved
Higher voltage ranges permit higher output levels and thus a better signal-tonoise ratio.
bit[13]
bit[12]
Enable DC/DC 2 (reset=1)
Enable DC/DC 1 (reset=1)
Both DC/DC converters are switched on by default with DCEN = high (1).
bit[11]
bit[10]
Enable and reset audio codec2)
Enable and reset DSP core2)
For normal operation (MPEG-decoding and D/A conversion), both, the DSP
core and the audio codec have to be enabled after the power-up procedure.
The DSP can be left off if an audio signal is routed from the analog inputs to
the analog outputs (set bit[15] in codec register 00 0Fhex). The audio codec
can be left off if the DSP uses digital inputs and outputs only.
1)
2)
24
bit[9]
bit[8]
Reset codec
Reset DSP core
bit[7]
Enable crystal input clock divider of 1.5
(extended range up to 28 MHz)1)
bit[6:0]
Reserved, must be set to zero
refer to Section 4.6.3. on page 81
refer to Section 2.11.2.1.
June 30, 2004; 6251-505-1DS
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MAS 35x9F
DATA SHEET
Table 3–3: Direct configuration registers, continued
I2C Subaddress
(hex)
Function
Name
76
DCCF Register (reset = 5050hex)
DCCF
DC/DC Converter 2
bit[15]
PUP2: Voltage monitor 2 flag (readback)
bit[14:11]
Converter 2 output voltage with respect to VREF2)
Code
bit[10]
bit[9:8]
1111
1110
1101
1100
1011
1010
1001
1000
0111
0110
0101
01001)
00111)
00101)
Nominal
output volt.
3.5 V
3.4 V
3.3 V
3.2 V
3.1 V
3.0 V
2.9 V
2.8 V
2.7 V
2.6 V
2.5 V
2.4 V
2.3 V
2.2 V
set level
of PUP2
3.4 V
3.3 V
3.2 V
3.1 V
3.0 V
2.9 V
2.8 V
2.7 V
2.6 V
2.5 V
2.4 V
2.3 V
2.2 V
2.1 V
reset level
of PUP2
3.3 V
3.2 V
3.1 V
3.0 V
2.9 V
2.8 V (reset)
2.7 V
2.6 V
2.5 V
2.4 V
2.3 V
2.2 V
2.1 V
2.0 V
Mode
1
0
pulse frequency modulation (PFM)
pulse width modulation (PWM) (reset)
Reserved, must be set to zero
The DC/DC converters are up-converters only. Thus, if the battery voltage is
higher than the selected nominal voltage, the output voltage will exceed the
nominal voltage.
DC/DC Converter 1
bit[7]
PUP1: Voltage monitor 1 flag (readback)
bit[6:3]
Converter 1 output voltage at VSENS1 with respect to VREF
(see bits 14 to 11)2)
bit[2]
Mode
1
0
bit[1:0]
pulse frequency modulation (PFM)
pulse width modulation (PWM) (reset)
Reserved, must be set to zero
Note, that the reference voltage for DC/DC converter 1 is derived from the
main reference source supplied via pin AVDD1. Therefore, if this DC/DC converter is used, its output must be connected to the analog supply.
The DC/DC converters are up-converters only. Thus, if the battery voltage is
higher than the selected nominal voltage, the output voltage will exceed the
nominal voltage.
1)
2)
refer to Section 4.3.3. on page 60
refer to Section 2.11.2.1.
Micronas
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MAS 35x9F
DATA SHEET
Table 3–3: Direct configuration registers, continued
I2C Subaddress
(hex)
Function
Name
77
DCFR Register (reset = 00hex)
DCFR
Battery Voltage Monitor
bit[15]
Comparison result (readback)
1
input voltage at pin VBAT above defined threshold
0
input voltage at pin VBAT below defined threshold
bit[14]
Number of battery cells
0
1 cell (range 0.8...1.5 V) (reset)
1
2 cells (range 1.6...3.0 V)
bit[13:10]
Voltage threshold level
1 cell
2 cells
1111
1.5
3.0 V
1110
1.45
2.9 V
...
0010
0.85
1.7 V
0001
0.8
1.6 V
0000
battery voltage supervision off (reset)
bit[9:8]
Reserved, must be set to 0
The result is stable 1 ms after enabling. The setup time for switching between
two thresholds is negligibly small.
For power management reasons, the battery voltage monitor should be
switched off by setting bit[13:10] to zero when the measurement is completed.
DC/DC Converter Frequency Control (PWM)
bit[7:4]
Reserved, must be set to 0
bit[3:0]
Frequency of DC/DC converter
Reference: 24.576
0111
315.1
0110
323.4
0101
332.1
0100
341.3
0011
351.1
0010
361.4
0001
372.4
0000
384.0
1111
396.4
1110
409.6
1101
423.7
1100
438.9
1011
455.1
1010
472.6
1001
491.5
1000
512.0
22.5792
289.5
297.1
305.1
313.6
322.6
332.0
342.1
352.8
364.2
376.3
389.3
403.2
418.1
434.2
451.6
470.4
18.432 MHz
297.3 kHz
307.2 kHz
317.8 kHz
329.1 kHz
341.3 kHz
354.5 kHz
368.6 kHz
384.0 kHz (reset)
400.7 kHz
418.9 kHz
438.9 kHz
460.8 kHz
485.1 kHz
512.0 kHz
542.1 kHz
576.0 kHz
If the audio codec is not enabled (bit[11] of the CONTROL register at I2C-subaddress 6Ahex is zero), the clock for the DC/DC converters is directly derived
from the crystal frequency (nominal 18.432 MHz). Otherwise, the synthesizer
clock is used as the reference (please refer to the respective column in
Table 2–1 on page 11).
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MAS 35x9F
DATA SHEET
3.3. DSP Core
S
3.3.1. Access Protocol
The I2C data register is used to communicate with the
internal firmware of the MAS 35x9F. It is readable
(subaddress “data_read”) and writable (subaddress
“data_write”) and also has a length of 16 bits. The data
transfer is done with the most significant bit (m) first.
Table 3–4: Data register bit assignment
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
m
l
A special command language is used that allows the
controller to access the DSP registers and RAM cells
and thus monitor internal states, set the parameters for
the DSP firmware, control the hardware, and even provide a download of alternative software modules. The
DSP commands consist of a “Code” which is sent to
the I2C data register together with additional parameters.
DW
W
A data_write A Code,... A
...,...
A
...
Fig. 3–2: General core access protocol
Table 3–5 gives an overview over the different commands which the DSP Core receives via the I2C data
register. The “Code” is always the first data nibble
transmitted after the “data_write” subaddress byte. A
second auxiliary code nibble is used for the short
memory (16-bit) access commands.
The MAS 35x9F firmware scans the I2C interface periodically and checks for pending or new commands.
The commands are then executed by the DSP during
its normal operation without any loss or interruption of
the incoming data or outgoing audio data stream.
However, due to some time critical firmware parts, a
certain latency time for the response has to be
expected at the locations marked with a “W” (= wait).
The theoretical worst case response time does not
exceed 4 ms. However, the typical response time is
less than 0.5 ms.
Due to the 16-bit width of the I2C data register, all
actions transmit telegrams with multiples of 16 data
bits.
Table 3–5: Basic controller command codes
Code
(hex)
Command
Function
0...3
Run
Start execution of an internal program. Run with start address 0 means
freeze the operating system.
5
Read Ancillary Data
The controller reads a block of MPEG Ancillary Data from the MAS 35x9F
6
Fast Program Download
The controller downloads custom software via the PIO interface
7
Read IC Version
The controller reads the version information of the IC
a
Read from Register
The controller reads an internal register of the MAS 35x9F
b
Write to Register
The controller writes an internal register of the MAS 35x9F
c
Read D0 Memory
The controller reads a block of the DSP memory
d
Read D1 Memory
The controller reads a block of the DSP memory
e
Write D0 Memory
The controller writes a block of the DSP memory
f
Write D1 Memory
The controller writes a block of the DSP memory
Micronas
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MAS 35x9F
DATA SHEET
3.3.2. Data Formats
The internal data word size is 20 bits. All RAMaddresses can be accessed in a 20-bit mode via I2C
bus. Because of the 16-bit width of the I2C data register the full transfer of all 20 bits requires two 16-bit I2C
words. Some commands only access the lower 16 bits
of a cell. For fast access of internal DSP states the
processor core also has an address space of 256 data
registers.
The internal data format is a 20 bit two’s complement
denoted “r”. If in some cases a fixed point notation “v”
is necessary. The conversion between the two forms
of notation is done as follows:
r = v*524288.0+0.5; (−1.0 ≤ v < 1.0)
v = r/524288.0; (−524288 < r < 524287)
3.3.2.1. Run and Freeze (Codes 0hex to 3hex)
S
DW
W
A data_write A
a3,a2
A
a1,a0
W
A
P
The Run command causes the start of a program part
at address a = (a3,a2,a1,a0). Since nibble a3 is also
the command code (see Table 3–5), it is restricted to
values between 0 and 3. This command is used to
start alternate code or downloaded code from a RAMarea that has been configured as program RAM.
If the start address is 1000hex ≤ a < 3FFFhex and the
respective RAM area has been configured as program
RAM (see Table 3–7 on page 31), the MAS 35x9F
continues execution with a custom program already
downloaded to this area.
Example 1: Start program execution at address
345hex:
The entry point of the default software will be accessed
automatically after a reset, thus issuing a Run or
Freeze command is only necessary for starting downloaded software or special program modules which are
not part of the standard set.
3.3.2.2. Read Register (Code Ahex)
1) send command
S
DW
W
A data_write A
a,r1
A
r0,0
W
A
P
W
N
P
2) get register value
S
DW
W
x,x
A
A data_read A
x,d4
W
A
S
DR
d3,d2
A
W
A
d1,d0
The MAS 35x9F has an address space of 256 DSPregisters. Some of the registers (r = r1,r0 in the figure
above) are direct control inputs for various hardware
blocks, others control the internal program flow. In
Table 3–7, the registers of interest are described in
detail. In contrast to memory cells, registers cannot be
accessed as a block but must always be addressed
individually.
Example:
Read the content of register C8hex:
define register
and read
<DW 68 ac 80>
<DW 69 <DR xx xd dd dd >
3.3.2.3. Write Register (Code Bhex)
S
DW
W
A data_write A
b,r1
A
r0,d4
W
A
d3,d2
A
d1,d0
W
A
P
<DW 68 03 45>
The controller writes the 20-bit value (d = d4,d3,d2,
d1,d0) into the MAS 35x9F register (r = r1,r0). A list of
registers needed for control purposes is given in Table
3–7.
Example 2: Start execution of a downloaded code at
address 1000hex:
Example: Writing the value 81234hex into the register
with the number AAhex:
<DW 68 10 00>
<DW 68 ba a8 12 34>
Freeze is a special run command with start address 0.
It suspends all normal program execution. The operating system will enter an idle loop so that all registers
and memory cells can be watched. This state is useful
for operations like downloading code or contents of
memory cells because the internal program cannot
overwrite these values. This freezing will be required if
alternative software is downloaded into the internal
RAM of the MAS 35x9F.
Freeze has the following I2C protocol:
<DW 68 00 00>
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MAS 35x9F
DATA SHEET
3.3.2.6. Write Memory
(Codes Ehex and Fhex)
3.3.2.4. Read Memory (Codes Chex and Dhex)
The MAS 35x9F has 2 memory areas of 2048 words
denoted D0 and D1. The memory areas D0 and D1
can be written by using the codes Chex and Dhex,
respectively.
The memory areas D0 and D1 can be written by using
the codes Ehex and Fhex, respectively.
S
DW
W
A data_write A
1) send command (Read D0)
S
DW
W
A data_write A
c,0
A
0,0
W
A
n3,n2
A
n1,n0
W
A
a3,a2
A
a1,a0
W
A
DW
W
x,x
A
A data_read A
x,d4
W
A
S
DR
d3,d2
A
W
A
x,d4
W
A
d3,d2
A
x,d4
x,x
A
x,d4
W
A
d1,d0
W
A
d1,d0
W
N
P
<DW 68 d0 00 00 03 01 00>
<DW 69 <DR xx xd dd dd
xx xd dd dd xx xd dd dd >
Because most cells in the user interface are only 16
bits wide, it is faster and more convenient to access
the memory locations with a special 16-bit mode for
reading:
W
A
DW
W
A data_read A
c,4
A
n3,n2
a3,a2
S
d3,d2
a3,a2
A
a1,a0
W
A
d3,d2
A
d1,d0
W
A
W
A
d3,d2
A
d1,d0
P
write D1 memory
1 word to write
start address
value = 80234hex
<3a 68 f0 00
00 01
04 56
00 08
02 34>
S
DW
W
e,4
A
0,0
W
A
A
n3,n2
A
n1,n0
W
A
A
a3,a2
A
a1,a0
W
A
A
d3,d2
A
d1,d0
W
A
W
A
A data_write A
....repeat for n data values....
0,0
W
A
A
n1,n0
W
A
A
a1,a0
W
A
W
A
W
N
P
2) get register value
S
A
Example: Write 80234hex to D1:456 has the following
I2C protocol:
A
A data_write A
A
W
....repeat for n data values....
1) send command (e.g. Short Read D0)
W
W
n1,n0
3.3.2.7. Short Write Memory
(Codes E4hex and F4hex)
3.3.2.5. Short Read Memory
(Codes C4hex and D4hex)
DW
0,0
A
With the Write D0/D1 Memory command n 20-bit
memory cells in D0 can be initialized with new data.
The Read D0 Memory command gives the controller
access to all 20 bits of the D0/D1 memory cells. The
telegram to read 3 words starting at location D1:100 is
S
A
A
....repeat for n data values....
x,x
A
P
2) get register value
S
x,x
e,0
n3,n2
DR
A
W
A
d1,d0
d3,d2
A
d1,d0
P
For faster access only the lower 16 bits of each memory cell are written. The 4 MSBs of the cell are cleared.
The command uses the same codes Ehex and Fhex for
D0/D1 as for the 20-bit command but followed by a 4
rather than a 0.
....repeat for n data values....
d3,d2
A
d1,d0
P
This command is similar to the normal 20 bit read command and uses the same command code Chex and
Dhex for D0 and D1 memory, respectively, however it is
followed by a 4hex rather than a 0hex.
Example: Read 16 bits of D1:123 has the following I2C
protocol:
<DW 68 d4 00
00 01
01 23
<DW 69 DR
dd dd >
Micronas
3.3.2.8. Clear SYNC Signal
(Code 5hex)
S
DW
W
A data_write A
5,0
A
0,0
W
A
P
After a successful decoding of an MPEG frame the signal at pin SYNC rises and thus generates an interrupt
event for the microcontroller. Issuing this command
lets the signal at pin SYNC return to ‘0’.
read 16 bits from D1
1 word to be read
start address
start reading
and read
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MAS 35x9F
DATA SHEET
3.3.2.9. Default Read
– Issue a Run command to start program execution at
entry point of downloaded code
The Default Read command is the fastest way to get
information from the MAS 35x9F. Executing the
Default Read in a polling loop can be used to detect a
special state during decoding.
S
DW
W
A data_read A
S
W
A
d3,d2
A
d1,d0
W
N
P
Example: For watching D1:123 the pointer D0:ffb must
be loaded with 8123hex:
write to D0 memory
1 word to write
start address ffb
value = 8...
...0123hex
e0 00
01
fb
08
23>
Now the Default Read commands can be issued as
often as desired:
Default Read command
16 bit content of the
address as defined by the
pointer
<DW 69 <DR dd dd > ... and do it again
<DW 69 <DR
dd dd >
DW
W
A data_write A
6,n2
A
n1,n0
W
A
a3,a2
A
a1,a0
W
A
<DW
<DW
<DW
<DW
<DW
<DW
<DW
<DW
68
68
68
68
68
68
68
68
b3
b4
b4
b5
b6
bb
bc
b0
b0
30
b0
30
b0
b0
30
60
<DW 68 60 05
08 00>
03
03
00
03
00
03
03
00
18>Stop all internal transfers
00>
00>
18>
00>
18>
00>
00>
initiate download of 5 words
start at address D0:800
Now transfer 5 20-bit words via the parallel PIO-port:
d4,d3
d4,d3
d4,d3
d2,d1
d2,d1
d2,d1
<DW 68 60 05
82 00>
d0,d4
d0,d4
d0,x
d3,d2
d3,d2
d1,d0
d1,d0
initiate download of 4 words
start at address D1:200
Now transfer 4 20-bit words via the parallel PIO-port:
d4,d3
d4,d3
d2,d1
d2,d1
d0,d4
d0,d4
d3,d2
d3,d2
d1,d0
d1,d0
<DW 68 b6 bc 00 00>switch the memory area
D0:800 ... D0:fff from
data to program usage
3.3.2.10.Fast Program Download (Code 6hex)
S
Freeze
<DW 68 00 00>
DR
The Default Read command immediately returns the
lower 16 bit content of a specific RAM location as
defined by the pointer D0:ffb. The pointer must be
loaded before the first Default Read action occurs. If
the MSB of the pointer is set, it points to a memory
location in D1 rather than to one in D0.
<DW 68
00
0f
00
01
Example for Fast Program Download command:
Download 5 words starting at D0:800,
then download 4 words starting at D1:200:
<DW 68 10 0a>
P
The Fast Program Download command introduces a
data transfer via the parallel port. n = n2,n1,n0
denotes the number of 20-bit data words to be transferred, a = a3,a2,a1,a0 gives the start address. The
data must be organized in two times five nibbles to get
two words of 20-bit length. If the number n of 20-bit
data words is odd, the very last word has to be padded
with one additional nibble.
start program execution at
address D0:100a
3.3.2.11.Serial Program Download
Program downloads may also be performed via the
I2C-interface by using the Write D0/D1 Memory commands. A similar command sequence as in the Fast
Program Download (Freeze, stop transfers...) applies.
The download must be initiated in the following order:
– Issue Freeze command
– Stop all DMA-transfers
– Issue Fast Program Download command
– Download code via PIO-interface
– Switch appropriate memory area to act as program
RAM (register EDhex)
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MAS 35x9F
DATA SHEET
3.3.2.12.Read IC Version (Code 7hex)
0 1
1) send command
0
S
DW
W
A data_write A
7,0
A
0,0
W
A
0 2
Derivate (0..F)
1
P
Version character (0 = “A”,.., F = “P”)
0 2
2) get version information
S
DW
W
A data_read A
S
DR
W
(hex)
Version number (01..FF)
A
n3,n2
A
n1,n0
W
A
d3,d2
A
d1,d0
W
N
P
With this command the version of the IC is read in two
16 bit words. The first word n = n3,n2,n1,n0 contains
the IC’s major number (one nibble for each digit). The
second word (d = d3,d2,d1,d0) returns the version as
shown in Table 3–6.
3.3.3. List of DSP Registers
The PSelect_Shadow register in Table 3–7 is used to
switch four RAM areas from data to program usage
and thus enabling the DSP’s program counter to
access downloaded program code stored at these
locations. For normal operation (firmware in ROM),
this register must be kept to zero.
Table 3–6: Second word of version information
Note: DSP registers not given in Table 3–7 must not
be written.
Bit
Nibble
Content
15:12
d3
IC family derivate
11:8
d2
Coded character of order
version (add 41hex to the
content of d2 to get ASCII)
7:0
d1,d0
Digit of order version
3.3.4. List of DSP Memory Cells
Among the user interface control memory cells there
are some which have a global meaning and some
which control application specific parts of the DSP
core. In Table 3–8 and Table 3–9, this is reflected by
the key words All, MPEG, and G.729.
Example:
Read the version information for MAS 35x9F, derivate
0, order version B2:
<DW 68 70 00
<DW 69 <DR
35 09
01 02 >
send version command
and read
MAS 3509F
derivate 0, version B2
(see Section 2.2. on page 8)
Table 3–7: Program Download registers
Address
(hex)
R/W
Function
6B
R/W
Configuration of Variable RAM Areas
bit[19]
bit[18]
bit[17]
bit[16]
Mode
Download
Default
(hex)
Name
0000
PSelect_Shadow
Affected RAM area
D0:800 ... D0:BFF
D0:C00 ... D0:FFF
D1:800 ... D1:BFF
D1:C00 ... D1:FFF
For details of program code download please refer to
Section 3.3.2.10. on page 30.
Micronas
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31
MAS 35x9F
DATA SHEET
3.3.4.2. Application Specific Control
3.3.4.1. Application Selection and
Application Running
The AppSelect cell is a global user interface configuration cell, which has to be written in order to start a specific application.
The AppRunning cell is a global user interface status
cell, which indicates, which application loop is actually
running.
The configuration of the MPEG Layer 2/3, AAC decoding and the G.729 codec firmware is done via the control memory cells described in Table 3–9. The changes
applied to any of the control memory cells have to be
validated by setting bit[0] of memory cell Main I/O Control. This bit will be reset automatically after the
changes have been taken over by the DSP.
The status memory cells in Table 3–11 are used to
read the decoder status and to get additional MPEG
bitstream information.
1. Write “0” to AppSelect
2. Check AppRunning for “0”
3. Write value to AppSelect according to Table 3–8
(determines start time of Application program)
4. Apply necessary/wanted control settings
(D0:346..357)
Note: DSP memory cells not given in Table 3–8 or
Table 3–9 must not be written.
Table 3–8: D0 control memory cells: mode selection
Memory
Address
(hex)
Function
Name
D0:34b
Application Selection
All
AppSelect
AppSelect is used for selecting an application. This is done by setting the
appropriate bit to one. It is principally allowed to set more than one bit to one,
e.g. setting AppSelect to 1Chex will select all MPEG audio decoders. The
auto-detection feature will automatically detect the Layer 2, Layer 3, or AAC
data. Setting bit[0] or bit[1] will make the DSP loop in the OS loop or the Top
Level loop respectively.
To add/remove MPEG layers while running in MPEG decoding mode (e.g.
change from Layer 2, Layer 3 (0Chex) to Layer 2, Layer 3, AAC (1Chex)), the
application selection has to be reset to 00hex before writing the new value.
bit[5]
bit[4]
bit[3]
bit[2]
bit[1]
bit[0]
D0:34c
G.729 Codec
MPEG AAC Decoder
MPEG Layer 3 Decoder
MPEG Layer 2 Decoder
Top Level
Operating System
Application Running
All
AppRunning
The AppRunning cell is a global user interface status cell, that indicates which
application loop is actually running. Prior to writing any of the configuration
registers or memory cells (except AppSelect), it has to be checked whether
the appropriate bit(s) in the AppRunning cell is set.
bit[5]
bit[4]
bit[3]
bit[2]
bit[1]
bit[0]
32
G.729 Codec
MPEG AAC Decoder
MPEG Layer 3 Decoder
MPEG Layer 2 Decoder
Top Level
Operating System
June 30, 2004; 6251-505-1DS
Micronas
MAS 35x9F
DATA SHEET
Table 3–9: D0 control memory cells
Memory
Address
(hex)
Function
Name
D0:346
Main I/O Control (reset = 8025hex)
MPEG
IOControlMain
IOControlMain is used for selecting/deselecting the appropriate data input
interface and for setting up the serial data output interface. In serial input
mode the coded audio data (Layer 2, Layer 3, AAC) is expected at the serial
input interface SDIB (default). In the 8-bit-parallel input mode the PIO pins
PI[19:12] are used.
bit[15]
MP3 block input selection
0: MP3 block input mode OFF
1: MP3 block input mode ON
bit[14]
Invert serial output clock (SOC)
0 (reset)
do not invert SOC
1
invert SOC
bit[13:12]
Reserved, must be set to zero
bit[11]
Serial data output delay
0 (reset)
no additional delay (reset)
1
additional delay of data related to word strobe
bit[10]
Reserved, must be set to zero
bit[9:8]
Input Select Main
00 (reset) serial input at interface B
01
parallel input at PIO pins PI[19...12]
10
reserved for future use
11
reserved for future use
bit[7:6]
Reserved, must be set to zero
bit[5]
SDO Word Strobe Invert
0
do not invert
1 (reset)
invert outgoing word strobe signal
bit[4]
Bits per Sample at SDO
0 (reset)
32 bits/sample
1
16 bits/sample
bit[3]
Reserved, must be set to zero
bit[2]
Serial data input interface B clock invert (pin SIBC)
0
not inverted (data latched at rising clock edge)
1 (reset)
incoming clock signal is inverted (data latched at
falling clock edge)
bit[1]
0 (reset)
1
bit[0]
Validate
0 (reset)
1
DEMAND MODE (PLL off, MAS 35x9F is clock
master)
BROADCAST MODE (PLL on, clock of MAS 35x9F
locks on data stream)
no forced evaluation of control memory cells
changes in control memory will become effective
Bit[0] is reset after the DSP has recognized the changes. The controller
should set this bit after the other D0 control memory cells have been initialized
with the desired values.
Micronas
June 30, 2004; 6251-505-1DS
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MAS 35x9F
DATA SHEET
Table 3–9: D0 control memory cells, continued
Memory
Address
(hex)
Function
Name
D0:347
Interface Status Control (reset = 05hex)
MPEG
InterfaceControl
This control cell allows to enable/disable the data I/O interfaces. In addition,
the clock of the output data interface interfaces, S/PDIF and SDO, can be set
to a low-impedance mode.
bit[6]
S/PDIF input selection (used for download modules)
0 (reset)
select S/PDIF input 1
1
select S/PDIF input 2
bit[5]
Enable/disable S/PDIF output
0 (reset)
enable S/PDIF output
1
S/PDIF output (invalid)
bit[4]
Reserved, must be set to zero
bit[3]
Enable/disable serial data output SDO
0 (reset)
SDO valid data
1
SDO invalid data
bit[2]
Output clock characteristic (SDO and S/PDIF outputs)
0
low impedance
1 (reset)
high impedance
bit[1]
reserved, must be set to zero
bit[0]
Enable/Disable SDI1)
0
enable
1 (reset)
disable
Both digital outputs, S/PDIF and I2S, and the D/A converters may use the
decoded audio independent of each other.
Changes at this memory address must be validated by setting bit[0] of
D0:346hex.
D0:348
Oscillator Frequency (reset = 18432dec)
bit[19:0]
All
OfreqControl
oscillator frequency in kHz
In order to achieve a correct internal operating frequency of the DSP, the nominal crystal frequency has to be deposited into this memory cell.
Changes at this memory address must be validated by setting bit[0] of
D0:346hex.
1)
34
Note: The pins SIC, SII, SID are switched to output mode, if bit [0] = 1 (Reset value).
June 30, 2004; 6251-505-1DS
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MAS 35x9F
DATA SHEET
Table 3–9: D0 control memory cells, continued
Memory
Address
(hex)
Function
D0:349
Output Clock Configuration (affects pin CLKO) (reset = 80000hex)
bit[19]
Name
All
OutClkConfig
CLKO configuration
0
output clock signal at CLKO
1 (reset)
CLKO is tristate
The CLKO output pin of the MAS 35x9F can be disabled via bit[19].
bit[18]
Reserved, must be set to zero
bit[17]
Additional division by 2 if scaler is on (bit[8] cleared)
0 (reset)
oversampling factor 512/768
1
oversampling factor 256/384
bit[16:9]
Reserved, must be set to zero
bit[8]
Output clock scaler
0 (reset)
set output clock according to audio sample rate
(see Table 2–1)
1
output clock fixed at 24.576 or 22.5792 MHz
For a list of output frequencies at pin CLKO please refer to Table 2–1.
bit[7:0]
reserved, must be set to zero
Changes at this memory address must be validated by setting bit[0] of
D0:346.
D0:350
Soft Mute
%0 (reset)
%1
D0:351
Micronas
MPEG
SoftMute
mute off
mute on
S/PDIF channel status bits category code setting (reset = 8200hex) All
June 30, 2004; 6251-505-1DS
SpdOutBits
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MAS 35x9F
DATA SHEET
Table 3–9: D0 control memory cells, continued
Memory
Address
(hex)
Function
Name
D0:34d
Operation Mode Selection (reset = 0hex)
G.729
UserControl
The register is used to switch between basic G.729 operation modes.
bit[19:7]
Reserved, set to 0
bit[6]
Page headers
0
enable
1
disable
If the page headers bit is 0, a header frame is transfered before each page of
50 data frames. If the header bit is 1, all the frames are G.729 data frames.
Please (see Section 3.3.8. on page 44).
bit[5:4]
Decoding speed
00
8 kHz (normal)
01
6 kHz (slow)
10
12 kHz (fast)
11
not allowed
The recording (encoding) is always done with a sampling rate of 8 kHz. During
decoding this control can be used to speed up or slow down the playback.
bit[3]
Reserved, set to 0
bit[2]
Pause encoder/decoder
0
normal operation
1
pause
If the pause bit is set, the processing continues until the current page is finished and then en-/decoding is paused. The pause mode lasts until the pause
bit is cleared again or the mode is set to 0.
bit[1:0]
Mode
00
01
10
11
idle
decode
not allowed
encode
To switch to encoder operation mode, UserControl has to be set to 3hex. Then
50 frames are encoded and sent via the PIO interface. This is repeated until
the UserControl register is changed. If the transmission of headers is enabled,
each page of 50 frames is preceeded by a header frame as shown in Fig. 3–4
on page 44.
To switch to decoder operation mode, UserControl has to be set to 1hex. For
decoding with slow speed, UserControl must be 11hex, for decoding with fast
speed it must be 21hex. Then the decoder is requesting several frames via the
PIO interface to fill its internal buffer. If enough data is available, 50 frames are
decoded. This is repeated until the UserControl register is changed. If the
transmission of headers is enabled, a header frame has to be sent before
each page of 50 frames (see Fig. 3–4 on page 44).
To switch off the encoder or decoder, UserControl has to be set to 0hex. Then
the encoding/decoding and sending/receiving of frames continues until the
end of the current page and the operation mode is set to stop.
36
June 30, 2004; 6251-505-1DS
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MAS 35x9F
DATA SHEET
Table 3–9: D0 control memory cells, continued
Memory
Address
(hex)
Function
Name
D0:34e
I2S Audio Input/Output Interface (reset = 60hex)
bit[19:15]
Reserved, set to 0
bit[14]
Output clock signal
0
standard signal
1
inverted signal
bit[13]
Reserved, set to 0
bit[12]
Additional delay of input data related to
word strobe
0
no delay
1
1 bit delay
bit[11]
Additional delay of output data related to
word strobe
0
no delay
1
1 bit delay
bit[10:7]
Reserveded, set to 0
bit[6]
Input word strobe signal
0
standard signal
1
inverted signal
bit[5]
Output word strobe signal
0
standard signal
1
inverted signal
bit[4]
Wordlength
0
32 bits/sample
1
16 bits/sample
G.729
SDISDOConfig
This setting affects the wordlength on the SDI and SDO interfaces.
bit[3]
Input clock signal
0
standard signal
1
inverted signal
bit[2:0]
Reserved, set to 0
Changes become effective when the codec is started or the mode is changed
by writing to the UserControl memory cell.
Micronas
June 30, 2004; 6251-505-1DS
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MAS 35x9F
DATA SHEET
Table 3–9: D0 control memory cells, continued
Memory
Address
(hex)
Function
Name
D0:34f
Interface Status Control (reset = 25hex)
G.729
g729_InterfaceCont
rol
This control cell is used to enable/disable interfaces in G.729 mode.
bit[6],[4]
reserved, must be set to zero
bit [5]
reserved, must be set to one
bit[3]
Enable/disable serial data output SDO
0 (reset)
SDO valid data
1
SDO invalid data
bit[2]
Output clock characteristic (SDO and S/PDIF outputs)
0
low impedance
1 (reset)
high impedance
bit[1]
reserved, must be set to zero
bit[0]
Enable/Disable SDI1)
0
enable
1 (reset)
disable
D0:352
Volume input control: left gain
(reset=80000hex)
G.729
in_L
D0:353
Volume input control: right gain
(reset=0hex)
G.729
in_R
D0:354
Volume output control: left → left gain (reset=80000hex)
All
out_LL
D0:355
Volume output control: left → right gain (reset=0hex)
All
out_LR
D0:356
Volume output control: right → left gain(reset=0hex)
All
out_RL
D0:357
Volume control: right → right gain (reset=80000hex)
All
out_RR
1)
38
Note: The pins SIC, SII, SID are switched to output mode, if bit [0] = 1 (Reset value).
June 30, 2004; 6251-505-1DS
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MAS 35x9F
DATA SHEET
Table 3–10: MP3 block input mode user interface (all addresses in hex notation)
Addr.
Name
Description
D0:346
IOControlMain
bit[15]
MP3 block input select
0: MP3 block input mode OFF
1: MP3 block input mode ON
works for input at serial input interface B
(bit[9:8] of IOControlMain = 00bin)
Reset value is 0x8024 (see Table 3–2).
R0:68
MP3BlockConfig
bit[17]
data end bit
Disables resync timeout. Should be set by the controller at the end of
an input file (file end, stop, or pause) when the last requested data
block has been fully sent.
0: resync timeout enabled
1: resync timeout disable ↔ no wait for end of block
bit[16]
reserved, set to “0”
bit[15]
start data request
0: MP3 decoder does not send data requests (wait loop)
1: MP3 decoder in operational mode, new input data will be requested
via pulses at the demand pin.
bit[14:0] input block size specific value, do not modify
Reset value is 0x6670. To set the start bit, the controller must write 0xe670.
R0:7e
PulseDelayCounter
bit[13:0] determines the variable fraction of the demand pulse length.
pulseLenVar[ns] = value * 88.58.
D0:34e
ResyncTimeout
bit[19:0] timeout after resync: timeout[µs] = value * 3.32.
The default value is 219-1, which results in a timeout of 1.74 seconds.
For an optimized resync behavior, it is recommended to set this value
to zero.
R0:5b
SerialInConfig
bit[14:0] configuration of the serial input interface
D0:350
SoftMute
bit[0]
Micronas
MP3 soft mute
0: audio output on
1: audio output soft muted
June 30, 2004; 6251-505-1DS
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MAS 35x9F
DATA SHEET
Table 3–11: D0 status memory cells
Memory
Address
Function
Name
D0:FCF
AAC bitrate in bit/s
AACbitrate
D0:FD0
MPEG Frame Counter
MPEGFrameCount
bit[19:0]
number of MPEG frames after synchronization
The counter will be incremented with every new frame that is decoded. With
an invalid MPEG bit stream at its input (e.g. an invalid header is detected), the
MAS 35x9F resets the MPEGFrameCount to ‘0’.
D0:FD1
MPEG Header and Status Information
bit[15]
reserved, must be set to zero
bit[14:13]
MPEG ID, Bits 12, 11 of the MPEG header
00
MPEG 2.5
01
reserved
10
MPEG 2
11
MPEG 1
not valid in case of AAC decoding (bit[12:11] = 00)
bit[12:11]
Bits 14 and 13 of the MPEG header
00
AAC
01
Layer 3
10
Layer 2
11
Layer 1
bit[10]
CRC Protection
0
bitstream protected by CRC
1
bitstream not protected by CRC
bit[9:2]
Reserved
bit[1]
CRC error
0
1
bit[0]
MPEGStatus1
no CRC error
CRC error
Invalid frame
0
no invalid frame´
1
invalid frame
This location contains bits 15...11 of the original MPEG header and other status bits. It will be set each frame directly after the header has been decoded
from the bit stream.
40
June 30, 2004; 6251-505-1DS
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MAS 35x9F
DATA SHEET
Table 3–11: D0 status memory cells, continued
Memory
Address
Function
Name
D0:FD2
MPEG Header Information
MPEGStatus2
bit[15:12]
MPEG Layer 2/3 Bitrate
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
bit[13:10]
MPEG1, L2
MPEG1, L3
MPEG2+2.5, L2/3
free
32
48
56
64
80
96
112
128
160
192
224
256
320
384
forbidden
free
32
40
48
56
64
80
96
112
128
160
192
224
256
320
forbidden
free
8
16
24
32
40
48
56
64
80
96
112
128
144
160
forbidden
Sampling frequency for MPEG2-AAC in Hz
0000..0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100..1111
reserved
48000
44100
32000
24000
22050
16000
12000
11025
8000
reserved
...
Micronas
June 30, 2004; 6251-505-1DS
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MAS 35x9F
DATA SHEET
Table 3–11: D0 status memory cells, continued
Memory
Address
Function
Name
D0:FD2
MPEG Header Information, continued
MPEGStatus2
(continued)
bit[11:10]
Sampling frequencies in Hz
00
01
10
11
bit[9]
Padding Bit
bit[8]
reserved
bit[7:6]
Mode
00
01
10
11
bit[5:4]
MPEG1
MPEG2
MPEG2.5
44100
48000
32000
reserved
22050
24000
16000
reserved
11025
12000
8000
reserved
stereo
joint_stereo (intensity stereo / m/s stereo)
dual channel
single channel
Mode extension (applies to joint stereo only)
00
01
10
11
intensity stereo
off
on
off
on
m/s stereo
off
off
on
on
bit[3]
Copyright Protect Bit
0/1
not copyright protected/copyright protected
bit[2]
Copy/Original Bit
0/1
bitstream is a copy/bitstream is an original
bit[1:0]
Emphasis, indicates the type of emphasis
00
none
01
50/15 µs
10
reserved
11
CCITT J.17
This memory cell contains the 16 LSBs of the MPEG header. It will be set
directly after synchronizing to the bit stream.
Note that for AAC four bits are needed to define the sampling frequency while
for Layer2/Layer3 two bits are sufficient. This leads to an inconsistency in the
format of bits 13...10.
D0:FD3
MPEG CRC Error Counter
CRCErrorCount
The counter will be increased by each CRC error detected in the MPEG bisstream. It will not be reset when losing the synchronization.
D0:FD4
Number of Bits in Ancillary Data
Number of valid ancillary bits in the current MPEG frame.
D0:FD5
...
D0:FF1
42
Ancillary Data
NumberOfAncillaryBits
AncillaryData
(see Section 3.3.6. on page 43).
June 30, 2004; 6251-505-1DS
Micronas
MAS 35x9F
DATA SHEET
3.3.6. Reading of the Memory Cells “Number of
Bits in Ancillary Data” and “Ancillary Data”
3.3.5. Ancillary Data
The memory fields D0:FD5...D0:ff1 contain the ancillary data. It is organized in 28 words of 16 bit each.
The last ancillary bit of a frame is placed at bit 0 in
D0:FD5. The position of the first ancillary data bit
received can be located via the content of
NumberOfAncillaryBits because
When in Broadcast Mode, reading of the cells “Number of Bits in Ancillary Data” and “Ancillary Data” will
lead to unpredictable results. These cells are
described in Table 3–11 on page 43.
The same applies to the “Number of Bits in Ancillary
Data” and “Ancillary Data” of the preliminary data
sheet MAS 3587F.
int[(NumberOfAncillaryBits-1)/16] + 1
of memory words are used.
Example:
First get the content of ‘NumberOfAncillaryBits’
<DW 68 c4 00 00 01 0f d4>
<DW 69 <DR dd dd>
Assume that the MAS 35x9F has received 19 ancillary
data bits. Therefore, it is necessary to read two 16-bit
words:
<DW 68 c4 00
Short Read from D0
00 02 0f d5> read 2 words starting at D0:fd5
<DW 69 <DR dd dd
dd dd>
receive the 2 16-bit words
The first bit received from the MPEG source is at position 2 of D0:FD6; the last bit received is at the LSB of
D0:fd5.
Table 3–12: Content of D0:fd5 after reception of 19 ancillary bits.
D0:fd5
MSB
14
13
12
11
10
9
8
7
6
5
4
3
2
1
LSB
Ancillary
Data
4th
bit
5th
bit
6th
bit
...
...
...
...
...
...
...
...
...
...
17th
bit
18th
bit
last
bit
Table 3–13: Content of D0:fd6 after reception of 19 ancillary bits.
D0:fd6
MSB
14
13
12
11
10
9
8
7
6
5
4
3
2
1
LSB
Ancillary
Data
x
x
x
x
x
x
x
x
x
x
x
x
x
first
bit
2nd
bit
3rd
bit
Micronas
June 30, 2004; 6251-505-1DS
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MAS 35x9F
DATA SHEET
3.3.7. DSP Volume Control
Table 3–14: Settings for the digital volume matrix
The digital baseband volume matrix is used for controlling the digital gain as shown in Fig. 3–3. This volume
control is effective on both, the digital audio output and
the data stream to the D/A converters. The values are
in 20-bit 2’s complement notation.
Table 3–14 shows the proposed settings for the 4 volume matrix coefficients for stereo, left and right mono.
The gain factors are given in fixed point notation
(−1.0×219 = 80000hex).
If channels are mixed, care must be taken to prevent
clipping at high amplitudes. Therefore, the sum of the
absolute values of coefficients for one output channel
must be less than 1.0.
For normal operating conditions it is recommended to
use the main volume control of the audio codec
instead (register 00 10hex of the audio codec).
from MPEG decoder
−1
−1
LR
−1
right audio
+
LL
to digital output and D/A
left audio
RL
−1
+
RR
Fig. 3–3: Digital volume matrix
page frame frame
header
1
2
frame
3
...
frame frame page frame
49
49 header 51
Memory
D0:354
D0:355
D0:356
D0:357
Name
LL
LR
RL
RR
Stereo
(default)
−1.0
0
0
−1.0
Mono left
−1.0
−1.0
0
0
Mono right
0
0
−1.0
−1.0
3.3.8. Explanation of the G.729A Data Format
The codec is working on a page basis where the
encoding and decoding is performed in blocks of 50
G.729 frames, whereas each frame consists of
10 bytes in byte-swapped order (see Fig. 3–4). Therefore most changes to the UserControl register become
effective when processing of the current page is finished. The pages are optionally preceeded by 10 byte
header frames (see Table 3–15).
Table 3–15: Content of page header
Byte
1
2
3
4
5
6
7
8
9
10
Value 64 6d 72 31 64 61 74 61 F4 01
(hex)
Switching directly from encoding to decoding mode (or
vice versa) is not allowed. Instead, the controller has to
send a stop request to the MAS 35x9F (writing 0hex to
UserControl) and must keep on sending data in decoding mode or receive data in encoding mode until the
current page of 50 frames is finished. After this run-out
time, the encoding or decoding can be started again.
frame
52
...
frame frame page frame frame
99
100 header 101
102
...
... 10 ms 10 ms ...
64
6D
72
31
64
61
74
61
F4
01
byte byte byte byte byte byte byte byte byte byte
2
1
4
3
6
5
8
7 10 9
Fig. 3–4: Schematic timing of the data transmission with preceeding header
44
June 30, 2004; 6251-505-1DS
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MAS 35x9F
DATA SHEET
3.4. Audio Codec Access Protocol
The MAS 35x9F has 16-bit wide registers for the control of the audio codec. These registers are accessed
via the I2C subaddresses codec_write (6Chex) and
codec_read (6Dhex).
3.4.1. Write Codec Register
S
DW
W
A
codec_write
A
r3,r2
A
r1,r0
A
d3,d2
A
d1,d0
A
P
The controller writes the 16-bit value (d = d3,d2,d1,d0)
into the MAS 35x9F codec register (r = r3,r2,r1,r0). A
list of registers is given in Table 3–16.
Example: Writing the value 1234hex into the codec register with the number 00 1Bhex:
<DW 6c 00 1b 12 34>
3.4.2. Read Codec Register
1) send command
S
DW
W
A
codec_write
A
codec_read
A
r3,r2
A
r1,r0
A
P
2) get register value
S
DW
W
A
S
d3,d2
DR
A
W
A
d1,d0
N
P
Reading the codec registers also needs a set-up for
the register address and an additional start condition
during the actual read cycle. A list of status registers is
given in Table 3–17.
Micronas
June 30, 2004; 6251-505-1DS
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MAS 35x9F
DATA SHEET
3.4.3. Codec Registers
Table 3–16: Codec control registers on I2C subaddress 6Chex
Register
Address
(hex)
Function
Name
CONVERTER CONFIGURATION
00 00
Audio Codec Configuration
CONV_CONF
0 dB is related to the D/A full-scale output voltage
Please refer to (see Section 4.6.3. on page 81).
bit[15:12]
A/D converter left amplifier gain = n*1.5−3 [dB]
bit[11:8]
A/D converter right amplifier gain = n*1.5−3 [dB]
1111
+19.5 dB
1110
+18.0 dB
...
...
0011
+1.5 dB
0010
0.0 dB
0001
−1.5 dB
0000
− 3.0 dB
bit[7:4]
Microphone amplifier gain = n*1.5+21 [dB]
1111
+43.5 dB
1110
+42.0 dB
...
...
0001
+22.5 dB
0000
+21.0 dB
bit[3]
Input selection for left A/D converter channel
0
line-in
1
microphone
bit[2]
Enable left A/D converter1)
bit[1]
Enable right A/D converter1)
bit[0]
Enable D/A converter1)
1)
The generation of the internal DC reference voltage for the D/A converter is also controlled with this bit. In order
to avoid click noise, the reference voltage at pin AGNDC should have reached a near ground potential before
repowering the D/A converter after a short down phase.
Alternatively, at least one of the A/D converters (bits[2] or [1]) should remain set during short power-down phases
of the D/A. Then the DC reference voltage generation for the D/A converter will not be interrupted.
46
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DATA SHEET
Table 3–16: Codec control registers on I2C subaddress 6Chex, continued
Register
Address
(hex)
Function
Name
INPUT MODE SELECT
00 08
Input Mode Setting
ADC_IN_MODE
bit[15]
Mono switch
0
stereo input mode
1
left channel is copied into the right channel
bit[14:2]
Reserved, must be set to 0
bit[1:0]
Deemphasis select
0
deemphasis off
1
deemphasis 50 µs
2
deemphasis 75 µs
OUTPUT MODE SELECT
D/A Converter Source Mixer
00 06
MIX ADC scale
DAC_IN_ADC
00 07
MIX DSP scale
DAC_IN_DSP
bit[15:8]
Linear scaling factor (hex)
0
off
20
50 % (−6 dB gain)
40
100 % (0 dB gain)
7f
200 % (+6 dB gain)
In the sum of both mixing inputs exceeds 100 %, clipping may occur in the
successive audio processing.
00 0E
D/A Converter Output Mode
DAC_OUT_MODE
bit[15]
Mono switch
0
stereo through
1
mono matrix applied
bit[14]
Invert right channel
0
through
1
right channel is inverted
bit[1:0]
Reserved, must be set to 0
In order to achieve more output power a single loudspeaker can be connected
as a bridge between pins OUTL and OUTR. In this mode bit[15] and bit[14]
must be set.
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MAS 35x9F
DATA SHEET
Table 3–16: Codec control registers on I2C subaddress 6Chex, continued
Register
Address
(hex)
Function
Name
BASSBAND FEATURES
00 14
Bass
bit[15:8]
BASS
Bass range
60hex
58hex
...
08hex
00hex
F8hex
...
A8hex
A0hex
+12 dB
+11 dB
+1 dB
0 dB
−1 dB
−11 dB
−12 dB
Higher resolution is possible, one LSB step results in a gain step of about
1/8 dB.
With positive bass settings clipping of the output signal may occur. Therefore,
it is not recommended to set bass to a value that, in conjunction with volume,
would result in an overall positive gain.
The settings require: max (bass, treble) + loudness + volume ≤ 0 dB
bit[7:0]
00 15
Not used, must be set to 0
Treble
bit[15:8]
TREBLE
Treble range
60hex
+12 dB
58hex
+11 dB
...
08hex
+1 dB
00hex
0 dB
F8hex
−1 dB
...
A8hex
−11 dB
A0hex
−12 dB
Higher resolution is possible, one LSB step results in a gain step of about
1/8 dB.
With positive treble settings, clipping of the output signal may occur. Therefore, it is not recommended to set treble to a value that, in conjunction with
loudness and volume, would result in an overall positive gain.
The settings require: max (bass, treble) + loudness + volume ≤ 0 dB
bit[7:0]
48
Not used, must be set to 0
June 30, 2004; 6251-505-1DS
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MAS 35x9F
DATA SHEET
Table 3–16: Codec control registers on I2C subaddress 6Chex, continued
Register
Address
(hex)
Function
Name
00 1E
Loudness
LDNESS
bit[15:8]
Loudness Gain
44hex
+17 dB
40hex
+16 dB
...
04hex
+1 dB
00hex
0 dB
bit[7:0]
Loudness Mode
00hex
normal (constant volume at 1 kHz)
04hex
Super Bass (constant volume at 2 kHz)
Higher resolution of Loudness Gain is possible: An LSB step results in a gain
step of about 1/4 dB.
Loudness increases the volume of low- and high-frequency signals, while
keeping the amplitude of the 1-kHz reference frequency constant. The
intended loudness has to be set according to the actual volume setting.
Because loudness introduces gain, it is not recommended to set loudness to a
value that, in conjunction with volume, would result in an overall positive gain.
The settings should be: max (bass, treble) + loudness + volume ≤ 0 dB
The corner frequency for bass amplification can be set to two different values.
In Super Bass mode, the corner frequency is shifted up. The point of constant
volume is shifted from 1 kHz to 2 kHz.
Micronas
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DATA SHEET
Table 3–16: Codec control registers on I2C subaddress 6Chex, continued
Register
Address
(hex)
Function
Name
Micronas Bass (MB)
00 22
MB Effect Strength
bit[15:8]
00hex
7Fhex
MB_STR
MB off (default)
maximum MB
The MB effect strength can be adjusted in 1dB steps. A value of 40hex will
yield a medium MB effect.
00 23
MB Harmonics
bit[15:8]
00hex
64hex
7Fhex
MB_HAR
no harmonics are added (default)
50% fundamentals + 50% harmonics
100% harmonics
The MB exploits the psychoacoustic phenomenon of the ‘missing fundamental
by creating harmonics of the frequencies below the center frequency of the
bandpass filter (MB_FC). This enables a loudspeaker to display frequencies
that are below its cutoff frequency. The Variable MB_HAR describes the ratio
of the harmonics towards the original signal.
00 24
MB Center Frequency
bit[15:8]
2
3
...
30
MB_FC
20 Hz
30 Hz
300 Hz
The MB Center Frequency defines the center frequency of the MB bandpass
filter (see Fig. 3–5 on page 52). The center frequency should approximately
match the cutoff frequency of the loudspeakers. For high end loudspeakers,
this frequency is around 50 Hz, for low end speakers around 90 Hz
00 21
MB Shape
bit[15:8]
MB_SHAPE
5...30
corner frequency in 10-Hz steps
(range: 50...300 Hz)
With a second lowpass filter the steepness of the falling edge of the MB bandpass can be increased (see Fig. 3–5 on page 52). Choosing the corner frequency of this filter close to the center frequency of the bandpass filter
(MB_FC) results in a narrow MB frequency range. The smaller this range, the
harder the bass sounds. The recommended value is around 1.5 × MB_FC
MB Switch
MB_SWITCH
bit[7:2]
reserved, must be set to zero
bit[1]
0
1
bit [0]
50
MB switch
MB off
MB on
reserved,must be set to zero
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MAS 35x9F
DATA SHEET
Table 3–16: Codec control registers on I2C subaddress 6Chex, continued
Register
Address
(hex)
Function
Name
Automatic Volume Correction (AVC) Loudspeaker Channel
AVC
VOLUME
00 12
bit[15:12] 0hex
8hex
AVC off (and reset internal variables)
AVC on
bit[11:8]
8 s decay time
4 s decay time
2 s decay time
20 ms decay time (intended for quick adaptation to the
average volume level after track or source change)
8hex
4hex
2hex
1hex
Note: To reset the internal variables, the AVC should be switched off and then
on again during any track or source change. For standard applications, the
recommended decay time is 4 s.
00 11
Balance
bit[15:8]
BALANCE
Balance range
7Fhex
left −127 dB, right 0 dB
7Ehex
left −126 dB, right 0 dB
...
01hex
left −1 dB, right 0 dB
00hex
left 0 dB, right 0 dB
FFhex
left 0 dB, right −1 dB
...
81hex
left 0 dB, right −127 dB
80hex
left 0 dB, right −128 dB
Positive balance settings reduce the left channel without affecting the right
channel; negative settings reduce the right channel leaving the left channel
unaffected.
00 10
Volume Control
VOLUME
bit[15:8]
Volume table with 1 dB step size
7Fhex
+12 dB (maximum volume)
7Ehex
+11 dB
...
74hex
+1 dB
73hex
0 dB
72hex
−1 dB
...
02hex
−113 dB
01hex
−114 dB
00hex
mute (reset)
bit[7:0]
Not used, must be set to 0
This main volume control is applied to the analog outputs only. It is split
between a digital and an analog function. In order to avoid noise due to large
changes of the setting, the actual setting is internally low-pass filtered.
With large scale input signals, positive volume settings may lead to signal clipping.
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MAS 35x9F
DATA SHEET
Table 3–17: Codec status registers on I2C subaddress 6Dhex
Register
Address
(hex)
Function
Name
INPUT QUASI-PEAK
00 0A
A/D Converter Quasi-Peak Detector Readout Left
bit[14:0]
0000
2000
4000
7FFF
00 0B
QPEAK_L
positive 15-bit value, linear scale
0%
25% (−12 dBFS)
50% (−6 dBFS)
100% (0 dBFS)
A/D Converter Quasi-Peak Detector Readout Right
bit[14:0]
0000
2000
4000
7FFF
QPEAK_R
positive 15-bit value, linear scale
0%
25% (−12 dBFS)
50% (−6 dBFS)
100% (0 dBFS)
OUTPUT QUASI-PEAK
Audio Processing Input Quasi-Peak Detector Readout Left
bit[14:0]
positive 15-bit value, linear scale
Audio Processing Input Quasi-Peak Detector Readout Right
bit[14:0]
DQPEAK_R
positive 15-bit value, linear scale
3.4.4. Basic MB Configuration
(which results in a softer/harder bass sound), turn
on/off the MB
With the parameters described in Table 3–16, the Micronas Bass system (MB) can be customized to create
different bass effects, as well as to fit the MB to various
loudspeaker characteristics. The easiest way to find a
good set of parameter is by selecting one of the settings below, listening to music with strong bass content
and adjusting the MB parameters:
– MB_STR: Increase/decrease the strength of the MB
effect
– MB_HAR: Increase/decrease the content of low frequency harmonics
– MB_FC: Shift the MB effect to lower/higher frequencies
– MB_SHAPE: Widen/narrow MB frequency range
Signal Level
00 0D
DQPEAK_L
Amplitude (db)
00 0C
Frequency
MB_FC
MB_SHAPE
Fig. 3–5: Micronas Bass (MB): Bass boost in relation
to input signal level
Table 3–18: Suggested MB settings
Function
MB_STR
(22hex)
MB_HAR
(23hex)
MB_FC
(24hex)
MB_SHAPE
(21hex)
MB off
xxxxhex
xxxxhex
xxxxhex
xx00hex
Low end headphones, medium effect
5000hex
3000hex
0600hex
0902hex
52
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MAS 35x9F
DATA SHEET
Micronas
June 30, 2004; 6251-505-1DS
53
MAS 35x9F
DATA SHEET
4. Specifications
4.1. Outline Dimensions
Fig. 4–1:
PLQFP64-1: Plastic Low Quad Flat Package, 64 leads, 10 × 10 × 1.4 mm3
Ordering code: FH
Weight approximately 0.66 g
54
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MAS 35x9F
DATA SHEET
Fig. 4–2:
PMQFP64-2: Plastic Metric Quad Flat Package, 64 leads, 10 × 10 × 2 mm3
Ordering code: QI
Weight approximately 0.5 g
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MAS 35x9F
DATA SHEET
Fig. 4–3:
PQFN64-1: Plastic Quad Flat Non-leaded package, 64 pins, 9 × 9 × 0.85 mm3, 0.5 mm pitch
Ordering code: XK
Weight approximately 0.23 g
56
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MAS 35x9F
DATA SHEET
4.2. Pin Connections and Short Descriptions
NC = not connected, leave vacant
LV = if not used, leave vacant
S.T.B. = shorted to BAGNDI if not used
DVSS = if not used, connect to DVSS
OBL = obligatory; connect as described in circuit diagram
AHVSS = connect to AHVSS
Pin No.
Pin Name
PLQFP
64-1
PMQFP
64-2
PQFN
64-1
1
1
1
AGNDC
2
2
2
MICIN
3
3
3
4
4
5
Type
Connection
Short Description
(If not used)
OBL
Analog reference voltage
IN
LV
Input for internal microphone amplifier
MICBI
IN
LV
Bias for internal microphone
4
INL
IN
LV
Left A/D input
5
5
INR
IN
LV
Right A/D input
6
6
6
TE
IN
OBL
Test enable
7
7
7
XTI
IN
OBL
Crystal oscillator (ext. clock)
input
8
8
8
XTO
OUT
LV
Crystal oscillator output
9
9
9
POR
IN
OBL
Power on reset, active low
10
10
10
VSS
SUPPLY
OBL
DSP supply ground
11
11
11
XVSS
SUPPLY
OBL
Digital output supply ground
12
12
12
VDD
SUPPLY
OBL
DSP supply
13
13
13
XVDD
SUPPLY
OBL
Digital output supply
14
14
14
I2CVDD
SUPPLY
OBL
I2C supply
15
15
15
DVS
IN
OBL
I2C device address selector
16
16
16
VSENS1
IN/OUT
VDD
Sense input and power output
of DC/DC 1 converter
17
17
17
DCSO1
SUPPLY
LV
DC/DC 1 switch output
18
18
18
DCSG1
SUPPLY
VSS
DC/DC 1 switch ground
19
19
19
DCSG2
SUPPLY
VSS
DC/DC 2 switch ground
20
20
20
DCSO2
SUPPLY
LV
DC/DC 2 switch output
21
21
21
VSENS2
IN/OUT
VDD
Sense input and power output
of DC/DC 2 converter
22
22
22
DCEN
IN
VSS
DC/DC enable (both converters)
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MAS 35x9F
DATA SHEET
Pin No.
Pin Name
Type
Connection
Short Description
PLQFP
64-1
PMQFP
64-2
PQFN
64-1
23
23
23
CLKO
OUT
LV
Clock output
24
24
24
I2CC
IN/OUT
OBL
I2C clock
25
25
25
I2CD
IN/OUT
OBL
I2C data
26
26
26
SYNC
OUT
LV
Sync output
27
27
27
VBAT
IN
LV
Battery voltage monitor
input
28
28
28
PUP
OUT
LV
DC Converters Power-Up
Signal
29
29
29
EOD
OUT
LV
PIO end of DMA, active low
30
30
30
PRTR
OUT
LV
PIO ready to read, active
low
31
31
31
PRTW
OUT
LV
PIO ready to write, active
low
32
32
32
PR
IN
VDD
PIO DMA request, active
high
33
33
33
PCS
IN
VSS
PIO chip select, active low
34
34
34
PI19
IN/OUT
LV
PIO data bit[7] (MSB)
35
35
35
PI18
IN/OUT
LV
PIO data bit[6]
36
36
36
PI17
IN/OUT
LV
PIO data bit[5]
37
37
37
PI16
IN/OUT
LV
PIO data bit[4]
38
38
38
PI15
IN/OUT
LV
PIO data bit[3]
39
39
39
PI14
IN/OUT
LV
PIO data bit[2]
40
40
40
PI13
IN/OUT
LV
PIO data bit[1]
41
41
41
PI12
IN/OUT
LV
PIO data bit[0] (LSB)
42
42
42
SOD
OUT
LV
Serial output data
43
43
43
SOI
OUT
LV
Serial output word identification
44
44
44
SOC
OUT
LV
Serial output clock
45
45
45
SID
IN/OUT
OBL
Serial input data, interface A
46
46
46
SII
IN/OUT
OBL
Serial input word identification, interface A
47
47
47
SIC
IN/OUT
OBL
Serial input clock, interface
A
48
48
48
SPDO
OUT
LV
S/PDIF output interface
49
49
49
SIBD
IN
VSS
Serial input data, interface B
58
(If not used)
June 30, 2004; 6251-505-1DS
Micronas
MAS 35x9F
DATA SHEET
Pin No.
Pin Name
Type
Connection
Short Description
PLQFP
64-1
PMQFP
64-2
PQFN
64-1
50
50
50
SIBC
IN
VSS
Serial input clock, interface
B
51
51
51
SIBI
IN
VSS
Serial input word identification, interface B
52
52
52
SPDI2
IN
LV
Active differential S/PDIF
input 2
53
53
53
SPDI1
IN
LV
Active differential S/PDIF
input 1
54
54
54
SPDIR
IN
LV
Reference differential S/
PDIF input 1 and 2
55
55
55
FILTL
IN
OBL
Feedback input for left
amplifier
56
56
56
AVDD0
SUPPLY
OBL
Analog supply for output
amplifiers
57
57
57
OUTL
OUT
LV
Left analog output
58
58
58
OUTR
OUT
LV
Right analog output
59
59
59
AVSS0
SUPPLY
OBL
Analog ground for output
amplifiers
60
60
60
FILTR
IN
OBL
Feedback for right output
amplifier
61
61
61
AVSS1
SUPPLY
OBL
Analog ground
62
62
62
VREF
OBL
Analog reference ground
63
63
63
PVDD
SUPPLY
OBL
Internal power supply
64
64
64
AVDD1
SUPPLY
OBL
Analog Supply
Micronas
(If not used)
June 30, 2004; 6251-505-1DS
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MAS 35x9F
DATA SHEET
4.3. Pin Descriptions
4.3.1. Power Supply Pins
The use of all power supply pins is mandatory to
achieve correct function of the MAS 35x9F.
VDD, VSS
Digital supply pins.
SUPPLY
XVDD, XVSS
Supply for digital output pins.
SUPPLY
I2CVDD
SUPPLY
Supply for I2C interface circuitry. This net uses VSS or
XVSS as the ground return line.
PVDD
SUPPLY
Auxiliary pin for analog circuitry. This pin has to be
connected via a 3 nF capacitor to AVDD1. Extra care
should be taken to achieve a low-inductance PCB line.
AVDD0/AVSS0
Supply for analog output amplifier.
SUPPLY
VSENS1/VSENS2
IN
Sense input and power output of DC/DC converters. If
the respective DC/DC converter is not used, this pin
should be connected to a supply to enable proper
function of the PUP-signals.
DCEN
IN
Enable signal for both DC/DC converters. If none of
the DC/DC converters is used, this pin must be connected to VSS.
PUP
OUT
Power-up. This signal is set when the required voltages are available at both DC/DC converter output
pins VSENS1 and VSENS2. The signal is cleared
when both voltages have dropped below the reset
level in the DCCF Register.
VBAT
Analog input for battery voltage supervision.
IN
4.3.4. Oscillator Pins and Clocking
AVDD0/AVSS0 and AVDD1/AVSS1 should receive the
same supply voltages.
XTI
IN
XTO
OUT
The XTI pin is connected to the input of the internal
crystal oscillator, the XTO pin to its output. Each pin
should be directly connected to the crystal and to a
ground-connected capacitor (see application diagram,
Fig. 5–1 on page 89).
4.3.2. Analog Reference Pins
CLKO
The CLKO can drive an output clock line.
AVDD1/AVSS1
SUPPLY
Supply for internal analog circuits (A/D, D/A converters, clock, PLL, S/PDIF input).
AGNDC
Internal analog reference voltage. This pin serves as
the internal ground connection for the analog circuitry.
VREF
Analog reference ground. All analog inputs and outputs should drive their return currents using separate
traces to a ground starpoint close to this pin. Connect
to AVSS1. This reference pin should be as noise-free
as possible.
4.3.3. DC/DC Converters and
Battery Voltage Supervision
DCSG1/DCSG2
SUPPLY
DC/DC converters switch ground. Connect using separate wide trace to negative pole of battery cell. Connect also to AVSS0/1 and VSS/XVSS, VREF.
DCSO1/DCSO2
SUPPLY
DC/DC converter switch connection. If the respective
DC/DC converter is not used, this pin must be left
vacant.
60
OUT
4.3.5. Control Lines
I2CC
SCL
I2CD
SDA
Standard I2C control lines.
IN/OUT
IN/OUT
DVS
IN
I2C device address selector. Connect this pin either to
VDD (I2C device address: 3E/3Fhex) or VSS (I2C
device address: 3C/3Dhex) to select a proper I2C
device address (see also Table 3–2 on page 23).
4.3.6. Parallel Interface Lines
PI12..PI19
IN/OUT
The PIO input pins PI12..PI19 are used as 8-bit I/O
interface to a microcontroller in order to transfer compressed and uncompressed data. PI12 is the LSB,
PI19 the MSB.
June 30, 2004; 6251-505-1DS
Micronas
MAS 35x9F
DATA SHEET
4.3.6.1. PIO Handshake Lines
PCS
IN
The PIO chip select PCS must be set to ‘0’ to activate
the PIO in operation mode.
PR
IN
Pin PR must be set to ‘1’ to validate data output from
MAS 35x9F PIO pins.
PRTR
OUT
Ready to read. This signal indicates that the
MAS 35x9F is able to receive data in PIO input mode.
PRTW
OUT
Ready to write. This pin indicates that MAS 35x9F has
data available for PIO output mode.
EOD
OUT
EOD indicates the end of an DMA cycle in the IC’s PIO
input mode. In ’serial’ input mode it is used as Demand
signal, that indicates that new input data are required.
4.3.7. Serial Input Interface (SDI)
SID
DATA
IN/OUT
SII
WORD STROBE
IN/OUT
SIC
CLOCK
IN/OUT
I2S compatible serial interface A for digital audio data.
In the standard firmware this interface is not used.
Note: Please refer to Bit [0] of Table 3–5
4.3.8. Serial Input Interface B (SDIB)
SIBD
DATA
IN
SIBI
WORD STROBE
IN
SIBC
CLOCK
IN
The serial interface B is primarily used as bitstream
input interface. The SIBI line must be connected to
VSS in the standard application.
4.3.9. Serial Output Interface (SDO)
SOD
DATA
OUT
SOI
WORD STROBE
OUT
SOC
CLOCK
IN/OUT
Data, Frame Indication, and Clock line of the serial
output interface. The SOI is reconfigurable and can be
adapted to several I2S compliant modes.
4.3.10. S/PDIF Input Interface
specification are used in conjunction with download
software only. A switch at D0:ff6 selects one of these
pins at a time. The SPDIR pin is a common reference
for both input lines (see Fig. 5–1 on page 89).
4.3.11. S/PDIF Output Interface
SPDO
OUT
The SPDO pin provides an digital output with standard
CMOS level that is compliant to the IEC 958 consumer
specification.
4.3.12. Analog Input Interfaces
In the standard MPEG-decoding DSP firmware the
analog inputs are not used. However, they can be
selected as a source for the D/A converters
(set MIX ADC scale of the D/A Converter Source
Mixer, Register 00 06hex in Table 3–16).
MICIN
IN
MICBI
IN
The MICIN input may be directly used as electret
microphone input, which should be connected as
described in application information (see Fig. 5–1 on
page 89). The MICBI signal provides the supply voltage for these microphones.
INL
IN
INR
IN
INL and INR are analog line-in input lines. They are
connected to the embedded stereo A/D converter of
the MAS 35x9F. The sources should be AC-coupled.
The reference ground for these analog input pins is the
VREF pin.
4.3.13. Analog Output Interfaces
OUTL
OUT
OUTR
OUT
OUTL and OUTR are left and right analog outputs, that
may be directly connected to the headphones as
described in the application information (see Fig. 5–1
on page 89).
FILTL
IN
FILTR
IN
Connection to input terminal of output amplifier.Can be
used to connect a capacitance from OUTL respectively
OUTR to FILTL respectively FILTR in parallel to feedback resistor and thus implement a low pass filter to
reduce the out-of-band noise of the DAC.
SPDI1
IN
SPDI2
IN
SPDIR
IN
SPDIF1 and SPDIF2 are alternative input pins for
S/PDIF sources according to the IEC 958 consumer
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MAS 35x9F
DATA SHEET
4.3.14. Miscellaneous
SYNC
OUT
The SYNC signal indicates the detection of a frame
start in the input data of MAS 35x9F. Usually this signal generates an interrupt in the controller.
POR
IN
The Power-On Reset pin is used to reset the whole
MAS 35x9F. The POR is an active-low signal (see
Fig. 5–1 on page 89).
TE
IN
The TE pin is for production test only and must be connected with VSS in all applications.
4.4. Pin Configuration
PI12
PI13
SOD
PI14
SOI
PI15
SOC
PI16
SID
PI17
SII
PI18
SIC
PI19
SPDO
PCS
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
SIBD
49
32
SIBC
50
31
PRTW
SIBI
51
30
PRTR
SPDI2
52
29
EOD
SPDI1
53
28
PUP
SPDIR
54
27
VBAT
FILTL
55
26
SYNC
AVDD0
56
25
I2CD
OUTL
57
24
I2CC
OUTR
58
23
CLKO
AVSS0
59
22
DCEN
FILTR
60
21
VSENS2
AVSS1
61
20
DCSO2
VREF
62
19
DCSG2
PVDD
63
18
DCSG1
AVDD1
64
17
DCSO1
MAS 35x9F
1
2
3
4
5
6
7
8
9
PR
10 11 12 13 14 15 16
AGNDC
VSENS1
MICIN
DVS
MICBI
I2CVDD
INL
XVDD
INR
VDD
TE
XVSS
XTI
XTO
VSS
POR
Fig. 4–4: PLQFP64-1/PMQFP64-2 and PQFN64-1 package
62
June 30, 2004; 6251-505-1DS
Micronas
MAS 35x9F
DATA SHEET
4.5. Internal Pin Circuits
VDD
TTLIN
N
VSS
Fig. 4–5: Input pins PCS, PR
Fig. 4–10: Input/output pins I2CC, I2CD
VSENS
Fig. 4–6: Input pin TE, DVS, POR
P
DCSO
N
DCSG
Fig. 4–11: Input/output pins DCSO1/2, DCSG1/2,
VSENS1/2
Fig. 4–7: Input pin DCEN
XVDD
XVDD
P
P
N
N
XVSS
Fig. 4–8: Input/output pins SOC, SOI, SOD,
PI12...PI19, SPDO
XVSS
Fig. 4–12: Output pins PRTW, EOD, PRTR, CLKO,
SYNC, PUP
AVDD
XVDD
P
P
P
N
N
XVSS
P
XTI
XTO
N
Enable
Fig. 4–9: Input pins SIC, SII, SID
N
AVSS
Fig. 4–13: Clock oscillator XTI, XTO
Micronas
June 30, 2004; 6251-505-1DS
63
MAS 35x9F
DATA SHEET
MICIN
INL
INR
XVDD
−
+
A
D
AGNDC
SPDI1,
SPDI2
−
SPDIR
+
Fig. 4–14: Analog input pins MICIN, INL, INR
XVDD
Bias
Fig. 4–18: S/PDIF inputs
AGNDC
+
MICBI
−
VBAT
+
−
VREF
Fig. 4–15: Microphone bias pin (MICBI)
VSS
=
programmable
VSS
Fig. 4–19: Battery voltage monitor VBAT
FILTL(R)
D
I
−
A
+
4.5.1.Reset Pin Configuration for MAS 3529F and
MAS 3539F
OUTL(R)
The Power-On Reset pin POR is used to reset the
entire MAS 35x9F. The POR is an active-low signal.
AGNDC
Fig. 4–16: Analog outputs OUTL(R) and connections
for filter capacitors FILTL(R)
Note: If a pull-up resistor is used for building a delay
time here (see Fig. 5–1 on page 89), referred to
the VDD pins, the maximum allowed value for
this resistor is 3.3 kOhm!
+
−
AGNDC
1.25 V
VREF
Fig. 4–17: Analog ground generation with pin to
connect external capacitor
64
June 30, 2004; 6251-505-1DS
Micronas
MAS 35x9F
DATA SHEET
4.6. Electrical Characteristics
Abbreviations:
tbd = to be defined
vacant = not applicable
positive current values mean current flowing into the chip
4.6.1. Absolute Maximum Ratings
Stresses beyond those listed in the “Absolute Maximum Ratings” may cause permanent damage to the device. This
is a stress rating only. Functional operation of the device at these conditions is not implied. Exposure to absolute
maximum rating conditions for extended periods will affect device reliability.
This device contains circuitry to protect the inputs and outputs against damage due to high static voltages or electric
fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than absolute maximum-rated voltages to this high-impedance circuit.
All voltages listed are referenced to ground (VSUP1, VSUP2, VSUP3 = 0 V) except where noted.
All GND pins must be connected to a low-resistive ground plane close to the IC.
Do not insert the device into a live socket. Instead, apply power by switching on the external power supply. For
power up/down sequences, see the instructions in Section 2.6. of this document.
Table 4–1: Absolute Maximum Ratings
Symbol
Parameter
Pin Name
Limit Values
Min.
TA1)
Unit
Max.
2)
°C
Ambient Temperature
- operating conditions
- extended temperature range1)
−10
−40
85
85
Case Temperature
PLQFP64-1
PMQFP64-2
PQFN64-1
−10
−10
−10
115
120
120
TS
Storage Temperature
−40
125
°C
PMAX
Maximum Power Dissipation
PLQFP64-1
PMQFP64-2
PQFN64-1
VDD, XVDD,
AVDD0/1,
I2CVDD
3)
W
Supply Voltage 1
VDD, XVDD,
I2CVDD,
AVDD0/14)
TC
VSUP1
°C
0.67
0.63
0.87
−0.3
6
V
1)
Data sheet parameters are valid for “operating conditions” only. The functionality of the device in the “extended
temperature range” was checked by electrical characterization on sample base.
2)
A power-optimized board layout is recommended. The Case Temperature mentioned in the “Absolute Maximum Ratings” must not be exceeded at worst case conditions of the application.
3)
Package limits
4) Both
Micronas
AVDD0 and AVDD1 have to be connected together!
June 30, 2004; 6251-505-1DS
65
MAS 35x9F
DATA SHEET
Table 4–1: Absolute Maximum Ratings, continued
Symbol
Parameter
Pin Name
Limit Values
Min.
Max.
Unit
VSUP2
Supply Voltage 2
VDD, XVDD,
I2CVDD,
AVDD0/11)
−0.3
6
V
VSUP3
Supply Voltage 3
VDD, XVDD,
I2CVDD,
AVDD0/11)
−0.3
6
V
VII2C
Input Voltage, I2C pins
I2CC,
I2CD
−0.3
6
V
VID
Input Voltage
all digital inputs
−0.3
VSUP + 0.3
V
IID
Input Current
all digital inputs
−20
+20
mA
VIA
Input Voltage
all analog inputs
−0.3
VSUP + 0.3
V
IIA
Input Current
all analog inputs
−5
+5
mA
IOaudio
Output Current, audio output2)
OUTL/R
−0.2
0.2
A
IOdig
Output Current, all digital outputs3)
−50
+50
mA
IOdcdc1
Output Current DCDC converter 1
DCSO1
1.5
A
IOdcdc2
Output Current DCDC converter 2
DCSO2
1.5
A
1) Both
AVDD0 and AVDD1 have to be connected together!
2)
These pins are not short-circuit-proof!
3)
Total chip power dissipation must not exceed maximum rating.
66
June 30, 2004; 6251-505-1DS
Micronas
MAS 35x9F
DATA SHEET
4.6.1.1. Recommended Operating Conditions
Functional operation of the device beyond those indicated in the “Recommended Operating Conditions/Characteristics” is not implied and may result in unpredictable behavior, reduce reliability and lifetime of the device.
All voltages listed are referenced to ground (VSUP1, VSUP2, VSUP3 = 0 V) except where noted.
All GND pins must be connected to a low-resistive ground plane close to the IC.
Do not insert the device into a live socket. Instead, apply power by switching on the external power supply. For
power up/down sequences, see the instructions in section Section 2.11.2. of this document.
Symbol
Parameter
Pin Name
Limit Values
Min.
TA
TC
Typ.
Unit
Max.
1)
Ambient Operating Temperature
PLQFP64-1
PMQFP64-2
PQFN64-1
0
0
0
25
25
25
85
85
85
Case Operating Temperature
PLQFP64-1
PMQFP64-2
PQFN64-1
15
20
15
95
100
95
100
105
100
°C
°C
PMAX_D1
MP3 Decoder (SC4 En-/Decoder)
VDD
80
mW
PMAX_D2
AAC Decoder/G729 Encoder
VDD
122
mW
PMAX_D3
G.729 Decoder
VDD
50
mW
PMAX_A
DAC-Headphone Playback
AVDD0/1
7
mW
VSUPD11)
Digital supply voltage (MP3
decoder, G729 Decoder)
VDD
VSUPD2
Digital supply voltage
(G.729 A encoder/MP3 Decoder
and SD Decryption/AAC Decoder)
VSUPI2C
I2C bus supply voltage
I2CVDD
VSUPDn2)
at VDD
VSUPx
PIN supply voltage
XVDD
2.2
PIN supply voltage in relation to
digital supply voltage
VSUPA
Analog audio supply voltage
2.5
3.6
2.5
2.7
3.6
2.5
0.62 *
VSUPDn2)
AVDD0/1
Analog audio supply voltage in relation to the digital supply voltage
VSUPDX
2.2
Voltage differences within supply
domains
2.2
0.62 *
VSUPDn2)
2.7
V
3.9
V
3.6
V
1.6 *
VSUPDn2)
V
3.6
V
1.6 *
VSUPDn2)
V
V
1)
A power-optimized board layout is recommended. The Case Operating Temperatures mentioned in the
“Recommended Operating Conditions” must not be exceeded at worst case conditions of the application.
For turn-on voltage of DSP and codec, please refer to Section 2.11.2.1.
2)
n = 1 or 2
Micronas
June 30, 2004; 6251-505-1DS
67
MAS 35x9F
DATA SHEET
Table 4–2: Reference Frequency Generation and Crystal Recommendation
Symbol
Parameter
Pin Name
Min.
Typ.
Max.
Unit
18.432
20.00
MHz
VPP
External Clock Input Recommendations
fCLK
Clock frequency
XTI, XTO
13.00
VCLKI
Clockamplitude of external clock
fed into XTI at VAVDD = 2.2 V
XTI
0.7
1.05
Clockamplitude of external clock
fed into XTI at VAVDD = 2.7 V
0.55
1.5
Clockamplitude of external clock
fed into XTI at VAVDD = 3.3 V
0.45
1.75
1.25
2.2
Clockamplitude of external clock
fed into XTO at VAVDD = 2.7 V
0.75
2.7
Clockamplitude of external clock
fed into XTO at VAVDD = 3.3 V
0.55
3.3
Clockamplitude of external clock
fed into XTO at VAVDD = 2.2 V
Duty cycle
XTO
XTI, XTO
45
50
55
%
Crystal Recommendations
fP
Load resonance frequency at
CI = 20 pF
∆f/fS
Accuracy of frequency adjustment
−50
50
ppm
∆f/fS
Frequency variation vs. temperature
−50
50
ppm
REQ
Equivalent series resistance
12
30
Ω
C0
Shunt (parallel) capacitance
3
5
pF
68
XTI, XTO
June 30, 2004; 6251-505-1DS
18.432
MHz
Micronas
MAS 35x9F
DATA SHEET
Table 4–3: Input clock frequency
Symbol
Parameter
Pin Name
Limit Values
Min.
fCLK1)
G.729 Decoder
G.729 Encoder
XTI, XTO
MPEG Decoder (SC4 EnDecoder)
1)
Typ.
Unit
Max.
16.4
13.7
MHz
MHz
11.0
MHz
Minimum FCLK for SD-card decryption is defined in a supplement.
Table 4–4: Input levels
Symbol
Parameter
Pin Name
Limit Values
Min.
VIL
Input low voltage
VIH
Input high voltage
VIL
Input low voltage
VIH
Input high voltage
VILD
Input low voltage
VIHD
Input high voltage
Micronas
I2CC,
I2CD
Typ.
Unit
Max.
0.3
1.4
POR,
DCEN
V
0.2
0.9
PI<I>,
SI(B)I,
SI(B)C,
SI(B)D, PR,
PCS,
TE, DVS
June 30, 2004; 6251-505-1DS
V
V
0.3
VSUPx
−0.5
V
V
V
69
MAS 35x9F
DATA SHEET
Table 4–5: Analog input and output recommendations
Symbol
Parameter
Pin Name
Limit Values
Unit
Min.
Typ.
Max.
1.0
3.3
µF
10
nF
Analog Reference
CAGNDC1
Analog filter capacitor
CAGNDC2
Ceramic capacitor in parallel
CPVDD
Capacitor for analog circuitry
AGNDC
PVDD
3
nF
Analog Audio Inputs
CinAD
DC-decoupling capacitor at A/Dconverter inputs
INL/R
390
nF
CinMI
DC-decoupling capacitor at
microphone-input
MICIN
390
nF
CLMICBI
Minimum-Capacitance at microphone bias
MICBI
3.3
FILTL/R
OUTL/R
−20 %
OUTL/R
16
nF
Analog Audio Filter Outputs
CFILT
Filter capacitor for headphone
amplifier
high-Q type,
NP0 or C0G material
470
+20 %
pF
Analog Audio Output
ZAOL_HP
Analog output load with stereo
headphones
Ω
100
pF
330
µF
DC/DC-Converter External Circuitry (please refer to application example)
C1
VSENS blocking
(<100 mΩ ESR)
VSENS1/2
VTH
Schottky diode threshold voltage
DCSO1/2
VSENS1/2
L
Ferrite core coil inductance
DCSO1/2
22
µH
SPDI1/2
SPDIR
100
nF
0.39
V
S/PDIF Interface Analog Input
CSPI
70
S/PDIF coupling capacitor
June 30, 2004; 6251-505-1DS
Micronas
MAS 35x9F
DATA SHEET
4.6.2. Digital Characteristics
at T = TA, VSUPD, VSUPA = 2.2 ... 3.6 V, fCrystal = 18.432 MHz, Typ. values for TA = 25 °C in P(L/M)QFP package
Symbol
Parameter
Limit Values
Pin Name
Min.
Unit
Test Conditions
36
mA
2.2 V, sampling frequency ≥ 32 kHz
Typ.
Max.
Digital Supply Voltage
ISUPD
Current consumption
ISUPD
Current consumption
23
mA
2.2 V, sampling frequency ≤ 24 kHz
ISUPD
Current consumption
15
mA
2.2 V, sampling frequency
≤ 12 kHz
ISTANDBY
Total current at stand-by
10
µA
DSP off, Codec off,
DC/DC off, AD and
DAC off, no I2C access
0.3
V
Iload = 2 mA
V
Iload = −2 mA
VDD,
XVDD,
I2CVDD
Digital Outputs and Inputs
ODigL
Output low voltage
ODigH
Output low voltage
ZDigI
Input impedance
IDLeak
Digital input leakage current
Micronas
PI<I>,
SOI,
SOC,
SOD,
EOD,
PRTR,
PRTW,
CLKO,
SYNC, PUP,
SPDO
ALL DIGITAL
INPUTS
VSUPx
−0.3
−1
June 30, 2004; 6251-505-1DS
7
pF
1
µA
0 V < Vpin < VSUPD
71
MAS 35x9F
DATA SHEET
4.6.2.1. I2C Characteristics
at T = 25°C, VSUPI2C = 2.2...3.6 V in P(L/M)QFP package
Symbol
Parameter
Limit Values
Pin Name
Min.
Typ.
Unit
Test Conditions
Max.
I2C Input Specifications
fI2C
Upper limit I2C bus frequency
operation
I2CC
400
kHz
tI2C1
I2C START condition setup
time
I2CC, I2CD
300
ns
tI2C2
I2C STOP condition setup
time
I2CC, I2CD
300
ns
tI2C3
I2C clock low pulse time
I2CC
1250
ns
tI2C4
I2C clock high pulse time
I2CC
1250
ns
tI2C5
I2C data setup time before
rising edge of clock
I2CC
80
ns
tI2C6
I2C data hold time after falling
edge of clock
I2CC
80
ns
VI2COL
I2C output low voltage
I2CC, I2CD
0.4
V
II2COH
I2C output high leakage
current
I2CC, I2CD
1
µA
tI2COL1
I2C data output hold time after
falling edge of clock
I2CC, I2CD
20
ns
tI2COL2
I2C data output setup time
before rising edge of clock
I2CC, I2CD
250
ns
VI2CIL
I2C input low voltage
I2CC, I2CD
VI2CIH
I2C input high voltage
I2CC, I2CD
0.6
tW
Wait time
I2CC, I2CD
0
0.3
Iload = 3 mA
fI2C = 400 kHz
VSUPI2C
VSUPI2C
0.5
4
ms
1/fI2C
tI2C4
tI2C3
H
L
I2CC
tI2C1
tI2C5
tI2C6
tI2C2
H
L
I2CD as input
tI2COL2
tIC2OL1
H
L
I2CD as output
Fig. 4–20: I2C timing diagram
72
June 30, 2004; 6251-505-1DS
Micronas
MAS 35x9F
DATA SHEET
4.6.2.2. Serial (I2S) Input Interface Characteristics (SDI, SDIB)
at T = TA, VSUPD, VSUPA = 2.2 ... 3.6 V, fCRYSTAL = 18.432 MHz, Typ. values for TA = 25 °C in P(L/M)QFP package
Symbol
Parameter
Limit Values
Pin Name
Min.
Typ.
Unit
Test Conditions
ns
fS = 48 kHz Stereo,
32 bits per sample
(for demand mode see
Table 4–6)
Max.
tSICLK
I2S clock input clock period
SI(B)C
tSIDS
I2S data setup time before
rising edge of clock (for
continuous data stream:
falling edge)
SI(B)C,
SI(B)D
50
ns
tSIDH
I2S data hold time
SI(B)D
50
ns
tSIIS
I2S ident setup time before
rising edge of clock (for
continuous data stream:
falling edge)
SI(B)C,
SI(B)I
50
ns
tSIIH
I2S ident hold time
SI(B)I
50
ns
tbw
Burst wait time
SI(B)C, SI(B)D
480
325
Table 4–6: Maximum allowed sample clock frequency in Demand Mode
fSample (kHz)
fC (MHz)
min. tSICLK (ns)
48, 32
6.144
162
44.1
5.6448
177
24, 16
3.072
325
22.05
2.8224
354
12, 8
1.536
651
11.025
1.4112
708
TSICLK
H
SI(B)C
L
H
SI(B)I
SI(B)D
L
H
L
TSIDS
TSIDH
Fig. 4–21: Continuous data stream at serial input A or B. In this mode, the word strobe SI(B)I is not used and the
data are read at the falling edge of the clock (bit[2] in D0:346 is set).
Micronas
June 30, 2004; 6251-505-1DS
73
MAS 35x9F
DATA SHEET
Table 4–7: Allowed transmission delays of external data source MPEG1/2 Layer 2/3
Symbol
Parameter
Limit Values
Pin Name
Unit
Test Conditions
3.1
ms
48 kHz/s, 320 kbit/s
5.7
ms
48 kHz/s, 64 kbit/s
tSTART24-320
4.2
ms
24 kHz/s, 320 kbit/s
tSTART24-32
9.2
ms
24 kHz/s, 32 kbit/s
tSTART12-64
23.1
ms
12 kHz/s, 64 kbit/s
tSTART12-16
25.6
ms
12 kHz/s, 16 kbit/s
tSTART8-64
34.8
ms
8 kHz/s, 64 kbit/s
tSTART8-8
38.4
ms
8 kHz/s, 8 kbit/s
1.3
ms
Clock rate of input data
1 Mbit/s
Min.
tSTART48-320
tSTART48-64
tSTOP
Allowed delay time before
start of serial data
transmission after assertion
of signal at EOD
Allowed delay time before
stop of serial data
transmission after
deassertion of signal at EOD
Typ.
EOD
EOD
Max.
TSICLK
SI(B)C
H
L
SI(B)I
H
L
TSIIS
SI(B)D
TSIIH
H
L
TSIDH
TSIDS
Fig. 4–22: Serial input of I2S signal
4.6.2.3. Serial Output Interface Characteristics (SDO)
at T = TA, VSUPD, VSUPA = 2.2 ... 3.6 V, fCRYSTAL = 18.432 MHz, Typ. values for TA = 25 °C in P(L/M)QFP package
Symbol
Parameter
Limit Values
Pin Name
Min.
Typ.
Unit
Test Conditions
ns
fS = 48 kHz Stereo
32 bits per sample
Max.
tSOCLK
I2S clock output frequency
SOC
tSOISS
I2S word strobe delay time
after falling edge of clock
SOC,
SOI
0
ns
tSOODC
I2S data delay time after
falling edge of clock
SOC,
SOD
0
ns
74
325
June 30, 2004; 6251-505-1DS
Micronas
MAS 35x9F
DATA SHEET
TSOCLK
H
SOC
SOI
L
H
L
TSOISS
TSOISS
SOD
H
L
TSOODC
Fig. 4–23: Serial output interface timing
Vh
SOC
Vl
Vh
SOD V
l
SOI
15 14 13 12 11 10 9 8
7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8
7 6 5 4 3 2 1 0
Vh
Vl
left 16-bit audio sample
right 16-bit audio sample
Fig. 4–24: Sample timing of the SDO interface in 16 bit/sample mode
D0:346 settings are
bit[14] = 0 (SOC not inverted)
bit[11] = 1 (SOI delay)
bit[5] = 0 (word strobe not inverted)
bit[4] = 1 (16 bits/sample)
SOC
Vh
...
...
Vl
Vh
SOD
31 30 29 28 27 26 25 ... 7 6 5 4 3 2 1 0 31 30 29 28 27 26 25 ... 7 6 5 4 3 2 1 0
Vl
Vh
SOI
Vl
left 32-bit audio sample
right 32-bit audio sample
Fig. 4–25: Sample timing of the SDO interface in 32 bit/sample mode
D0:346 settings are
bit[14] = 0 (SOC not inverted)
bit[11] = 0 (no SOI delay)
bit[5] = 1 (word strobe inverted)
bit[4] = 0 (32 bits/sample)
Micronas
June 30, 2004; 6251-505-1DS
75
MAS 35x9F
DATA SHEET
4.6.2.4. S/PDIF Input Characteristics
at T = TA, VSUPD, VSUPA = 2.2 ... 3.6 V, fCrystal = 18.432 MHz, Typ. values for TA = 25 °C in P(L/M)QFP package.
Symbol
Parameter
Limit Values
Pin Name
Min.
Typ.
Max.
200
500
1000
Unit
Test Conditions
VS
Signal amplitude
SPDI1, SPDI2,
SPDIR
fs1
Bi-phase frequency
SPDI1, SPDI2,
SPDIR
2.048
MHz
±1000 ppm, fs = 48 kHz
fs2
Bi-phase frequency
SPDI1, SPDI2,
SPDIR
2.822
MHz
±1000 ppm,
fs = 44.1 kHz
fs3
Bi-phase frequency
SPDI1, SPDI2,
SPDIR
3.072
MHz
±1000 ppm, fs = 32 kHz
tP
Bi-phase period
SPDI1, SPDI2,
SPDIR
326
ns
at fs = 48 kHz, (highest
sampling rate)
tR
Rise time
SPDI1, SPDI2,
SPDIR
0
65
ns
at fs = 48 kHz, (highest
sampling rate)
tF
Fall time
SPDI1, SPDI2,
SPDIR
0
65
ns
at fs = 48 kHz, (highest
sampling rate)
Duty cycle
SPDI
40
60
%
at bit value=1 and
fs = 48 kHz
tH1,L1
SPDI
81
163
ns
minimum/maximum pulse
duration with a level
above 90 % or below
10 % and at fs = 48 kHz
tH0,L0
SPDI
163
244
ns
minimum/maximum pulse
duration with a level
above 90 % or below
10 % and at fs = 48 kHz
tR
50
mVpp
tF
tH1
tL1
Bit value = 1
tH0
tL0
Bit value = 0
tP
Fig. 4–26: Timing of the S/PDIF input
76
June 30, 2004; 6251-505-1DS
Micronas
MAS 35x9F
DATA SHEET
4.6.2.5. S/PDIF Output Characteristics
at T = TA, VSUPD, VSUPA = 2.2 ... 3.6 V, fCRYSTAL = 18.432 MHz, Typ. values for TA = 25 °C in P(L/M)QFP package.
Symbol
Parameter
Limit Values
Pin Name
Min.
Typ.
Unit
Test Conditions
Max.
fs1
Bi-phase frequency
SPDO
3.072
MHz
fs = 48 kHz
fs2
Bi-phase frequency
SPDO
2.822
MHz
fs = 44.1 kHz
fs3
Bi-phase frequency
SPDO
2.048
MHz
fs = 32 kHz
tP
Bi-phase period
SPDO
326
ns
at fs = 48 kHz, (highest
sampling rate)
tR
Rise time
SPDO
0
2
ns
Cload = 10 pF
tF
Fall time
SPDO
0
2
ns
Cload = 10 pF
Duty cycle
SPDO
50
%
tH1,L1
SPDO
163
ns
minimum/maximum pulse
duration with a level
above 90% or below 10%
and at fs = 48 kHz
tH0,L0
SPDO
326
ns
minimum/maximum pulse
duration with a level
above 90% or below 10%
and at fs = 48 kHz
SPDO
VSUPD
VS
Signal amplitude
tR
tF
tH1
tL1
Bit value = 1
tH0
tL0
Bit value = 0
tP
Fig. 4–27: Timing of the S/PDIF output
4.6.2.6. PIO as Parallel Input Interface: DMA Mode
In decoding mode, the data transfer can be started
after the EOD pin of the MAS 35x9F is set to “high”.
After verifying this, the controller signalizes the sending of data by activating the PR line. The MAS 35x9F
responds by setting the RTR line to the “low” level. The
MAS 35x9F reads the data PI[19:12] and sets RTR to
low after rising edge of PR. After RTR is set to high,
the mC sets PR to low. The next data word write operation will be initialized again by setting the PR line via
Micronas
the controller. Please refer to Figure for the exact timing.
The procedure above will be repeated until the
MAS 35x9F sets the EOD signal to “0” which indicates
that the transfer of one data block has been executed.
Subsequently, the controller should set PR to “0”, wait
until EOD rises again and then repeat the procedure to
send the next block of data. The DMA buffer for MPEG
decoding is 30 bytes long. The size for G.729 is 10
bytes.
June 30, 2004; 6251-505-1DS
77
MAS 35x9F
DATA SHEET
Table 4–9: t_clm in MP3
Table 4–8: PIO input DMA mode timing
Symbol
Pin Name
Min.
Max.
tst
PR, EOD
10 ns
2000 µs
tr
PR, RTR
t_clm
tset1
PI[19:12]
2*t_clm33 ns
tset2
PI[19:12]
dep. on
appl.
th
PI[19:12]
5*t_
clm
trtrq
RTR
5*t_
clm
Sample rate
[kHz]
t_clm [ns]
f_clm [MHz]
48 or 32
41
24.5760
44.1
44
22.5792
24 or 16
81
12.2880
22.05
89
11.2896
12 or 8
163
6.1440
11.025
177
5.6448
MP3:
60*t_clm
Table 4–10: t_clm in AAC
AAC:
140*t_clm
tpr
PR
5*t_
clm
Sample rate
[kHz]
t_clm [ns]
f_clm [MHz]
trpr
PR, RTR
t_clm
48 or 32
33
30.720
teod
PR, EOD
t_clm
44.1
35
28.224
teodq
EOD
150*t_clm1)
24 or 16
65
15.360
22.05
71
14.112
12 or 8
130
7.680
11.025
142
7.056
200 ms1)
1)
See Parallel I/O Application Note,
Order no. 6251-590-2-1IC.
tst
teod
GPIO
teodq
/EOD
/EOD
tpr = Twr
tr
/CS
/WR
PR
PR
trtrq
Customer IC
trpr
MAS3509F
/RTR
GPIO
/RTR
D7-D0
PI(19:12)
tset1 = Tchl_dov
th
Twrh
_csh
tset2
PI(19:12)
Fig. 4–28: Handshake protocol for writing MPEG data to the PIO-DMA
78
June 30, 2004; 6251-505-1DS
Micronas
MAS 35x9F
DATA SHEET
Table 4–11: PIO Program Download Mode timing
4.6.2.7. PIO as Parallel Input Interface:
Program Download Mode
Handshake for PIO input in Program Download
Mode is accomplished through the RTR, PCS, and
PI12..PI19 signal lines (see Fig. 4–29). The PR line
should be set to low level.
The MAS 35x9F will drive RTR low as soon as it is
ready to receive a byte and RTR will stay low until one
byte has been written. Writing of a byte is performed
with a PCS pulse, driven by the microcontroller. The
MAS 35x9F reads data after the falling edge of PCS
and will finish the cycle by setting RTR to high level
after the rising edge of PCS. The next data transfer is
initialized by the MAS 35x9F by driving the RTR line.
t0
t1
t2
Symbol
Pin
Min.
Max.
Unit
t0
RTR, PCS
0
µs
t1
PCS
150
ns
t2
PCS, RTR
0
30
ns
t3
RTR
0.4
5
µs
t4
PI
50
ns
t5
PI
50
ns
t3
RTW
PIxx
t4
t5
PCS
Fig. 4–29: PIO program download mode timing
Micronas
June 30, 2004; 6251-505-1DS
79
MAS 35x9F
DATA SHEET
4.6.2.8. PIO as Parallel Output Interface
Table 4–12: PIO output mode timing
Some downloadable software may use the PIO interface (lines PI19...PI12) as output. The data transfer
rate and conditions are defines by the software function.
Handshaking for PIO output mode is accomplished
through the RTW, PCS, and PI12..PI19 signal lines
(see Fig. 4–30). The PR line has to be set to high level.
RTW will go low as soon as a byte is available in the
output buffer and will stay low until a byte has been
read. Reading of a byte is performed with a PCS
pulse. Data is latched out from the MAS on the falling
edge of PCS and removed from the bus on the rising
edge of PCS.
t0
t1
t2
Symbol
Pin
Min.
Max.
Unit
t0
RTW, PCS
0.010
1800
µs
t1
PCS
0.330
µs
t2
PCS, RTW
0.010
µs
t3
RTW
0.330
t4
PI
0.330
µs
t5
PI
0.081
µs
10000
µs
t3
RTW
PIxx
t4
t5
PCS
Fig. 4–30: Output timing
80
June 30, 2004; 6251-505-1DS
Micronas
MAS 35x9F
DATA SHEET
4.6.3. Analog Characteristics
at T = TA, VSUPDn, VSUPx = 2.2 to 3.6 V, VSUPA = 2.2 to 3.6 V, fCRYSTAL = 13 to 20 MHz,
typical values at TA = 25 °C and fCRYSTAL = 18.432 MHz in P(L/M)QFP package
Symbol
Parameter
Limit Values
Pin Name
Min.
Typ.
Unit
Test Conditions
Max.
Analog Supply
IAVDD
Current consumption analog
audio
AVDD0/1
5
mA
VSUPA = 2.2 V, Mute
IQOSC
Current consumption crystal
oscillator
AVDD0/1
200
µA
Codec = off
DSP = off
DC/DC = on
ISTANDBY
10
Codec = off
DSP = off
DC/DC = off
Crystal Oscillator
VDCCLK
DC voltage at oscillator pins
VACLK
Clock amplitude
CIN
Input capacitance
ROUT
Output resistance
XTI, XTO
0.5
0.5
XTO
VSUPA
VSUPA
−0.5
VPP
3
pF
220
Ω
if crystal is used
VSUPA = 2.2 V
125
VSUPA = 2.7 V
94
VSUPA = 3.3 V
Analog Reference
VAGNDC
VMICBI
Analog Reference Voltage
Bias voltage for microphone
AGNDC
V
VSUPA
bits[15], [14] in
register 6Ahex
1.1
>2.2 V
00
1.3
>2.4 V
01
1.6
>3.0 V
10
VSUPA
bits[15], [14] in
register 6Ahex
1.8
>2.2 V
00
2.13
>2.4 V
01
2.62
>3.0 V
10
VSUPA
bits[15], [14] in
register 6Ahex
>2.2 V
00
MICBI
RMICBI
Source resistance
MICBI
IMAX
Maximum current microphone
bias
MICBI
180
Ω
µA
300
Micronas
RL >> 10 MΩ,
referred to VREF
June 30, 2004; 6251-505-1DS
81
MAS 35x9F
Symbol
Parameter
DATA SHEET
Limit Values
Pin Name
Min.
Unit
Test Conditions
Vpp
VSUPA
bits[15], [14] in
register 6Ahex
2.2
>2.2 V
00
2.6
>2.4 V
01
3.2
>3.0 V
10
VSUPA
bits[15], [14] in
register 6Ahex
141
>2.0 V
00
167
>2.4 V
01
282
>3.0 V
10
Typ.
Max.
Analog Audio Input
VAI
VMI
RinAI
RinMI
Analog line input clipping
level (at minimum analog
input gain, i.e. −3 dB)
Microphone input clipping
level (at minimum analog
input gain, i.e. +21 dB)
Analog line input resistance
Microphone input resistance
INL/R
MICIN
INL/R
MICIN
mVpp
97
kΩ
at minimum analog input
gain, i.e. −3 dB
20
at maximum analog input
gain, i.e. +19.5 dB
67
not selected
94
kΩ
at minimum analog input
gain, i.e. −21 dB
8
at maximum analog input
gain, i.e. +43.5 dB
94
not selected
SNRAI
Signal-to-noise ratio of line
input
INL/R
74
dB(A)
BW = 20 Hz...20 kHz,
analog gain = 0 dB,
input 1 kHz at VAI−20 dB
SNRMI
Signal-to-noise ratio of
microphone input
MICIN
73
dB(A)
BW = 20 Hz...20 kHz,
analog gain = +21 dB,
input 1 kHz at VMI−20 dB
THDAI
Total harmonic distortion of
analog inputs
INL/R
MICIN
0.01
%
BW = 20 Hz...20 kHz,
analog gain = 0 dB,
resp. 24 dB,
input 1 kHz at
−3 dBFS = VAI−6 dB
resp. VMI−6 dB
XTALKAI
Crosstalk attenuation
left/right channel
(analog inputs)
INL/R
MICIN
80
dB
f = 1 kHz, sine wave,
analog gain = 0 dB,
input = −3 dBFS
PSRRAI
Power supply rejection ratio
for analog audio inputs
AVDD0/1,
INL/R
MICIN
45
dB
1 kHz sine at 100 mVrms
20
dB
≤100 kHz sine at
100 mVrms
82
June 30, 2004; 6251-505-1DS
0.02
Micronas
MAS 35x9F
DATA SHEET
Symbol
Parameter
Limit Values
Pin Name
Min.
Typ.
Unit
Test Conditions
Max.
Audio Output
VAO1
Analog output voltage AC
RL ≥1 kΩ
OUTL/R
input = 0 dBFS digital
at 0 dB output gain
VSUPA
bits[15], [14] in
register 6Ahex
>2.2 V
00
1.84
>2.4 V
01
2.27
>3.0 V
10
>2.2 V
00
2.60
>2.6 V
01
3.20
>3.2 V
10
1.56
at +3 dB output gain
Vpp
2.20
dVAO1
Deviation of DC-level at
analog output for AGNDCVoltage
OUTL/R
VAO2
Analog output voltage AC
OUTL/R
−20
Vpp
20
mV
RLis 16 Ω headphone and
22 Ω series resistor
Input = 0 dBFS digital
(see Fig. 5–1 on page 89)
at 0 dB output gain
VSUPA
bits[15], [14] in
register 6Ahex
>2.2 V
00
1.84
>2.4 V
01
2.27
>3.0 V
10
>2.2 V
00
2.40
>2.6 V
01
3.00
>3.2 V
10
1.56
at +3 dB output gain
Vpp
2.00
Vpp
RoutAO
Analog output resistance
OUTL/R
SNRAO
Signal-to-noise ratio of analog
output
OUTL/R
94
THDAO
Total harmonic distortion
(headphone)
OUTL/R
0.03
0.05
0.003
0.01
LevMuteAO
Mute level
OUTL/R
6
−113
Ω
analog gain = +3 dB,
input = 0 dBFS digital
dB(A)
RL≥16 Ω
BW = 20 Hz...20 kHz,
analog gain = 0 dB
input = −20 dBFS
%
for RL≥16 Ω plus 22 Ω
series resistor
(see Fig. 5–1 on page 89)
for RL≥1 kΩ
dBV
A-weighted
BW = 20 Hz...22 kHz,
no digital input signal,
analog gain = mute
Micronas
June 30, 2004; 6251-505-1DS
83
MAS 35x9F
Symbol
Parameter
DATA SHEET
Limit Values
Pin Name
Min.
XTALKAO
Crosstalk attenuation left/right
channel (headphone)
OUTLR
Typ.
Unit
Test Conditions
dB
f = 1 kHz, sine wave,
OUTL/R: RL≥16 Ω
Max.
80
(see Fig. 5–1 on page 89)
analog gain = 0 dB
input = −3 dBFS
PSRRAO
Power supply rejection ratio
for analog audio outputs
AVDD0/1
OUTL/R
70
dB
1 kHz sine at 100 mVrms
35
dB
≤100 kHz sine at
100 mVrms
4.6.4. DC/DC Converter Characteristics
at T = TA, Vin = 1.2 V, Voutn = 3.0 V, fclk = 18.432 MHz, fsw = 384 kHz, PWM mode, L = 22 µH, in P(L/M)QFP package (unless otherwise noted) Typ. values for TA = 25 °C
Symbol
Parameter
Limit Values
Pin Name
Min.
VIN
Minimum start-up input
voltage
VIN
Minimum operating input
voltage
Typ.
Unit
Test Conditions
V
ILOAD ≤ 1 mA,
DCCF = 5050hex (reset)
Max.
0.9
1)
DC1
DC2
0.7
0.8
V
ILOAD = 50 mA,
DCCF = 5050hex (reset)
DC1
DC2
1.1
1.2
V
ILOAD = 200 mA,
DCCF = 5050hex (reset)
VOUT
Programmable output voltage
range
VSENSn
2.0
3.5
V
Voltage settings in DCCF
register (I2C subaddress
76hex)
VOTOL
Output voltage tolerance
VSENSn
−4
4
%
ILOAD = 20 mA
TA = 25 °C2)
ILOAD1
Output current
1 battery cell
VSENSn
200
mA
VIN = 0.9...1.5 V, 330 µF
ILOAD2
Output current
2 battery cells
600
mA
VIN = 1.8...3.0 V, 330 µF
dVOUT/
dVIN/VOUT
Line regulation
VSENSn
0.7
%/V
ILOAD = 20 mA
dVOUT/
VOUT
Load regulation
VSENSn
−1.8
%
ILOAD = 20...200 mA,
hmax
Maximum efficiency
95
%
VIN = 2.4 V, VOUT = 3.5 V
fswitch
Switching frequency
DCSOn
576
kHz
(see Section 2.6.2. on
page 12), (see Table 3–3)
fstartup
Switching frequency during
start-up
DCSOn
kHz
VSENSn < 1.9 V
1)
Since the regulators are bootstrapped, once
2) PFM mode regulates approx. 1% higher
84
297
384
250
started they will operate down to 0.7 V input voltage
June 30, 2004; 6251-505-1DS
Micronas
MAS 35x9F
DATA SHEET
Symbol
Parameter
Limit Values
Pin Name
Min.
IsupPFM1
Supply current in PFM mode
IsupPFM2
IsupPWM1
Supply current in PWM mode
IsupPWM2
Ilnmax
NMOS switch current limit
(low side switch)
Typ.
Unit
Test Conditions
µA
3)
Max.
VSENS1
75
VSENS2
135
VSENS1
265
VSENS2
325
DCSOn,
DCSGn
1
A
PWM-Mode
0.4
A
PFM-Mode
µA
IIptoff
PMOS switch turnoff current
(rectifier switch)
DCSOn
VSENSn
70
mA
Ron
NMOS switch on Resistance
(low side switch)
DCSO1,
DCSG1
170
mΩ
DCSO2,
DCSG2
280
mΩ
DCSOn,
DCSGn
0.1
µA
ILEAK
3)
4)
Leakage current
VSENSn
3)
4)
Converter off, no load
Current into VSENSn Pin. VIN > VOUT + 0.4V; no DC/DC-Converter switching action present
Add. current of oscillator at PIN AVDD0/1, (see Section 4.6.3. on page 81)
Micronas
June 30, 2004; 6251-505-1DS
85
MAS 35x9F
DATA SHEET
4.6.5. Typical Performance Characteristics
Efficiency vs. Load Current
Efficiency vs. Load Current
DCDC1 (VOUT = 3.5 V)
DCDC2 (VOUT = 3.5 V)
100
80
1.8 V
60
VIN:
3.0 V
2.4 V
1.8 V
40
PFM
PWM
20
0
10−4
−3
10
10
−2
10
60
VIN:
3.0 V
2.4 V
1.8 V
40
PFM
PWM
20
−1
0
10−4
1
10−3
10−2
10−1
Load Current (A)
Efficiency vs. Load Current
Efficiency vs. Load Current
DCDC1 (VOUT = 3.0 V)
DCDC2 (VOUT = 3.0 V)
100
2.4 V
2.4 V
80
60
Efficiency (%)
80
0.9 V
VIN:
2.4 V
1.5 V
1.2 V
0.9 V
40
20
0.9 V
60
VIN:
2.4 V
1.5 V
1.2 V
0.9 V
40
20
PFM
PFM
PWM
PWM
0
10−4
1
Load Current (A)
100
Efficiency (%)
3.0 V
80
1.8 V
Efficiency (%)
Efficiency (%)
100
3.0 V
−3
10
10
−2
10
−1
1
0
10−4
Load Current (A)
10−3
10−2
10−1
1
Load Current (A)
Fig. 4–31: Efficiency vs. Load Current
86
June 30, 2004; 6251-505-1DS
Micronas
MAS 35x9F
DATA SHEET
Efficiency vs. Load Current
Efficiency vs. Load Current
DCDC1 (VOUT = 2.2 V)
DCDC2 (VOUT = 2.2 V)
100
100
1.5 V
1.5 V
80
Efficiency (%)
Efficiency (%)
80
0.9 V
60
VIN:
1.5 V
1.2 V
0.9 V
40
PFM
PWM
20
0
10−4
−3
10
10
−2
10
−1
0.9 V
60
VIN:
1.5 V
1.2 V
0.9 V
40
PFM
PWM
20
0
10−4
1
10−3
10−2
Load Current (A)
Load Current (A)
Maximum Load Current
vs. Input Voltage
Maximum Load Current
vs. Input Voltage
0.8
1
0.8
DCDC1
DCDC2
Vout:
2.2 V
3.0 V
3.5 V
0.6
Maximum Load Current (A)
Maximum Load Current (A)
10−1
PFM
PWM
0.4
0.2
0
Vout:
2.2 V
3.0 V
3.5 V
0.6
PFM
PWM
0.4
0.2
0
0.0
1.0
2.0
3.0
Input Voltage (V)
0.0
1.0
2.0
3.0
Input Voltage (V)
Fig. 4–32: Maximum Load Current vs. Input Voltag
Note: Efficiency is measured as VSENSn × ILOAD / (Vin × Iin).
IAVDD is not included (Oscillator current)
Micronas
June 30, 2004; 6251-505-1DS
87
MAS 35x9F
DATA SHEET
Loadregulation
Loadregulation
at VOUT = 2.7 V, 2.5 V
at VOUT = 3.0 V, 3.5 V
2.75
3.55
3.5
1.5 V
Output Voltage (V)
Output Voltage (V)
2.7
2.65
0.9 V
VIN:
1.5 V
1.2 V
0.9 V
2.6
2.55
2.5
1.5 V
3.45
0.9 V
VIN:
1.5 V
1.2 V
0.9 V
3.4
3.05
3.0
2.45
2.95
DCDC1
DCDC1
2.4
2.9
0
50
100
150
200
Load Current (mA)
0
50
100
150
200
Load Current (mA)
No-Load Battery Current
VOUT = 3.0 V
10
Both DCDC running in PWM
Battery Current (mA)
One DCDC running in PFM
8
6
4
2
0
0.5
1.0
1.5
2.0
2.5
3.0
Input Voltage (V)
88
June 30, 2004; 6251-505-1DS
Micronas
Micronas
L
6.8n
A
6.8n
MICIN
AGNDC
June 30, 2004; 6251-505-1DS
Tape recorder
FM radio
MIC
3.6...5.6 k
INL
3.3 n
INR
390 n
TE
A
18p
390p
390n
A
18.432 MHz
18p
390p
390n
XTI
separate trace
A
XTO
D
VDC2
4u7
1n
D
1u
D
1.5u
1n
PRTRQ
EODQ
PUP
VBAT
SYNC
I2CD
I2CC
CLKO
DCEN
VSENS2
DCSO2
DCSG2
30
29
28
27
26
25
24
23
22
21
20
19
DCSO1
4k7
D
Star point
ground connection
very close to pins
DCSG1 and DCSG2
A
See figure caption
VDC2
4k7
PIO-control
5
Reference
clock
see note on page 69
Option for
I2C-address
connect to
VSS or I2CVDD
17
DCSG1
PRTWQ
18
PR
31
D
32
Place VDD / XVDD -filter
capacitors above ground plane
<3.3 kOhm
VDC1
1.5u
220p
10 11 12 13 14 15 16
VSS
VDC1
POR
9
XVSS
8
VDD
PI15
7
XVDD
6
PI16
5
PI17
4
I2CVDD
2
DVS
PI18
10n
SIC
3
SPDO
MICBI
1
MAS 35x9F
VSENS1
470p capacitorss should be
high-Q (NP0 or C0G)
63
SII
64
62
VREF
PVDD
SID
AVDD1
61
AVSS1
SOC
3u3
3n
60
FILTR
59
8
PCSQ
10n
22u
470p
AVSS0
MPEG, CELP, SC4
e.g. SmartMediaCard
PI19
Place all ceramic capacitors
as close as possible to IC pins
1.5k
100
57
OUTL
58
56
AVDD0
OUTR
55
54
SPDIR
FILTL
53
SPDI1
3
VDC2
Parallel memory device
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
3
SOI
100
1.5k
100n
470p
51
SIBI
52
50
SIBC
SPDI2
49
SIBD
100 k
PI12
Headphone
> 16 Ω
100n
100n
10k
2
D
SOD
22
22
75
75
D
MPEG, SC4
PI13
220u
220u
MPEG (IEC 61937)
IEC 60958
Portable radio
telephone
PI14
R
ADR-receiver
DAB-receiver
DVD-player
DigiAmp
MD-recorder
e.g. SDI-Card
Serial memory device
VDC2
µC
VDC2
DATA SHEET
MAS 35x9F
5. Application
5.1. Typical Application in a Portable Player
− MMC/SDI-Card or SMC/CF2+ used as storage media
− Dashed lines show optional (external) devices
Fig. 5–1: Application circuit of the MAS 35x9F. For connections of the DC/DC converters, please refer to Fig. 5–2.
89
MAS 35x9F
DATA SHEET
5.2. Recommended DC/DC Converter Application Circuit
(Power optimized scenario, (see Fig. 2–7 on page 13)).
VBAT
L1 = 22 µH
DCSO1
D1, Schottky
AVDD0/1
C3 = 330 µF
+
Vin (Input Voltage)
(0.9..1.5 V)
VSENS1
C1 = 330 µF
+
VDC1
e.g. 2.2 V
(low ESR)
MAS 35x9F
DCSG1
VSS, XVSS
D
Power-On Push Button
DCEN
L2 = 22 µH
DCSO2
D2, Schottky
VSENS2
C2 = 330 µF
+
VDC2
e.g. 3.0 V
for µC,
Storage Media
(low ESR)
DCSG2
VREF
AVSS0/1
Star Point
Ground Connection
very close to Pins
DCSG1 and DCSG2
A
A
D
Fig. 5–2: External circuitry for the DC/DC converters
For turn-on voltage of DSP and codec, please refer
to Section 2.11.2.1.
90
June 30, 2004; 6251-505-1DS
Micronas
MAS 35x9F
DATA SHEET
Micronas
June 30, 2004; 6251-505-1DS
91
MAS 35x9F
DATA SHEET
6. Data Sheet History
1. Preliminary data sheet: “MAS 35x9F, MPEG Layer
2/3, AAC Audio Decoder, G.729 Annex A Codec”,
Aug. 01, 2001, 6251-505-1PD. First release of the
preliminary data sheet.
2. Data Sheet: “MAS 35X9F MPEG Layer 2/3, AAC
Audio Decoder, G.729 Annex A Codec”, June 30,
2004, 6251-505-1DS. First release of the data
sheet.
Major changes:
– New package diagrams were included for
PLQFP64-1, PMQFP64-2, PQFN64-1
– Functional description of the MP3 Block Input Mode
now available for improved input timing behavior of
the MPEG 1/2/2.5 Layer3 decoder
– Important advice for turn-on and operating voltage
– Changes in configuration registers
– Tables were added: PIO input DMA mode timing;
Sample rate in MP3; Sample rate in AAC
– Handshake protocol for writing MPEG data to the
PIO-DMA was added.
Micronas GmbH
Hans-Bunte-Strasse 19
D-79108 Freiburg (Germany)
P.O. Box 840
D-79008 Freiburg (Germany)
Tel. +49-761-517-0
Fax +49-761-517-2174
E-mail: [email protected]
Internet: www.micronas.com
Printed in Germany
Order No. 6251-505-1DS
92
All information and data contained in this data sheet are without any
commitment, are not to be considered as an offer for conclusion of a
contract, nor shall they be construed as to create any liability. Any new
issue of this data sheet invalidates previous issues. Product availability
and delivery are exclusively subject to our respective order confirmation
form; the same applies to orders based on development samples delivered. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may
result from its use.
Further, Micronas GmbH reserves the right to revise this publication
and to make changes to its content, at any time, without obligation to
notify any person or entity of such revisions or changes.
No part of this publication may be reproduced, photocopied, stored on a
retrieval system, or transmitted without the express written consent of
Micronas GmbH.
June 30, 2004; 6251-505-1DS
Micronas
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