AD AD8027ARTZ-R21 Low distortion, high speed rail-to-rail input/output amplifier Datasheet

Low Distortion, High Speed
Rail-to-Rail Input/Output Amplifiers
AD8027/AD8028
CONNECTION DIAGRAMS
FEATURES
High speed
190 MHz, –3 dB bandwidth (G = +1)
100 V/μs slew rate
Low distortion
120 dBc @ 1 MHz SFDR
80 dBc @ 5 MHz SFDR
Selectable input crossover threshold
Low noise
4.3 nV/√Hz
1.6 pA/√Hz
Low offset voltage: 900 μV max
Low power: 6.5 mA/amplifier supply current
Power-down mode
No phase reversal: VIN > |VS| + 200 mV
Wide supply range: 2.7 V to 12 V
Small packaging: SOIC-8, SOT-23-6, MSOP-10
APPLICATIONS
Filters
ADC drivers
Level shifting
Buffering
Professional video
Low voltage instrumentation
GENERAL DESCRIPTION
AD8027
AD8027
SOIC-8
(R)
SOT-23-6
(RT)
NC 1
8
DISABLE/SELECT
–IN 2
7
+VS
+IN 3
6
VOUT
–VS 4
5
NC
–VS 2
+IN A 3
+
–
AD8028
AD8028
SOIC-8
(R)
MSOP-10
(RM)
VOUTA 1
–
+
+IN 3
NC = NO CONNECT
–IN A 2
VOUT 1
–VS 4
6
+VS
5
DISABLE/SELECT
4
–IN
VOUTA 1
8
+VS
7
VOUTB
–IN A 2
–
10 +VS
–
6
–IN B
+IN A 3
+
+
5
+IN B
–VS 4
9
VOUTB
–
8
–IN B
+
7
+IN B
6
DISABLE/SELECT B
DISABLE/SELECT A 5
03327-B-001
Figure 1. Connection Diagrams (Top View)
With their wide supply voltage range (2.7 V to 12 V) and wide
bandwidth (190 MHz), the AD8027/AD8028 amplifiers are
designed to work in a variety of applications where speed and
performance are needed on low supply voltages. The high performance of the AD8027/AD8028 is achieved with a quiescent
current of only 6.5 mA/amplifier typical. The AD8027/AD8028
have a shutdown mode that is controlled via the SELECT pin.
The AD8027/AD8028 are available in SOIC-8, MSOP-10, and
SOT-23-6 packages. They are rated to work over the industrial
temperature range of –40°C to +125°C.
The AD8027/AD80281 are high speed amplifiers with rail-torail input and output that operate on low supply voltages and
are optimized for high performance and wide dynamic signal
range. The AD8027/AD8028 have low noise (4.3 nV/√Hz,
1.6 pA/√Hz) and low distortion (120 dBc at 1 MHz). In applications that use a fraction of, or the entire input dynamic range
and require low distortion, the AD8027/AD8028 are ideal
choices.
–20
G = +1
FREQUENCY = 100kHz
RL = 1kΩ
–40
–60
VS = +5V
SFDR (dB)
VS = +3V
VS = ±5V
–80
–100
Many rail-to-rail input amplifiers have an input stage that
switches from one differential pair to another as the input signal
crosses a threshold voltage, which causes distortion. The
AD8027/AD8028 have a unique feature that allows the user to
select the input crossover threshold voltage through the
SELECT pin. This feature controls the voltage at which the
complementary transistor input pairs switch. The AD8027/
AD8028 also have intrinsically low crossover distortion.
–120
–140
0
1
2
3
4
5
6
7
OUTPUT VOLTAGE (V p-p)
8
9
10
03327-A-063
Figure 2. SFDR vs. Output Amplitude
1
Protected by U.S. patent numbers 6,486,737B1; 6,518,842B1
Rev. C
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Fax: 781.461.3113
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IMPORTANT LINKS for the AD8027_8028*
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DOCUMENTATION
PARAMETRIC SELECTION TABLES
AN-649: Using the Analog Devices Active Filter Design Tool
AN-581: Biasing and Decoupling Op Amps in Single Supply
Applications
AN-402: Replacing Output Clamping Op Amps with Input Clamping
Amps
AN-417: Fast Rail-to-Rail Operational Amplifiers Ease Design
Constraints in Low Voltage High Speed Systems
MT-060: Choosing Between Voltage Feedback and Current Feedback
Op Amps
MT-059: Compensating for the Effects of Input Capacitance on VFB
and CFB Op Amps Used in Current-to-Voltage Converters
MT-058: Effects of Feedback Capacitance on VFB and CFB Op Amps
MT-056: High Speed Voltage Feedback Op Amps
MT-053: Op Amp Distortion: HD, THD, THD + N, IMD, SFDR, MTPR
MT-052: Op Amp Noise Figure: Don’t Be Mislead
MT-050: Op Amp Total Output Noise Calculations for Second-Order
System
MT-049: Op Amp Total Output Noise Calculations for Single-Pole
System
MT-047: Op Amp Noise
MT-033: Voltage Feedback Op Amp Gain and Bandwidth
MT-032: Ideal Voltage Feedback (VFB) Op Amp
A Stress-Free Method for Choosing High-Speed Op Amps
FOR THE AD8027
Find Similar Products By Operating Parameters for the AD8027
Find Similar Products By Operating Parameters for the AD8028
High Speed Amplifiers Selection Table
UG-127: Universal Evaluation Board for High Speed Op Amps in
SOT-23-5/SOT-23-6 Packages
UG-101: Evaluation Board User Guide
Op Amps Increasingly Swing Rail-to-Rail
Low-Cost Video Multiplexing Using High-Speed Amplifiers
FOR THE AD8028
DESIGN SUPPORT
Submit your support request here:
AD8028-KGD-CHIP: Low Distortion, High Speed Rail-to-Rail
Input/Output Amplifier Data Sheet
UG-128: Universal Evaluation Board for Dual High Speed Op Amps in
SOIC Packages
EVALUATION KITS & SYMBOLS & FOOTPRINTS
View the Evaluation Boards and Kits page for the AD8027
View the Evaluation Boards and Kits page for the AD8028
Symbols and Footprints for the AD8027
Symbols and Footprints for the AD8028
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DESIGN TOOLS, MODELS, DRIVERS & SOFTWARE
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AD8027/AD8028
TABLE OF CONTENTS
Specifications..................................................................................... 3
Wideband Operation ..................................................................... 19
Absolute Maximum Ratings............................................................ 6
Circuit Considerations .............................................................. 19
Maximum Power Dissipation ..................................................... 6
Applications..................................................................................... 21
ESD Caution.................................................................................. 6
Using the SELECT Pin............................................................... 21
Typical Performance Characteristics ............................................. 8
Driving a 16-Bit ADC................................................................ 21
Theory of Operation ...................................................................... 17
Band-Pass Filter.......................................................................... 22
Input Stage................................................................................... 17
Design Tools and Technical Support ....................................... 22
Crossover Selection .................................................................... 17
Outline Dimensions ....................................................................... 23
Output Stage................................................................................ 18
Ordering Guide .......................................................................... 24
DC Errors .................................................................................... 18
REVISION HISTORY
3/05—Rev. B to Rev. C
Updated Format..................................................................Universal
Change to Figure 1 ........................................................................... 1
10/03—Rev. A to Rev. B
Changes to Figure 1...........................................................................1
8/03—Rev. 0 to Rev. A
Addition of AD8028........................................................... Universal
Changes to GENERAL DESCRIPTION.........................................1
Changes to Figures 1, 3, 4, 8, 13, 15, 17 ......................... 1, 6, 7, 8, 9
Changes to Figures 58, 60........................................................ 18, 20
Changes to SPECIFICATIONS........................................................3
Updated OUTLINE DIMENSIONS .............................................22
Updated ORDERING GUIDE.......................................................23
3/03—Revision 0: Initial Version
Rev. C | Page 2 of 24
AD8027/AD8028
SPECIFICATIONS
VS = ±5 V at TA = 25°C, RL = 1 kΩ to midsupply, G = 1, unless otherwise noted.
Table 1.
Parameter
DYNAMIC PERFORMANCE
–3 dB Bandwidth
Bandwidth for 0.1 dB Flatness
Slew Rate
Settling Time to 0.1%
NOISE/DISTORTION PERFORMANCE
Spurious-Free Dynamic Range (SFDR)
Input Voltage Noise
Input Current Noise
Differential Gain Error
Differential Phase Error
Crosstalk, Output to Output
DC PERFORMANCE
Input Offset Voltage
Input Offset Voltage Drift
Input Bias Current 1
Input Offset Current
Open-Loop Gain
INPUT CHARACTERISTICS
Input Impedance
Input Capacitance
Input Common-Mode Voltage Range
Common-Mode Rejection Ratio
SELECT PIN
Crossover Low, Selection Input Voltage
Crossover High, Selection Input Voltage
Disable Input Voltage
Disable Switching Speed
Enable Switching Speed
OUTPUT CHARACTERISTICS
Output Overdrive Recovery Time
(Rising/Falling Edge)
Output Voltage Swing
Short-Circuit Output
Off Isolation
Capacitive Load Drive
POWER SUPPLY
Operating Range
Quiescent Current/Amplifier
Quiescent Current (Disabled)
Power Supply Rejection Ratio
1
Conditions
Min
Typ
G = 1, VO = 0.2 V p-p
G = 1, VO = 2 V p-p
G = 2, VO = 0.2 V p-p
G = +1, VO = 2 V step/G = −1, VO = 2 V step
G = 2, VO = 2 V step
138
20
190
32
16
90/100
35
MHz
MHz
MHz
V/μs
ns
fC = 1 MHz, VO = 2 V p-p, RF = 24.9 Ω
fC = 5 MHz, VO = 2 V p-p, RF = 24.9 Ω
f = 100 kHz
f = 100 kHz
NTSC, G = 2, RL = 150 Ω
NTSC, G = 2, RL = 150 Ω
G = 1, RL = 100 Ω, VOUT = 2 V p-p,
VS = ±5 V @ 1 MHz
120
80
4.3
1.6
0.1
0.2
−93
dBc
dBc
nV/√Hz
pA/√Hz
%
Degrees
dB
SELECT = three-state or open, PNP active
SELECT = high NPN active
TMIN to TMAX
VCM = 0 V, NPN active
TMIN to TMAX
VCM = 0 V, PNP active
TMIN to TMAX
100
200
240
1.50
4
4
−8
−8
±0.1
110
90
6
2
−5.2 to +5.2
110
MΩ
pF
V
dB
−3.3 to +5
−3.9 to −3.3
−5 to −3.9
980
45
V
V
V
ns
ns
40/45
ns
VO = ±2.5 V
VCM = ±2.5 V
Three-state < ±20 μA
50% of input to <10% of final VO
VI = +6 V to −6 V, G = −1
−VS + 0.10
Sinking and Sourcing
VIN = 0.2 V p-p, f = 1 MHz, SELECT = low
30% overshoot
+VS − 0.06,
−VS + 0.06
120
−49
20
2.7
SELECT = low
VS ± 1 V
90
No sign or a plus sign indicates current into the pin; a minus sign indicates current out of the pin.
Rev. C | Page 3 of 24
6.5
370
110
Max
800
900
6
−11
±0.9
+VS − 0.10
Unit
μV
μV
μV/°C
μA
μA
μA
μA
μA
dB
V
mA
dB
pF
12
8.5
500
V
mA
μA
dB
AD8027/AD8028
VS = 5 V at TA = 25°C, RL = 1 kΩ to midsupply, unless otherwise noted.
Table 2.
Parameter
DYNAMIC PERFORMANCE
−3 dB Bandwidth
Bandwidth for 0.1 dB Flatness
Slew Rate
Settling Time to 0.1%
NOISE/DISTORTION PERFORMANCE
Spurious-Free Dynamic Range (SFDR)
Input Voltage Noise
Input Current Noise
Differential Gain Error
Differential Phase Error
Crosstalk, Output to Output
DC PERFORMANCE
Input Offset Voltage
Input Offset Voltage Drift
Input Bias Current 1
Input Offset Current
Open-Loop Gain
INPUT CHARACTERISTICS
Input Impedance
Input Capacitance
Input Common-Mode Voltage Range
Common-Mode Rejection Ratio
SELECT PIN
Crossover Low, Selection Input Voltage
Crossover High, Selection Input Voltage
Disable Input Voltage
Disable Switching Speed
Enable Switching Speed
OUTPUT CHARACTERISTICS
Overdrive Recovery Time
(Rising/Falling Edge)
Output Voltage Swing
Off Isolation
Short-Circuit Current
Capacitive Load Drive
POWER SUPPLY
Operating Range
Quiescent Current/Amplifier
Quiescent Current (Disabled)
Power Supply Rejection Ratio
1
Conditions
Min
Typ
G = 1, VO = 0.2 V p-p
G = 1, VO = 2 V p-p
G = 2, VO = 0.2 V p-p
G = +1, VO = 2 V step/G = −1, VO = 2 V step
G = 2, VO = 2 V step
131
18
185
28
12
85/100
40
MHz
MHz
MHz
V/μs
ns
fC = 1 MHz, VO = 2 V p-p, RF = 24.9 Ω
fC = 5 MHz, VO = 2 V p-p, RF = 24.9 Ω
f = 100 kHz
f = 100 kHz
NTSC, G = 2, RL = 150 Ω
NTSC, G = 2, RL = 150 Ω
G = 1, RL = 100 Ω, VOUT = 2 V p-p,
VS = ±5 V @ 1 MHz
90
64
4.3
1.6
0.1
0.2
−92
dBc
dBc
nV/√Hz
pA/√Hz
%
Degrees
dB
SELECT = three-state or open, PNP active
SELECT = high NPN active
TMIN to TMAX
VCM = 2.5 V, NPN active
TMIN to TMAX
VCM = 2.5 V, PNP active
TMIN to TMAX
96
200
240
2
4
4
−8
−8
±0.1
105
90
6
2
−0.2 to +5.2
105
MΩ
pF
V
dB
1.7 to 5
1.1 to 1.7
0 to 1.1
1100
50
V
V
V
ns
ns
50/50
ns
VO = 1 V to 4 V
VCM = 0 V to 2.5 V
Three-state < ±20 μA
50% of input to <10% of final VO
VI = −1 V to +6 V, G = −1
RL = 1 kΩ
−VS + 0.08
VIN = 0.2 V p-p, f = 1 MHz, SELECT = low
Sinking and sourcing
30% overshoot
+VS − 0.04,
−VS + 0.04
−49
105
20
2.7
SELECT = low
VS ± 1 V
No sign or a plus sign indicates current into the pin; a minus sign indicates current out of the pin.
Rev. C | Page 4 of 24
90
6
320
105
Max
800
900
6
−11
±0.9
+VS − 0.08
Unit
μV
μV
μV/°C
μA
μA
μA
μA
μA
dB
V
dB
mA
pF
12
8.5
450
V
mA
μA
dB
AD8027/AD8028
VS = 3 V at TA = 25°C, RL = 1 kΩ to midsupply, unless otherwise noted.
Table 3.
Parameter
DYNAMIC PERFORMANCE
–3 dB Bandwidth
Bandwidth for 0.1 dB Flatness
Slew Rate
Settling Time to 0.1%
NOISE/DISTORTION PERFORMANCE
Spurious-Free Dynamic Range (SFDR)
Input Voltage Noise
Input Current Noise
Differential Gain Error
Differential Phase Error
Crosstalk, Output to Output
DC PERFORMANCE
Input Offset Voltage
Input Offset Voltage Drift
Input Bias Current 1
Input Offset Current
Open-Loop Gain
INPUT CHARACTERISTICS
Input Impedance
Input Capacitance
Input Common-Mode Voltage Range
Common-Mode Rejection Ratio
SELECT PIN
Crossover Low, Selection Input Voltage
Crossover High, Selection Input Voltage
Disable Input Voltage
Disable Switching Speed
Enable Switching Speed
OUTPUT CHARACTERISTICS
Output Overdrive Recovery Time
(Rising/Falling Edge)
Output Voltage Swing
Short-Circuit Current
Off Isolation
Capacitive Load Drive
POWER SUPPLY
Operating Range
Quiescent Current/Amplifier
Quiescent Current (Disabled)
Power Supply Rejection Ratio
1
Conditions
Min
Typ
G = 1, VO = 0.2 V p-p
G = 1, VO = 2 V p-p
G = 2, VO = 0.2 V p-p
G = +1, VO = 2 V step/G = –1, VO = 2 V step
G = 2, VO = 2 V step
125
19
180
29
10
73/100
48
MHz
MHz
MHz
V/μs
ns
fC = 1 MHz, VO = 2 V p-p, RF = 24.9 Ω
fC = 5 MHz, VO = 2 V p-p, RF = 24.9 Ω
f = 100 kHz
f = 100 kHz
NTSC, G = 2, RL = 150 Ω
NTSC, G = 2, RL = 150 Ω
G = 1, RL = 100 Ω, VOUT = 2 V p-p,
VS = 3 V @ 1 MHz
85
64
4.3
1.6
0.15
0.20
–89
dBc
dBc
nV/√Hz
pA/√Hz
%
Degrees
dB
SELECT = three-state or open, PNP active
SELECT = high NPN active
TMIN to TMAX
VCM = 1.5 V, NPN active
TMIN to TMAX
VCM = 1.5 V, PNP active
TMIN to TMAX
90
200
240
2
4
4
–8
–8
±0.1
100
88
6
2
–0.2 to +3.2
100
MΩ
pF
V
dB
1.7 to 3
1.1 to 1.7
0 to 1.1
1150
50
V
V
V
ns
ns
55/55
ns
VO = 1 V to 2 V
RL = 1 kΩ
VCM = 0 V to 1.5 V
Three-state < ±20 μA
50% of input to <10% of final VO
VI = –1 V to +4 V, G = –1
RL = 1 kΩ
–VS + 0.07
Sinking and sourcing
VIN = 0.2 V p-p, f = 1 MHz, SELECT = low
30% Overshoot
+VS – 0.03,
–VS + 0.03
72
–49
20
2.7
SELECT = low
VS ± 1 V
88
No sign or a plus sign indicates current into the pin; a minus sign indicates current out of the pin.
Rev. C | Page 5 of 24
6.0
300
100
Max
800
900
6
–11
±0.9
+VS – 0.07
Unit
μV
μV
μV/°C
μA
μA
μA
μA
μA
dB
V
mA
dB
pF
12
8.0
420
V
mA
μA
dB
AD8027/AD8028
ABSOLUTE MAXIMUM RATINGS
Table 4.
Parameter
Supply Voltage
Power Dissipation
Common-Mode Input Voltage
Differential Input Voltage
Storage Temperature
Operating Temperature Range
Lead Temperature Range
(Soldering 10 sec)
Junction Temperature
The power dissipated in the package (PD) is the sum of the
quiescent power dissipation and the power dissipated in the
package due to the load drive for all outputs. The quiescent
power is the voltage between the supply pins (VS) times the
quiescent current (IS). Assuming the load (RL) is referenced to
midsupply, then the total drive power is VS/2 × IOUT, some of
which is dissipated in the package and some in the load (VOUT ×
IOUT). The difference between the total drive power and the load
power is the drive power dissipated in the package.
Rating
12.6 V
See Figure 3
±VS ± 0.5 V
±1.8 V
–65°C to +125°C
–40°C to +125°C
300°C
PD = Quiescent Power + (Total Drive Power − Load Power)
150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
MAXIMUM POWER DISSIPATION
The maximum safe power dissipation in the AD8027/AD8028
package is limited by the associated rise in junction temperature
(TJ) on the die. The plastic encapsulating the die locally reaches
the junction temperature. At approximately 150°C, which is the
glass transition temperature, the plastic changes its properties.
Even temporarily exceeding this temperature limit may change
the stresses that the package exerts on the die, permanently
shifting the parametric performance of the AD8027/AD8028.
Exceeding a junction temperature of 175°C for an extended
period of time can result in changes in the silicon devices,
potentially causing failure.
The still-air thermal properties of the package and PCB (θJA),
ambient temperature (TA), and the total power dissipated in the
package (PD) determine the junction temperature of the die.
The junction temperature can be calculated as
(
TJ = TA + PD × θ JA
⎛V V
PD = (VS × I S )+ ⎜⎜ S × OUT
RL
⎝ 2
⎞ VOUT 2
⎟–
⎟
RL
⎠
RMS output voltages should be considered. If RL is referenced
to VS−, as in single-supply operation, then the total drive power
is VS × IOUT.
If the rms signal levels are indeterminate, then consider the
worst case, when VOUT = VS/4 for RL to midsupply.
PD = (VS × I S ) +
(VS /4 )2
RL
In single-supply operation with RL referenced to VS–, worst case
is VOUT = VS/2.
Airflow increases heat dissipation, effectively reducing θJA. Also,
more metal directly in contact with the package leads from
metal traces, through holes, ground, and power planes reduces
the θJA. Care must be taken to minimize parasitic capacitances
at the input leads of high speed op amps, as discussed in the
PCB Layout section.
)
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. C | Page 6 of 24
AD8027/AD8028
Output Short Circuit
Shorting the output to ground or drawing excessive current
from the AD8027/AD8028 can likely cause catastrophic failure.
2.0
MAXIMUM POWER DISSIPATION (W)
Figure 3 shows the maximum safe power dissipation in the
package vs. the ambient temperature for the SOIC-8
(125°C/W), SOT-23-6 (170°C/W), and MSOP-10 (130°C/W)
packages on a JEDEC standard 4-layer board.
1.5
SOIC-8
1.0
MSOP-10
SOT-23-6
0.5
0
–55
–35
–15
5
25
45
65
85
AMBIENT TEMPERATURE (°C)
105
125
03327-A-002
Figure 3. Maximum Power Dissipation vs. Ambient Temperature
Rev. C | Page 7 of 24
AD8027/AD8028
TYPICAL PERFORMANCE CHARACTERISTICS
Default conditions: VS = 5 V at TA = 25°C, RL = 1 kΩ, unless otherwise noted.
2
8
AD8027
G = +1
VOUT = 200mV p-p
G = +2
7 VOUT = 200mV p-p
0
6
–1
5
CLOSED-LOOP GAIN (dB)
NORMALIZED CLOSED-LOOP GAIN (dB)
1
–2
–3
G = +2
–4
AD8028
G = +1
–5
G = +10
–6
–7
G = –1
1
10
FREQUENCY (MHz)
100
–1
–4
0.1
1000
10
FREQUENCY (MHz)
100
1000
03327-A-006
Figure 7. Small Signal Frequency Response for Various Supplies
2
G = +1
1 VOUT = 200mV p-p
VS = +3V
0
–1
–2
CLOSED-LOOP GAIN (dB)
0
–1
VS = ±5V
–3
–4
–5
–6
–7
–8
VS = +3V
–2
–3
–4
–5
–6
–7
VS = +5V
–8
VS = +5V
–9
1
10
FREQUENCY (MHz)
100
–9
–10
0.1
1000
VS = ±5V
1
03327-A-004
Figure 5. AD8027 Small Signal Frequency Response for Various Supplies
10
FREQUENCY (MHz)
100
1000
03327-A-007
Figure 8. AD8028 Small Signal Frequency Response for Various Supplies
2
8
G = +2
7 VOUT = 2V p-p
G = +1
1 VOUT = 2V p-p
0
6
CLOSED-LOOP GAIN (dB)
VS = ±5V
–1
–2
–3
VS = +3V
–4
–5
–6
–7
–8
5
VS = ±5V
4
3
VS = +5V
2
1
0
VS = +3V
–1
–2
VS = +5V
–9
–10
0.1
1
03327-A-003
G = +1
VS = +3V RF = 24.9Ω
1 VOUT = 200mV p-p
–10
0.1
VS = ±5V
0
–3
2
CLOSED- LOOP GAIN (dB)
2
–2
Figure 4. Small Signal Frequency Response for Various Gains
CLOSED-LOOP GAIN (dB)
3
–9
1
VS = +5V
4
–8
–10
0.1
VS = +3V
1
10
FREQUENCY (MHz)
–3
100
–4
0.1
1000
03327-A-005
Figure 6. Large Signal Frequency Response for Various Supplies
1
10
FREQUENCY (MHz)
100
1000
03327-A-008
Figure 9. Large Signal Frequency Response for Various Supplies
Rev. C | Page 8 of 24
AD8027/AD8028
4
3
G = +1
3 VOUT = 200mV p-p
2
CL = 5pF
0
–1
–2
–3
CL = 0pF
–4
–5
–6
1
10
FREQUENCY (MHz)
–3
CL = 0pF
–4
–5
–6
–7
100
1000
G = +2
100
1000
03327-A-012
VOUT = 0.2V p-p
RL = 150Ω
7
6
5
5
CLOSED-LOOP GAIN (dB)
6
4
3
VOUT = 2V p-p
1
10
FREQUENCY (MHz)
Figure 13. AD8028 Small Signal Frequency Response for Various CLOAD
VOUT = 200mV p-p
2
1
03327-A-009
8
G = +2
7
CLOSED-LOOP GAIN (dB)
–2
–10
0.1
Figure 10. AD8027 Small Signal Frequency Response for Various CLOAD
0
–1
VOUT = 0.2V p-p
RL = 1kΩ
4
3
VOUT = 2.0V p-p
RL = 150Ω
2
1
0
–1
–2
–2
VOUT = 4V p-p
–3
–4
0.1
1
10
FREQUENCY (MHz)
100
–4
0.1
1000
1
0
0
CLOSED-LOOP GAIN (dB)
1
–1
–2
–40°C
–3
+125°C
–4
–5
+25°C
10
FREQUENCY (MHz)
100
100
1000
03327-A-013
–1
–2
–3
+125°C
–4
–5
–40°C
–6
G = +1
VOUT = 200mV p-p
1
10
FREQUENCY (MHz)
Figure 14. Small Signal Frequency Response for Various RLOAD Values
2
–6
1
03327-A-010
2
–8
0.1
VOUT = 2.0V p-p
RL = 1kΩ
–3
Figure 11. Frequency Response for Various Output Amplitudes
CLOSED-LOOP GAIN (dB)
–1
–9
–8
0.1
–7
CL = 5pF
–8
–7
8
CL = 20pF
0
1
CLOSED-LOOP GAIN (dB)
CLOSED-LOOP GAIN (dB)
G = +1
2 VOUT = 200mV p-p
1
CL = 20pF
–7 G = +1
VOUT = 200mV p-p
–8
0.1
1
1000
03327-A-011
+25°C
10
FREQUENCY (MHz)
100
1000
03327-A-014
Figure 15. AD8028 Small Signal Frequency Response vs. Temperature
Figure 12. AD8027 Small Signal Frequency Response vs. Temperature
Rev. C | Page 9 of 24
AD8027/AD8028
4
100
2
VOLTAGE NOISE (nV/ Hz)
0
–1
VICM = VS– + 0.2V
SELECT = TRI
–2
–3
–4
VICM = 0V
SELECT = HIGH OR TRI
–5
100
VICM = VS+ – 0.3V
SELECT = HIGH
VICM = VS+ – 0.2V
SELECT = HIGH
1
CLOSED-LOOP GAI (dB)
VICM = VS– + 0.3V
SELECT = TRI
10
10
VOLTAGE
CURRENT NOISE (pA/ Hz)
G = +1
3 VOUT = 200mV p-p
CURRENT
–6
–7
–8
0.1
1
10
FREQUENCY (MHz)
100
1
10
1000
V1
VI
+
R2
50Ω
U1
+
1/2
AD8028
10k
R3
1kΩ
100k
1M
10M
1
1G
100M
FREQUENCY (Hz)
03327-A-018
Figure 19. Voltage and Current Noise vs. Frequency
U2
1/2
AD8028
–
1k
03327-A-015
Figure 16. Small Signal Frequency Response vs.
Input Common-Mode Voltages
R1
50Ω
100
6.9
VOUT
G = +2
6.8 RL = 150Ω
–
CLOSED-LOOP GAIN (dB)
6.7
CROSSTALK = 20log (VOUT/VIN)
–10
–20
–30
–40
CROSSTALK (dB)
–50
–60
–70
VOUT = 200mV p-p
6.6
6.5
6.4
6.3
6.2
VOUT = 2V p-p
6.1
–80
B TO A
–90
6.0
A TO B
5.9
0.1
–100
–110
G = +1
VS = 5V
RL = 1kΩ
–120
–130
–140
0.001
0.01
0.1
1
10
FREQUENCY (MHz)
100
1
10
FREQUENCY (MHz)
1000
100
03327-A-019
Figure 20. 0.1 dB Flatness Frequency Response
1000
03327-A-016
Figure 17. AD8028 Crosstalk Output to Output
110
100
135
GAIN
–20
G = +1
VOUT = 2V p-p
RL = 1kΩ
–40
SECOND HARMONIC: SOLID LINE
THIRD HARMONIC: DASHED LINE
115
90
PHASE
75
60
50
55
40
35
30
20
DISTORTION (dB)
95
70
PHASE (Degrees)
OPEN-LOOP GAIN (dB)
80
–60
VS = +3V
–80
–100
VS = +5V
15
10
–120
–5
VS = ±5V
0
–10
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
10M
100M
–25
1G
–140
0.1
03327-A-017
Figure 18. Open-Loop Gain and Phase vs. Frequency
1
FREQUENCY (MHz)
10
20
03327-A-020
Figure 21. Harmonic Distortion vs. Frequency and Supply Voltage
Rev. C | Page 10 of 24
AD8027/AD8028
–20
–45
G = +1 (RF = 24.9Ω)
FREQUENCY = 100kHz
RL = 1kΩ
–40
G = +1 (RF = 24.9Ω)
VOUT = 1.0V p-p @ 2MHz
–55
SELECT = TRI
SELECT = HIGH
–60
VS = +5V
VS = +3V
DISTORTION (dB)
DISTORTION (dB)
–65
VS = ±5V
–80
–100
–75
–85
–95
–105
–120
SECOND HARMONIC: SOLID LINE
THIRD HARMONIC: DASHED LINE
–140
0
1
2
3
4
5
6
7
OUTPUT VOLTAGE (V p-p)
8
9
1.0
03327-A-021
1.5
2.0
2.5
3.0
3.5
INPUT COMMON-MODE VOLTAGE (V)
4.0
4.5
03327-A-024
Figure 25. Harmonic Distortion vs. Input Common-Mode Voltage, VS = 5 V
Figure 22. Harmonic Distortion vs. Output Amplitude
–50
–50
–60
SECOND HARMONIC: SOLID LINE
THIRD HARMONIC: DASHED LINE
–125
0.5
10
SELECT = HIGH
SELECT = TRI
–115
G = +1 (RF = 24.9Ω)
VOUT = 1.0V p-p @ 100kHz
RL = 1kΩ
–60
G = +1 (RF = 24.9Ω)
VOUT = 1.0V p-p @ 100kHz
VS = +3V
VS = +5V
VS = +5V
–70
–70
DISTORTION (dB)
DISTORTION (dB)
VS = +3V
–80
–90
–100
–110
–140
0.5
–110
1.0
1.5
2.0
2.5
3.0
3.5
INPUT COMMON-MODE VOLTAGE (V)
4.0
–140
0.5
4.5
03327-A-022
SECOND HARMONIC: SOLID LINE
THIRD HARMONIC: DASHED LINE
1.0
1.5
2.0
2.5
3.0
3.5
INPUT COMMON-MODE VOLTAGE (V)
4.0
4.5
03327-A-025
Figure 26. Harmonic Distortion vs. Input Common-Mode Voltage,
SELECT = Three-State or Open
–20
–20
G = +1 (RF = 24.9Ω)
VOUT = 2.0V p-p
SECOND HARMONIC: SOLID LINE
–40 THIRD HARMONIC: DASHED LINE
VS = +5
VOUT = 2.0V p-p
SECOND HARMONIC: SOLID LINE
–40 THIRD HARMONIC: DASHED LINE
RL = 1kΩ
–60
DISTORTION (dB)
DISTORTION (dB)
–100
–130
SECOND HARMONIC: SOLID LINE
THIRD HARMONIC: DASHED LINE
Figure 23. Harmonic Distortion vs. Input Common-Mode Voltage,
SELECT = High
–80
RL = 150Ω
–100
G = +2
–60
G = +10
G = +1
–80
–100
–120
–120
–140
0.1
–90
–120
–120
–130
–80
1
FREQUENCY (MHz)
10
–140
0.1
20
03327-A-023
1
FREQUENCY (MHz)
10
Figure 27. Harmonic Distortion vs. Frequency and Gain
Figure 24. Harmonic Distortion vs. Frequency and Load
Rev. C | Page 11 of 24
20
03327-A-026
AD8027/AD8028
0.20
0.15
0.20
G = +1
VS = ± 2.5V
0.15
0.10
0.10
0.05
0.05
0
0
–0.05
–0.05
–0.10
–0.10
–0.15
G = +1
VS = ±2.5V
CL = 20pF
CL = 5pF
–0.15
50mV/DIV
50mV/DIV
20ns/DIV
–0.20
03327-A-027
03327-A-030
Figure 28. Small Signal Transient Response
2.0
20ns/DIV
–0.20
G = +1
VS = ±2.5V
Figure 31. Small Signal Transient Response with Capacitive Load
4.0
G = –1
3.5
RL = 1kΩ
3.0 V = ±2.5V
S
2.5
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
–3.5
500mV/DIV
–4.0
VOUT = 4V p-p
VOUT = 2V p-p
1.0
0
–1.0
–2.0
500mV/DIV
100ns/DIV
03327-A-028
50ns/DIV
03327-A-031
Figure 29. Large Signal Transient Response, G = +1
Figure 32. Output Overdrive Recovery
2.5
G = +2
2.0 VS = ±2.5V
4.0
G = +1
3.5
RL = 1kΩ
3.0 V = ±2.5V
S
2.5
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
–3.5
500mV/DIV
–4.0
VOUT = 4V p-p
1.5
VOUT = 2V p-p
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
50mV/DIV
–2.5
20ns/DIV
03327-A-029
50ns/DIV
03327-A-032
Figure 30. Large Signal Transient Response, G = +2
Figure 33. Input Overdrive Recovery
Rev. C | Page 12 of 24
AD8027/AD8028
–10
–8
G = +2
SELECT = TRI
–6
INPUT BIAS CURRENT (μA)
VIN (200mV/DIV)
+0.1%
VOUT – 2VIN (2mV/DIV)
–0.1%
–4
–2
VS = +5V
VS = ±5V
0
2
4
VS = +3V
6
SELECT = HIGH
8
10
5μs/DIV
0
1
2
3
4
5
6
7
8
INPUT COMMON-MODE VOLTAGE (V)
03327-A-033
Figure 34. Long-Term Settling Time
9
10
03327-A-036
Figure 37. Input Bias Current vs. Input Common-Mode Voltage
250
VIN (200mV/DIV)
FREQUENCY
200
VOUT (400mV/DIV)
+0.1%
COUNT = 1780
SELECT HIGH
MEAN
49μV
STD. DEV 193μV
TRI
55μV
150μV
SELECT = TRI
150
SELECT = HIGH
100
–0.1%
VOUT – 2VIN (0.1%/DIV)
50
0
–800
20ns/DIV
–600
–400
Figure 35. 0.1% Short-Term Settling Time
0
200
400
600
800
03327-A-037
Figure 38. Input Offset Voltage Distribution
–6.5
4.5
360
340
SELECT = HIGH
3.5 VS = ±5V
VS = +3V
3.0
2.5
–40
–7.5
VS = +5V
–8.0
SELECT = TRI
–25
–10
5
20
35
50
65
TEMPERATURE (°C)
80
95
110
–8.5
125
320
300
INPUT OFFSET VOLTAGE (μV)
–7.0
4.0
INPUT BIAS CURRENT (SELECT = TRI) (μA)
INPUT BIAS CURRENT (SELECT = HIGH) (μA)
–200
INPUT OFFSET VOLTAGE (μV)
03327-A-034
280
260
240
Figure 36. Input Bias Current vs. Temperature
VS = +3V
220
SELECT = HIGH
200
180
VS = +5V
160
140
120
100
80
60
–40
03327-A-035
SELECT = TRI
VS = ±5V
–25
–10
5
20
35
50
65
TEMPERATURE (°C)
80
95
Figure 39. Input Offset Voltage vs. Temperature
Rev. C | Page 13 of 24
110
125
03327-A-038
AD8027/AD8028
120
290
VS = ±5V
100
SELECT = HIGH
250
80
CMRR (dB)
INPUT OFFSET VOLTAGE (μV)
270
230
210
SELECT = TRI
60
40
190
20
170
150
–5
–4
–3
–2
–1
0
1
2
3
INPUT COMMON-MODE VOLTAGE (V)
4
0
1k
5
10k
100k
1M
FREQUENCY (Hz)
03327-A-039
10M
100M
03327-A-042
Figure 43. CMRR vs. Frequency
Figure 40. Input Offset Voltage vs. Input Common-Mode Voltage, VS = ±5
290
0
VS = +5V
–10
270
–30
SELECT = HIGH
–40
230
PSSR (dB)
INPUT OFFSET VOLTAGE (μV)
–20
250
210
SELECT = TRI
190
–PSRR
–50
+PSRR
–60
–70
–80
–90
170
–100
–110
100
150
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
INPUT COMMON-MODE VOLTAGE (V)
4.5
5.0
1k
10k
03327-A-040
100k
1M
FREQUENCY (Hz)
10M
100M
1G
03327-A-043
Figure 44. PSRR vs. Frequency
Figure 41. Input Offset Voltage vs. Input Common-Mode Voltage, VS = 5
–20
270
VIN = 0.2V p-p
G = +1
–30 SELECT = LOW
VS = +3V
–40
SELECT = HIGH
OFF ISOLATION (dB)
INPUT OFFSET VOLTAGE (μV)
250
230
210
SELECT = TRI
190
–50
–60
–70
–80
170
–90
–100
10k
150
0
0.50
1.00
1.50
2.00
2.50
3.00
INPUT COMMON-MODE VOLTAGE (V)
03327-A-041
Figure 42. Input Offset Voltage vs. Input Common-Mode Voltage, VS = 3
Rev. C | Page 14 of 24
100k
1M
10M
FREQUENCY (Hz)
100M
Figure 45. Off Isolation vs. Frequency
1G
03327-A-044
AD8027/AD8028
200
130
LOAD RESISTANCE TIED
TO MIDSUPPLY
OUTPUT SATURATION VOLTAGE (mV)
150
120
OPEN-LOOP GAIN (dB)
100
VOL – VS–
50
VS = +3V
0
VS = +5V VS = ±5V
–50
VOH – VS+
–100
±5V
110
+5V
100
+3V
90
80
70
–150
–200
100
60
1000
LOAD RESISTANCE (Ω)
10000
0
10
20
30
ILOAD (mA)
03327-A-045
Figure 46. Output Saturation Voltage vs. Output Load
40
50
60
03327-A-048
Figure 49. Open-Loop Gain vs. Load Current
100
1M
SELECT = LOW
100k
1
OUTPUT IMPEDANCE (Ω)
OUTPUT IMPEDANCE (Ω)
10
G = +5
0.1
G = +2
G = +1
0.001
1k
10k
100k
1M
10M
FREQUENCY (Hz)
100M
10
100k
1G
1M
03327-A-046
Figure 47. Output Enabled— Impedance vs. Frequency
10M
FREQUENCY (Hz)
100M
1G
03327-A-049
Figure 50. Output Disabled—Impedance vs. Frequency
80
VS = +5V
RL = 1kΩ TIED TO MIDSUPPLY
VS = +5V
+125°C
60
40
VS = +10V
@ +25°C
40
SELECT CURRENT (μA)
OUTPUT SATURATION VOLTAGE (mV)
1k
100
0.01
45
10k
VOL – VS–
35
VS+ – VOH
30
+25°C
20
–40°C
0
–20
–40
–60
25
–40
–25
–10
5
20
35
50
65
TEMPERATURE (°C)
80
95
110
–80
125
0
03327-A-047
Figure 48. Output Saturation Voltage vs. Temperature
0.5
1.0
1.5
2.0
SELECT VOLTAGE (V)
Figure 51. SELECT Pin Current vs.
SELECT Pin Voltage and Temperature
Rev. C | Page 15 of 24
2.5
3.0
03327-A-050
AD8027/AD8028
9.0
1.5
SELECT PIN (–2.0V TO –0.5V)
8.5
1.0
8.0
SUPPLY CURRENT (mA)
OUTPUT VOLTAGE (V)
OUTPUT
0.5
RL = 100Ω
0
RL = 1kΩ
–0.5
RL = 10kΩ
VS = ±5V
7.0
VS = +5V
6.5
VS = +3V
6.0
5.5
5.0
–1.0
G = –1
VS = ±2.5V
VIN = –1.0V
4.5
–1.5
0
50
100
150
TIME (ns)
200
4.0
–40
250
03327-A-051
Figure 52. Enable Turn-On Timing
SELECT PIN (–2.0V TO –0.5V)
1.0
OUTPUT
0.5
RL = 100Ω
0
RL = 1kΩ
–0.5
RL = 10kΩ
–1.0
G = –1
VS = ±2.5V
VIN = –1.0V
–1.5
0.5 1
2
3
4
5
6
TIME (μs)
7
–25
–10
5
20
35
50
65
TEMPERATURE (°C)
80
95
110
125
03327-A-053
Figure 54. Quiescent Supply Current vs. Supply Voltage and Temperature
1.5
OUTPUT VOLTAGE (V)
7.5
8
9
10
03327-A-052
Figure 53. Disable Turn-Off Timing
Rev. C | Page 16 of 24
AD8027/AD8028
THEORY OF OPERATION
The NPN input pair can now operate at 200 mV above the
positive rail. Both input pairs are protected from differential
input signals above 1.4 V by four diodes across the input (see
Figure 55). In the event of differential input signals that exceed
1.4 V, the diodes conduct and excessive current flows through
them. A series input resistor should be included to limit the
input current to 10 mA.
The AD8027/AD8028 are rail-to-rail input/output amplifiers
designed in the Analog Devices XFCB process. The XFCB
process enables the AD8027/AD8028 to run on 2.7 V to 12 V
supplies with 190 MHz of bandwidth and over 100 V/μs of slew
rate. The AD8027/AD8028 have 4.3 nV/√Hz of wideband noise
with 17 nV/√Hz noise at 10 Hz. This noise performance, with
an offset and drift performance of less than 900 μV maximum
and 1.5 μV/°C typical, respectively, makes the AD8027/AD8028
ideal for high speed, precision applications. Additionally, the
input stage operates 200 mV beyond the supply rails and shows
no phase reversal. The amplifiers feature overvoltage protection
on the input stage. Once the inputs exceed the supply rails by
0.7 V, ESD protection diodes are turned on, drawing excessive
current through the differential input pins. A series input
resistor should be included to limit the input current to less
than 10 mA.
CROSSOVER SELECTION
The AD8027/AD8028 have a feature called crossover selection,
which allows the user to choose the crossover point between the
PNP/NPN differential pairs. Although the crossover region is
small, operating in this region should be avoided, because it can
introduce offset and distortion to the output signal. To help
avoid operating in the crossover region, the AD8027/AD8028
allow the user to select from two preset crossover locations
(voltage levels) using the SELECT pin. As shown in Figure 55,
the crossover region is about 200 mV and is defined by the
voltage level at the base of Q5. Internally, two separate voltage
sources are created approximately 1.2 V from either rail. One or
the other is connected to Q5, based on the voltage applied to the
SELECT pin. This allows either dominant PNP pair operation,
when the SELECT pin is left open, or dominant NPN pair
operation, when the SELECT pin is pulled high.
INPUT STAGE
The rail-to-rail input performance is achieved by operating
complementary input pairs. Which pair is on is determined by
the common-mode level of the differential input signal. As
shown in Figure 55, a tail current (ITAIL) is generated that
sources the PNP differential input structure consisting of Q1
and Q2. A reference voltage is generated internally that is
connected to the base of Q5. This voltage is continually compared against the common-mode input voltage. When the
common-mode level exceeds the internal reference voltage,
Q5 diverts the tail current (ITAIL) from the PNP input pair to a
current mirror that sources the NPN input pair consisting of
Q3 and Q4.
The SELECT pin also provides the traditional power-down
function when it is pulled low. This allows the designer to
achieve the best precision and ac performance for high-side and
low-side signal applications. See Figure 50 through Figure 53 for
SELECT pin characteristics.
VCC
+
ITAIL
1.2V
–
VOUTP
ICMFB
Q5
Q3
Q1
Q2
Q4
VN
VP
VSEL
VEE
LOGIC
VCC
ICMFB
+
1.2V
–
VEE
03327-A-054
Figure 55. Simplified Input Stage
Rev. C | Page 17 of 24
VOUTN
AD8027/AD8028
In the event that the crossover region cannot be avoided,
specific attention has been given to the input stage to ensure
constant transconductance and minimal offset in all regions of
operation. The regions are PNP input pair running, NPN input
pair running, and both running at the same time (in the
200 mV crossover region). Maintaining constant transconductance in all regions ensures the best wideband distortion
performance when going between these regions. With this
technique, the AD8027/AD8028 can achieve greater than 80 dB
SFDR for a 2 V p-p, 1 MHz, and G = 1 signal on ±1.5 V
supplies. Another requirement needed to achieve this level of
distortion is that the offset of each pair must be laser trimmed
to achieve greater than 80 dB SFDR, even for low frequency
signals.
The size of the discontinuity is defined as
(
B
DC ERRORS
The AD8027/AD8028 use two complementary input stages to
achieve rail-to-rail input performance, as mentioned in the
Input Stage section. To use the dc performance over the entire
common-mode range, the input bias current and input offset
voltage of each pair must be considered.
Because the input pairs are complementary, the input bias current reverses polarity when going through the crossover region
shown in Figure 37. The offset between pairs is described by
(
⎞
⎟,
⎟
⎠
⎛ R + RF
VOS , NPN ,OUT = VOS , NPN ⎜⎜ G
⎝ RG
⎞
⎟
⎟
⎠
)
⎡ ⎛ R + RF ⎞
⎤
⎟ − RF ⎥
VOS,PNP − VOS,NPN = I B, PNP − I B, NPN × ⎢RS ⎜⎜ G
⎟
⎣⎢ ⎝ RG ⎠
⎦⎥
IB, PNP is the input bias current of either input when the PNP
input pair is active, and IB, NPN is the input bias current of either
input pair when the NPN pair is active. If RS is sized so that
when multiplied by the gain factor it equals RF, this effect is
eliminated. It is strongly recommended to balance the impedances in this manner when traveling through the crossover
region to minimize the dc error and distortion. As an example,
assuming that the PNP input pair has an input bias current of
6 μA and the NPN input pair has an input bias current of
−2 μA, a 200 μV shift in offset occurs when traveling through
the crossover region with RF equal to 0 Ω and RS equal to 25 Ω.
In addition to the input bias current shift between pairs, each
input pair has an input bias current offset that contributes to the
total offset in the following manner:
Referring to Figure 56, the output offset voltage of each pair is
calculated by
⎛ R + RF
VOS , PNP ,OUT = VOS , PNP ⎜⎜ G
⎝ RG
⎞
⎟
⎟
⎠
Using the crossover select feature of the AD8027/AD8028 helps
to avoid this region. In the event that the region cannot be
avoided, the quantity (VOS, PNP – VOS, NPN) is trimmed to minimize
this effect.
OUTPUT STAGE
The AD8027/AD8028 use a common-emitter output structure
to achieve rail-to-rail output capability. The output stage is
designed to drive 50 mA of linear output current, 40 mA within
200 mV of the rail, and 2.5 mA within 35 mV of the rail.
Loading of the output stage, including any possible feedback
network, lowers the open-loop gain of the amplifier. Refer to
Figure 49 for the loading behavior. Capacitive load can degrade
the phase margin of the amplifier. The AD8027/AD8028 can
drive up to 20 pF, G = 1, as shown in Figure 10. A small (25 Ω
to 50 Ω) series resistor, RSNUB, should be included, if the
capacitive load is to exceed 20 pF for a gain of 1. Increasing the
closed-loop gain increases the amount of capacitive load that
can be driven before a series resistor needs to be included.
)
⎛ R + RF
VDIS = VOS, PNP − VOS, NPN × ⎜⎜ G
⎝ RG
⎛ R + RF
ΔVOS = I B + RS ⎜⎜ G
⎝ RG
⎞
⎟ − I B − RF
⎟
⎠
RF
RG
+
VOS
+V
–
IB–
–
VI
+
RS
–
SELECT
+
IB +
VOUT
+
–
AD8027/
AD8028
–V
03327-A-055
Figure 56. Op Amp DC Error Sources
where the difference of the two is the discontinuity experienced
when going through the crossover region.
Rev. C | Page 18 of 24
AD8027/AD8028
WIDEBAND OPERATION
CF
Voltage feedback amplifiers can use a wide range of resistor
values to set their gain. Proper design of the application’s
feedback network requires consideration of the following issues:
•
+V
Poles formed by the amplifier’s input capacitances with the
resistances seen at the amplifier’s input terminals
•
Effects of mismatched source impedances
•
Resistor value impact on the application’s voltage noise
•
RF
RG
VIN
With a wide bandwidth of over 190 MHz, the AD8027/AD8028
have numerous applications and configurations. The AD8027/
AD8028 part shown in Figure 57 is configured as a noninverting amplifier. An easy selection table of gain, resistor values,
bandwidth, slew rate, and noise performance is presented in
Table 5, and the inverting configuration is shown in Figure 58.
RF
+V
C1
0.1μF
C5
C3
10μF
03327-A-057
CIRCUIT CONSIDERATIONS
Balanced Input Impedances
Balanced input impedances can help to improve distortion
performance. When the amplifier transitions from PNP pair to
NPN pair operation, a change in both the magnitude and
direction of the input bias current occurs. When multiplied
times imbalanced input impedances, a change in offset can
result. The key to minimizing this distortion is to keep the input
impedances balanced on both inputs. Figure 59 shows the effect
of the imbalance and degradation in distortion performance for
a 50 Ω source impedance, with and without a 50 Ω balanced
feedback path.
G = +1
VOUT = 2V p-p
–30 RL = 1kΩ
VS = +3V
VOUT
–40
SELECT
DISTORTION (dB)
C3
10μF
C4
0.1μF
–V
C4
0.1μF
–20
AD8027/
AD8028
R1 = RF||RG
R1
SELECT
Figure 58. Wideband Inverting Gain Configuration
–
+
VOUT
–V
C2
10μF
RG
VIN
–
+
Amplifier loading effects
R1
C2
10μF
AD8027/
AD8028
R1 = RF||RG
The AD8027/AD8028 have an input capacitance of 2 pF. This
input capacitance forms a pole with the amplifier’s feedback
network, destabilizing the loop. For this reason, it is generally
desirable to keep the source resistances below 500 Ω, unless
some capacitance is included in the feedback network. Likewise,
keeping the source resistances low also takes advantage of the
AD8027/AD8028’s low input referred voltage noise of
4.3 nV/√Hz.
C1
0.1μF
03327-A-056
–50
–60
RF = 0Ω
–70
RF = 24.9Ω
–80
Figure 57. Wideband Noninverting Gain Configuration
–90
RF = 49.9Ω
Table 5. Component Values, Bandwidth, and Noise
Performance (VS = ±2.5 V)
Noise Gain
(Noninverting)
1
2
10
RSOURCE
(Ω)
50
50
50
RF
(Ω)
0
499
499
RG
(Ω)
N/A
499
54.9
–3 dB
SS BW
(MHz)
190
95
13
–100
0.1
Output
Noise with
Resistors
(nV/√Hz)
4.4
10
45
Rev. C | Page 19 of 24
1
FREQUENCY (MHz)
Figure 59. SFDR vs. Frequency and Various RF
10
20
03327-A-058
AD8027/AD8028
PCB Layout
As with all high speed op amps, achieving optimum performance from the AD8027/AD8028 requires careful attention to
PCB layout. Particular care must be exercised to minimize lead
lengths of the bypass capacitors. Excess lead inductance can
influence the frequency response and even cause high
frequency oscillations. The use of a multilayer board with an
internal ground plane can reduce ground noise and enable a
tighter layout.
The length of the high frequency bypass capacitor pads and
traces is critical. A parasitic inductance in the bypass grounding
works against the low impedance created by the bypass
capacitor. Because load currents flow from supplies as well as
ground, the load should be placed at the same physical location
as the bypass capacitor ground. For large values of capacitors,
which are intended to be effective at lower frequencies, the
current return path length is less critical.
Power-Supply Bypassing
To achieve the shortest possible lead length at the inverting
input, the feedback resistor, RF, should be located beneath the
board and span the distance from the output, Pin 6, to the
input, Pin 2. The return node of the resistor, RG, should be
situated as closely as possible to the return node of the negative
supply bypass capacitor connected to Pin 4.
Power-supply pins are actually inputs, and care must be taken to
provide a clean, low noise, dc voltage source to these inputs.
The bypass capacitors have two functions:
•
Provide a low impedance path for unwanted frequencies
from the supply inputs to ground, thereby reducing the
effect of noise on the supply lines.
On multilayer boards, all layers underneath the op amp should
be cleared of metal to avoid creating parasitic capacitive
elements. This is especially true at the summing junction
(the −input). Extra capacitance at the summing junction can
cause increased peaking in the frequency response and lower
phase margin.
•
Provide sufficient localized charge storage, for fast switching
conditions and minimizing the voltage drop at the supply
pins and the output of the amplifier. This is usually accomplished with larger electrolytic capacitors.
Grounding
To minimize parasitic inductances and ground loops in high
speed, densely populated boards, a ground plane layer is critical.
Understanding where the current flows in a circuit is critical in
the implementation of high speed circuit design. The length of
the current path is directly proportional to the magnitude of the
parasitic inductances and, therefore, the high frequency
impedance of the path. Fast current changes in an inductive
ground return can create unwanted noise and ringing.
Decoupling methods are designed to minimize the bypassing
impedance at all frequencies. This can be accomplished with a
combination of capacitors in parallel to ground.
Good-quality ceramic chip capacitors should be used and
always kept as close as possible to the amplifier package . A
parallel combination of a 0.01 μF ceramic and a 10 μF electrolytic covers a wide range of rejection for unwanted noise. The
10 μF capacitor is less critical for high frequency bypassing, and,
in most cases, one per supply line is sufficient.
Rev. C | Page 20 of 24
AD8027/AD8028
APPLICATIONS
USING THE SELECT PIN
The AD8027/AD8028’s unique SELECT pin has two functions:
•
The power-down function places the AD8027/AD8028 into
low power consumption mode. In power-down mode, the
amplifiers draw 450 μA (typical) of supply current.
•
The second function, as mentioned in the Theory of
Operation section, shifts the crossover point (where the
NPN/PNP input differential pairs transition from one to the
other) closer to either the positive supply rail or the negative
supply rail. This selectable crossover point allows the user to
minimize distortion based on the input signal and environment. The default state is 1.2 V from the positive power
supply, with the SELECT pin left floating or in three-state.
In this application, the SELECT pins are biased to avoid the
crossover region of the AD8028 for low distortion operation.
Summary test data for the schematic shown in Figure 60 is
listed in Table 8.
+5V
0.1μF
–
15Ω
AD8028
ANALOG INPUT +
INPUT RANGE
(0.15V TO 2.65V)
4MHz LPF +5V
2.7nF
+
SELECT
(OPEN)
+5V
AD7677
16 BITS
0.1μF
–
Table 6 lists the SELECT pin’s required voltages and modes.
AD8028
ANALOG INPUT –
Table 6. SELECT Pin Mode Control
Mode
Disable
Crossover Referenced
–1.2 V to Positive
Supply
Crossover Referenced
+1.2 V to Negative
Supply
+
2.7nF
SELECT Pin Voltage (V)
VS = ±5 V
VS = +5 V
VS = +3 V
−5 to −4.2 0 to 0.8
0 to 0.8
0.8 to 1.7
0.8 to 1.7
−4.2 to
−3.3
−3.3 to +5
15Ω
1.7 to 5.0
1.7 to 3.0
When the input stage transitions from one input differential
pair to the other, there is virtually no noticeable change in the
output waveform.
The disable time of the AD8027/AD8028 amplifiers is loaddependent. Typical data is presented in Table 7. See Figure 52
and Figure 53 for the actual switching measurements.
4MHz LPF
SELECT
(OPEN)
03327-A-059
Figure 60. Unity Gain Differential Drive
Table 8. ADC Driver Performance, fC = 100 kHz,
VOUT = 4.7 V p-p
Parameter
Second Harmonic Distortion
Third Harmonic Distortion
THD
SFDR
Measurement
–105 dB
–102 dB
–102 dB
+105 dBc
As shown in Figure 61, the AD8028 and AD7677 combination
offers excellent integral nonlinearity (INL).
1.0
Table 7. DISABLE Switching Speeds
±5 V
45 ns
980 ns
Supply Voltages (RL = 1 kΩ)
+5 V
+3 V
50 ns
50 ns
1100 ns
1150 ns
0.5
INL (LSB)
Time
tON
tOFF
DRIVING A 16-BIT ADC
With the adjustable crossover distortion selection point and low
noise, the AD8028 is an ideal amplifier for driving or buffering
input signals into high resolution ADCs such as the AD7767, a
16-bit, 1 LSB INL, 1 MSPS differential ADC. Figure 60 shows
the typical schematic for driving the ADC. The AD8028 driving
the AD7677 offers performance close to non-rail-to-rail
amplifiers and avoids the need for an additional supply other
than the single 5 V supply already used by the ADC.
Rev. C | Page 21 of 24
0
–0.5
–1.0
0
16384
32768
CODE
49152
Figure 61. Integral Nonlinearity
65536
03327-A-060
AD8027/AD8028
BAND-PASS FILTER
In communication systems, active filters are used extensively in
signal processing. The AD8027/AD8028 are excellent choices
for active filter applications. In realizing this filter, it is important that the amplifier have a large signal bandwidth of at least
10× the center frequency, fO. Otherwise, a phase shift can occur
in the amplifier, causing instability and oscillations.
The test data shown in Figure 63 indicates that this design
yields a filter response with a center frequency of fO = 1 MHz,
and a bandwidth of 450 kHz.
CH1 S21 LOG
5dB/REF 6.342dB
1:6.3348dB 1.00 000MHz
1
In Figure 62, the AD8027/AD8028 part is configured as a
1 MHz band-pass filter. The target specifications are fO = 1 MHz
and a −3 dB pass band of 500 kHz. To start the design, select fO,
Q, C1, and R4. Then use the following equations to calculate the
remaining variables:
Q=
f O (MHz)
Band Pass (MHz)
0.1
k = 2πfOC1
Figure 63. Band-Pass Filter Response
R1 = 2/k, R2 = 2/(3k), R3 = 4/k
DESIGN TOOLS AND TECHNICAL SUPPORT
H = 1/3(6.5 – 1/Q)
Analog Devices, Inc. (ADI) is committed to simplifying the
design process by providing technical support and online
design tools. ADI offers technical support via free evaluation
boards, sample ICs, interactive evaluation tools, data sheets,
spice models, application notes, and phone and email support
available at www. analog.com.
R5 = R4/(H – 1)
+5
R2
105Ω
VIN
10
03327-A-062
C2 = 0.5C1
R1
316Ω
1
FREQUENCY – MHz
C3
0.1μF
C1
1000pF
+
C2
500pF
R3
634Ω
AD8027/
AD8028
VOUT
SELECT
–
C4
–5 0.1μF
R5
523Ω
R4
523Ω
03327-A-061
Figure 62. Band-Pass Filter Schematic
Rev. C | Page 22 of 24
AD8027/AD8028
OUTLINE DIMENSIONS
5.00 (0.1968)
4.80 (0.1890)
8
5
4.00 (0.1574)
3.80 (0.1497) 1
4
6.20 (0.2440)
5.80 (0.2284)
1.27 (0.0500)
BSC
0.25 (0.0098)
0.10 (0.0040)
0.50 (0.0196)
× 45°
0.25 (0.0099)
1.75 (0.0688)
1.35 (0.0532)
8°
0.25 (0.0098) 0° 1.27 (0.0500)
0.40 (0.0157)
0.17 (0.0067)
0.51 (0.0201)
COPLANARITY
SEATING 0.31 (0.0122)
0.10
PLANE
COMPLIANT TO JEDEC STANDARDS MS-012AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
Figure 64. 8-Lead Standard Small Outline Package [SOIC]
Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)
2.90 BSC
6
5
4
1
2
3
2.80 BSC
1.60 BSC
PIN 1
0.95 BSC
1.90
BSC
1.30
1.15
0.90
1.45 MAX
0.50
0.30
0.15 MAX
0.22
0.08
10°
4°
0°
SEATING
PLANE
0.60
0.45
0.30
COMPLIANT TO JEDEC STANDARDS MO-178AB
Figure 65. 6-Lead Small Outline Transistor Package [SOT-23]
(RT-6)
Dimensions shown in millimeters
3.00 BSC
10
6
4.90 BSC
3.00 BSC
1
5
PIN 1
0.50 BSC
0.95
0.85
0.75
0.15
0.00
1.10 MAX
0.27
0.17
SEATING
PLANE
0.23
0.08
8°
0°
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187BA
Figure 66. 10-Lead Mini Small Outline Package [MSOP]
(RM-10)
Dimensions shown in millimeters
Rev. C | Page 23 of 24
0.80
0.60
0.40
AD8027/AD8028
ORDERING GUIDE
Model
AD8027AR
AD8027AR-REEL
AD8027AR-REEL7
AD8027ARZ 1
AD8027ARZ-REEL1
AD8027ARZ-REEL71
AD8027ART-R2
AD8027ART-REEL
AD8027ART-REEL7
AD8027ARTZ-R21
AD8027ARTZ-REEL1
AD8027ARTZ-REEL71
AD8028AR
AD8028AR-REEL
AD8028AR-REEL7
AD8028ARZ1
AD8028ARZ-REEL1
AD8028ARZ-REEL71
AD8028ARM
AD8028ARM-REEL
AD8028ARM-REEL7
AD8028ARMZ1
AD8028ARMZ-REEL1
AD8028ARMZ-REEL71
1
Minimum
Ordering Quantity
1
2,500
1,000
1
2,500
1,000
250
10,000
3,000
250
10,000
3,000
1
2,500
1,000
1
2,500
1,000
1
3,000
1,000
1
3,000
1,000
Temperature Range
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
Z = Pb-free part, # denotes lead-free, may be top or bottom marked.
© 2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C03327–0–3/05(C)
Rev. C | Page 24 of 24
Package Description
8-Lead SOIC
8-Lead SOIC
8-Lead SOIC
8-Lead SOIC
8-Lead SOIC
8-Lead SOIC
6-Lead SOT-23
6-Lead SOT-23
6-Lead SOT-23
6-Lead SOT-23
6-Lead SOT-23
6-Lead SOT-23
8-Lead SOIC
8-Lead SOIC
8-Lead SOIC
8-Lead SOIC
8-Lead SOIC
8-Lead SOIC
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
Package Option
R-8
R-8
R-8
R-8
R-8
R-8
RT-6
RT-6
RT-6
RT-6
RT-6
RT-6
R-8
R-8
R-8
R-8
R-8
R-8
RM-10
RM-10
RM-10
RM-10
RM-10
RM-10
Branding
H4B
H4B
H4B
H4B#
H4B#
H4B#
H5B
H5B
H5B
H5B#
H5B#
H5B#