Aplus API820G Tiny-controller-based voice synthesizer ic Datasheet

API 820G
GENERAL DESCRIPTION
API820G is a tiny-controller-based voice synthesizer IC which contains all the function of API820G series
and has an OTP (One Time Programmable) ROM inside.
FEATURES
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API820G – ROM : 64k x 10 bits (21 sec@6K sample rate).
Single power supply 2.4V ~ 5.5V.
Port1 and Port2 with wake-up function.
Power down mode for saving power consumption.
Single ROM for voice and program data.
Readable ROM code data.
One 6-bit timer overflow control.
Two stacks for subroutine calling.
Fixed current D/A to drive external connected transistor for audio output.
Multiple playing sppeeds in 2KHz ~ 32KHz for voice playback.
5-bit ASPCM synthesizer.
Multiple levels of volume control.
Multiple playing sppeeds in 2KHz ~ 32KHz for voice playback.
PIN DESCRIPTIONS
Pin NO.
I/O
Symbol
Function
1
2
3
4
5
I
I
I
I
I
P1.2/OEB/Mode option
P1.1/PGMB/Mode option
P1.0
VSS
OSC/ACLK
I
O
TEST/Vpp
VO2
VO1
VDD
P3.3
P3.2
P3.1
P3.0
P2.3
P2.2
P2.1/Dout
P2.0/Din
P1.3/Din.out.clk/Mode option
Bit 2 of Port 1 / Program control signal
Bit 1 of Port 1 / Program control signal
Bit 0 of Port 1
Negative power supply.
Oscillation component connection pin /
Program control signal
Test/Programing.
Voice output.
No connect
Positive power supply.
Bit 3 of Port 3.
Bit 2 of Port 3.
Bit 1 of Port 3.
Bit 0 of Port 3.
Bit 3 of Port 2.
Bit 2 of Port 2.
Bit 1 of Port 2 / Program data output signal
Bit 0 of Port 2 / Program data input signal
Bit 3 of Port 1 / Program control signal
6
7
8
9
10
11
12
13
14
15
16
17
18
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
1
API 820G
PIN ASSIGNMENT
API 820G
P1.2
P1.1
P1.0
GND
OSC
VPP
VO2
VO1
VDD
1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
10
P1.3
P2.0
P2.1
P2.2
P2.3
P3.0
P3.1
P3.2
P3.3
18 pin DIP
PROGRAMMING MODE
Mode
Regular
Security
P13
0
0
P12
0
0
P11
0
1
TIMING PARAMETER
Symbol
Parameter
Min.
Trs
Level set up time
2
Tmcs
Mode code setup time
2
Tdsu
Data set up time
100
Tdsh
Data hold time
100
Tas
ACLK to byte select time
2
Tacpw
Address clock pulse width
2
Tppw
Program pulse width
100
Tps
Programming mode set up time
4
Toed
Output enable setup time
300
Note : Segment ROM S1, S0 is programed just while 5 LSBs of ADDR are all 0.
Max.
Unit
us
us
ns
ns
us
us
us
us
ns
Programming for security mode :
When programming in security mode, the waveform is just like above. The programming data is as below :
B11 ~ B1
B0
User defined
Security bit
Note : When security = 0, enable security;
When security = 1, disable security.
2
API 820G
DC PROGRAMMING CHARACTERISTICS (VDD = 5V+0.5v, VPP = 12.5V+0.5v)
Items
Sym.
Min.
Max.
Unit
Test Conditions
Input high voltage
VIH
2.2
VDD+1.0
V
Input low voltage
VIL
-0.3
0.8
V
Input current
IIN
-
10
µA
VDD=5V, VIN=0~VDD
Output high voltage
V OH
2.4
-
V
IOH =400µA
Output low volatge
V OL
-
0.4
V
IOL =2.1mA
VDD supply current
IDD
-
100
mA
VDD=5V
VPP supply current
I PP
-
50
mA
VPP=12.5V
ABSOLUTE MAXIMUM RATINGS
Items
Sym.
Min.
Max.
Unit
Supply Voltage
V DD -V SS
-0.3
6.0
V
Input Voltage
V IN
VSS-0.3
VDD+0.3
V
Operating Temperature
Storage Temperature
T OP
TSTG
0
-55
70
+125
o
o
C
C
ELECTRICAL CHARACTERISTICS (VDD = 3V,25oC unless otherwise specified)
Parameter
Sym.
Min.
Typ.
Max.
Operating voltage
V DD
2.4
3.0
5.5
V
Standby current
IDDS
-
-
1.0
µA
VDD=3V
Operating current
IDDO
-
-
250
µA
VDD=3V, No load
Drive current of P2,P3
IOD
2.0
3.0
-
mA
VDD=3V, VO=2.4V
Sink current of P3
IOS
2.3
3.5
-
mA
VDD=3V, VO=0.4V
Sink current of P2 (after KEYB)
Sink current of P2
(before KEYB)
IOS1
IOS2
2.3
-
3.5
3.0
10
mA
µA
VDD=3V, VO=0.4V
VDD=3V, VO=0.4V
Input current of P1
I IH
-
3.0
10
µA
VDD=3V
Output current of VO1, VO2
IVO
4.0
5.0
6.0
mA
VDD=3V, VO=0.7V,
two channel full scale output
Oscillation resistor
Rosc
-
100
-
KΩ
VDD=2.4V ~ 5.5V
Oscillator frequency
Fosc
0.9
1.0
1.1
MHz
VDD=2.4V ~ 5.5V
Oscillator frequency deviation
∆Fosc
-10
-
10
%
VDD=2.4V ~ 5.5V
/ Fosc
Unit
Condition
3
API 820G
PAD DIAGRAM
OSC
GND
5
4
P1.0 P1.1 P1.2 P1.3 P2.0 P2.1 P2.2 P2.3
3
2
1
18
17
16
14
15
(0,0)
API 820G
6
7
VPP
VO2
8
9
VO1 VDD
10
11
12
13
P3.3 P3.2 P3.1 P3.0
Chip Size : 2930 x 2100 um
For PCB layout, IC substrate must be connected to Vss.
Pad No.
Symbol
X
Y
1
P1.2
325.8
900.6
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
P1.1
P1.0
GND
OSC
VPP
VO2
VO1
VDD
P3.3
P3.2
P3.1
P3.0
P2.3
P2.2
P2.1
P2.0
P1.3
128.7
-56.5
-708.4
-1325.0
-1256.2
-879.3
-233.4
-13.7
963.2
1084.1
1205.0
1325.9
1275.9
1090.6
893.5
708.2
511.1
900.6
900.6
876.7
879.0
-890.0
-890.0
-890.0
-878.4
-878.4
-878.4
-878.4
-878.4
900.6
900.6
900.6
900.6
900.6
4
API 820G
VDD
OSC
470k
TEST
VSS
P1.3
P1.2
P1.1
P1.0
VO1
VO2
P3.3
P3.2
P3.1
P3.0
P2.3
P2.2
P2.1
P2.0
8 Key Application Circuit
VDD
OSC
470k
TEST
VSS
P1.3
P1.2
P1.1
P1.0
VO1
VO2
P3.3
P3.2
P3.1
P3.0
P2.3
P2.2
P2.1
P2.0
16 Key Application Circuit
*This specification are subject to be changed without notice.
5
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