LINER LTC4425IDD Linear supercap charger with current-limited ideal diode and v/i monitor Datasheet

Electrical Specifications Subject to Change
LTC4425
Linear SuperCap Charger
with Current-Limited Ideal
Diode and V/I Monitor
DESCRIPTION
FEATURES
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50mΩ Ideal Diode from VIN to VOUT
Smart Charge Current Profile Limits Inrush Current
Internal Cell Balancer (No External Resistors)
Programmable Output Voltage (LDO Mode)
Programmable VIN to VOUT Current Limit
Continuous Monitoring of VIN to VOUT Current via
PROG Pin
Low Quiescent Current: 20μA
VIN Power Fail, PGOOD Indicator
2.45V/2.7V Cell Protection Shunts
(4.9V/5.4V SuperCap Max Top-Off Voltage)
3A Peak Current Limit, Thermal Limiting
Tiny Application Circuit, 3mm × 3mm × 0.75mm DFN
and 12-Lead MSOP Packages
APPLICATIONS
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High Peak Power Battery/USB Powered Equipment
Industrial PDAs
Portable Instruments/Monitoring Equipment
Power Meters, SuperCap Backup Circuits
PC Card/USB Modems
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
The LTC®4425 is a constant-current/constant-voltage linear
charger designed to charge a 2-cell supercap stack from
either a Li-Ion/Polymer battery, a USB port, or a 2.7V to
5.5V current-limited supply. The part operates as an ideal
diode with an extremely low 50mΩ on-resistance making it
suitable for high peak-power/low average power applications.
The LTC4425 charges the output capacitors to an externally
programmed output voltage in LDO mode at a constant
charge current, or to VIN in normal mode with a smart charge
current profile to limit the inrush current until the VIN to VOUT
differential is less than 250mV. In addition the LTC4425 can
be set to clamp the output voltage to 4.9V or 5.4V.
Charge current (VOUT current limit) is programmed by
connecting a resistor between PROG and GND. The
voltage on the PROG pin represents the current flowing
from VIN to VOUT for current monitoring. An internal active
balancing circuit maintains equal voltages across each
supercapacitor and clamps the peak voltage across each
cell to a pin-selectable maximum value. The LTC4425
operates at a very low 20μA quiescent current (shutdown
current <3μA) and is available in a low profile 12-pin
3mm × 3mm DFN or a 12-lead MSOP package.
TYPICAL APPLICATION
Charging 2-Cell Series Supercapacitor from Li-Ion Source
Charge Current vs VIN to VOUT
0.6
VOUT VIN
TO HIGH PEAK
POWER LOAD
Li-Ion
1F
1.5M
VMID
PFI
1F
+
–
VIN
FB
1.2M
PFI_RET
PFO
LTC4425
EN
CURRENT LIMITED
BY PMOS RDSON
0.3
0.2
1/10 CHARGE
CURRENT
0.1
IMONITOR
2.45V/2.7V
2k
GND
0.4
470k
PROG
SEL
VFB = VIN
FULL CHARGE CURRENT
0.5
CHARGE CURRENT (A)
VIN
IDEAL DIODE
FORWARD VOLTAGE = 15mV
0
0
0.2
0.4
0.6
VIN – VOUT (V)
0.8
1
4425 TA02
4425 TA01
4425p
1
LTC4425
ABSOLUTE MAXIMUM RATINGS
(Notes 1, 2)
VIN , VOUT, VMID , FB, PFI_RET, PFO Voltage .– 0.3V to 6V
EN, SEL, PFI Voltage ....–0.3V to MAX(VIN, VOUT) + 0.3V
Operating Junction Temperature ............– 40°C to 125°C
Storage Temperature Range ..................– 65°C to 150°C
Lead Temperature, MSOP Only
(Soldering, 10 sec) ................................................ 300°C
PIN CONFIGURATION
TOP VIEW
TOP VIEW
VOUT
1
12 VIN
VOUT
2
11 VIN
PROG
3
SEL
4
FB
5
8 PFO
EN
6
7 PFI_RET
13
GND
VOUT
VOUT
PROG
SEL
FB
EN
10 VMID
9 PFI
DD PACKAGE
12-LEAD (3mm s 3mm) PLASTIC DFN
TJMAX = 110°C, θJA = 43°C/W (Note 3)
EXPOSED PAD (PIN 13) IS GND, MUST BE SOLDERED TO PCB
1
2
3
4
5
6
13
GND
12
11
10
9
8
7
VIN
VIN
VMID
PFI
PFO
PFI_RET
MSE PACKAGE
12-LEAD PLASTIC MSOP
TJMAX = XXX°C, θJA = 35°C/W (Note 3)
EXPOSED PAD (PIN 13) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC4425EDD#PBF
LTC4425EDD#TRPBF
LFMQ
12-Lead (3mm × 3mm) Plastic DFN
–40°C to 125°C
LTC4425IDD#PBF
LTC4425IDD#TRPBF
LFMQ
12-Lead (3mm × 3mm) Plastic DFN
–40°C to 125°C
LTC4425EMSE#PBF
LTC4425EMSE#TRPBF
4425
12-Lead Plastic MSOP
–40°C to 125°C
LTC4425IMSE#PBF
LTC4425IMSE#TRPBF
4425
12-Lead Plastic MSOP
–40°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
4425p
2
LTC4425
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
junction temperature range, otherwise specifications are at TA = TJ = 25°C, VIN = 3.8V. (Note 4)
SYMBOL PARAMETER
CONDITIONS
MIN
l
TYP
VIN
Operating Supply Range
2.7
IQ(IN)
Quiescent Current from VIN
VIN = VOUT
20
IQ(OUT)
Quiescent Current from VOUT
VIN = VOUT
3
ISD
Quiescent Current in Shutdown
EN = 0
MAX
5.5
UNITS
V
μA
μA
3
μA
Ideal Diode
VFWD
Forward Voltage
15
mV
RFWD
Open Loop Forward On-Resistance
50
mΩ
Supercap Charger
VFB
Feedback Voltage
IFB
Feedback Pin Input Leakage
ICHG
Charge Current in LDO Mode
(FB = 0V)
Charge Current in Normal Mode (FB = VIN)
l
1.18
1.2
1.22
V
100
nA
RPROG = 0.5k
RPROG = 5k
2
0.2
A
A
RPROG = 0.5k, VIN – VOUT < 250mV
RPROG = 0.5k, VIN – VOUT > 750mV
2
0.2
A
A
RPROG = 5k, VIN – VOUT < 250mV
RPROG = 5k, VIN – VOUT > 750mV
200
20
mA
mA
VPROG
PROG Pin Servo Voltage in LDO Mode
hPROG
Ratio of Charge Current to PROG Pin Current
FB < 1.2V
VPROG
PROG Pin Servo Voltage in Normal Mode (FB = VIN)
ISC
Charger Short-Circuit Current Limit
PROG Pin Shorted to GND, FB = 0
tSS
Charger Soft Start Time
FB = 0
1.5
ms
TLIM
Junction Temperature in Constant Temperature
Mode (Note 5)
VOUT = 0, FB = 0, RPROG = 0.5k
105
°C
VIN – VOUT < 250mV
VIN – VOUT > 750mV
2
1.00
V
1000
mA/mA
1.00
0.1
V
V
3
4
A
Voltage Clamps
Maximum Voltage Across the Top Capacitor
VSEL = Lo
VSEL = Hi
l
l
2.45
2.7
2.5
2.75
V
V
Maximum Voltage Across the Bottom Capacitor
VSEL = Lo
VSEL = Hi
l
l
2.45
2.7
2.5
2.75
V
V
VRIP
VOUT Clamp Hysteresis
If Either Capacitor Reaches Clamp
Voltage i.e. VOUT < VIN
50
mV
ISH(TOP)
Top Shunt Current
RPROG = 1k, (VOUT – VMID) > VCLAMP
160
mA
ISH(BOT)
Bottom Shunt Current
RPROG = 1k, VMID > VCLAMP
140
mA
VCLAMP
4425p
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LTC4425
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
junction temperature range, otherwise specifications are at TA = TJ = 25°C, VIN = 3.8V. (Note 4)
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
1.8
1.84
UNITS
VMID Output Voltage
VOUT = 3.6V
1.76
VMID Maximum Current Sourcing Capability
VMID < VOUT/2 , VMID < VCLAMP
0.7
mA
VMID Maximum Current Sinking Capability
VMID > VOUT/2 , VMID < VCLAMP
1.2
mA
Output Low Voltage (PFO, PFI_RET)
IPIN = 5mA
65
100
mV
Pin Leakage Current (PFO, PFI_RET)
VPIN = 5V, EN = 0
1
μA
FB Threshold Voltage for Power Good (Rising)
LDO Mode
1.11
1.13
V
Leakage Balancer
VMID
V
PFO, PFI_RET, PFI
l
1.09
Input-to-Output Differential for Power Good (Rising) Normal Mode
VPFI
IPFI
265
l
PFI Threshold (Falling)
1.18
1.2
mV
1.22
V
PFI Hysteresis
10
mV
PFI Pin Input Leakage
100
nA
Power Good Timer Delay
200
ms
Logic Inputs (EN, SEL)
VIL
Logic Low Input Voltage
l
l
1.2
0.4
V
VIH
Logic High Input Voltage
IIH
Input Current High
EN, SEL Pins at 5.5V
l
–1
1
μA
IIL
Input Current Low
EN, SEL Pins at GND
l
–1
1
μA
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The current limit features of this part are intended to protect the
IC from short term or intermittent fault conditions. Continuous operation
above the maximum specified pin current rating may result in device
degradation or failure.
Note 3: Failure to solder the exposed backside of the package to the PC
board ground plane will result in a thermal resistance much greater than
43°C/W on the DD package and greater than 35°C C/W on MSE package.
V
Note 4: The LTC4425E (E grade) is guaranteed to meet specifications
from 0°C to 85°C junction temperature. Specifications over the –40°C
to 125°C operating junction temperature range are assured by design,
characterization and correlation with statistical process controls. The
LTC4425I (I grade) is guaranteed over the full –40°C to 125°C operating
junction temperature range. The junction temperature, TJ, is calculated
from the ambient temperature, TA, and power dissipation, PD, according to
the formula:
TJ = TA + (PD • θJA °C/W).
Note that the maximum ambient temperature is determined by specific
operating conditions in conjunction with board layout, the rated thermal
package thermal resistance and other environmental factors.
Note 5: VIN to VOUT charge current is reduced by thermal foldback as
junction temperature approaches 105°C.
4425p
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LTC4425
TYPICAL PERFORMANCE CHARACTERISTICS
LDO Regulation Voltage
vs Charge Current
LDO Regulation Voltage
vs Temperature
3.295
80
3.286
VIN = 3.8V
3.285 VOUT SET FOR 3.3V
3.290
70
90°C
ON-RESISTANCE (mΩ)
3.284
3.285
3.283
3.280
VOUT (V)
3.282
3.275
3.281
3.270
3.280
3.265
3.279
VIN = 3.8V, IOUT = 10mA
3.260 RPROG = 1k
VOUT SET FOR 3.3V
3.255
200
400
600
800
0
IOUT (mA)
1000
3.277
–45 –30 –15
1200
0 15 30 45 60
TEMPERATURE (°C)
3586 G35
1200
400
20
0
LDO MODE (FB GROUNDED)
NORMAL MODE
600
400
0
–45
Charge Current vs VOUT in
Thermal Regulation
CHARGE CURRENT (mA)
0
–45 –30 –15 0 15 30 45 60 75 90 105 120
TEMPERATURE (°C)
4425 G07
–25
–5
15
35
55
TEMPERATURE (°C)
VOUT Quiescent Current vs VOUT
and Temperature (VIN ≥ VOUT)
20
VIN = 5V
PROG PIN SHORTED TO GND
2500 FB PIN SHORTED TO GND
AMBIENT TEMP 24°C
18
VIN < VOUT
VIN = 3.8V
16
14
2000
1500
1000
500 THERMAL REGULATION
ON-CHIP POWER DISSIPATION ~4W
CASE TEMP ~100°C
0
0 0.5 1 1.5 2 2.5 3 3.5
OUTPUT VOLTAGE (V)
75
4425 G06
3000
200
VIN = 2.7V
10
4425 G05
Charge Current vs Temperature in
Thermal Regulation
400
15
5
4425 G04
1000
4.8
VIN = 3.8V
20
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
VIN TO VOUT DIFFERENTIAL (V)
VIN = 3.8V, VOUT = 3.5V
RPROG = 1k, FB GROUNDED
4.5
25
VIN = 3.8V
RPROG = 1k
0
600
3.3 3.6 3.9 4.2
INPUT VOLTAGE (V)
VIN Quiescent Current vs Supply
and Temperature (VIN ≥ VOUT)
800
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
VIN TO VOUT DIFFERENTIAL (V)
800
3
4425 G03
200
200
CHARGE CURRENT (mA)
30
0
2.7
90
CURRENT (μA)
NORMAL MODE
PROG VOLTAGE (mV)
CHARGE CURRENT (mA)
LDO MODE (FB GROUNDED)
1200
75
1000
1000
800
–45°C
40
PROG Pin Voltage
vs (VIN – VOUT) Differential
VIN = 3.8V
RPROG = 1k
600
25°C
50
4425 G02
Charge Current
vs (VIN–VOUT) Differential
1200
60
10
3.278
CURRENT (μA)
VOLTAGE (V)
Charger FET On-Resistance
vs Supply
VOUT = 2.7V
12
10
8
6
4
2
4
4.5
4425 G08
0
–45
–25
–5
15
35
55
TEMPERATURE (°C)
75
4425 G09
4425p
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LTC4425
TYPICAL PERFORMANCE CHARACTERISTICS
Open Drain Outputs
(PFI_RET and PFO)
FET On-Resistance vs Temperature
Logic Inputs (EN and SEL)
Threshold Voltage vs Temperature
0.9
18
VIN = 3.8V
0.8
16
0.7
14
0.6
12
PROG Pin Short Circuit Charge
Current vs Temperature
3.00
VIN = 3.8V
VIN = 3.8V
VOUT = 3.3V
PROG PIN SHORTED TO GND
0.5
0.4
0.3
CHARGE CURRENT (A)
RESISTANCE (Ω)
VOLTAGE (V)
2.95
10
8
6
0.2
4
0.1
2
2.90
2.85
2.80
2.75
0
–45
–25
–5
15
35
55
TEMPERATURE (°C)
0
–45
75
–25
–5
15
35
55
TEMPERATURE (°C)
4425 G10
3500
3000
3000
CHARGE CURRENT (mA)
CHARGE CURRENT (mA)
3500
2000
1500
1000
–5
15
35
55
TEMPERATURE (°C)
RPROG = 1k
500 VIN = 3.8V
VOUT = 3.4V
SEL = 0
0
1.6 1.7 1.8 1.9 2 2.1 2.2 2.3 2.4 2.5
VOUT TO VMID (V)
Output Voltage Transient Step
Response Waveform (LDO Mode)
VOUT
20mV/DIV
(AC-COUPLED)
PROG PIN GROUNDED
2500
75
4425 G011a
Charge Current vs Voltage Across
Bottom Capacitor (VMID)
PROG PIN GROUNDED
–25
4425 G11
Charge Current vs Voltage Across
Top Capacitor (VOUT – VMID)
2500
2.70
–45
75
2000
1500
ILOAD
800mA
100mA
1000
500 VIN = 3.8V
VOUT = 3.4V
SEL = 0
0
1.6 1.7 1.8 1.9
500μs/DIV
VIN = 3.8V
RPROG = 500Ω
SUPERCAP VALUE = 0.55F
4425 G14
2 2.1 2.2 2.3 2.4 2.5
VMID (V)
4425 G13
4425 G12
Output Voltage Waveform When
VMID is Shorted to GND
Output Voltage Waveform When
VMID is Shorted to VOUT
PROG Pin Soft-Start Waveform
(Normal Mode)
VIN = 3.8V
RPROG = 1k
VOUT
(1V/DIV)
VOUT
20mV/DIV
AC-COUPLED
VOUT
20mV/DIV
AC-COUPLED
EN
VIN = 3.8V
RPROG = 1k
4425 G16
250ms/DIV
SUPERCAP VALUE = 0.55F
VIN = 3.8V
RPROG = 1k
4425 G15
100ms/DIV
SUPERCAP VALUE = 0.55F
VIN = 5V
RPROG = 1k
500μs/DIV
4425 G18
4425p
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LTC4425
PIN FUNCTIONS
VOUT (Pin 1, 2): Output Pin of the Charger. Typically connects to the top of the 2-cell supercap stack.
PROG (Pin 3): Charge Current Program and Charge
Current Monitor Pin. A resistor connected from PROG to
ground programs the charge current. In LDO mode, this
pin always servos to 1V. However, if the charge current
profile is turned on, this pin servos to a voltage between
1V and 0.1V depending on the input-to-output differential.
In all cases, the voltage on this pin always represents the
actual charge current.
SEL (Pin 4): Logic Input to Select One of the Two Possible
Clamp Voltages (VCLAMP). If the pin is a logic low, the
maximum voltage across any supercap of the stack is
2.45V. If the pin is a logic high, it is 2.7V. Do not float
this pin.
FB (Pin 5): In LDO mode, output voltage is programmed
by a resistor divider from VOUT via the FB pin. In this
mode, the voltage on this pin always servos to the internal
reference voltage of 1.2V. If the FB pin is pulled up to VIN ,
the LDO mode is disabled and the charge current profile
mode is turned on. Do not float this pin.
EN (Pin 6): Digital Input to Enable the Charger. If this pin
is a logic high, the part is enabled and it draws only 20μA
of quiescent current from the input or output when idle.
If this pin is a logic low, the part is in shutdown mode and
draws less than 2μA. Do not float this pin.
PFO (Pin 8): Open Drain Output of the Power-Fail Comparator. This pin is driven to logic low if at least one of the
following conditions is true: (1) VIN is less than a value
programmed by an external divider via PFI, (2) VOUT has
not reached within 7.5% of its final programmed value
in LDO mode, or (3) VOUT is not within 250mV of VIN in
charge current profile mode. When all these conditions
are false for at least 200ms, this pin goes high impedance
indicating that power is good.
PFI (Pin 9): Input to the Power-Fail Comparator. The input
voltage below which PFO pin indicates a power-fail condition can be programmed by connecting this pin to an
external resistor divider between VIN and PFI_RET pin.
VMID (Pin 10): Connects to the Midpoint of the 2-Cell
supercap stack. An internal leakage balancing amplifier
drives this pin to a voltage which is exactly half of VOUT.
VIN (Pin 11, 12): Input Power Pin. Typically connected to
a DC source like a Li-Ion/Polymer battery or a USB port.
GND (Exposed Pad Pin 13): GND. The Exposed Pad should
be connected to a continuous ground plane on the second
layer of the printed circuit board by several vias directly
under the part to achieve optimum thermal conduction.
PFI_RET (Pin 7): This pin connects to the bottom of the
external resistor divider for the input power-fail comparator. In shutdown mode, an internal switch opens up this
path to reduce the current drawn by the resistor divider.
4425p
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LTC4425
BLOCK DIAGRAM
VIN
1.2V
BANDGAP 1.11V
REFERENCE
0.1V
VOUT
VIN – 15mV
+
–
MPSNS
s1
MPSW
s1000
VOUT
IDEAL DIODE
CONTROLLER
CBIG
PSHUNT
VMID
CONSTANT-VOLTAGE/
CONSTANT-CURRENT/
CONSTANT-TEMPERATURE
CHARGER CIRCUITRY
10X
VOLTAGE CLAMP
CIRCUITRY
CBIG
R
LBA
NSHUNT
+
–
CHARGE CURRENT
CHARGE CURRENT
PROFILE GENERATOR
1X
VOUT/2
250mV
150mV
VIN – VOUT
R
VIN – VOUT
COMPARATOR
VIN
VIN
RPF1
VOUT + 250mV
+
–
OSCILLATOR
PFI
1.2V
RPF2
PFI_RET
+
PFC
–
PFI
COMPARATOR
+
–
LEAKAGE
BALANCER
VSEL
2.7V 2.45V
1.11V
PROG
PGOOD
COMPARATOR
RPROG
200ms
TIMER
RFB1
FB
EN
RFB2
PFO
GND
4425 BD
Figure 1. LTC4425 Block Diagram
4425p
8
LTC4425
OPERATION
LDO Mode
In LDO mode, the output voltage VOUT is programmed
by an external resistor divider network consisting of
RFB1 and RFB2 via the FB pin and the charge current is
programmed by an external resistor RPROG via the PROG
pin. Please refer to the Block Diagram shown in Figure
1. The charger control circuitry consists of a constantcurrent amplifier and a constant-voltage amplifier. When
the part is enabled to charge a discharged supercap stack,
initially the constant-current amplifier is in control and
servos the PROG pin voltage to 1V. The current through
the PROG resistor gets multiplied by approximately 1000,
the ratio of the sense MOSFET (MPSNS) and the power
MOSFET (MPSW), to charge the supercap stack. As the
output voltage VOUT gets close to the programmed value,
the constant-voltage amplifier takes over and backs off
the charge current as necessary to maintain the FB pin
voltage equal to an internal reference voltage of 1.2V.
Since the PROG pin current is always about 1/1000 of the
charge current, the PROG pin voltage continues to give
an indication of the actual charge current even when the
constant-voltage amplifier is in control.
Charge Current Profile or Normal Mode
The LTC4425 is in charge current profile mode when the
FB pin is shorted to the input voltage VIN . In this mode
of operation, the constant-voltage amplifier is internally
disabled but the charge current is still programmed by the
external RPROG resistor. The charger provides 1/10 of the
programmed charge current if the input-to-output voltage
differential (VIN–VOUT) is more than 750mV to limit the
power dissipation within the chip. As this differential voltage
decreases from 750mV, the charge current increases
linearly to its full programmed value when VOUT is within
250mV or closer to VIN . As VOUT rises further, the voltage
across the charger FET gets too small to support the full
charge current. So the charge current gradually falls off
and the charger FET enters into its triode (ohmic) region of
operation (see Figure 2). Since the charger FET RDS(ON) is
approximately 50mΩ, with a programmed charge current
of 2A, the FET will enter the ohmic (triode) region and the
charge current will start to fall off when VOUT is within
about 100mV of VIN .
IDEAL DIODE
CONTROL REGION
2A
CHARGE CURRENT (A)
The LTC4425 is a linear charger designed to charge a
two-cell supercap stack by employing a constant-current,
constant-voltage, and constant-temperature architecture. It
has two modes of operation: charge current profile mode
(also referred to as normal mode) and LDO mode. In LDO
mode, the LTC4425 charges the top of the stack to an
externally programmed output voltage with a fixed charge
current that is also externally programmable. In charge
current profile mode, the LTC4425 charges the top of the
stack to the input voltage VIN with a charge current that
varies based on the input-to-output differential voltage.
OHMIC
REGION
FULL CHARGE
CURRENT
REGION
LINEAR CHARGE
CURRENT REGION
1/10 CHARGE
CURRENT REGION
0.2A
0.3A
15
100
250
VIN – VOUT (mV)
750
4425 F02
Figure 2. Different Regions of Charge Current Profile
The Ideal Diode Controller
When the input-to-output differential approaches 15mV,
the ideal diode controller takes over the control from the
constant-current amplifier and backs off the charge current by pulling up the gate of the charger FET as much
as necessary to maintain a 15mV delta across the FET
(see Figure 2). As a result, VOUT can only be charged to
15mV below VIN. In the event VIN suddenly drops below
VOUT, the controller will quickly turn the FET completely
off to prevent any loss of charge due to the reverse flow
of charge from the supercap back to the supply.
4425p
9
LTC4425
OPERATION
Thermal Regulation
In either mode, if the die temperature starts to approach
105°C due to internal power dissipation, a thermal regulator limits the die temperature to approximately 105°C by
reducing the charge current. Even in thermal regulation,
the PROG pin continues to give an indication of the charge
current. The thermal regulation protects the LTC4425 from
excessive temperature and allows the user to push the
limits of the power handling capability of a given circuit
board without the risk of damaging the LTC4425 or the
external components. Another benefit of this feature is that
the charge current can be set according to typical, rather
than worst-case, ambient temperatures for a given application with the assurance that the charger will automatically
reduce the charge current in worst-case conditions.
both capacitors exceed their maximum allowable voltage,
VCLAMP, the main charger FET completely shuts off and
both shunt devices turn on. Both shunt devices are actually
current mirrors guaranteed to shunt more current away
than that coming through the charger FET.
Leakage Balancing Circuitry
The LTC4425 is equipped with an internal leakage balancing
amplifier, LBA, which servos the midpoint, i.e., VMID pin
voltage, to exactly half of the output voltage, VOUT . However
it has a very limited source and sink capability of approximately 1mA. It is designed to handle slight mismatch of
the supercaps due to leakage currents; not to correct any
gross mismatch due to defects. The balancer is only active
as long as there is an input present. The internal balancer
eliminates the need for external balancing resistors.
Voltage Clamp Circuitry
The LTC4425 is equipped with circuitry to limit the voltage
across any supercap of the stack to a maximum allowable
voltage VCLAMP. There are two preset voltages, 2.45V or
2.7V, for VCLAMP selectable by the SEL pin. The SEL pin
should be set to logic low for lower VCLAMP voltage of
2.45V and to logic high for the higher VCLAMP voltage of
2.7V. If the voltage across the bottom capacitor, i.e., the
VMID pin voltage reaches VCLAMP first, an NMOS shunt
transistor turns on and starts to bleed charge off of the
bottom capacitor to GND. Similarly, if the voltage across
the top capacitor, VTOP, reaches the VCLAMP voltage first, a
PMOS shunt transistor turns on and starts to bleed charge
off of the top capacitor to the bottom one.
When the voltage across any of the supercaps reaches
within 50mV of VCLAMP, a transconductance amplifier
starts to cut back the charge current linearly. By the time
any of the shunt devices are on, the charge current gets
reduced to 1/10 of the programmed value and stays at
this reduced level as long as the shunt device is on. This
is to prevent the shunt devices from getting damaged by
excessive heat. The comparators that control the shunt
devices have a 50mV hysteresis meaning that when the
voltage across either capacitor is reduced by 50mV, the
shunt devices turn off and normal charging resumes with
full charge current unless limited by any of the other amplifiers controlling the gate of the charger FET. In the event
Short-Circuit Current Limit
In the event the PROG pin gets shorted to GND, the LTC4425
limits the PROG pin current to approximately 3mA which,
in turn, limits the maximum charge current to about 3A.
While in short-circuit, if one of the supercaps approaches
within 50mV of its maximum allowable voltage, VCLAMP,
a current-limit foldback circuit cuts back the short-circuit
current limit to approximately 1/10 of its full value or to
about 300mA.
Supply Status Monitor
The LTC4425 includes an input power-fail comparator, PFC,
which monitors the input voltage VIN via the PFI pin. At anytime, if VIN falls below a certain externally program-mable
threshold, it reports the undervoltage situation by pulling
down the open-drain output PFO low. This under-voltage
threshold is programmed by connecting an external resistor divider network (consisting of RPF1 andRPF2) between
VIN and the PFI_RET pins. When the part is enabled, a low
RDS(ON) (approx. 13Ω) internal pull-down transistor pulls
the bottom end of RPF2 , i.e., the PFI_RET pin to GND to
complete the divider network. When the part is disabled,
this transistor opens RPF2 from GND, thereby saving the
current drawn by the divider network. The power-fail comparator has a built-in filter to reject any transient supply
glitch that is less than 10μS long.
4425p
10
LTC4425
OPERATION
Output Status Monitor
Shutdown Mode
The LTC4425 has an internal comparator to always monitor
the output voltage VOUT . At any time, if VOUT falls below
7.5% of its final programmed value in LDO mode or more
than 250mV below the input voltage VIN in charge current profile mode, the comparator reports the power-fail
condition by pulling the same open-drain output PFO low.
When both input and output voltages are good for at least
200ms, the PFO pin goes high impedance and can be
pulled up to any external supply by a resistor to indicate
a power good situation. In normal mode, the load should
not exceed 1/10th of the programmed charge current
until PFO is high.
The LTC4425 can be shut down by pulling the EN pin low.
In shutdown mode, very minimal circuitry is alive and
the part draws less than 2μA from the supply or from the
output capacitors if the supply is not present.
VOUT > VIN Operation
If for some reason VIN falls below VOUT or the input is
not present and the EN pin is pulled high, most of the
circuitry including the voltage clamp circuitry is kept alive
and the part draws about 20μA from the output capacitors. However, the internal leakage balancer is turned off
under this condition.
Charge Current Soft-Start
The LTC4425 includes a soft-start circuit to minimize
the inrush current at the start of a charge cycle. When a
charge cycle is initiated, the charge current ramps from
zero to full-scale over a period of approximately 1ms and
this soft-start can be monitored by observing the PROG
pin voltage. This has the effect of minimizing the transient
current load on the power supply during start-up.
Thermal Shutdown
The LTC4425 includes a thermal shutdown circuit in addition to the thermal regulator. If for any reason, the die
temperature exceeds 160°C, the entire part shuts down.
It resumes normal operation once the temperature drops
by about 14°C, to approximately 146°C.
4425p
11
LTC4425
APPLICATIONS INFORMATION
Programming the Output Voltage
In LDO mode, the LTC4425 output voltage can be programmed for any voltage between 2.7V and VIN by using
a resistor divider from VOUT pin to GND via the FB pin
such that:
VOUT = VFB • (1 + RFB1/RFB2)
where VFB is 1.2V. See Figure 3.
Typical values for RFB are in the range of 40k to 1M. Too
small a resistor will result in a large quiescent current
whereas too large a resistor coupled with FB pin capacitance will create an additional pole and may cause loop
instability.
VIN
VIN
RPF1
VOUT
LTC4425
PFI
VOUT
RFB1
FB
RPF2
RFB2
PFI_RET
4425 F03
Figure 3. Programming Output Voltage and Input
Threshold for Power Fail Comparator.
Programming the Input Voltage Threshold for Power
Fail Status Indicator
The input voltage below which the power fail status pin
PFO indicates a power-fail condition is programmed by
using a resistor divider from the VIN pin to the PFI_RET
pin via the PFI pin such that:
VIN , PFO = VPFI • (1 + RPF1/RPF2)
where VPFI is 1.2V. See Figure 3.
Typical values for RPF are in the range of 40k to 1M. In
shutdown mode, this divider network is disconnected from
ground via the PFI_RET pin to save the quiescent current
drawn by the network.
Programming the Charge Current
The LTC4425 charge current is programmed using a single
resistor from the PROG pin to ground. The charge current
out of the VOUT pin is 1000 times the current out of the
PROG pin. The program resistor and the charge current
are calculated using the following equations:
RPROG = 1000 • (1V/ICHRG), ICHRG = 1000 • (1V/RPROG)
where ICHRG is the charge current out of the VOUT pin. The
charge current out of the VOUT pin can be determined at
any time by monitoring the PROG pin voltage and using
the following equation:
ICHRG = 1000 • (VPROG /RPROG)
Stability Considerations
In LDO mode, the LTC4425 supercapacitor charger
has two principal control loops: constant-voltage and
constant-current. The constant-voltage loop is stable
when con-nected to a supercap of at least 0.2F. However,
when disconnected from the supercap, the voltage loop
requires at least 10μF capacitance in series with 500Ω
resistance for stability.
In constant-current mode, the PROG pin voltage is in
the feedback loop, not the VOUT pin voltage. Because of
the additional pole created by the PROG pin capacitance,
capacitance on this pin must be kept to a minimum. With
no additional capacitance on the PROG pin, the charger is
stable with a program resistor as high as 100k. However,
any additional capacitance on this node reduces the
maximum allowed program resistor. The pole frequency
at the PROG pin should be kept above 100kHz. Therefore,
if the PROG pin is loaded with a capacitance, CPROG ,
the following equation should be used to calculate the
maximum resistance value for RPROG:
RPROG ≤ 1/(2π • 100kHz • CPROG)
Board Layout Considerations
To be able to deliver maximum charge current under all
conditions, it is critical that the exposed metal pad on the
backside of the LTC4425’s package has a good thermal
contact to the PC board ground. Correctly soldered to a
2500mm2 double-sided 1 oz. copper board, the part has
a thermal resistance of approximately 43°C/W. Failure to
make thermal contact between the exposed pad on the
backside of the package and the copper board will result
in a thermal resistance far greater than 43°C/W.
4425p
12
LTC4425
APPLICATIONS INFORMATION
To protect the part against excessive heat generated by
internal power dissipation, the LTC4425 is equipped with a
thermal regulator which automatically reduces the charge
current to maintain a maximum die temperature of 105°C.
Ignoring the quiescent current, the power dissipation can
be approximated by the following equation:
Figure 4 shows the graph of charge current vs output
voltage when the charge current profile is turned off by
shorting the FB pin to GND and the charge current is
limited by thermal regulation.
2.5
VIN = 5V
RPROG = 500Ω
TA = 25°C
2.0 Q = 43° C/W
JA
THERMAL
REGULATION = 105°C
1.5 FB PIN GROUNDED
THERMAL REGULATION
CHARGE CURRENT(A)
Charge Current Reduction by the Thermal Regulator
PD = (VIN – VOUT) • ICHRG
If θJA is the thermal resistance and TA is the ambient temperature, then the die temperature can be calculated as:
1.0
0.5
TDIE = TA + PD • θJA
When the part is in thermal regulation, the die temperature
is 105°C and for a given VIN and VOUT, the charge current
can be determined by the following equation:
ICHRG =
105 – TA
(VIN – VOUT ) • θJA
105°C – 25°C
(5 – 0) V • 43°C / W
=
80°C
= 372mA
215°C / A
As the output voltage rises, the charge current will gradually
rise to the full charge current programmed by the PROG pin
resistor as long as the constant-current loop is in control.
If the LTC4425 is programmed for a charge current of 2A,
the output voltage at which the part will deliver full charge
current can be determined by the following equation:
VOUT = VIN –
105 – TA
ICHRG • θ JA
(105 – 25) °C
2 A • 43°C / W
372mA
0
1
2
3
4
OUTPUT VOLTAGE (V)
5
6
4425 F04
Figure 4. Charge Current vs Output Voltage under Thermal
Regulation (LDO Mode)
The LTC4425 can also be used to charge a single supercapacitor by connecting two series-connected matched
ceramic capacitors with a minimum capacitance of 100μF
in parallel with the supercapacitor as shown in Figure 5.
Refer to Table 1 for supercapacitor manufacturers.
Table 1. Supercapacitor Manufacturers
CAP-XX
www.cap-xx.com
NESS CAP
www.nesscap.com
Maxwell
www.maxwell.com
Bussmann
www.cooperbussmann.com
AVX
www.avx.com
Illinois Capacitor
www.illcap.com
Tecate Group
www.tecategroup.com
LTC4425
VOUT
Using the previous example, for full charge current, the
output voltage has to rise to at least:
VOUT = 5 V –
0
Charging a Single Supercapacitor
For example, if the LTC4425 is used in LDO mode to charge
a completely discharged supercap stack (VOUT = 0V) at a
room temperature of 25°C from a 5V source, the charge
current, at first, will be limited to approximately:
ICHRG =
4.07V
= 5V –
80°C
= 4.07 V
86°C / V
VOUT
C1
VMID
C2
CSUP
GND
4425 F05
C1 = C2 ≥ 100μF
Figure 5. Charging a Single Supercapacitor
4425p
13
LTC4425
TYPICAL APPLICATIONS
USB to High Peak Power 3.3V Charging
USB
3.3V
5V, 500mA
TO
LOAD
VOUT
VIN
1F
1.5M
2.1M
VMID
PFI
1F
1.2M
LTC4425
PFI_RET
FB
1.2M
470k
SEL
PFO
PROG
μC
EN
2k
4425 TA03
3 × AA Alkaline to High Peak Power 3.3V Charging
3.3V, 2A
4.5V TO 3.6V
3s AA
TO
LOAD
VOUT
VIN
1F
1.5M
2.1M
VMID
PFI
1F
LTC4425
1.2M
PFI_RET
FB
1.2M
470k
SEL
PFO
μC
EN
CURRENT
MONITOR
PROG
500Ω
4425 TA04
Li-Ion High Peak Power Battery Buffer
VOUT
VIN
+
0.6F
Li-Ion
TO
LOAD
VMID
SEL
0.6F
LTC4425
1.5M
EN
470k
FB
PFI
PFO
PROG
1.2M
PFI-RET
CURRENT
MONITOR
500Ω
4425 TA04a
4425p
14
LTC4425
TYPICAL APPLICATIONS
High Current USB Charging with Power Path Control
L1
3.3μH
USB
INSTANT-ON
SW
R1
100k
5V
VOUT
VBUS
D0
C3
10μF
0805
LDO3V3
D1
μC
D2
C1
10μF
0805
GATE
LTC4088
VIN
LOAD
VMID
CSC
0.55F
HS203F
LTC4425
R7
1.5M
M1
VOUT
PFI
CHRG
R8
1.2M
BAT
NTC
VIN
FB
PFI_RET
CLPROG
R2
100k
PROG
GND
C/X
R5
8.2Ω
C2
0.1μF
0603
PFO
+
R3
2.94k
LI-Ion
μC
PROG
SEL
EN
R4
2k
R6
2k
GND
4425 TA05
L1: COILCRAFT LPS4018-332MLC
M1: SILICONIX Si2333
R2: VISHAY-DALE NTHS0603N011-N1003F
C1, C3: MURATA GRM21BR61A106KE19
C2: MURATA GRM188R71C104KA01
CSC: CAP-XX HS203F
3.3V Peak-Power/Back-up Supply
2.2μH
5V
≈5V
VOUT
VIN
LTC4425
1.5M
CSC
0.55F
HS203F
VMID
PFI
PVOUT
VIN
VOUT
340k
LTC3533
OFF ON
10μF
VIN
6.49k
VOUT
3.3V
1.5A
47pF
RUN/SS
FB
RT
VC
330pF
100μF
4.7pF
FB
PFI_RET
BURST
PFO
PROG
33.2k
SEL
EN
SW2
PVIN
107k
1.2M
μC
SW1
2k
SGND
PGND
0.1μF
200k
200k
4425 TA05a
GND
4425p
15
LTC4425
TYPICAL APPLICATIONS
12V to 5V/3.3V High Peak Power Supply
12V
D1
VIN
VOUT (5V)
5V
BOOST
0.1μF
10μH
LT3505
R7
1.5M
68pF
61.1k
VMID
GND
D2
10μF
69.8k
FB
PFI_RET
11.3k
PFO
1μF
70pF
2.1M
R8
1.2M
VC
75k
CSP2
1F
PFI
FB
HIGH PEAKPOWER LOAD
CSP1
1F
LTC4425
SHDN
RT
3.3V
VOUT
VIN
SW
PROG
SEL
μC
EN
D1: 1N4148
D2: MBRM140
CSP1, CSP2:
R6
2k
GND
1.2M
4425 TA06
12V Input to 5V Outputs with Input Voltage Monitoring
12V
BOOST
VIN
0.1μF
2.2μF
ON OFF
SW
RUN
ILIM
28.7k
D1
LT3663
6.8μH D1: DFLS240
CSP1, CSP2:
ISENSE
GND
VOUT
5V INSTANT-ON
59k
22μF
FB
VOUT
VIN
11k
FB
VMID
1.5M
R8
1.2M
CSP1
1F
5V
HIGH-PEAK POWER,
OR BACKUP SUPPLY
CSP2
1F
PFI
LTC4425
PFI_RET
PFO
μC
PROG
SEL
EN
R6
2k
GND
4425 TA07
4425p
16
LTC4425
TYPICAL APPLICATIONS
Redundant High Peak Power Battery Supplies
USB
VIN
1.5M
VOUT
FB
TO LOAD
1F
VMID
PFI
LTC4425
1.2M
1F
PFI_RET
SEL
μC
EN
USB POWER OK
3sAA
1.5M
PROG
PFO
2k
VIN
VOUT
FB
PFI
VMID
LTC4425
1.2M
PFI_RET
SEL
EN
470k
PFO
PROG
BAT POWER OK
500Ω
4425 TA08
4425p
17
LTC4425
PACKAGE DESCRIPTION
DD Package
12-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1725 Rev A)
0.70 ±0.05
3.50 ±0.05
2.10 ±0.05
2.38 ±0.05
1.65 ±0.05
PACKAGE
OUTLINE
0.25 ± 0.05
0.45 BSC
2.25 REF
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
3.00 ±0.10
(4 SIDES)
R = 0.115
TYP
7
0.40 ± 0.10
12
2.38 ±0.10
1.65 ± 0.10
PIN 1 NOTCH
R = 0.20 OR
0.25 s 45°
CHAMFER
PIN 1
TOP MARK
(SEE NOTE 6)
6
0.200 REF
1
0.23 ± 0.05
0.45 BSC
0.75 ±0.05
2.25 REF
(DD12) DFN 0106 REV A
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD AND TIE BARS SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
4425p
18
LTC4425
PACKAGE DESCRIPTION
MSE Package
12-Lead Plastic MSOP, Exposed Die Pad
(Reference LTC DWG # 05-08-1666 Rev B)
BOTTOM VIEW OF
EXPOSED PAD OPTION
2.845 ± 0.102
(.112 ± .004)
5.23
(.206)
MIN
2.845 ± 0.102
(.112 ± .004)
0.889 ± 0.127
(.035 ± .005)
6
1
1.651 ± 0.102 3.20 – 3.45
(.065 ± .004) (.126 – .136)
0.12 REF
12
0.65
0.42 ± 0.038
(.0256)
(.0165 ± .0015)
BSC
TYP
RECOMMENDED SOLDER PAD LAYOUT
0.254
(.010)
0.35
REF
4.039 ± 0.102
(.159 ± .004)
(NOTE 3)
DETAIL “B”
CORNER TAIL IS PART OF
DETAIL “B” THE LEADFRAME FEATURE.
FOR REFERENCE ONLY
7
NO MEASUREMENT PURPOSE
0.406 ± 0.076
(.016 ± .003)
REF
12 11 10 9 8 7
DETAIL “A”
0° – 6° TYP
3.00 ± 0.102
(.118 ± .004)
(NOTE 4)
4.90 ± 0.152
(.193 ± .006)
GAUGE PLANE
0.53 ± 0.152
(.021 ± .006)
1 2 3 4 5 6
DETAIL “A”
1.10
(.043)
MAX
0.18
(.007)
SEATING
PLANE
0.22 – 0.38
(.009 – .015)
TYP
0.650
NOTE:
(.0256)
1. DIMENSIONS IN MILLIMETER/(INCH)
BSC
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
0.86
(.034)
REF
0.1016 ± 0.0508
(.004 ± .002)
MSOP (MSE12) 0608 REV B
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
4425p
19
LTC4425
TYPICAL APPLICATION
Embedded Automotive Backup Controller
6V to 36V
VIN
11, 12
VOUT (5V)
BD
2.2μF
CAR
BATTERY
VOUT
VIN
1, 2
5V, 2A
5
ON OFF
BOOST
RUN
R7
1.5M
L1
0.1μF
2.2μH
VMID
9
SW
VC
LT3684
D1
20k
RT
BIAS
7
590k
8
200k
GND
CSP2
1F
LTC4425
FB
PG
10μF
μC
10
PFI
R8
1.2M
330pF
28.7k
CSP1
1F
FB
4
6
PROG
PFI_RET
3
PFO
R6
500Ω
SEL
EN
GND
13
4425 TA09
22μF
SVIN
PVIN, 1, 2, 3
L2
2.2μH
3.3V
SW1
20pF
EN1
750k
10μF
240k
FB1
EN2
L3
2.5μH
EN3
1.8V
SW2
MODE
RT
LTC3569
(UD PACKAGE)
20pF
300k
4.7μF
240k
FB2
L4
2.5μH
PGOOD
D1: DIODES INC. DFLS240
L1: SUMIDA CDRH4D22/HP-2R2
L2: WURTH 7440430022
L3, L4 WURTH 744031002
CSP1, CSP2:
1.2V
SW3
SGND
20pF
PGND, 1, 2, 3
150k
4.7μF
240k
FB3
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTC3625-1
LTC3625
1A High Efficiency SuperCap Charger
Programmable Average Charge Current 1A, 12-Lead
3mm × 4mm DFN Package
LT3485-0/LT3485-1/
LT3485-2/LT3485-3
1.4A/0.7A/1A/2A Photoflash Capacitor Charger with Output
Voltage Monitor and IGBT
VIN; 1.8V to 10V, Charge Time = 3.7 Seconds for the LT3485-0 (0V to
320V, 100μF, VIN = 3.6V), ISD < 1μA, 3mm × 3mm 10-Lead DFN
LT3750
Capacitor Charger Controller
Charges Any Size Capacitor, 10-Lead MS Package
LT3751
Capacitor Controller with Regulation
Charges Any Size Capacitor, 4mm x 5mm QFN-20 Package
LTC3225-1
LTC3225
150mA Supercapacitor Charger
Programmable Supercapacitor Charger Designed to Charge Two
Supercapacitors in Series to a Fixed Output Voltage
(4.8V/5/3V Selectable)
4425p
20 Linear Technology Corporation
LT 0310 • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2010