Microchip MCP633 Unity-gain stable Datasheet

MCP631/2/3/4/5/9
24 MHz, 2.5 mA Rail-to-Rail Output (RRO) Op Amps
Features:
Description:
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The Microchip Technology Inc. MCP631/2/3/4/5/9
family of operational amplifiers features high gain
bandwidth product (24 MHz, typical) and high output
short-circuit current (70 mA, typical). Some also
provide a Chip Select (CS) pin that supports a
low-power mode of operation. These amplifiers are
optimized for high speed, low noise and distortion,
single-supply operation with rail-to-rail output and an
input that includes the negative rail.
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Gain-Bandwidth Product: 24 MHz
Slew Rate: 10 V/µs
Noise: 10 nV/Hz at 1 MHz)
Low Input Bias Current: 4 pA (typical)
Ease of Use:
- Unity-Gain Stable
- Rail-to-Rail Output
- Input Range including Negative Rail
- No Phase Reversal
Supply Voltage Range: +2.5V to +5.5V
High Output Current: ±70 mA
Supply Current: 2.5 mA/ch (typical)
Low-Power Mode: 1 µA/ch
Small Packages: SOT23-5, DFN
Extended Temperature Range: -40°C to +125°C
This family is offered in single (MCP631), single with
CS pin (MCP633), dual (MCP632), dual with two CS
pins (MCP635), quad (MCP634) and quad with two
Chip Select pins (MCP639). All devices are fully
specified from -40°C to +125°C.
Typical Application Circuit
Typical Applications:
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MCP63X
0A – 20 A
+5V
Fast Low-Side Current Sensing
Point-of-Load Control Loops
Power Amplifier Control Loops
Barcode Scanners
Optical Detector Amplifier
Multi-Pole Active Filter
51.1
+
0.005
51.1
VOUT
-
0V – 4V
2.0 k
Design Aids:
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SPICE Macro Models
FilterLab® Software
Microchip Advanced Part Selector (MAPS)
Analog Demonstration and Evaluation Boards
Application Notes
High Gain-Bandwidth Op Amp Portfolio
Model Family
Channels/Package
Gain-Bandwidth
VOS (max.)
IQ/Ch (typ.)
MCP621/1S/2/3/4/5/9
1, 2, 4
20 MHz
0.2 mV
2.5 mA
MCP631/2/3/4/5/9
1, 2, 4
24 MHz
8.0 mV
2.5 mA
MCP651/1S/2/3/4/5/9
1, 2, 4
50 MHz
0.2 mV
6.0 mA
1, 2, 3, 4
60 MHz
8.0 mV
6.0 mA
MCP660/1/2/3/4/5/9
 2009-2014 Microchip Technology Inc.
DS20002197C-page 1
MCP631/2/3/4/5/9
Package Types
MCP631
SOIC
MCP631
2x3 TDFN*
NC 1
8 NC
VIN– 2
7 VDD
VIN+ 3
6 VOUT
VSS 4
5 NC
NC 1
VIN– 2
VIN+ 3
8 VDD
VINA– 2
7 VOUTB VINA– 2
6 VINB- VINA+ 3
5 VINB+
VSS 4
EP
9
7 VDD
VSS 2
6 VOUT
5 NC
VOUTA 1
VOUTA 1
14 VOUTD
VINA- 2
VINA+ 3
VDD 4
13 VIND-
VINB+ 5
VINB- 6
10 VINC+
VOUTB 7
8 VOUTC
12 VIND+
11 VSS
9 VINC-
MCP633
SOT-23-6
7 VOUTB
6 VINB–
5 VINB+
VSS 4
4 VIN-
VIN+ 3
8 VDD
EP
9
MCP634
SOIC, TSSOP
5 VDD
VOUT 1
MCP632
3x3 DFN*
VOUTA 1
VINA+ 3
8 NC
VSS 4
MCP632
SOIC
MCP631
SOT-23-5
VOUT 1
VSS 2
VIN+ 3
MCP633
SOIC
NC 1
8 CS
VIN– 2
7 VDD
VIN+ 3
6 VOUT
6 VDD
5
CS
VSS 4
4 VIN-
5 NC
9 VOUTB
VSS 4
CSA 5
8 VINB7 VINB+
6 CSB
1
2
3
4
5
EP
11
VIND-
VOUTD
CSAD
16 15 14 13
10 VDD
VINA- 1
9
8
7
6
VINA+ 2
VOUTB
VINBVINB+
CSB
12 VIND+
11 VSS
EP
17
VDD 3
10 VINC+
9 VINC-
VINB+ 4
5
6
7
8
VOUTC
VINA– 2
VINA+ 3
VOUTA
VINA–
VINA+
VSS
CSA
CSBC
10 VDD
VINB-
VOUTA 1
MCP635
3x3 DFN*
VOUTB
MCP635
MSOP
VOUTA
MCP639
4x4 QFN*
* Includes Exposed Thermal Pad (EP); see Table 3-1.
DS20002197C-page 2
 2009-2014 Microchip Technology Inc.
MCP631/2/3/4/5/9
1.0
ELECTRICAL
CHARACTERISTICS
1.1
Absolute Maximum Ratings †
† Notice: Stresses above those listed under “Absolute
Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of
the device at those or any other conditions above those
indicated in the operational listings of this specification is not
implied. Exposure to maximum rating conditions for extended
periods may affect device reliability.
VDD – VSS .......................................................................6.5V
Current at Input Pins ....................................................±2 mA
Analog Inputs (VIN+ and VIN–) †† . VSS – 1.0V to VDD + 1.0V
All other Inputs and Outputs .......... VSS – 0.3V to VDD + 0.3V
Output Short-Circuit Current ................................ Continuous
Current at Output and Supply Pins ..........................±150 mA
Storage Temperature ...................................-65°C to +150°C
Maximum Junction Temperature ................................ +150°C
ESD protection on all pins (HBM, MM)  1 kV, 200V
1.2
†† See Section 4.1.2 “Input Voltage and Current Limits”.
Specifications
DC ELECTRICAL SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to +5.5V, VSS = GND, VCM = VDD/3,
VOUT  VDD/2, VL = VDD/2, RL = 2 k to VL and CS = VSS (refer to Figure 1-2).
Parameters
Sym.
Min.
Typ.
Max.
Units
Conditions
Input Offset
Input Offset Voltage
Input Offset Voltage Drift
VOS
-8
±1.8
+8
VOS/TA
—
±2.0
—
PSRR
61
76
—
IB
—
4
—
pA
IB
—
100
—
pA
TA = +85°C
TA = +125°C
Power Supply Rejection Ratio
mV
µV/°C TA = -40°C to +125°C
dB
Input Current and Impedance
Input Bias Current
Across Temperature
IB
—
1500
5000
pA
Input Offset Current
Across Temperature
IOS
—
±2
—
pA
Common-Mode Input Impedance
ZCM
—
1013||9
—
||pF
Differential Input Impedance
ZDIFF
—
1013||2
—
||pF
Common-Mode Input Voltage Range
VCMR
VSS  0.3
—
VDD  1.3
V
Note 1
Common-Mode Rejection Ratio
CMRR
63
78
—
dB
VDD = 2.5V, VCM = -0.3V to 1.2V
66
81
—
dB
VDD = 5.5V, VCM = -0.3V to 4.2V
Common Mode
Open-Loop Gain
DC Open-Loop Gain (large signal)
AOL
88
115
—
dB
VDD = 2.5V, VOUT = 0.3V to 2.2V
94
124
—
dB
VDD = 5.5V, VOUT = 0.3V to 5.2V
VSS + 20
—
VDD  20
mV
VDD = 2.5V, G = +2,
0.5V Input Overdrive
VSS + 40
—
VDD  40
mV
VDD = 5.5V, G = +2,
0.5V Input Overdrive
Output
Maximum Output Voltage Swing
Output Short-Circuit Current
VOL, VOH
ISC
±40
±85
±130
mA
VDD = 2.5V (Note 2)
ISC
±35
±70
±110
mA
VDD = 5.5V (Note 2)
VDD
2.5
—
5.5
V
IQ
1.2
2.5
3.6
mA
Power Supply
Supply Voltage
Quiescent Current per Amplifier
Note 1:
2:
No Load Current
See Figure 2-5 for temperature effects.
The ISC specifications are for design guidance only; they are not tested.
 2009-2014 Microchip Technology Inc.
DS20002197C-page 3
MCP631/2/3/4/5/9
AC ELECTRICAL SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to +5.5V, VSS = GND, VCM = VDD/2,
VOUT  VDD/2, VL = VDD/2, RL = 2 k to VL, CL = 50 pF and CS = VSS (refer to Figure 1-2).
Parameters
Sym.
Min.
Typ.
Max.
Units
MHz
Conditions
AC Response
Gain-Bandwidth Product
GBWP
—
24
—
PM
—
65
—
°
ROUT
—
20
—

THD + N
—
0.0015
—
%
G = +1, VOUT = 2VP-P, f = 1 kHz,
VDD = 5.5V, BW = 80 kHz
G = +1, VOUT = 100 mVP-P
Phase Margin
Open-Loop Output Impedance
G = +1
AC Distortion
Total Harmonic Distortion plus Noise
Step Response
tr
—
20
—
ns
SR
—
10
—
V/µs
G = +1
Input Noise Voltage
Eni
—
16
—
µVP-P
f = 0.1 Hz to 10 Hz
Input Noise Voltage Density
eni
—
10
—
nV/Hz f = 1 MHz
Input Noise Current Density
ini
4
—
fA/Hz f = 1 kHz
Rise Time, 10% to 90%
Slew Rate
Noise
DIGITAL ELECTRICAL SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to +5.5V, VSS = GND, VCM = VDD/2,
VOUT  VDD/2, VL = VDD/2, RL = 2 k to VL, CL = 50 pF and CS = VSS (refer to Figures 1-1 and 1-2).
Parameters
Sym.
Min.
Typ.
Max.
Units
Conditions
CS Logic Threshold, Low
VIL
VSS
—
0.2VDD
V
CS Input Current, Low
ICSL
—
0.1
—
nA
CS Logic Threshold, High
VIH
0.8VDD
VDD
V
CS Input Current, High
ICSH
—
0.7
—
µA
GND Current
ISS
-2
-1
—
µA
CS Internal Pull-Down Resistor
RPD
—
5
—
M
IO(LEAK)
—
50
—
nA
VHYST
—
0.25
—
V
CS High to Amplifier Off Time
(output goes High Z)
tOFF
—
200
—
ns
G = +1 V/V, VL = VSS,
CS = 0.8VDD to VOUT = 0.1(VDD/2)
CS Low to Amplifier On Time
tON
—
2
10
µs
G = +1 V/V, VL = VSS,
CS = 0.2VDD to VOUT = 0.9(VDD/2)
CS Low Specifications
CS = 0V
CS High Specifications
Amplifier Output Leakage
CS = VDD
CS = VDD, TA = +125°C
CS Dynamic Specifications
CS Input Hysteresis
DS20002197C-page 4
 2009-2014 Microchip Technology Inc.
MCP631/2/3/4/5/9
TEMPERATURE SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, all limits are specified for: VDD = +2.5V to +5.5V, VSS = GND.
Parameters
Sym.
Min.
Typ.
Max.
Units
Conditions
Temperature Ranges
Specified Temperature Range
TA
-40
—
+125
°C
Operating Temperature Range
TA
-40
—
+125
°C
Storage Temperature Range
TA
-65
—
+150
°C
Note 1
Thermal Package Resistances
Thermal Resistance, 5L-SOT-23
θJA
—
201.0
—
°C/W
Thermal Resistance, 6L-SOT-23
θJA
—
190.5
—
°C/W
Thermal Resistance, 8L-2x3 TDFN
θJA
—
52.5
—
°C/W
Thermal Resistance, 8L-3x3 DFN
θJA
—
56.7
—
°C/W
Thermal Resistance, 8L-SOIC
θJA
—
149.5
—
°C/W
Thermal Resistance, 10L-3x3 DFN
θJA
—
54.0
—
°C/W
Thermal Resistance, 10L-MSOP
θJA
—
202
—
°C/W
Thermal Resistance, 14L-SOIC
θJA
—
90.8
—
°C/W
Thermal Resistance, 14L-TSSOP
θJA
—
100
—
°C/W
Thermal Resistance, 16L-4x4-QFN
θJA
—
52.1
—
°C/W
Timing Diagram
ICS
Note 2
ISS
tOFF
High Z
High Z
On
-2.5 mA
(typical)
-1 µA
(typical)
FIGURE 1-1:
0.7 µA
(typical)
VIH
VIL
tON
VOUT
EQUATION 1-1:
0.1 nA
(typical)
0.7 µA
(typical)
CS
1.4
Note 2
Operation must not cause TJ to exceed Maximum Junction Temperature specification (+150°C).
Measured on a standard JC51-7, four-layer printed circuit board with ground plane and vias.
Note 1:
2:
1.3
Note 2
-1 µA
(typical)
Timing Diagram.
Test Circuits
The circuit used for most DC and AC tests is shown in
Figure 1-2. It independently sets VCM and VOUT; see
Equation 1-1. The circuit’s Common-Mode voltage is
(VP + VM)/2, not VCM. VOST includes VOS plus the
effects of temperature, CMRR, PSRR and AOL.
 2009-2014 Microchip Technology Inc.
RF
G DM = ------RG
G N = 1 + G DM
1
1
VCM = V P  1 – ------- + V REF  -------

 G N
G N
VOST = V IN- – V IN+
VOUT = V REF +  V P – V M G DM + VOST G N
Where:
GDM = Differential Mode Gain
GN = Noise Gain
(V/V)
(V/V)
VCM = Op Amp’s Common-Mode
Input Voltage
VOST = Op Amp’s Total Input Offset
Voltage
(V)
(mV)
DS20002197C-page 5
MCP631/2/3/4/5/9
CF
6.8 pF
RG
10 k
RF
10 k
VREF = VDD/2
VP
VDD
VIN+
CB1
100 nF
MCP63X
CB2
2.2 µF
VINVM
RG
10 k
RL
2 k
RF
10 k
CF
6.8 pF
VOUT
CL
50 pF
VL
FIGURE 1-2:
AC and DC Test Circuit for
Most Specifications.
DS20002197C-page 6
 2009-2014 Microchip Technology Inc.
MCP631/2/3/4/5/9
2.0
TYPICAL PERFORMANCE CURVES
Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,
VL = VDD/2, RL = 2 kto VL, CL = 50 pF and CS = VSS.
DC Signal Inputs
Percentage of Occurrences
14%
396 Samples
TA = +25°C
VDD = 2.5V and 5.5V
12%
10%
8%
6%
4%
2%
0%
-6 -5 -4 -3 -2 -1 0 1 2 3
Input Offset Voltage (mV)
FIGURE 2-1:
14%
12%
5
-1.0
-1.2
-1.4
-1.6
-1.8
-2.0
-2.2
-2.4
-2.6
-2.8
-3.0
6
Input Offset Voltage.
Representative Part
VDD = 2.5V
VDD = 5.5V
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Output Voltage (V)
FIGURE 2-4:
Output Voltage.
0.0
398 Samples
VDD = 2.5V and 5.5V
TA = -40°C to +125°C
Low Input Common
Mode Headroom (V)
Percentage of Occurrences
16%
4
Input Offset Voltage (mV)
2.1
10%
8%
6%
4%
2%
0%
1 Lot
Low (VCMR_L – VSS)
-0.1
-0.2
-0.3
VDD = 2.5V and 5.5V
-0.4
-0.5
-8 -7 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 7 8
-50
-25
Input Offset Voltage Drift (µV/°C)
-2.0
-2.2
-2.4
-2.6
-2.8
-3.0
-3.2
-3.4
-3.6
-3.8
-4.0
Input Offset Voltage Drift.
1.3
Representative Part
VCM = VSS
+125°C
+85°C
+25°C
-40°C
0
25
50
75
100
Ambient Temperature (°C)
125
FIGURE 2-5:
Low-Input Common-Mode
Voltage Headroom vs. Ambient Temperature.
High Input Common
Mode Headroom (V)
Input Offset Voltage (mV)
FIGURE 2-2:
Input Offset Voltage vs.
1 Lot
High (VDD – VCMR_H)
1.2
VDD = 2.5V
1.1
1.0
VDD = 5.5V
0.9
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5
Power Supply Voltage (V)
FIGURE 2-3:
Input Offset Voltage vs.
Power Supply Voltage with VCM = 0V.
 2009-2014 Microchip Technology Inc.
-50
-25
0
25
50
75
100
Ambient Temperature (°C)
125
FIGURE 2-6:
High-Input Common-Mode
Voltage Headroom vs. Ambient Temperature.
DS20002197C-page 7
MCP631/2/3/4/5/9
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,
VL = VDD/2, RL = 2 kto VL, CL = 50 pF and CS = VSS.
1.5
130
VDD = 2.5V
Representative Part
DC Open-Loop Gain (dB)
Input Offset Voltage (mV)
2.0
+125°C
+85°C
+25°C
-40°C
1.0
0.5
0.0
-0.5
-1.0
-1.5
VDD = 5.5V
120
115
VDD = 2.5V
110
105
100
3.0
2.5
2.0
1.5
1.0
0.5
-0.5
0.0
-2.0
125
-50
-25
Input Common Mode Voltage (V)
1.0
+125°C
+85°C
+25°C
-40°C
0.5
0.0
-0.5
-1.0
-1.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
-0.5
-2.0
Input Common Mode Voltage (V)
120
115
VDD = 2.5V
110
105
100
95
100
1.E+02
1.E-08
10n
Input Bias, Offset Currents
(pA)
CMRR, PSRR (dB)
VDD = 5.5V
125
1k
10k
1.E+03
1.E+04
Load Resistance (Ω)
FIGURE 2-11:
Load Resistance.
FIGURE 2-8:
Input Offset Voltage vs.
Common-Mode Voltage with VDD = 5.5V.
110
105
100
95
90
85
80
75
70
65
60
125
130
VDD = 5.5V
Representative Part
DC Open-Loop Gain (dB)
Input Offset Voltage (mV)
1.5
100
FIGURE 2-10:
DC Open-Loop Gain vs.
Ambient Temperature.
FIGURE 2-7:
Input Offset Voltage vs.
Common-Mode Voltage with VDD = 2.5V.
2.0
0
25
50
75
Ambient Temperature (°C)
100k
1.E+05
DC Open-Loop Gain vs.
VDD = 5.5V
VCM = VCMR_H
1n
1.E-09
CMRR, VDD = 2.5V
CMRR, VDD = 5.5V
100p
1.E-10
IB
10p
1.E-11
PSRR
| IOS |
1p
1.E-12
-50
-25
0
25
50
75
Ambient Temperature (°C)
100
FIGURE 2-9:
CMRR and PSRR vs.
Ambient Temperature.
DS20002197C-page 8
125
25
45
65
85
105
Ambient Temperature (°C)
125
FIGURE 2-12:
Input Bias and Offset
Currents vs. Ambient Temperature with
VDD = 5.5V.
 2009-2014 Microchip Technology Inc.
MCP631/2/3/4/5/9
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,
VL = VDD/2, RL = 2 kto VL, CL = 50 pF and CS = VSS.
Input Current Magnitude (A)
1.E-03
1m
100µ
1.E-04
10µ
1.E-05
1µ
1.E-06
100n
1.E-07
10n
1.E-08
1n
1.E-09
100p
1.E-10
+125°C
+85°C
+25°C
-40°C
10p
1.E-11
1p
1.E-12
-1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0
Input Voltage (V)
FIGURE 2-13:
Input Bias Current vs. Input
Voltage (below VSS).
150
IB
100
50
0
IOS
-50
-100
-150
Representative Part
TA = +85°C
VDD = 5.5V
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
-200
0.0
Input Bias, Offset Currents
(pA)
200
Common Mode Input Voltage (V)
FIGURE 2-14:
Input Bias and Offset
Currents vs. Common-Mode Input Voltage with
TA = +85°C.
Input Bias, Offset Currents
(pA)
2000
IB
1500
1000
500
IOS
0
-500
-1000
Representative Part
TA = +125°C
VDD = 5.5V
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
-1500
Common Mode Input Voltage (V)
FIGURE 2-15:
Input Bias and Offset
Currents vs. Common-Mode Input Voltage with
TA = +125°C.
 2009-2014 Microchip Technology Inc.
DS20002197C-page 9
MCP631/2/3/4/5/9
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,
VL = VDD/2, RL = 2 kto VL, CL = 50 pF and CS = VSS.
Other DC Voltages and Currents
3.5
3.0
VDD = 5.5V
Supply Current
(mA/amplifier)
100
VDD = 2.5V
VOL – VSS
10
6.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
100
Power Supply Voltage (V)
FIGURE 2-19:
Supply Voltage.
Supply Current vs. Power
3.5
RL = 2 kΩ
3.0
Supply Current
(mA/amplifier)
VOL – VSS
VDD = 5.5V
VDD = 5.5V
2.5
2.0
VDD = 2.5V
1.5
1.0
0.5
VDD – VOH
6.0
5.5
5.0
4.5
4.0
Common Mode Input Voltage (V)
FIGURE 2-17:
Output Voltage Headroom
vs. Ambient Temperature.
100
80
60
40
20
0
-20
-40
-60
-80
-100
3.5
125
3.0
100
2.5
0.0
0
25
50
75
Ambient Temperature (°C)
2.0
-25
1.5
-50
1.0
VDD = 2.5V
-0.5
Output Headroom (mV)
1.0
0.0
1
10
Output Current Magnitude (mA)
FIGURE 2-16:
Output Voltage Headroom
vs. Output Current.
FIGURE 2-20:
Supply Current vs.
Common-Mode Input Voltage.
6.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
+125°C
+85°C
+25°C
-40°C
0.0
Output Short Circuit Current
(mA)
+125°C
+85°C
+25°C
-40°C
1.5
0.0
1
20
18
16
14
12
10
8
6
4
2
0
2.0
0.5
VDD – VOH
0.1
2.5
0.5
Output Voltage Headroom
(mV)
1000
0.0
2.2
Power Supply Voltage (V)
FIGURE 2-18:
Output Short-Circuit Current
vs. Power Supply Voltage.
DS20002197C-page 10
 2009-2014 Microchip Technology Inc.
MCP631/2/3/4/5/9
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,
VL = VDD/2, RL = 2 kto VL, CL = 50 pF and CS = VSS.
Frequency Response
34
80
70
60
50
CMRR
PSRR+
PSRR-
30
20
55
24
50
22
45
GBWP
0
36
-30
34
100
-60
AOL
-90
60
-120
40
-150
| AOL |
-180
0
-210
-20
-240
65
60
55
50
22
GBWP
20
-50
-25
0
25
50
75 100
Ambient Temperature (°C)
45
40
125
FIGURE 2-23:
Gain-Bandwidth Product
and Phase Margin vs. Ambient Temperature.
 2009-2014 Microchip Technology Inc.
Closed-Loop Output Impedance (Ω)
70
Phase Margin (°)
32
24
6.0
5.5
5.0
4.5
4.0
3.5
60
26
55
24
50
22
45
GBWP
40
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Output Voltage (V)
80
75
VDD = 5.5V
VDD = 2.5V
65
VDD = 5.5V
VDD = 2.5V
28
FIGURE 2-25:
Gain-Bandwidth Product
and Phase Margin vs. Output Voltage.
34
30
70
20
Open-Loop Gain vs.
PM
75
PM
30
Frequency (Hz)
36
80
32
1 1.E+1
1M 10M
10 1.E+2
100 1.E+3
1k 1.E+4
10k 100k
1.E+0
1.E+5 1.E+6
1.E+7 100M
1.E+8
FIGURE 2-22:
Frequency.
3.0
FIGURE 2-24:
Gain-Bandwidth Product
and Phase Margin vs. Common-Mode Input
Voltage.
120
20
2.5
Common Mode Input Voltage (V)
CMRR and PSRR vs.
80
2.0
40
1.5
10M
1.E+7
1.0
1M
1.E+6
0.5
100k
1.E+5
Frequency (Hz)
0.0
10k
1.E+4
Gain Bandwidth Product
(MHz)
Open-Loop Gain (dB)
60
26
140
Gain Bandwidth Product
(MHz)
65
VDD = 5.5V
VDD = 2.5V
28
-0.5
1k
1.E+3
FIGURE 2-21:
Frequency.
26
70
30
20
10
100
1.E+2
28
75
PM
32
Phase Margin (°)
40
80
Phase Margin (°)
36
90
Gain Bandwidth Product
(MHz)
100
Open-Loop Phase (°)
CMRR, PSRR (dB)
2.3
100
10
G = 101 V/V
G = 11 V/V
G = 1 V/V
1
0.1
10k
1.0E+04
100k
1.0E+05
1M
10M
1.0E+06
1.0E+07
Frequency (Hz)
100M
1.0E+08
FIGURE 2-26:
Closed-Loop Output
Impedance vs. Frequency.
DS20002197C-page 11
MCP631/2/3/4/5/9
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,
10
150
9
140
8
GN = 1 V/V
GN = 2 V/V
GN  4 V/V
7
6
5
4
3
2
100p
1n
1.0E-10
1.0E-09
Normalized Capacitive Load; CL/GN (F)
FIGURE 2-27:
Gain Peaking vs.
Normalized Capacitive Load.
DS20002197C-page 12
RS = 0Ω
RS = 100Ω
RS = 1 kΩ
130
120
110
VCM = VDD/2
G = +1 V/V
100
90
80
70
60
1
0
10p
1.0E-11
Channel-to-Channel
Separation; RTI (dB)
Gain Peaking (dB)
VL = VDD/2, RL = 2 kto VL, CL = 50 pF and CS = VSS.
RS = 10 kΩ
RS = 100 kΩ
50
1k
1.E+03
10k
1.E+04
100k
1M
1.E+05
1.E+06
Frequency (Hz)
10M
1.E+07
FIGURE 2-28:
Channel-to-Channel
Separation vs. Frequency.
 2009-2014 Microchip Technology Inc.
MCP631/2/3/4/5/9
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,
VL = VDD/2, RL = 2 kto VL, CL = 50 pF and CS = VSS.
Noise and Distortion
1.E+4
10µ
Input Noise; e ni(t) (µV)
20
1.E+3
1µ
1.E+2
100n
10n
1.E+1
1
1.E+0
10
5
0
-5
-10
Analog NPBW = 0.1 Hz
Sample Rate = 2 SPS
VOS = -3150 µV
-15
1k
1.E+3
10k
1.E+4
0
1M 1.E+7
100k
10M
1.E+5 1.E+6
Frequency (Hz)
Input Noise Voltage Density
5
10 15 20 25 30 35 40 45 50 55 60 65
Time (min)
FIGURE 2-32:
0.1 Hz Filter.
THD + Noise (%)
V DD = 2.5V
VDD = 5.5V
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.0
0.5
FIGURE 2-30:
Input Noise Voltage Density
vs. Input Common-Mode Voltage with
f = 100 Hz.
0.01
0.001
0.0001
100
1.E+2
FIGURE 2-33:
VDD = 5.0V
VOUT = 2 VP-P
1k
1.E+3
10k
1.E+4
Frequency (Hz)
100k
1.E+5
THD+N vs. Frequency.
VDD = 2.5V
VDD = 5.5V
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
f = 1 MHz
-0.5
Input Noise Voltage Density
(nV/Hz)
G = 1 V/V
G = 11 V/V
BW = 22 Hz to > 500 kHz
BW = 22 Hz to 80 kHz
f = 100 Hz
0.0
0.1
Common Mode Input Voltage (V)
20
18
16
14
12
10
8
6
4
2
0
Input Noise vs. Time with
1
-0.5
Input Noise Voltage Density
(nV/Hz)
100
1.E+2
10
1.E+1
FIGURE 2-29:
vs. Frequency.
200
180
160
140
120
100
80
60
40
20
0
Representative Part
15
-20
1n
1.E+0
0.1
1.E-1
1.5
Input Noise Voltage Density (V/Hz)
2.4
Common Mode Input Voltage (V)
FIGURE 2-31:
Input Noise Voltage Density
vs. Input Common-Mode Voltage with f = 1 MHz.
 2009-2014 Microchip Technology Inc.
DS20002197C-page 13
MCP631/2/3/4/5/9
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,
VL = VDD/2, RL = 2 kto VL, CL = 50 pF and CS = VSS.
2.5
Time Response
0.0
0.1
VOUT
0.2
Output Voltage (V)
FIGURE 2-34:
Step Response.
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
Output Voltage (V)
VIN
0.3
0.4
0.5
Time (µs)
0.6
0.7
Non-Inverting Small Signal
VIN
VOUT
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
Time (µs)
FIGURE 2-37:
Response.
Inverting Large Signal Step
VOUT
VDD = 5.5V
G=2
6
VOUT
5
VIN
4
3
2
1
0
-1
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
Time (µs)
FIGURE 2-35:
Step Response.
Non-Inverting Large Signal
0
Slew Rate (V/µs)
Output Voltage (10 mV/div)
VDD = 5.5V
G = -1
RF = 1 kΩ
VOUT
0.1
0.2
FIGURE 2-36:
Response.
DS20002197C-page 14
0.3
0.4
0.5
Time (µs)
0.6
0.7
0.8
Inverting Small Signal Step
1
2
3
4
5
6
Time (ms)
7
8
9
10
FIGURE 2-38:
The MCP631/2/3/4/5/9
Family Shows No Input Phase Reversal With
Overdrive.
VIN
0.0
VDD = 5.5V
G = -1
RF = 1 kΩ
7
VDD = 5.5V
G=1
VIN
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
0.8
Input, Output Voltages (V)
Output Voltage (10 mV/div)
VDD = 5.5V
G=1
24
22
20
18
16
14
12
10
8
6
4
2
0
Falling Edge
VDD = 5.5V
VDD = 2.5V
Rising Edge
-50
-25
FIGURE 2-39:
Temperature.
0
25
50
75
Ambient Temperature (°C)
100
125
Slew Rate vs. Ambient
 2009-2014 Microchip Technology Inc.
MCP631/2/3/4/5/9
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,
VL = VDD/2, RL = 2 kto VL, CL = 50 pF and CS = VSS.
Maximum Output Voltage
Swing (V P-P )
10
VDD = 5.5V
VDD = 2.5V
1
0.1
100k
1.E+05
1M
10M
1.E+06
1.E+07
Frequency (Hz)
100M
1.E+08
FIGURE 2-40:
Maximum Output Voltage
Swing vs. Frequency.
 2009-2014 Microchip Technology Inc.
DS20002197C-page 15
MCP631/2/3/4/5/9
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,
VL = VDD/2, RL = 2 kto VL, CL = 50 pF and CS = VSS.
Chip Select Response
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
0.40
CS = VDD
0.35
CS Hysteresis (V)
CS Current (µA)
2.6
0.30
0.25
0.15
0.05
0.00
FIGURE 2-41:
Supply Voltage.
CS Current vs. Power
3.0
-50
2.0
1.5
VOUT
1.0
On
0.5
0.0
Off
100
125
CS Hysteresis vs. Ambient
4
3
VDD = 2.5V
2
1
VDD = 5.5V
Off
0
-0.5
2
4
6
8
10 12
Time (µs)
14
16
18
20
FIGURE 2-42:
CS and Output Voltages vs.
Time with VDD = 2.5V.
6
5
4
3
VOUT
2
On
1
-25
Off
Off
0
25
50
75
Ambient Temperature (°C)
100
125
FIGURE 2-45:
CS Turn-On Time vs.
Ambient Temperature.
8
VDD = 5.5V
G=1
VL = 0V
CS
-50
CS Pull-down Resistor
(MΩ)
0
0
0
25
50
75
Ambient Temperature (°C)
5
VDD = 2.5V
G=1
VL = 0V
CS
-25
FIGURE 2-44:
Temperature.
CS Turn On Time (µs)
2.5
CS, V OUT (V)
VDD = 2.5V
0.10
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Power Supply Voltage (V)
CS, V OUT (V)
VDD = 5.5V
0.20
Representative Part
7
6
5
4
3
2
1
0
-1
0
2
4
6
8
10 12
Time (µs)
14
16
18
20
FIGURE 2-43:
CS and Output Voltages vs.
Time with VDD = 5.5V.
DS20002197C-page 16
-50
-25
0
25
50
75
Ambient Temperature (°C)
100
125
FIGURE 2-46:
CS Pull-Down Resistor
(RPD) vs. Ambient Temperature.
 2009-2014 Microchip Technology Inc.
MCP631/2/3/4/5/9
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,
CS = VDD
1.E-06
1µ
Output Leakage Current (A)
0.0
-0.2
-0.4
-0.6
-0.8
-1.0
-1.2
-1.4
-1.6
-1.8
-2.0
-2.2
CS = VDD = 5.5V
100n
1.E-07
10n
1.E-08
1n
1.E-09
+125°C
+85°C
Power Supply Voltage (V)
FIGURE 2-47:
Quiescent Current in
Shutdown vs. Power Supply Voltage.
 2009-2014 Microchip Technology Inc.
6.5
6.0
5.5
5.0
4.5
4.0
100p
1.E-10
3.5
3.0
2.5
2.0
1.5
1.0
0.5
-40°C
+25°C
+85°C
+125°C
0.0
Negative Power Supply
Current; I SS (µA)
VL = VDD/2, RL = 2 kto VL, CL = 50 pF and CS = VSS.
+25°C
10p
1.E-11
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
Output Voltage (V)
FIGURE 2-48:
Output Voltage.
Output Leakage Current vs.
DS20002197C-page 17
MCP631/2/3/4/5/9
3.0
PIN DESCRIPTIONS
Descriptions of the pins are listed in Table 3-1.
MCP639
MCP635
MCP634
MCP633
SOT 2x3
3x3
SOT3x3
SOIC
SOIC
SOIC TSSOP MSOP
QFN
-23 TDFN
DFN
23
DFN
Symbol
SOIC
MCP632
PIN FUNCTION TABLE
MCP631
TABLE 3-1:
Description
2
4
2
2
2
2
4
2
2
2
2
1
VIN-,
VINA-
Inverting Input (op amp A)
3
3
3
3
3
3
3
3
3
3
3
2
VIN+,
VINA+
Non-Inverting Input (op
amp A)
7
5
7
8
8
7
6
4
4
10
10
3
VDD
Positive Power Supply
—
—
—
5
5
—
—
5
5
7
7
4
VINB+
Non-Inverting Input (op
amp B)
—
—
—
6
6
—
—
6
6
8
8
5
VINB-
Inverting Input (op amp B)
—
—
—
7
7
—
—
7
7
9
9
6
VOUTB
Output (op amp B)
—
—
—
—
—
—
—
—
—
—
—
7
CSBC
Chip Select Digital Input
(op amp B and C)
—
—
—
—
—
—
—
8
8
—
—
8
VOUTC
Output (op amp C)
—
—
—
—
—
—
—
9
9
—
—
9
VINC-
Inverting Input (op amp C)
—
—
—
—
—
—
—
10
10
—
—
10
VINC+
Non-Inverting Input (op
amp C)
4
2
4
4
4
4
2
11
11
4
4
11
VSS
Negative Power Supply
—
—
—
—
—
—
—
12
12
—
—
12
VIND+
Non-Inverting Input (op
amp D)
—
—
—
—
—
—
—
13
13
—
—
13
VIND-
Inverting Input (op amp D)
—
—
—
—
—
—
—
14
14
—
—
14
VOUTD
Output (op amp D)
—
—
—
—
—
—
—
—
—
—
—
15
CSAD
Chip Select Digital Input
(op amp A and D)
6
1
6
1
1
6
1
1
1
1
1
16
VOUT,
VOUTA
Output (op amp A)
—
—
9
—
9
—
—
—
—
—
11
17
EP
—
—
—
—
—
8
5
—
—
5
5
—
—
—
—
—
—
—
—
—
—
6
6
—
CSB
Chip Select Digital Input
(op amp B)
1,5,
8
—
1, 5,
8
—
—
1, 5
—
—
—
—
—
—
NC
No Internal Connection
DS20002197C-page 18
Exposed Thermal Pad
(EP); must be connected to
VSS
CS, CSA Chip Select Digital Input
(op amp A)
 2009-2014 Microchip Technology Inc.
MCP631/2/3/4/5/9
3.1
Analog Outputs
The analog output pins (VOUT) are low-impedance
voltage sources.
3.2
Analog Inputs
The non-inverting and inverting inputs (VIN+, VIN-, …)
are high-impedance CMOS inputs with low bias
currents.
3.3
Power Supply Pins
The positive power supply (VDD) is 2.5V to 5.5V higher
than the negative power supply (VSS). For normal
operation, the other pins are between VSS and VDD.
3.4
Chip Select Digital Input (CS)
This input (CS) is a CMOS, Schmitt-triggered input that
places the part into a low-power mode of operation.
3.5
Exposed Thermal Pad (EP)
There is an internal connection between the exposed
thermal pad (EP) and the VSS pin; they must be
connected to the same potential on the printed circuit
board (PCB).
This pad can be connected to a PCB ground plane to
provide a larger heat sink. This improves the package
thermal resistance (JA).
Typically, these parts are used in a single (positive)
supply configuration. In that case, VSS is connected to
ground and VDD is connected to the supply. VDD will
need bypass capacitors.
 2009-2014 Microchip Technology Inc.
DS20002197C-page 19
MCP631/2/3/4/5/9
4.0
APPLICATIONS
The MCP631/2/3/4/5/9 family is manufactured using
the Microchip state-of-the-art CMOS process. It is
designed for low-cost, low-power and high-speed
applications. Its low supply voltage, low quiescent
current
and
wide
bandwidth
make
the
MCP631/2/3/4/5/9
ideal
for
battery-powered
applications.
4.1
When implemented as shown, resistors R1 and R2 also
limit the current through D1 and D2.
VDD
V1
V2
Input
4.1.1
PHASE REVERSAL
INPUT VOLTAGE AND CURRENT
LIMITS
The electrostatic discharge (ESD) protection on the
inputs can be depicted as shown in Figure 4-1. This
structure was chosen to protect the input transistors
and to minimize input bias current (IB). The input ESD
diodes clamp the inputs when they try to go more than
one diode drop below VSS. They also clamp any
voltages that go too far above VDD; their breakdown
voltage is high enough to allow normal operation and
low enough to bypass quick ESD events within the
specified limits.
VDD
VIN+ Bond
Pad
Input
Stage
Bond V IN
Pad
R2
FIGURE 4-2:
Inputs.
Protecting the Analog
It is also possible to connect the diodes to the left of the
resistors R1 and R2. If so, the currents through the
diodes D1 and D2 need to be limited by some other
mechanism. The resistors then serve as in-rush current
limiters; the DC current into the input pins (VIN+ and
VIN-) should be very small.
A significant amount of current can flow out of the
inputs (through the ESD diodes) when the
Common-Mode voltage (VCM) is below ground (VSS);
see Figure 2-13. Applications that are high-impedance
may need to limit the usable voltage range.
NORMAL OPERATION
The input stage of the MCP631/2/3/4/5/9 op amps uses
a differential PMOS input stage. It operates at low
Common-Mode input voltages (VCM), with VCM
between VSS – 0.3V and VDD – 1.3V. To ensure proper
operation, the input offset voltage (VOS) is measured at
both VCM = VSS – 0.3V and VCM = VDD – 1.3V. See
Figures 2-5 and 2-6 for temperature effects.
Simplified Analog Input ESD
In order to prevent damage and/or improper operation
of these amplifiers, the circuit must limit the currents
(and voltages) at the input pins (see Section 1.1
“Absolute Maximum Ratings †”). Figure 4-2 shows
the recommended approach to protecting these inputs.
The internal ESD diodes prevent the input pins (VIN+
and VIN-) from going too far below ground, while the
resistors R1 and R2 limit the possible current drawn out
of the input pins. Diodes D1 and D2 prevent the input
pins (VIN+ and VIN-) from going too far above VDD and
dump any currents onto VDD.
DS20002197C-page 20
VOUT
When operating at very low non-inverting gains, the
output voltage is limited at the top by the VCM range
(< VDD – 1.3V); see Figure 4-3.
VSS Bond
Pad
FIGURE 4-1:
Structures.
MCP63X
V SS –  minimum expected V2 
R2  -----------------------------------------------------------------------2 mA
4.1.3
Bond
Pad
D2
V SS –  minimum expected V1 
R1  -----------------------------------------------------------------------2 mA
The input devices are designed to exhibit no phase
inversion when the input pins exceed the supply
voltages. Figure 2-38 shows an input voltage
exceeding both supplies with no phase inversion.
4.1.2
D1
R1
VDD
VIN
+
-
MCP63X
VOUT
V SS  V IN
V OUT  V DD – 1.3V
FIGURE 4-3:
Unity-Gain Voltage
Limitations for Linear Operation.
 2009-2014 Microchip Technology Inc.
MCP631/2/3/4/5/9
4.2
Rail-to-Rail Output
4.2.1
Figure 4-5 shows the power calculations used for a
single op amp:
MAXIMUM OUTPUT VOLTAGE
The maximum output voltage (see Figures 2-16
and 2-17) describes the output range for a given load.
For instance, the output voltage swings to within 50 mV
of the negative rail with a 1 k load tied to VDD/2.
4.2.2
OUTPUT CURRENT
• RSER is 0 in most applications and can be used
to limit IOUT.
• VOUT is the op amp’s output voltage.
• VL is the voltage at the load.
• VLG is the load’s ground point.
• VSS is usually ground (0V).
The input currents are assumed to be negligible. The
currents shown in Figure 4-5 can be approximated
using Equation 4-1:
IOUT is positive when it flows out of the op amp into the
external circuit.
EQUATION 4-1:
V OUT – V LG
I OUT = IL = -----------------------------R SER + R L
VOH Limited
(VDD = 5.5V)
RL = 1 kΩ
-ISC Limited
RL = 100Ω
RL = 10Ω
I DD  I Q + max  0, IOUT 
I SS  – I Q + min  0, IOUT 
+ISC Limited
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
-0.5
Where:
IQ = Quiescent supply current
120
80
100
60
40
0
20
-20
-40
IOUT (mA)
FIGURE 4-4:
4.2.3
-60
-100
-80
VOL Limited
-120
VOUT (V)
Figure 4-4 shows the possible combinations of output
voltage (VOUT) and output current (IOUT), when
VDD = 5.5V.
EQUATION 4-2:
Output Current.
POA(t) = IDD (VDD – VOUT) + ISS (VSS – VOUT)
POWER DISSIPATION
Since the output short-circuit current (ISC) is specified
at ±70 mA (typical), these op amps are capable of both
delivering and dissipating significant power.
PRSER(t) = IOUT2RSER
PL(t) = IL2RL
The maximum op amp power, for resistive loads,
occurs when VOUT is halfway between VDD and VLG or
halfway between VSS and VLG.
VDD
VOUT
IDD
IOUT
+
-
The instantaneous op amp power (POA(t)), RSER power
(PRSER(t)) and load power (PL(t)) are:
MCP63X
EQUATION 4-3:
2
VL
IL
ISS
RL
VLG
VSS
FIGURE 4-5:
Calculations.
max  V DD – V LG V LG – V SS 
P OAmax  ------------------------------------------------------------------------4  RSER + RL 
RSER
Diagram for Power
The maximum ambient to junction temperature rise
(TJA) and junction temperature (TJ) can be calculated
using POAmax, the ambient temperature (TA), the
package thermal resistance (JA, found in the
Temperature Specifications table) and the number of
op amps in the package (assuming equal power
dissipations), as shown in Equation 4-4:
EQUATION 4-4:
TJA = POA  t   JA  nP OAmax  JA
T J = T A + T JA
Where:
n =
 2009-2014 Microchip Technology Inc.
Number of op amps in the package (1, 2)
DS20002197C-page 21
MCP631/2/3/4/5/9
The power derating across temperature for an op amp
in a particular package can be easily calculated
(assuming equal power dissipations):
EQUATION 4-5:
T Jmax – T A
P OAmax  -------------------------n  JA
TJmax = Absolute maximum junction temperature
Several techniques are available to reduce TJA for a
given POAmax:
• Lower JA
- Use another package
- PCB layout (ground plane, etc.)
- Heat sinks and air flow
• Reduce POAmax
- Increase RL
- Limit IOUT (using RSER)
- Decrease VDD
4.3.1
GN = +1
GN  +2
100p
1n
1.E-11
1.E-10
1.E-09
Normalized Capacitance; CL/GN (F)
10n
1.E-08
FIGURE 4-7:
Recommended RISO Values
for Capacitive Loads.
After selecting RISO, double-check the resulting
frequency response peaking and step response
overshoot. Modify the value of RISO until the response
is reasonable. Bench evaluation and simulations with
the MCP631/2/3/4/5/9 SPICE macro model are helpful.
CAPACITIVE LOADS
Driving large capacitive loads can cause stability
problems for voltage feedback op amps. As the load
capacitance increases, the phase margin (stability) of
the feedback loop decreases and the closed-loop
bandwidth is reduced. This produces gain peaking in
the frequency response, with overshoot and ringing in
the step response. A unity-gain buffer (G = +1) is the
most sensitive to capacitive loads, though all gains
show the same general behavior.
When driving large capacitive loads with these op
amps (e.g., > 20 pF when G = +1), a small series
resistor at the output (RISO in Figure 4-6) improves the
phase margin of the feedback loop by making the
output load resistive at higher frequencies. The
bandwidth will be generally lower than the bandwidth
with no capacitive load.
RF
100
10
10p
1.E-12
Improving Stability
RG
Recommended R ISO (Ω)
1,000
Where:
4.3
Figure 4-7 gives recommended RISO values for
different capacitive loads and gains. The x-axis is the
normalized load capacitance (CL/GN), where GN is the
circuit’s noise gain. For non-inverting gains, GN and the
Signal Gain are equal. For inverting gains, GN is
1 + |Signal Gain| (e.g., -1 V/V gives GN = +2 V/V).
4.3.2
GAIN PEAKING
Figure 4-8 shows an op amp circuit that represents
non-inverting amplifiers (VM is a DC voltage and VP is
the input) or inverting amplifiers (VP is a DC voltage
and VM is the input). The capacitances CN and CG
represent the total capacitance at the input pins; they
include the op amp’s Common-Mode input capacitance
(CCM), board parasitic capacitance and any capacitor
placed in parallel.
VP
RN
CN
+
MCP63X
VOUT
-
VM
RISO
RG
CG
RF
VOUT
+
RN
CL
MCP63X
FIGURE 4-6:
Output Resistor, RISO,
Stabilizes Large Capacitive Loads.
FIGURE 4-8:
Capacitance.
Amplifier with Parasitic
CG acts in parallel with RG (except for a gain of +1 V/V),
which causes an increase in gain at high frequencies.
CG also reduces the phase margin of the feedback
loop, which becomes less stable. This effect can be
reduced by either reducing CG or RF.
CN and RN form a low-pass filter that affects the signal
at VP. This filter has a single real pole at 1/(2RNCN).
DS20002197C-page 22
 2009-2014 Microchip Technology Inc.
MCP631/2/3/4/5/9
1.E+05
100k
CG = 10 pF
CG = 32 pF
CG = 100 pF
CG = 320 pF
CG = 1 nF
Maximum Recommended R
(Ω)
F
The largest value of RF that should be used depends
on the noise gain (see GN in Section 4.3.1
“Capacitive Loads”), CG and the open-loop gain’s
phase shift. Figure 4-9 shows the maximum
recommended RF for several CG values. Some
applications may modify these values to reduce either
output loading or gain peaking (step response
overshoot).
10k
1.E+04
1k
1.E+03
GN > +1 V/V
100
1.E+02
1
10
Noise Gain; GN (V/V)
FIGURE 4-9:
RF vs. Gain.
100
Maximum Recommended
Figures 2-34 and 2-35 show the small signal and large
signal step responses at G = +1 V/V. The unity-gain
buffer usually has RF = 0 and RG open.
Figures 2-36 and 2-37 show the small signal and large
signal step responses at G = -1 V/V. Since the noise
gain is 2 V/V and CG  10 pF, the resistors were
chosen to be RF = RG = 1 k and RN = 500.
It is also possible to add a capacitor (CF) in parallel with
RF to compensate for the destabilizing effect of CG.
This makes it possible to use larger values of RF. The
conditions for stability are summarized in Equation 4-6.
EQUATION 4-6:
Given:
4.4
MCP633, MCP635 and MCP639
Chip Select
The MCP633 is a single amplifier with Chip Select
(CS). When CS is pulled high, the supply current drops
to 1 µA (typical) and flows through the CS pin to VSS.
When this happens, the amplifier output is put into a
high-impedance state. By pulling CS low, the amplifier
is enabled. The CS pin has an internal 5 M (typical)
pull-down resistor connected to VSS, so it will go low if
the CS pin is left floating. Figures 1-1, 2-42 and 2-43
show the output voltage and supply current response to
a CS pulse.
The MCP635 is a dual amplifier with two CS pins; CSA
controls op amp A and CSB controls op amp B. These
op amps are controlled independently, with an enabled
quiescent current (IQ) of 2.5 mA/amplifier (typical) and
a disabled IQ of 1 µA/amplifier (typical). The IQ seen at
the supply pins is the sum of the two op amps’ IQ; the
typical value for the IQ of the MCP635 will be 2 µA,
2.5 mA or 5 mA when there are 0, 1 or 2 amplifiers
enabled, respectively.
The MCP639 is a quad amplifier with two CS pins; CSB
controls op amp B and CSD controls op amp D.
4.5
Power Supply
With this family of operational amplifiers, the Power
Supply pin (VDD for single supply) should have a local
bypass capacitor (i.e., 0.01 µF to 0.1 µF) within 2 mm
for good high-frequency performance. Surface mount,
multilayer ceramic capacitors, or their equivalent,
should be used.
These op amps require a bulk capacitor (i.e., 2.2 µF or
larger) within 50 mm to provide large, slow currents.
Tantalum capacitors, or their equivalent, may be a good
choice. This bulk capacitor can be shared with other
nearby analog parts as long as crosstalk through the
supplies does not prove to be a problem.
RF
G N1 = 1 + ------RG
CG
G N2 = 1 + ------CF
1
f F = --------------------2  RF C F
G N1
f Z = f F  ----------
 G N2
We need:
f GBWP
fF  ---------------, G N1  G N2
2G N2
f GBWP
fF  ---------------, G N1  G N2
4G N1
 2009-2014 Microchip Technology Inc.
DS20002197C-page 23
MCP631/2/3/4/5/9
4.6
High-Speed PCB Layout
4.7.2
These op amps are fast enough that a little extra care
in the printed circuit board (PCB) layout can make a
significant difference in performance. Good PCB layout
techniques will help achieve the performance shown in
the specifications and typical performance curves; it
will also help minimize electromagnetic compatibility
(EMC) issues.
Use a solid ground plane. Connect the bypass local
capacitor(s) to this plane with minimal length traces.
This cuts down inductive and capacitive crosstalk.
OPTICAL DETECTOR AMPLIFIER
Figure 4-11 shows a transimpedance amplifier, using
the MCP63X op amp, in a photo detector circuit. The
photo detector is a capacitive current source. RF
provides enough gain to produce 10 mV at VOUT. CF
stabilizes the gain and limits the transimpedance
bandwidth to about 1.1 MHz. The parasitic capacitance
of RF (e.g., 0.2 pF for a 0805 SMD) acts in parallel with
CF.
CF
1.5 pF
Separate digital from analog, low-speed from
high-speed, and low-power from high-power. This will
reduce interference.
Keep sensitive traces short and straight. Separate
them from interfering components and traces. This is
especially important for high-frequency (low rise time)
signals.
Sometimes, it helps to place guard traces next to victim
traces. They should be on both sides of the victim trace
and as close as possible. Connect guard traces to
ground plane at both ends and in the middle for long
traces.
Use coax cables, or low-inductance wiring, to route
signal and power to and from the PCB. Mutual and
self-inductance of power wires is often a cause of
crosstalk and unusual behavior.
4.7
Photo
Detector
ID
100 nA
RF
100 k
CD
30 pF
+
POWER DRIVER WITH HIGH GAIN
MCP632
VDD/2
FIGURE 4-11:
Transimpedance Amplifier
for an Optical Detector.
4.7.3
H-BRIDGE DRIVER
Figure 4-12 shows the MCP632 dual op amp used as
a H-bridge driver. The load could be a speaker or a DC
motor.
Typical Applications
4.7.1
VOUT
VIN
+
½ MCP633
-
Figure 4-10 shows a power driver with high gain
(1 + R2/R1). The short-circuit current of the
MCP631/2/3/4/5/9 op amps makes it possible to drive
significant loads. The calibrated input offset voltage
supports accurate response at high gains. R3 should
be small and equal to R1||R2 in order to minimize the
bias current induced offset.
RF
RF
VOT
RL
RGT
RGB
RF
VOB
-
VDD/2
R1
R3
VIN
FIGURE 4-10:
DS20002197C-page 24
R2
VOUT
+
RL
MCP63X
Power Driver.
VDD/2
FIGURE 4-12:
+
½ MCP633
H-Bridge Driver.
This circuit automatically makes the noise gains (GN)
equal when the gains are set properly, so that the
frequency responses match well (in magnitude and in
phase). Equation 4-7 shows how to calculate RGT and
RGB so that both op amps have the same DC gains;
GDM needs to be selected first.
 2009-2014 Microchip Technology Inc.
MCP631/2/3/4/5/9
EQUATION 4-7:
VOT – V OB
GDM  --------------------------  1 V/V
VDD
V IN – ----------2
RF
R GT = --------------------G DM
------------ – 1
2
RF
R GB = -----------G DM
-----------2
Equation 4-8 gives the resulting Common-Mode and
Differential mode output voltages.
EQUATION 4-8:
VOT + V OB
V DD
--------------------------- = ----------2
2
VDD
V OT – V OB = GDM  V IN – -----------
2
 2009-2014 Microchip Technology Inc.
DS20002197C-page 25
MCP631/2/3/4/5/9
5.0
DESIGN AIDS
Microchip provides the basic design aids needed for
the MCP631/2/3/4/5/9 family of op amps.
5.1
SPICE Macro Model
The latest SPICE macro model for the
MCP631/2/3/4/5/9 op amps is available on the
Microchip web site at www.microchip.com. This model
is intended to be an initial design tool that works well in
the linear region of operation over the temperature
range of the op amp. See the model file for information
on its capabilities.
Bench testing is a very important part of any design and
cannot be replaced with simulations. Also, simulation
results using this macro model need to be validated by
comparing them to the data sheet specifications and
characteristic curves.
5.2
FilterLab® Software
Microchip’s FilterLab® software is an innovative
software tool that simplifies analog active filter (using
op amps) design. Available at no cost from the
Microchip web site at www.microchip.com/filterlab, the
FilterLab design tool provides full schematic diagrams
of the filter circuit with component values. It also
outputs the filter circuit in SPICE format, which can be
used with the macro model to simulate actual filter
performance.
5.3
Microchip Advanced Part Selector
(MAPS)
MAPS is a software tool that helps efficiently identify
Microchip devices that fit a particular design
requirement. Available at no cost from the Microchip
web site at www.microchip.com/maps, the MAPS is an
overall selection tool for Microchip’s product portfolio
that includes Analog, Memory, MCUs and DSCs. Using
this tool, a filter can be defined to sort features for a
parametric search of devices and export side-by-side
technical comparison reports. Helpful links are also
provided for data sheets, purchase and sampling of
Microchip parts.
DS20002197C-page 26
5.4
Analog Demonstration and
Evaluation Boards
Microchip offers a broad spectrum of analog
demonstration and evaluation boards that are
designed to help customers achieve faster time to
market. For a complete listing of these boards and their
corresponding user’s guides and technical information,
visit
the
Microchip
web
site
at
www.microchip.com/analog tools.
Some boards that are especially useful are:
• MCP6XXX Amplifier Evaluation Board 1,
part number: MCP6XXXEV-AMP1
• MCP6XXX Amplifier Evaluation Board 2,
part number: MCP6XXXEV-AMP2
• MCP6XXX Amplifier Evaluation Board 3,
part number: MCP6XXXEV-AMP3
• MCP6XXX Amplifier Evaluation Board 4,
part number: MCP6XXXEV-AMP4
• Active Filter Demo Board Kit,
part number: MCP6XXXDM-FLTR
• 8-Pin SOIC/MSOP/TSSOP/DIP Evaluation
Board, part number: SOIC8EV
5.5
Application Notes
The following Microchip Analog Design Note and
Application Notes are available on the Microchip web
site at www.microchip.com/appnotes and are
recommended as supplemental reference resources.
• ADN003: “Select the Right Operational Amplifier
for your Filtering Circuits”, DS21821
• AN722: “Operational Amplifier Topologies and DC
Specifications”, DS00722
• AN723: “Operational Amplifier AC Specifications
and Applications”, DS00723
• AN884: “Driving Capacitive Loads With Op
Amps”, DS00884
• AN990: “Analog Sensor Conditioning Circuits –
An Overview”, DS00990
• AN1228: “Op Amp Precision Design: Random
Noise”, DS01228
Some of these application notes, and others, are listed
in the “Signal Chain Design Guide”, DS21825.
 2009-2014 Microchip Technology Inc.
MCP631/2/3/4/5/9
6.0
PACKAGING INFORMATION
6.1
Package Marking Information
Example
5-Lead SOT-23 (MCP631)
XXNN
YV25
6-Lead SOT-23 (MCP633)
Example
XXNN
JC25
8-Lead TDFN (2x3x0.75 mm) (MCP631)
Example
ABK
425
25
8-Lead DFN (3x3x0.9 mm) (MCP632)
Device
Code
MCP632T-E/MF
DABM
Note 1:
Legend: XX...X
Y
YY
WW
NNN
e3
*
Note:
Example
DABM
1425
256
Applies to 8-lead 3x3 DFN
Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC® designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
 2009-2014 Microchip Technology Inc.
DS20002197C-page 27
MCP631/2/3/4/5/9
8-Lead SOIC (3.90 mm) (MCP631, MCP632)
Example
MCP631E
e3
SN^^1425
256
NNN
10-Lead DFN (3x3x0.9 mm) (MCP635)
Example
Device
Code
MCP635T-E/MF
BAFB
Note 1:
10-Lead MSOP (3x3 mm) (MCP635)
BAFB
1425
256
Applies to 10-lead 3x3 DFN
Example
665EUN
425256
Legend: XX...X
Y
YY
WW
NNN
e3
*
Note:
DS20002197C-page 28
Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC® designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
 2009-2014 Microchip Technology Inc.
MCP631/2/3/4/5/9
14-Lead SOIC (3.90 mm) (MCP634)
Example
MCP634
e3
E/SL^^
1425256
14-Lead TSSOP (4.4 mm) (MCP634)
Example
XXXXXXXX
YYWW
NNN
634E/ST
1425
256
16-Lead QFN (4x4x0.9 mm) (MCP639)
PIN 1
PIN 1
Legend: XX...X
Y
YY
WW
NNN
e3
*
Note:
Example
639
e3
E/ML^^
1425256
Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC® designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
 2009-2014 Microchip Technology Inc.
DS20002197C-page 29
MCP631/2/3/4/5/9
.# #$ # /
## +22--- 2
! -
/ 0 # 1 /
% # # ! #
b
N
E
E1
3
2
1
e
e1
D
A2
A
c
φ
A1
L
L1
3#
4#
5$8 %1
4
44""
5
5
7
(
!1#
6$# ! 4
56
()*
!1#
6, 9 #
! !1 /
/
# !%%
6, <!#
! !1 /
6, 4 #
<!#
)*
:
;
:
(
:
(
"
:
"
:
;
:
.#4 #
4
:
=
.# #
4
(
:
;
.# >
:
>
4
;
:
=
!/
4 !<!#
8
:
(
!"!#$! !% #$ !% #$ # & !
!# "'(
)*+ ) # & #, $ --#$## ! - * )
DS20002197C-page 30
 2009-2014 Microchip Technology Inc.
MCP631/2/3/4/5/9
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
 2009-2014 Microchip Technology Inc.
DS20002197C-page 31
MCP631/2/3/4/5/9
6-Lead Plastic Small Outline Transistor (CHY) [SOT-23]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
b
4
N
E
E1
PIN 1 ID BY
LASER MARK
1
2
3
e
e1
D
A
A2
c
φ
L
A1
L1
Units
Dimension Limits
Number of Pins
MILLIMETERS
MIN
N
NOM
MAX
6
Pitch
e
0.95 BSC
Outside Lead Pitch
e1
1.90 BSC
Overall Height
A
0.90
–
Molded Package Thickness
A2
0.89
–
1.45
1.30
Standoff
A1
0.00
–
0.15
Overall Width
E
2.20
–
3.20
Molded Package Width
E1
1.30
–
1.80
Overall Length
D
2.70
–
3.10
Foot Length
L
0.10
–
0.60
Footprint
L1
0.35
–
0.80
Foot Angle
I
0°
–
30°
Lead Thickness
c
0.08
–
0.26
Lead Width
b
0.20
–
0.51
Notes:
1. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.127 mm per side.
2. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing C04-028B
DS20002197C-page 32
 2009-2014 Microchip Technology Inc.
MCP631/2/3/4/5/9
6-Lead Plastic Small Outline Transistor (CHY) [SOT-23]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
 2009-2014 Microchip Technology Inc.
DS20002197C-page 33
MCP631/2/3/4/5/9
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS20002197C-page 34
 2009-2014 Microchip Technology Inc.
MCP631/2/3/4/5/9
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
 2009-2014 Microchip Technology Inc.
DS20002197C-page 35
MCP631/2/3/4/5/9
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS20002197C-page 36
 2009-2014 Microchip Technology Inc.
MCP631/2/3/4/5/9
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
 2009-2014 Microchip Technology Inc.
DS20002197C-page 37
MCP631/2/3/4/5/9
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS20002197C-page 38
 2009-2014 Microchip Technology Inc.
MCP631/2/3/4/5/9
!"#$%&'*+,
.# #$ # /
## +22--- 2
 2009-2014 Microchip Technology Inc.
! -
/ 0 # 1 /
% # # ! #
DS20002197C-page 39
MCP631/2/3/4/5/9
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS20002197C-page 40
 2009-2014 Microchip Technology Inc.
MCP631/2/3/4/5/9
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
 2009-2014 Microchip Technology Inc.
DS20002197C-page 41
MCP631/2/3/4/5/9
. / # 014!55&$7'*./
.# #$ # /
## +22--- 2
DS20002197C-page 42
! -
/ 0 # 1 /
% # # ! #
 2009-2014 Microchip Technology Inc.
MCP631/2/3/4/5/9
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
 2009-2014 Microchip Technology Inc.
DS20002197C-page 43
MCP631/2/3/4/5/9
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS20002197C-page 44
 2009-2014 Microchip Technology Inc.
MCP631/2/3/4/5/9
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
 2009-2014 Microchip Technology Inc.
DS20002197C-page 45
MCP631/2/3/4/5/9
UN
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS20002197C-page 46
 2009-2014 Microchip Technology Inc.
MCP631/2/3/4/5/9
UN
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
 2009-2014 Microchip Technology Inc.
DS20002197C-page 47
MCP631/2/3/4/5/9
10-Lead Plastic Micro Small Outline Package (UN) [MSOP]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS20002197C-page 48
 2009-2014 Microchip Technology Inc.
MCP631/2/3/4/5/9
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
 2009-2014 Microchip Technology Inc.
DS20002197C-page 49
MCP631/2/3/4/5/9
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS20002197C-page 50
 2009-2014 Microchip Technology Inc.
MCP631/2/3/4/5/9
.# #$ # /
## +22--- 2
 2009-2014 Microchip Technology Inc.
! -
/ 0 # 1 /
% # # ! #
DS20002197C-page 51
MCP631/2/3/4/5/9
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS20002197C-page 52
 2009-2014 Microchip Technology Inc.
MCP631/2/3/4/5/9
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
 2009-2014 Microchip Technology Inc.
DS20002197C-page 53
MCP631/2/3/4/5/9
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS20002197C-page 54
 2009-2014 Microchip Technology Inc.
MCP631/2/3/4/5/9
89 ;/ # 014!<5<5&$%'*;/
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D2
D
EXPOSED
PAD
e
E2
E
2
2
1
1
b
TOP VIEW
K
N
N
NOTE 1
L
BOTTOM VIEW
A3
A
A1
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4#
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 2009-2014 Microchip Technology Inc.
DS20002197C-page 55
MCP631/2/3/4/5/9
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS20002197C-page 56
 2009-2014 Microchip Technology Inc.
MCP631/2/3/4/5/9
APPENDIX A:
REVISION HISTORY
Revision C (July 2014)
The following is the list of modifications:
1.
2.
3.
4.
5.
Updated the Features: list.
Added the High Gain-Bandwidth Op Amp
Portfolio table in the Features: section.
Updated Figures 4-6 and 4-11.
Updated
Section 6.0
“Packaging
Information” and Section 6.1 “Package
Marking Information”.
Minor typographical changes.
Revision B (November 2011)
The following is the list of modifications:
1.
2.
3.
4.
5.
6.
Added the MCP634 and MCP639 amplifiers to
the product family and the related information
throughout the document.
Added the 2x3 TDFN (8L), SOT23 (5L) package
option for MCP631, SOT23 (6L) package option
for MCP633, 4x4 QFN (16L) package option for
MCP639, SOIC and TSSOP (14L) package
options for MCP634 and the related information
throughout the document. Updated package
types drawing with pin designation for each new
package.
Updated the Temperature Specifications table to
show the temperature specifications for new
packages.
Updated Table 3-1 to show all the pin functions.
Updated Section 6.0 “Packaging Information” with markings for the new additions.
Added the corresponding SOT23 (5L), SOT23
(6L), TDFN (8L), SOIC, TSSOP (14L), and 4x4
QFN (16L) package options and related information.
Updated table description and examples in the
Product Identification System section.
Revision A (August 2009)
• Original Release of this Document.
 2009-2014 Microchip Technology Inc.
DS20002197C-page 57
MCP631/2/3/4/5/9
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
-X
/XX
Device
Temperature
Range
Package
Examples:
a)
b)
Device:
MCP631
MCP631T
MCP632
MCP632T
MCP633
MCP633T
MCP634
MCP634T
MCP635
MCP635T
MCP639
MCP639T
Temperature
Range:
E
Package:
OT =
CHY =
MNY=
MF =
=
ML =
DS20002197C-page 58
c)
MCP631T-E/SN: Tape and Reel
Extended temperature,
8LD SOIC package
d)
MCP632T-E/MF: Tape and Reel
Extended temperature,
8LD DFN package
e)
MCP632T-E/SN: Tape and Reel
Extended temperature,
8LD SOIC package
f)
MCP633T-E/SN: Tape and Reel
Extended temperature,
8LD SOIC package
g)
MCP633T-E/CHY: Tape and Reel
Extended temperature,
6LD SOT package
h)
MCP634T-E/SL:
Tape and Reel
Extended temperature,
14LD SOIC package
i)
MCP634T-E/ST:
Tape and Reel
Extended temperature,
14LD TSSOP package
j)
MCP635T-E/MF: Tape and Reel
Extended temperature,
10LD DFN package
k)
MCP635T-E/UN: Tape and Reel
Extended temperature,
10LD MSOP package
l)
MCP639T-E/ML: Tape and Reel
Extended temperature,
16LD QFN package.
= -40°C to +125°C
SN =
UN =
SL =
ST
Single Op Amp
Single Op Amp (Tape and Reel)
(SOIC, SOT-23, TDFN)
Dual Op Amp
Dual Op Amp (Tape and Reel)
(DFN and SOIC)
Single Op Amp with CS
Single Op Amp with CS (Tape and Reel)
(SOIC, SOT-23)
Quad Op Amp
Quad Op Amp (Tape and Reel)
(TSSOP and SOIC)
Dual Op Amp with CS
Dual Op Amp with CS (Tape and Reel)
(DFN and MSOP)
Quad Op Amp
Quad Op Amp (Tape and Reel)
(QFN)
MCP631T-E/OT: Tape and Reel
Extended temperature,
5LD SOT-23 package
MCP631T-E/MNY:Tape and Reel
Extended temperature,
8LD TDFN package
Plastic Small Outline (SOT-23), 5-lead
Plastic Small Outline (SOT-23), 6-lead
Plastic Dual Flat, No Lead (2x3 TDFN), 8-lead
Plastic Dual Flat, No Lead (3×3 DFN),
8-lead, 10-lead
Plastic Small Outline (3.90 mm), 8-lead
Plastic Micro Small Outline (MSOP), 10-lead
Plastic Small Outline, Narrow, (3.90 mm SOIC),
14-lead
Plastic Thin Shrink Small Outline, (4.4 mm TSSOP),
14-lead
Plastic Quad Flat, No Lead Package (4x4 QFN),
(4x4x0.9 mm), 16-lead
 2009-2014 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
FlashFlex, flexPWR, JukeBlox, KEELOQ, KEELOQ logo, Kleer,
LANCheck, MediaLB, MOST, MOST logo, MPLAB,
OptoLyzer, PIC, PICSTART, PIC32 logo, RightTouch, SpyNIC,
SST, SST Logo, SuperFlash and UNI/O are registered
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
The Embedded Control Solutions Company and mTouch are
registered trademarks of Microchip Technology Incorporated
in the U.S.A.
Analog-for-the-Digital Age, BodyCom, chipKIT, chipKIT logo,
CodeGuard, dsPICDEM, dsPICDEM.net, ECAN, In-Circuit
Serial Programming, ICSP, Inter-Chip Connectivity, KleerNet,
KleerNet logo, MiWi, MPASM, MPF, MPLAB Certified logo,
MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code
Generation, PICDEM, PICDEM.net, PICkit, PICtail,
RightTouch logo, REAL ICE, SQI, Serial Quad I/O, Total
Endurance, TSHARC, USBCheck, VariSense, ViewSpan,
WiperLock, Wireless DNA, and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
Silicon Storage Technology is a registered trademark of
Microchip Technology Inc. in other countries.
GestIC is a registered trademarks of Microchip Technology
Germany II GmbH & Co. KG, a subsidiary of Microchip
Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2009-2014, Microchip Technology Incorporated, Printed in
the U.S.A., All Rights Reserved.
ISBN: 978-1-63276-382-2
QUALITY MANAGEMENT SYSTEM
CERTIFIED BY DNV
== ISO/TS 16949 ==
 2009-2014 Microchip Technology Inc.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
DS20002197C-page 59
Worldwide Sales and Service
AMERICAS
ASIA/PACIFIC
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EUROPE
Corporate Office
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Technical Support:
http://www.microchip.com/
support
Web Address:
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DS20002197C-page 60
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03/25/14
 2009-2014 Microchip Technology Inc.