Cypress CY7C1350F-250BGI 4-mb (128k x 36) pipelined sram with nobl architecture Datasheet

1CY7C1350F
CY7C1350F
4-Mb (128K x 36) Pipelined SRAM with Nobl™ Architecture
Functional Description[1]
Features
• Pin compatible and functionally equivalent to ZBT™
devices
• Internally self-timed output buffer control to eliminate
the need to use OE
• Byte Write capability
• 128K x 36 common I/O architecture
• Single 3.3V power supply
• 2.5V/3.3V I/O Operation
The CY7C1350F is a 3.3V, 128K x 36 synchronous-pipelined
Burst SRAM designed specifically to support unlimited true
back-to-back Read/Write operations without the insertion of
wait states. The CY7C1350F is equipped with the advanced
No Bus Latency™ (NoBL™) logic required to enable consecutive Read/Write operations with data being transferred on
every clock cycle. This feature dramatically improves the
throughput of the SRAM, especially in systems that require
frequent Write/Read transitions.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock. The
clock input is qualified by the Clock Enable (CEN) signal,
which, when deasserted, suspends operation and extends the
previous clock cycle. Maximum access delay from the clock
rise is 2.8 ns (200-MHz device)
• Fast clock-to-output times
— 2.6 ns (for 250-MHz device)
— 2.6 ns (for 225-MHz device)
— 2.8 ns (for 200-MHz device)
— 3.5 ns (for 166-MHz device)
Write operations are controlled by the four Byte Write Select
(BW[A:D]) and a Write Enable (WE) input. All writes are
conducted with on-chip synchronous self-timed write circuitry.
— 4.0 ns (for 133-MHz device)
— 4.5 ns (for 100-MHz device)
• Clock Enable (CEN) pin to suspend operation
• JEDEC-standard 100 TQFP and 119 BGA packages
Three synchronous Chip Enables (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output three-state control. In order to avoid bus
contention, the output drivers are synchronously three-stated
during the data portion of a write sequence.
• Burst Capability—linear or interleaved burst order
.
• Synchronous self-timed writes
• Asynchronous output enable (OE)
• “ZZ” Sleep mode option
Logic Block Diagram
A0, A1, A
ADDRESS
REGISTER 0
A1
A1'
D1
Q1
A0
A0'
BURST
D0
Q0
LOGIC
MODE
CLK
CEN
ADV/LD
C
C
WRITE ADDRESS
REGISTER 1
WRITE ADDRESS
REGISTER 2
S
E
N
S
E
ADV/LD
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
BWA
BWB
BWC
BWD
MEMORY
ARRAY
WRITE
DRIVERS
A
M
P
S
WE
O
U
T
P
U
T
R
E
G
I
S
T
E
R
S
S
T
E
E
R
I
N
G
E
INPUT
REGISTER 1
OE
CE1
CE2
CE3
ZZ
E
O
U
T
P
U
T
D
A
T
A
INPUT
REGISTER 0
B
U
F
F
E
R
S
DQs
DQPA
DQPB
DQPC
DQPD
E
E
READ LOGIC
SLEEP
CONTROL
Note:
1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
Cypress Semiconductor Corporation
Document #: 38-05305 Rev. *A
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Revised January 19, 2004
CY7C1350F
.
Selection Guide
250 MHz
225 MHz
200 MHz
166 MHz
133 MHz
100 MHz
Unit
2.6
325
40
2.6
290
40
2.8
265
40
3.5
240
40
4.0
225
40
4.5
205
40
ns
mA
mA
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
Shaded area contains advance information.
Please contact your local Cypress sales representative for availability of these parts.
VDD
VSS
CLK
WE
CEN
OE
ADV/LD
92
91
90
89
88
87
86
85
A
CE3
93
A
BWA
94
81
BWB
95
82
BWC
96
NC / 9M
BWD
97
83
CE2
98
84
A
CE1
99
A
1
80
DQC
2
79
3
DQB
DQC
78
VDDQ
4
DQB
77
5
VDDQ
VSS
76
6
VSS
DQC
75
DQC
7
DQB
74
DQC
8
DQB
73
DQC
9
DQB
72
10
DQB
VSS
71
VDDQ
11
VSS
70
12
VDDQ
DQC
69
13
DQB
DQC
68
NC
14
DQB
67
15
VSS
VDD
66
NC
NC
16
65
VSS
17
64
VDD
ZZ
DQD
18
63
19
DQA
DQD
62
VDDQ
20
DQA
61
21
VDDQ
VSS
60
DQD
22
VSS
59
23
DQA
DQD
58
24
DQA
DQD
57
DQD
25
DQA
56
26
DQA
VSS
55
VDDQ
27
VSS
54
28
VDDQ
DQD
53
DQD
29
DQA
52
DQPD
30
DQA
51
DQPA
Document #: 38-05305 Rev. *A
49
50
A
43
A
42
NC / 72M
NC / 36M
48
41
VDD
A
40
VSS
47
39
NC / 144M
46
38
A0
NC / 288M
A
37
A1
A
36
A
45
35
44
34
A
A
33
A
32
CY7C1350F
A
MODE
31
BYTE D
DQPC
A
BYTE C
100
100-Pin TQFP
NC / 18M
Pin Configuration
DQPB
BYTE B
BYTE A
Page 2 of 16
CY7C1350F
Pin Configuration (continued)
119-Ball Bump BGA
1
2
3
4
5
6
7
A
B
C
D
E
F
G
H
J
K
L
M
N
P
VDDQ
A
A
NC / 18M
A
A
VDDQ
NC
CE2
A
A
A
DQPC
A
VSS
A
VSS
CE3
A
DQPB
NC
NC
DQC
ADV/LD
VDD
NC
R
T
U
NC
DQB
DQC
DQC
VSS
CE1
VSS
DQB
DQB
VDDQ
DQC
VSS
OE
VSS
DQB
VDDQ
DQC
DQC
VDDQ
DQD
DQC
DQC
VDD
DQD
BWC
VSS
VSS
VSS
NC / 9M
BWB
VSS
VSS
VSS
DQB
DQB
VDD
DQA
DQB
DQB
VDDQ
DQA
DQD
VDDQ
DQD
DQD
BWD
VSS
BWA
VSS
DQA
DQA
DQA
VDDQ
DQD
DQD
VSS
CEN
A1
VSS
DQA
DQA
DQD
DQPD
VSS
A0
VSS
DQPA
DQA
NC
A
MODE
VDD
NC
A
NC
NC
NC / 72M
A
A
A
NC / 36M
ZZ
VDDQ
NC
NC
NC
NC
NC
VDDQ
WE
VDD
CLK
NC
Pin Definitions
Name
119BGA
TQFP
I/O
Description
P4,N4,A2,
A3,A5,A6,
B3,B5,C2,
C3,C5,C6,
R2,R6,T3,
T4,T5
37,38,32,
33,34,35,
44,45,46,
47,48,49,
50,81,82,
99,10
InputSynchronous
Address Inputs used to select one of the 128K address locations.
Sampled at the rising edge of the CLK. A[1:0] are fed to the two-bit burst
counter.
L5,G5,
G3,L3
93,94,
95,96
InputSynchronous
Byte Write Inputs, active LOW. Qualified with WE to conduct writes
to the SRAM. Sampled on the rising edge of CLK.
WE
H4
88
InputSynchronous
Write Enable Input, active LOW. Sampled on the rising edge of CLK
if CEN is active LOW. This signal must be asserted LOW to initiate a
write sequence.
ADV/LD
B4
85
InputSynchronous
Advance/Load Input. Used to advance the on-chip address counter
or load a new address. When HIGH (and CEN is asserted LOW) the
internal burst counter is advanced. When LOW, a new address can be
loaded into the device for an access. After being deselected, ADV/LD
should be driven LOW in order to load a new address.
CLK
K4
89
Input-Clock
Clock Input. Used to capture all synchronous inputs to the device. CLK
is qualified with CEN. CLK is only recognized if CEN is active LOW.
CE1
E4
98
InputSynchronous
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK.
Used in conjunction with CE2 and CE3 to select/deselect the device.
CE2
B2
97
InputSynchronous
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK.
Used in conjunction with CE1 and CE3 to select/deselect the device.
CE3
B6
92
InputSynchronous
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK.
Used in conjunction with CE1 and CE2 to select/deselect the device.
A0, A1, A
BW[A:D]
Document #: 38-05305 Rev. *A
Page 3 of 16
CY7C1350F
Pin Definitions
Name
119BGA
TQFP
OE
F4
86
InputOutput Enable, asynchronous input, active LOW. Combined with
Asynchronous the synchronous logic block inside the device to control the direction of
the I/O pins. When LOW, the I/O pins are allowed to behave as outputs.
When deasserted HIGH, I/O pins are three-stated, and act as input data
pins. OE is masked during the data portion of a write sequence, during
the first clock when emerging from a deselected state, when the device
has been deselected.
CEN
M4
87
InputSynchronous
ZZ
T7
64
InputZZ “sleep” Input. This active HIGH input places the device in a
Asynchronous non-time critical “sleep” condition with data integrity preserved. During
normal operation, this pin can be connected to Vss or left floating.
K6,K7,L6,
L7,M6,N6,
N7,P7,D7,
E6,E7,F6,
G6,G7,H6,
H7,D1,E1,
E2,F2,G1,
G2,H1,H2,
K1,K2,L1,
L2,M2,N1,
N2,P1
52,53,56,
57,58,59,
62,63,68,
69,72,73,
74,75,78,
79,2,3,6,
7,8,9,12,
13,18,19,
22,23,23,
24,25,28,
29
I/OSynchronous
Bidirectional Data I/O Lines. As inputs, they feed into an on-chip data
register that is triggered by the rising edge of CLK. As outputs, they
deliver the data contained in the memory location specified by the address during the clock rise of the read cycle. The direction of the pins
is controlled by OE and the internal control logic. When OE is asserted
LOW, the pins can behave as outputs. When HIGH, DQs and DQPX are
placed in a three-state condition. The outputs are automatically
three-stated during the data portion of a write sequence, during the first
clock when emerging from a deselected state, and when the device is
deselected, regardless of the state of OE.
P6,D6,
D2,P2
51,80,
1,30
I/OSynchronous
Bidirectional Data Parity I/O Lines. Functionally, these signals are
identical to DQs. During write sequences, DQP[A:D] is controlled by
BW[A:D] correspondingly.
R3
31
Input
Strap pin
Mode Input. Selects the burst order of the device.
When tied to GND selects linear burst sequence. When tied to VDD or
left floating selects interleaved burst sequence.
C4,J2,
J4,J6,R4
15,16,41,
65,66,91
Power Supply
DQs
DQP[A:D]
MODE
VDD
I/O
VDDQ
A1,A7,F1, 4,11,14,
F7,J1,J7, 20,27,54,
M1,M7,U1,
61,70
U7
I/O Power
Supply
VSS
D3,D5,E3, 5,10,17,2
E5,F3,F5 1,26,40,5
H3,H5,J3, 5,60,67,
J5,K3,K5, 71,76,90
M3,M5,N3,
N5,P3,P5
Ground
NC
A4,B1,B7,
C1,C7,D4,
G4,L4,R1,
R5,R7,T1,
T2,T6,U6
38,39,42,
43,83,84
Document #: 38-05305 Rev. *A
Description
Clock Enable Input, active LOW. When asserted LOW the Clock signal is recognized by the SRAM. When deasserted HIGH the Clock
signal is masked. Since deasserting CEN does not deselect the device,
CEN can be used to extend the previous cycle when required.
Power supply inputs to the core of the device.
Power supply for the I/O circuitry.
Ground for the device.
No Connects. Not internally connected to the die.
9M, 18M, 36M, 72M, 144M and 288M are address expansion pins in
this device and will be used as address pins in their respective densities.
Page 4 of 16
CY7C1350F
Introduction
Functional Overview
The CY7C1350F is a synchronous-pipelined Burst SRAM
designed specifically to eliminate wait states during
Write/Read transitions. All synchronous inputs pass through
input registers controlled by the rising edge of the clock. The
clock signal is qualified with the Clock Enable input signal
(CEN). If CEN is HIGH, the clock signal is not recognized and
all internal states are maintained. All synchronous operations
are qualified with CEN. All data outputs pass through output
registers controlled by the rising edge of the clock. Maximum
access delay from the clock rise (tCO) is 2.8 ns (200-MHz
device).
Accesses can be initiated by asserting all three Chip Enables
(CE1, CE2, CE3) active at the rising edge of the clock. If Clock
Enable (CEN) is active LOW and ADV/LD is asserted LOW,
the address presented to the device will be latched. The
access can either be a read or write operation, depending on
the status of the Write Enable (WE). BW[A:D] can be used to
conduct Byte Write operations.
Write operations are qualified by the Write Enable (WE). All
writes are simplified with on-chip synchronous self-timed write
circuitry.
Three synchronous Chip Enables (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) simplify depth expansion.
All operations (Reads, Writes, and Deselects) are pipelined.
ADV/LD should be driven LOW once the device has been
deselected in order to load a new address for the next
operation.
Single Read Accesses
A read access is initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,
and CE3 are ALL asserted active, (3) the Write Enable input
signal WE is deasserted HIGH, and (4) ADV/LD is asserted
LOW. The address presented to the address inputs is latched
into the Address Register and presented to the memory core
and control logic. The control logic determines that a read
access is in progress and allows the requested data to
propagate to the input of the output register. At the rising edge
of the next clock the requested data is allowed to propagate
through the output register and onto the data bus, provided OE
is active LOW. After the first clock of the read access the output
buffers are controlled by OE and the internal control logic. OE
must be driven LOW in order for the device to drive out the
requested data. During the second clock, a subsequent
operation (Read/Write/Deselect) can be initiated. Deselecting
the device is also pipelined. Therefore, when the SRAM is
deselected at clock rise by one of the chip enable signals, its
output will three-state following the next clock rise.
Burst Read Accesses
The CY7C1350F has an on-chip burst counter that allows the
user the ability to supply a single address and conduct up to
four Reads without reasserting the address inputs. ADV/LD
must be driven LOW in order to load a new address into the
SRAM, as described in the Single Read Access section above.
The sequence of the burst counter is determined by the MODE
input signal. A LOW input on MODE selects a linear burst
mode, a HIGH selects an interleaved burst sequence. Both
burst counters use A0 and A1 in the burst sequence, and will
wrap around when incremented sufficiently. A HIGH input on
Document #: 38-05305 Rev. *A
ADV/LD will increment the internal burst counter regardless of
the state of chip enables inputs or WE. WE is latched at the
beginning of a burst cycle. Therefore, the type of access (Read
or Write) is maintained throughout the burst sequence.
Single Write Accesses
Write accesses are initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,
and CE3 are ALL asserted active, and (3) the Write signal WE
is asserted LOW. The address presented to the address inputs
is loaded into the Address Register. The write signals are
latched into the Control Logic block.
On the subsequent clock rise the data lines are automatically
three-stated regardless of the state of the OE input signal. This
allows the external logic to present the data on DQs and
DQP[A:D]. In addition, the address for the subsequent access
(Read/Write/Deselect) is latched into the Address Register
(provided the appropriate control signals are asserted).
On the next clock rise the data presented to DQs and DQP[A:D]
(or a subset for Byte Write operations, see Write Cycle
Description table for details) inputs is latched into the device
and the write is complete.
The data written during the Write operation is controlled by
BW[A:D] signals. The CY7C1350F provides byte write
capability that is described in the Write Cycle Description table.
Asserting the Write Enable input (WE) with the selected Byte
Write Select (BW[A:D]) input will selectively write to only the
desired bytes. Bytes not selected during a Byte Write
operation will remain unaltered. A synchronous self-timed
write mechanism has been provided to simplify the write
operations. Byte write capability has been included in order to
greatly simplify Read/Modify/Write sequences, which can be
reduced to simple byte write operations.
Because the CY7C1350F is a common I/O device, data should
not be driven into the device while the outputs are active. The
Output Enable (OE) can be deasserted HIGH before
presenting data to the DQs and DQP[A:D] inputs. Doing so will
tri-state the output drivers. As a safety precaution, DQs and
DQP[A:D] are automatically three-stated during the data
portion of a write cycle, regardless of the state of OE.
Burst Write Accesses
The CY7C1350F has an on-chip burst counter that allows the
user the ability to supply a single address and conduct up to
four Write operations without reasserting the address inputs.
ADV/LD must be driven LOW in order to load the initial
address, as described in the Single Write Access section
above. When ADV/LD is driven HIGH on the subsequent clock
rise, the chip enables (CE1, CE2, and CE3) and WE inputs are
ignored and the burst counter is incremented. The correct
BW[A:D] inputs must be driven in each cycle of the burst write
in order to write the correct bytes of data.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CE1, CE2, and CE3, must remain inactive
for the duration of tZZREC after the ZZ input returns LOW.
Page 5 of 16
CY7C1350F
Linear Burst Address Table
(MODE = GND)
Interleaved Burst Address Table
(MODE = Floating or VDD)
First
Address
A1, A0
Second
Address
A1, A0
Third
Address
A1, A0
Fourth
Address
A1, A0
First
Address
A1, A0
Second
Address
A1, A0
Third
Address
A1, A0
Fourth
Address
A1, A0
00
01
10
11
00
01
10
11
01
00
11
10
01
10
11
00
10
11
00
01
10
11
00
01
11
10
01
00
11
00
01
10
Truth Table[2, 3, 4, 5, 6, 7, 8]
Operation
Address
Used
CE
ZZ
ADV/LD
WE
BWx
Deselect Cycle
None
H
L
L
X
X
X
OE
L
CEN
L-H
CLK
Three-State
DQ
Continue
Deselect Cycle
None
X
L
H
X
X
X
L
L-H
Three-State
Read Cycle
(Begin Burst)
External
L
L
L
H
X
L
L
L-H
Data Out (Q)
Read Cycle
(Continue Burst)
Next
X
L
H
X
X
L
L
L-H
Data Out (Q)
NOP/Dummy Read
(Begin Burst)
External
L
L
L
H
X
H
L
L-H
Three-State
Dummy Read
(Continue Burst)
Next
X
L
H
X
X
H
L
L-H
Three-State
Write Cycle
(Begin Burst)
External
L
L
L
L
L
X
L
L-H
Data In (D)
Write Cycle
(Continue Burst)
Next
X
L
H
X
L
X
L
L-H
Data In (D)
NOP/WRITE ABORT
(Begin Burst)
None
L
L
L
L
H
X
L
L-H
Three-State
WRITE ABORT
(Continue Burst)
Next
X
L
H
X
H
X
L
L-H
Three-State
IGNORE CLOCK EDGE
(Stall)
Current
X
L
X
X
X
X
H
L-H
—
SNOOZE MODE
None
X
H
X
X
X
X
X
X
Three-State
Notes:
2. X =”Don't Care.” H = Logic HIGH, L = Logic LOW. CE stands for ALL Chip Enables active. BWx = 0 signifies at least one Byte Write Select is active, BWx =
Valid signifies that the desired byte write selects are asserted, see Write Cycle Description table for details.
3. Write is defined by BW[A:D], and WE. See Write Cycle Descriptions table.
4. When a write cycle is detected, all DQs are three-stated, even during byte writes.
5. The DQ and DQP pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
6. CEN = H, inserts wait states.
7. Device will power-up deselected and the DQs in a three-state condition, regardless of OE.
8. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQs and DQP[A:D] = Three-state
when OE is inactive or when the device is deselected, and DQs and DQP[A:D] = data when OE is active.
Document #: 38-05305 Rev. *A
Page 6 of 16
CY7C1350F
Partial Truth Table for Read/Write[2, 3, 9]
Function
WE
H
BWD
X
BWC
X
BWB
X
BWA
X
Write − No bytes written
L
H
H
H
H
Write Byte A − (DQA and DQPA)
L
H
H
H
L
Write Byte B − (DQB and DQPB)
L
H
H
L
H
Write Bytes A, B
L
H
H
L
L
Write Byte C − (DQC and DQPC)
L
H
L
H
H
Write Bytes C,A
L
H
L
H
L
Write Bytes C, B
L
H
L
L
H
Write Bytes C, B, A
L
H
L
L
L
Write Byte D − (DQD and DQPD)
L
L
H
H
H
Write Bytes D, A
L
L
H
H
L
Write Bytes D, B
L
L
H
L
H
Write Bytes D, B, A
L
L
H
L
L
Write Bytes D, C
L
L
L
H
H
Write Bytes D, C, A
L
L
L
H
L
Write Bytes D, C, B
L
L
L
L
H
Write All Bytes
L
L
L
L
L
Read
Note:
9. Table only lists a partial listing of the byte write combinations. Any combination of BW[A:D] is valid. Appropriate write will be done on which byte write is active.
ZZ Mode Electrical Characteristics
Parameter
Description
Test Conditions
IDDZZ
Snooze mode standby current
ZZ > VDD − 0.2V
tZZS
Device operation to ZZ
ZZ > VDD − 0.2V
tZZREC
ZZ recovery time
ZZ < 0.2V
tZZI
ZZ active to snooze current
This parameter is sampled
tRZZI
ZZ inactive to exit snooze current
This parameter is sampled
Document #: 38-05305 Rev. *A
Min.
Max.
Unit
40
mA
2tCYC
ns
2tCYC
ns
2tCYC
0
ns
ns
Page 7 of 16
CY7C1350F
Maximum Ratings
Current into Outputs (LOW)......................................... 20 mA
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ..................................... −65°C to +150°C
Ambient Temperature with
Power Applied.................................................. −55°C to +125°C
Static Discharge Voltage........................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current .................................................... >200 mA
Operating Range
Supply Voltage on VDD Relative to GND.........−0.5V to +4.6V
DC Voltage Applied to Outputs
in Three-State ..........................................−0.5V to VDDQ + 0.5V
DC Input Voltage ....................................... −0.5V to VDD + 0.5V
Range
Ambient
Temperature (TA)
VDD
VDDQ
0°C to +70°C
3.3V - 5%/+10%
2.5V - 5%
to VDD
Com’l
−40°C to +85°C
Ind’l
Electrical Characteristics Over the Operating Range[10, 11]
Parameter
Description
VDD
Power Supply Voltage
VDDQ
I/O Supply Voltage
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
VIH
Input HIGH Voltage[10]
VIL
Input LOW Voltage[10]
IX
Input Load Current
except ZZ and MODE
Test Conditions
Min.
Max.
Unit
3.135
3.6
V
2.375
VDD
V
VDDQ = 3.3V, VDD = Min., IOH = –4.0 mA
2.4
VDDQ = 2.5V, VDD = Min., IOH = –1.0 mA
2.0
VDDQ = 3.3V, VDD = Min., IOL = 8.0 mA
VDDQ = 2.5V, VDD = Min., IOL = 1.0 mA
0.4
V
V
VDDQ = 2.5V
1.7
VDD + 0.3V
V
VDDQ = 3.3V
–0.3
0.8
V
VDDQ = 2.5V
–0.3
0.7
V
−5
5
µA
GND ≤ VI ≤ VDDQ
−30
5
GND ≤ VI ≤ VDDQ, Output Disabled
IDD
VDD Operating Supply
Current
VDD = Max., IOUT = 0 mA,
f = fMAX = 1/tCYC
VDD = Max, Device Deselected,
VIN ≥ VIH or VIN ≤ VIL
f = fMAX = 1/tCYC
µA
µA
30
µA
5
µA
4-ns cycle, 250 MHz
325
mA
4.4-ns cycle, 225 MHz
290
mA
5-ns cycle, 200 MHz
265
mA
Input = VDD
Output Leakage
Current
µA
−5
Input = VSS
IOZ
Automatic CE
Power-Down
Current—TTL Inputs
V
VDD + 0.3V
Input = VDD
ISB1
V
0.4
2.0
VDDQ = 3.3V
Input Current of MODE Input = VSS
Input Current of ZZ
V
−5
6-ns cycle, 166 MHz
240
mA
7.5-ns cycle, 133 MHz
225
mA
10-ns cycle, 100MHz
205
mA
4-ns cycle, 250 MHz
120
mA
4.4-ns cycle, 225 MHz
115
mA
5-ns cycle, 200 MHz
110
mA
6-ns cycle, 166 MHz
100
mA
7.5-ns cycle, 133 MHz
90
mA
10-ns cycle, 100 MHz
80
mA
Shaded areas contain advance information.
Notes:
10. Overshoot: VIH(AC) < VDD +1.5V (Pulse width less than tCYC/2), undershoot: VIL(AC)> –2V (Pulse width less than tCYC/2).
11. TPower-up: Assumes a linear ramp from 0V to VDD (min.) within 200 ms. During this time VIH < VDD and VDDQ < VDD.
Document #: 38-05305 Rev. *A
Page 8 of 16
CY7C1350F
Electrical Characteristics Over the Operating Range[10, 11](continued)
Max.
Unit
ISB2
Parameter
Automatic CE
VDD = Max, Device Deselected,
Power-Down
VIN ≤ 0.3V or VIN > VDDQ – 0.3V,
Current—CMOS Inputs f = 0
All speeds
40
mA
ISB3
Automatic CE
VDD = Max, Device Deselected, or
Power-Down
VIN ≤ 0.3V or VIN > VDDQ – 0.3V
Current—CMOS Inputs f = fMAX = 1/tCYC
4-ns cycle, 250 MHz
105
mA
4.4-ns cycle, 225 MHz
100
mA
5-ns cycle, 200 MHz
95
mA
6-ns cycle, 166 MHz
85
mA
7.5-ns cycle, 133 MHz
75
mA
10-ns cycle, 100 MHz
65
mA
All speeds
45
mA
ISB4
Description
Automatic CE
Power-Down
Current—TTL Inputs
Test Conditions
VDD = Max, Device Deselected,
VIN ≥ VIH or VIN ≤ VIL, f = 0
Min.
AC Test Loads and Waveforms
3.3V I/O Test Load
R = 317Ω
3.3V
OUTPUT
OUTPUT
RL = 50Ω
Z0 = 50Ω
GND
5 pF
R = 351Ω
INCLUDING
JIG AND
SCOPE
90%
10%
90%
10%
≤ 1 ns
≤ 1 ns
VL = 1.5V
(a)
ALL INPUT PULSES
VDD
(c)
(b)
2.5V I/O Test Load
R = 1667Ω
2.5V
OUTPUT
OUTPUT
RL = 50Ω
Z0 = 50Ω
GND
5 pF
R =1538Ω
VL = 1.25V
INCLUDING
JIG AND
SCOPE
(a)
ALL INPUT PULSES
VDD
90%
10%
90%
10%
≤ 1 ns
≤ 1 ns
(c)
(b)
Thermal Resistance[12]
Parameter
Description
ΘJA
Thermal Resistance
(Junction to Ambient)
ΘJC
Thermal Resistance
(Junction to Case)
Test Conditions
TQFP
Package
BGA
Package
Units
41.83
47.63
°C/W
9.99
11.71
°C/W
TQFP
Package
BGA
Package
Unit
5
5
pF
5
7
pF
Test conditions follow standard test methods
and procedures for measuring thermal impedance, per EIA / JESD51.
Capacitance[12]
Parameter
Description
CIN
Input Capacitance
CI/O
Input/Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
VDD = 3.3V, VDDQ = 3.3V
Note:
12. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05305 Rev. *A
Page 9 of 16
CY7C1350F
Switching Characteristics Over the Operating Range[17, 18]
250 MHz
Parameter
tPOWER
Description
VDD (typical) to the first
Access[13]
225 MHz
200 MHz
166 MHz
133 MHz
100 MHz
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
1
1
1
1
1
1
ms
Clock
tCYC
Clock Cycle Time
4.0
4.4
5.0
6.0
7.5
10
ns
tCH
Clock HIGH
1.7
2.0
2.0
2.5
3.0
3.5
ns
tCL
Clock LOW
1.7
2.0
2.0
2.5
3.0
3.5
ns
Output Times
tCO
Data Output Valid After CLK
Rise
tDOH
Data Output Hold After CLK
Rise
tCLZ
Clock to Low-Z[14, 15, 16]
tCHZ
Clock to High-Z[14, 15, 16]
tOEV
OE LOW to Output Valid
OE LOW to Output
Low-Z[14, 15, 16]
tOELZ
2.6
1.0
2.6
1.0
0
2.6
OE HIGH to Output
High-Z[14, 15, 16]
Set-up Times
2.6
2.8
ns
4.0
0
3.5
ns
ns
0
4.0
3.5
0
4.5
2.0
0
3.5
2.8
0
4.0
2.0
0
2.8
2.6
0
3.5
2.0
0
2.6
2.6
0
tOEHZ
1.0
0
2.6
2.8
4.5
ns
4.5
ns
0
ns
4.0
4.5
ns
tAS
Address Set-up Before CLK
Rise
0.8
1.2
1.2
1.5
1.5
1.5
ns
tALS
ADV/LD Set-up Before CLK
Rise
0.8
1.2
1.2
1.5
1.5
1.5
ns
tWES
GW, BW[A:D] Set-Up Before
CLK Rise
0.8
1.2
1.2
1.5
1.5
1.5
ns
tCENS
CEN Set-up Before CLK Rise
Data Input Set-up Before CLK
Rise
0.8
1.2
1.2
1.5
1.5
1.5
ns
tDS
0.8
1.2
1.2
1.5
1.5
1.5
ns
tCES
Chip Enable Set-Up Before
CLK Rise
0.8
1.2
1.2
1.5
1.5
1.5
ns
Address Hold After CLK Rise
0.4
0.5
0.5
0.5
0.5
0.5
ns
ADV/LD Hold after CLK Rise
GW, BW[A:D] Hold After CLK
Rise
0.4
0.5
0.5
0.5
0.5
0.5
ns
0.4
0.5
0.5
0.5
0.5
0.5
ns
0.4
CEN Hold After CLK Rise
Data Input Hold After CLK Rise 0.4
0.5
0.5
0.5
0.5
0.5
ns
0.5
0.5
0.5
0.5
0.5
ns
Chip Enable Hold After CLK
Rise
0.5
0.5
0.5
0.5
0.5
ns
Hold Times
tAH
tALH
tWEH
tCENH
tDH
tCEH
0.4
Shaded areas contain advance information.
Notes:
13. This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD minimum initially before a Read or Write operation
can be initiated.
14. tCHZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
15. At any given voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve Three-state prior to Low-Z under the same system conditions
16. This parameter is sampled and not 100% tested.
17. Timing reference level is 1.5V when VDDQ = 3.3V and is 1.25V when VDDQ = 2.5V.
18. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
Document #: 38-05305 Rev. *A
Page 10 of 16
CY7C1350F
Switching Waveforms
Read/Write Timing[19, 20, 21]
1
2
3
t CYC
4
5
6
A3
A4
7
8
9
A5
A6
A7
10
CLK
tCENS
tCENH
tCH
tCL
CEN
tCES
tCEH
CE
ADV/LD
WE
BW[A:D]
A1
ADDRESS
A2
tCO
tAS
tDS
tAH
Data
In-Out (DQ)
tDH
D(A1)
tCLZ
D(A2)
D(A2+1)
tDOH
Q(A3)
tOEV
Q(A4)
tCHZ
Q(A4+1)
D(A5)
Q(A6)
tOEHZ
tDOH
tOELZ
OE
WRITE
D(A1)
WRITE
D(A2)
BURST
WRITE
D(A2+1)
READ
Q(A3)
READ
Q(A4)
DON’T CARE
BURST
READ
Q(A4+1)
WRITE
D(A5)
READ
Q(A6)
WRITE
D(A7)
DESELECT
UNDEFINED
Notes:
19. For this waveform ZZ is tied LOW.
20. When CE is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH, CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
21. Order of the Burst sequence is determined by the status of the MODE (0 = Linear, 1 = Interleaved). Burst operations are optional.
Document #: 38-05305 Rev. *A
Page 11 of 16
CY7C1350F
Switching Waveforms (continued)
NOP, STALL, and DESELECT Cycles[19, 20, 22]
1
2
A1
A2
3
4
5
A3
A4
6
7
8
9
10
CLK
CEN
CE
ADV/LD
WE
BW[A:D]
ADDRESS
A5
tCHZ
D(A1)
Data
In-Out (DQ)
WRITE
D(A1)
READ
Q(A2)
STALL
READ
Q(A3)
DON’T CARE
Q(A2)
D(A4)
Q(A3)
WRITE
D(A4)
STALL
NOP
READ
Q(A5)
Q(A5)
DESELECT
CONTINUE
DESELECT
UNDEFINED
ZZ Mode Timing[23, 24]
CLK
t ZZ
ZZ
I
t ZZREC
t ZZI
SUPPLY
I DDZZ
t RZZI
ALL INPUTS
(except ZZ)
Outputs (Q)
DESELECT or READ Only
High-Z
DON’T CARE
Notes:
22. The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrates CEN being used to create a pause. A write is not performed during this cycle.
23. Device must be deselected when entering ZZ mode. See cycle description table for all possible signal conditions to deselect the device.
24. DQs are in high-Z when exiting ZZ sleep mode.
Document #: 38-05305 Rev. *A
Page 12 of 16
CY7C1350F
Ordering Information
Speed
(MHz)
250
Ordering Code
CY7C1350F-250AC
CY7C1350F-250BGC
CY7C1350F-250AI
CY7C1350F-250BGI
225
CY7C1350F-225AC
CY7C1350F-225BGC
CY7C1350F-225AI
CY7C1350F-225BGI
200
CY7C1350F-200AC
CY7C1350F-200BGC
CY7C1350F-200AI
CY7C1350F-200BGI
166
CY7C1350F-166AC
CY7C1350F-166BGC
CY7C1350F-166AI
CY7C1350F-166BGI
133
CY7C1350F-133AC
CY7C1350F-133BGC
CY7C1350F-133AI
CY7C1350F-133BGI
100
CY7C1350F-100AC
CY7C1350F-100BGC
CY7C1350F-100AI
CY7C1350F-100BGI
Package
Name
Package Type
Operating
Range
A101
100-Lead (14 x 20 x 1.4 mm) Thin Quad Flat Pack
Commercial
BG119
A101
BG119
A101
BG119
A101
BG119
A101
BG119
A101
BG119
A101
BG119
A101
BG119
A101
BG119
A101
BG119
A101
BG119
A101
BG119
119-Ball BGA (14 x 22 x 2.4mm)
100-Lead (14 x 20 x 1.4 mm) Thin Quad Flat Pack
Industrial
119-Ball BGA (14 x 22 x 2.4mm)
100-Lead (14 x 20 x 1.4 mm) Thin Quad Flat Pack
Commercial
119-Ball BGA (14 x 22 x 2.4mm)
100-Lead (14 x 20 x 1.4 mm) Thin Quad Flat Pack
Industrial
119-Ball BGA (14 x 22 x 2.4mm)
100-Lead (14 x 20 x 1.4 mm) Thin Quad Flat Pack
Commercial
119-Ball BGA (14 x 22 x 2.4mm)
100-Lead (14 x 20 x 1.4 mm) Thin Quad Flat Pack
Industrial
119-Ball BGA (14 x 22 x 2.4mm)
100-Lead (14 x 20 x 1.4 mm) Thin Quad Flat Pack
Commercial
119-Ball BGA (14 x 22 x 2.4mm)
100-Lead (14 x 20 x 1.4 mm) Thin Quad Flat Pack
Industrial
119-Ball BGA (14 x 22 x 2.4mm)
100-Lead (14 x 20 x 1.4 mm) Thin Quad Flat Pack
Commercial
119-Ball BGA (14 x 22 x 2.4mm)
100-Lead (14 x 20 x 1.4 mm) Thin Quad Flat Pack
Industrial
119-Ball BGA (14 x 22 x 2.4mm)
100-Lead (14 x 20 x 1.4 mm) Thin Quad Flat Pack
Commercial
119-Ball BGA (14 x 22 x 2.4mm)
100-Lead (14 x 20 x 1.4 mm) Thin Quad Flat Pack
Industrial
119-Ball BGA (14 x 22 x 2.4mm)
Shaded areas contain advance information.
Please contact your local Cypress sales representative to order parts that are not listed in the ordering information table.
Document #: 38-05305 Rev. *A
Page 13 of 16
CY7C1350F
Package Diagram
100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101
51-85050-*A
51-85050-*A
Document #: 38-05305 Rev. *A
Page 14 of 16
CY7C1350F
Package Diagram
119-Lead BGA (14 x 22 x 2.4 mm) BG119
51-85115-*B
NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation.
ZBT is a trademark of Integrated Device Technology.
All product and company names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-05305 Rev. *A
Page 15 of 16
© Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C1350F
Document History Page
Document Title: CY7C1350F 4-Mb (128K x 36) Pipelined SRAM with Nobl™ Architecture
Document Number: 38-05305
REV.
ECN NO.
Orig. of
Issue Date Change
Description of Change
**
119828
12/11/02
HGK
New Data Sheet
*A
200662
See ECN
REF
Final Data Sheet
Document #: 38-05305 Rev. *A
Page 16 of 16