MC68HC705J1A MC68HRC705J1A MC68HSC705J1A MC68HSR705J1A Technical Data M68HC05 Microcontrollers MC68HC705J1A/D Rev. 4, 5/2002 WWW.MOTOROLA.COM/SEMICONDUCTORS MC68HC705J1A MC68HRC705J1A MC68HSC705J1A MC68HSR705J1A Technical Data To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://www.motorola.com/semiconductors/ The following revision history table summarizes changes contained in this document. For your convenience, the page number designators have been linked to the appropriate location. Motorola and the Stylized M Logo are registered trademarks of Motorola, Inc. digital dna is a trademark of Motorola, Inc. MC68HC705J1A — Rev. 4.0 MOTOROLA © Motorola, Inc., 2002 Technical Data 3 Technical Data Revision History Date May, 2002 Technical Data 4 Revision Level 4.0 Description Page Number(s) Figure 2-2. I/O Register Summary — Corrected reset state for last entry (Mask Option Register) 37 Figure 2-4. Mask Option Register (MOR) — Corrected reset state 41 6.3.3 Pulldown Register A — Corrected note 91 6.4.3 Pulldown Register B — Corrected note 94 MC68HC705J1A — Rev. 4.0 MOTOROLA Technical Data — MC68HC705J1A List of Sections Section 1. General Description . . . . . . . . . . . . . . . . . . . . 21 Section 2. Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Section 3. Central Processor Unit (CPU) . . . . . . . . . . . . 45 Section 4. Resets and Interrupts . . . . . . . . . . . . . . . . . . . 69 Section 5. Low-Power Modes. . . . . . . . . . . . . . . . . . . . . . 79 Section 6. Parallel Input/Output (I/O) Ports . . . . . . . . . . 87 Section 7. Computer Operating Properly (COP) Module . . . . . . . . . . . . . . . . . . . . . . . . . 97 Section 8. External Interrupt Module (IRQ). . . . . . . . . . 101 Section 9. Multifunction Timer Module . . . . . . . . . . . . . 109 Section 10. Electrical Specifications. . . . . . . . . . . . . . . 117 Section 11. Mechanical Specifications . . . . . . . . . . . . . 131 Section 12. Ordering Information . . . . . . . . . . . . . . . . . 135 Appendix A. MC68HRC705J1A . . . . . . . . . . . . . . . . . . . 137 Appendix B. MC68HSC705J1A . . . . . . . . . . . . . . . . . . . 141 Appendix C. MC68HSR705J1A . . . . . . . . . . . . . . . . . . . 145 Index. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 MC68HC705J1A — Rev. 4.0 MOTOROLA Technical Data List of Sections 5 List of Sections Technical Data 6 MC68HC705J1A — Rev. 4.0 List of Sections MOTOROLA Technical Data — MC68HC705J1A Table of Contents Section 1. General Description 1.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 1.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 1.4 Programmable Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 1.5 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 1.5.1 VDD and VSS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 1.5.2 OSC1 and OSC2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 1.5.2.1 Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 1.5.2.2 Ceramic Resonator Oscillator . . . . . . . . . . . . . . . . . . . . . 28 1.5.2.3 RC Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 1.5.2.4 External Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 1.6 RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 1.7 IRQ/VPP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 1.8 PA0–PA7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 1.9 PB0–PB5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Section 2. Memory 2.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 2.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 2.3 Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2.4 Input/Output Register Summary . . . . . . . . . . . . . . . . . . . . . . . .35 2.5 RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 MC68HC705J1A — Rev. 4.0 MOTOROLA Technical Data Table of Contents 7 Table of Contents 2.6 EPROM/OTPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 2.6.1 EPROM/OTPROM Programming . . . . . . . . . . . . . . . . . . . . . 38 2.6.2 EPROM Programming Register . . . . . . . . . . . . . . . . . . . . . 39 2.6.3 EPROM Erasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 2.7 Mask Option Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 2.8 EPROM Programming Characteristics . . . . . . . . . . . . . . . . . . . 43 Section 3. Central Processor Unit (CPU) 3.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 3.3 CPU Control Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 3.4 Arithmetic/Logic Unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 3.5 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 3.5.1 Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 3.5.2 Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 3.5.3 Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 3.5.4 Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 3.5.5 Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 3.6 Instruction Set. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 3.6.1 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 3.6.1.1 Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 3.6.1.2 Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 3.6.1.3 Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 3.6.1.4 Extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 3.6.1.5 Indexed, No Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 3.6.1.6 Indexed, 8-Bit Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 3.6.1.7 Indexed, 16-Bit Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 3.6.1.8 Relative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 3.6.2 Instruction Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 3.6.2.1 Register/Memory Instructions . . . . . . . . . . . . . . . . . . . . . 55 3.6.2.2 Read-Modify-Write Instructions . . . . . . . . . . . . . . . . . . . . 56 3.6.2.3 Jump/Branch Instructions . . . . . . . . . . . . . . . . . . . . . . . .57 3.6.2.4 Bit Manipulation Instructions . . . . . . . . . . . . . . . . . . . . . . 59 3.6.2.5 Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Technical Data 8 MC68HC705J1A — Rev. 4.0 Table of Contents MOTOROLA Table of Contents 3.7 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 3.8 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Section 4. Resets and Interrupts 4.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 4.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 4.3 Resets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 4.3.1 Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 4.3.2 External Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 4.3.3 COP Watchdog Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 4.3.4 Illegal Address Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 4.4 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 4.4.1 Software Interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 4.4.2 External Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 4.4.3 Timer Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 4.4.3.1 Real-Time Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 4.4.3.2 Timer Overflow Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . 76 4.4.4 Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Section 5. Low-Power Modes 5.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 5.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 5.3 Exiting Stop and Wait Modes . . . . . . . . . . . . . . . . . . . . . . . . . . 80 5.4 Effects of Stop and Wait Modes . . . . . . . . . . . . . . . . . . . . . . . .81 5.4.1 Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 5.4.2 CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 5.4.3 COP Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 5.4.4 Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 5.4.5 EPROM/OTPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 5.4.6 Data-Retention Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 5.5 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 MC68HC705J1A — Rev. 4.0 MOTOROLA Technical Data Table of Contents 9 Table of Contents Section 6. Parallel Input/Output (I/O) Ports 6.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 6.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 6.3 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 6.3.1 Port A Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 6.3.2 Data Direction Register A. . . . . . . . . . . . . . . . . . . . . . . . . . . 90 6.3.3 Pulldown Register A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 6.3.4 Port A LED Drive Capability . . . . . . . . . . . . . . . . . . . . . . . . . 92 6.3.5 Port A I/O Pin Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 6.4 Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 6.4.1 Port B Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 6.4.2 Data Direction Register B. . . . . . . . . . . . . . . . . . . . . . . . . . . 93 6.4.3 Pulldown Register B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 6.5 5.0-Volt I/O Port Electrical Characteristics . . . . . . . . . . . . . . . . 95 6.6 3.3-Volt I/O Port Electrical Characteristics . . . . . . . . . . . . . . . . 95 Section 7. Computer Operating Properly (COP) Module 7.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 7.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 7.3 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 7.3.1 COP Watchdog Timeout . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 7.3.2 COP Watchdog Timeout Period . . . . . . . . . . . . . . . . . . . . . . 98 7.3.3 Clearing the COP Watchdog . . . . . . . . . . . . . . . . . . . . . . . .98 7.4 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 7.5 COP Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99 7.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 7.6.1 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100 7.6.2 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100 Technical Data 10 MC68HC705J1A — Rev. 4.0 Table of Contents MOTOROLA Table of Contents Section 8. External Interrupt Module (IRQ) 8.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 8.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 8.3 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 8.3.1 IRQ/VPP Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 8.3.2 Optional External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . 104 8.4 IRQ Status and Control Register . . . . . . . . . . . . . . . . . . . . . . 106 8.5 External Interrupt Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 8.5.1 5.0-Volt External Interrupt Timing Characteristics . . . . . . . 107 8.5.2 3.3-Volt External Interrupt Timing Characteristics . . . . . . . 107 Section 9. Multifunction Timer Module 9.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 9.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 9.3 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 9.4 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 9.5 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 9.5.1 Timer Status and Control Register . . . . . . . . . . . . . . . . . . .112 9.5.2 Timer Counter Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 9.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 9.6.1 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115 9.6.2 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115 Section 10. Electrical Specifications 10.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 10.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 10.3 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 10.4 Operating Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . 119 10.5 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 MC68HC705J1A — Rev. 4.0 MOTOROLA Technical Data Table of Contents 11 Table of Contents 10.6 Power Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 10.7 5.0-Volt DC Electrical Characteristics. . . . . . . . . . . . . . . . . . .121 10.8 3.3-Volt DC Electrical Characteristics . . . . . . . . . . . . . . . . . . 122 10.9 Driver Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 10.10 Typical Supply Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 10.11 EPROM Programming Characteristics . . . . . . . . . . . . . . . . . . 126 10.12 5.0-Volt Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 10.13 3.3-Volt Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 Section 11. Mechanical Specifications 11.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 11.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 11.3 Plastic Dual In-Line Package (Case 738) . . . . . . . . . . . . . . . . 132 11.4 Small Outline Integrated Circuit (Case 751) . . . . . . . . . . . . . .132 11.5 Ceramic Dual In-Line Package (Case 732) . . . . . . . . . . . . . . 133 Section 12. Ordering Information 12.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 12.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 12.3 MCU Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 Appendix A. MC68HRC705J1A A.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 A.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 A.3 RC Oscillator Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 A.4 Typical Internal Operating Frequency for RC Oscillator Option. . . . . . . . . . . . . . . . . . . . . . . . . . . 139 A.5 Package Types and Order Numbers . . . . . . . . . . . . . . . . . . . 140 Technical Data 12 MC68HC705J1A — Rev. 4.0 Table of Contents MOTOROLA Table of Contents Appendix B. MC68HSC705J1A B.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 B.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 B.3 5.0-Volt DC Electrical Characteristics. . . . . . . . . . . . . . . . . . .142 B.4 3.3-Volt DC Electrical Characteristics. . . . . . . . . . . . . . . . . . .142 B.5 Typical Supply Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 B.6 Package Types and Order Numbers . . . . . . . . . . . . . . . . . . . 144 Appendix C. MC68HSR705J1A C.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 C.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 C.3 RC Oscillator Connections (External Resistor). . . . . . . . . . . . 145 C.4 Typical Internal Operating Frequency at 25°C for High-Speed RC Oscillator Option. . . . . . . . . . . . . . . . . 146 C.5 RC Oscillator Connections (No External Resistor) . . . . . . . . .147 C.6 Typical Internal Operating Frequency versus Temperature (No External Resistor) . . . . . . . . . . . . . . . . . . . . . . . . . . . .148 C.7 Package Types and Order Numbers . . . . . . . . . . . . . . . . . . . 149 Index Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 MC68HC705J1A — Rev. 4.0 MOTOROLA Technical Data Table of Contents 13 Table of Contents Technical Data 14 MC68HC705J1A — Rev. 4.0 Table of Contents MOTOROLA Technical Data — MC68HC705J1A List of Figures Figure 1-1 1-2 1-3 1-4 Title 1-8 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Bypassing Layout Recommendation . . . . . . . . . . . . . . . . . . 26 Crystal Connections with Oscillator Internal Resistor Mask Option . . . . . . . . . . . . . 28 Crystal Connections without Oscillator Internal Resistor Mask Option . . . . . . . . . . . . . 28 Ceramic Resonator Connections with Oscillator Internal Resistor Mask Option . . . . . . . . . 29 Ceramic Resonator Connections without Oscillator Internal Resistor Mask Option. . . . . . . 29 External Clock Connections . . . . . . . . . . . . . . . . . . . . . . . . . 30 2-1 2-2 2-3 2-4 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 EPROM Programming Register (EPROG). . . . . . . . . . . . . . 39 Mask Option Register (MOR) . . . . . . . . . . . . . . . . . . . . . . . .41 3-1 3-2 3-3 3-4 3-5 3-6 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Accumulator (A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Index Register (X) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Stack Pointer (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Program Counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 Condition Code Register (CCR) . . . . . . . . . . . . . . . . . . . . . . 50 4-1 4-2 Reset Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Power-On Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 1-5 1-6 1-7 MC68HC705J1A — Rev. 4.0 MOTOROLA Page Technical Data List of Figures 15 List of Figures Figure Title 4-3 4-4 4-5 4-6 4-7 External Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 External Interrupt Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 External Interrupt Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Interrupt Stacking Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Interrupt Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 5-1 5-2 Stop Mode Recovery Timing . . . . . . . . . . . . . . . . . . . . . . . .85 Stop/Halt/Wait Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 6-1 6-2 6-3 6-4 6-5 6-6 6-7 6-8 6-9 Parallel I/O Port Register Summary . . . . . . . . . . . . . . . . . . . 88 Port A Data Register (PORTA). . . . . . . . . . . . . . . . . . . . . . . 89 Data Direction Register A (DDRA) . . . . . . . . . . . . . . . . . . . .90 Port A I/O Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Pulldown Register A (PDRA) . . . . . . . . . . . . . . . . . . . . . . . .91 Port B Data Register (PORTB). . . . . . . . . . . . . . . . . . . . . . . 92 Data Direction Register B (DDRB) . . . . . . . . . . . . . . . . . . . .93 Port B I/O Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Pulldown Register B (PDRB) . . . . . . . . . . . . . . . . . . . . . . . .94 7-1 COP Register (COPR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99 8-1 8-2 8-3 8-4 IRQ Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . 102 Interrupt Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 IRQ Status and Control Register (ISCR) . . . . . . . . . . . . . . 106 External Interrupt Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 107 9-1 9-2 9-3 9-4 Multifunction Timer Block Diagram. . . . . . . . . . . . . . . . . . .110 I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Timer Status and Control Register (TSCR) . . . . . . . . . . . . 112 Timer Counter Register (TCR) . . . . . . . . . . . . . . . . . . . . . . 114 Technical Data 16 Page MC68HC705J1A — Rev. 4.0 List of Figures MOTOROLA List of Figures Figure 10-1 10-2 10-3 10-4 10-5 10-6 10-7 10-8 10-9 Title PA0–PA7, PB0–PB5 Typical High-Side Driver Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 123 PA0–PA3, PB0–PB5 Typical Low-Side Driver Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 123 PA4–PA7 Typical Low-Side Driver Characteristics . . . . . . 124 Typical Operating IDD (25°C) . . . . . . . . . . . . . . . . . . . . . . .125 Typical Wait Mode IDD (25°C) . . . . . . . . . . . . . . . . . . . . . . 125 External Interrupt Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 128 Stop Mode Recovery Timing . . . . . . . . . . . . . . . . . . . . . . .128 Power-On Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 External Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 A-1 A-2 RC Oscillator Connections . . . . . . . . . . . . . . . . . . . . . . . . . 138 Typical Internal Operating Frequency for Various VDD at 25°C — RC Oscillator Option Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 B-1 B-2 Typical High-Speed Operating IDD (25°C) . . . . . . . . . . . . . 142 Typical High-Speed Wait Mode IDD (25°C) . . . . . . . . . . . . 143 C-1 Typical Internal Operating Frequency at 25°C for High-Speed RC Oscillator Option . . . . . . . . 146 RC Oscillator Connections (No External Resistor) . . . . . . . 147 Typical Internal Operating Frequency versus Temperature (OSCRES Bit = 1) . . . . . . . . . . . . 148 C-2 C-3 MC68HC705J1A — Rev. 4.0 MOTOROLA Page Technical Data List of Figures 17 List of Figures Technical Data 18 MC68HC705J1A — Rev. 4.0 List of Figures MOTOROLA Technical Data — MC68HC705J1A List of Tables Table Title 1-1 Programmable Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3-1 3-2 3-3 3-4 3-5 3-6 3-7 Register/Memory Instructions. . . . . . . . . . . . . . . . . . . . . . . . . 55 Read-Modify-Write Instructions . . . . . . . . . . . . . . . . . . . . . . . 56 Jump and Branch Instructions . . . . . . . . . . . . . . . . . . . . . . . .58 Bit Manipulation Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . 59 Control Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 4-1 4-2 4-3 4-4 External Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 External Interrupt Timing (VDD = 5.0 Vdc) . . . . . . . . . . . . . . . 75 External Interrupt Timing (VDD = 3.3 Vdc) . . . . . . . . . . . . . . . 75 Reset/Interrupt Vector Addresses . . . . . . . . . . . . . . . . . . . . . 77 6-1 6-2 Port A Pin Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Port B Pin Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 9-1 Real-Time Interrupt Rate Selection . . . . . . . . . . . . . . . . . . . 114 12-1 Order Numbers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 A-1 MC68HRC705J1A (RC Oscillator Option) Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140 B-1 MC68HSC705J1A (High Speed) Order Numbers . . . . . . . . 144 C-1 MC68HSR705J1A (High-Speed RC Oscillator Option) Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149 MC68HC705J1A — Rev. 4.0 MOTOROLA Page Technical Data List of Tables 19 List of Tables Technical Data 20 MC68HC705J1A — Rev. 4.0 List of Tables MOTOROLA Technical Data — MC68HC705J1A Section 1. General Description 1.1 Contents 1.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 1.4 Programmable Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 1.5 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 1.5.1 VDD and VSS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 1.5.2 OSC1 and OSC2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 1.5.2.1 Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 1.5.2.2 Ceramic Resonator Oscillator . . . . . . . . . . . . . . . . . . . . . 28 1.5.2.3 RC Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 1.5.2.4 External Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 1.6 RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 1.7 IRQ/VPP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 1.8 PA0–PA7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 1.9 PB0–PB5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 MC68HC705J1A — Rev. 4.0 MOTOROLA Technical Data General Description 21 General Description 1.2 Introduction The MC68HC705J1A is a member of Motorola’s low-cost, high-performance M68HC05 Family of 8-bit microcontroller units (MCUs). The M68HC05 Family is based on the customer-specified integrated circuit (CSIC) design strategy. All MCUs in the family use the popular M68HC05 central processor unit (CPU) and are available with a variety of subsystems, memory sizes and types, and package types. On-chip memory of the MC68HC705J1A includes 1240 bytes of erasable, programmable read-only memory (EPROM). In packages without the transparent window for EPROM erasure, the 1240 EPROM bytes serve as one-time programmable read-only memory (OTPROM). The MC68HRC705J1A is a resistor-capacitor (RC) oscillator mask option version of the MC68HC705J1A and is discussed in Appendix A. MC68HRC705J1A. A high-speed version of the MC68HC705J1A, the MC68HSC705J1A, is discussed in Appendix B. MC68HSC705J1A. The MC68HSR705J1A, discussed in Appendix C. MC68HSR705J1A, is a high-speed version of the MC68HRC705J1A. A functional block diagram of the MC68HC705J1A is shown in Figure 1-1. Technical Data 22 MC68HC705J1A — Rev. 4.0 General Description MOTOROLA General Description Introduction OSC1 OSC2 INTERNAL OSCILLATOR 15-STAGE MULTIFUNCTION TIMER SYSTEM DIVIDE BY ³2 ALU 68HC05 CPU IRQ/VPP ACCUMULATOR CPU REGISTERS INDEX REGISTER 0 0 0 0 0 0 0 0 1 1 STK PTR PB5 PB4 PORT B CPU CONTROL RESET DATA DIRECTION REGISTER B WATCHDOG AND ILLEGAL ADDRESS DETECT PB3 PB2 PB1 PB0 STATIC RAM (SRAM) — 64 BYTES USER EPROM — 1240 BYTES PA7* PA6* PA5* PORT A CONDITION CODE REGISTER 1 1 1 H I N Z C DATA DIRECTION REGISTER A PROGRAM COUNTER PA4* PA3** PA2** PA1** PA0** *10-mA sink capability **External interrupt capability MASK OPTION REGISTER (EPROM) Figure 1-1. Block Diagram MC68HC705J1A — Rev. 4.0 MOTOROLA Technical Data General Description 23 General Description 1.3 Features Features of the MC68HC705J1A include: • Peripheral modules: – 15-stage multifunction timer – Computer operating properly (COP) watchdog • 14 bidirectional input/output (I/O) lines, including: – 10-mA sink capability on four I/O pins – Mask option register (MOR) and software programmable pulldowns on all I/O pins – MOR selectable interrupt on four I/O pins, a keyboard scan feature • MOR selectable sensitivity on external interrupt (edge- and level-sensitive or edge-sensitive only) • On-chip oscillator with connections for: – Crystal – Ceramic resonator – Resistor-capacitor (RC) oscillator – External clock • 1240 bytes of EPROM/OTPROM, including eight bytes for user vectors • 64 bytes of user random-access memory (RAM) • Memory-mapped I/O registers • Fully static operation with no minimum clock speed • Power-saving stop, halt, wait, and data-retention modes • External interrupt mask bit and acknowledge bit • Illegal address reset • Internal steering diode and pullup resistor from RESET pin to VDD Technical Data 24 MC68HC705J1A — Rev. 4.0 General Description MOTOROLA General Description Programmable Options 1.4 Programmable Options The options in Table 1-1 are programmable in the mask option register (MOR). Table 1-1. Programmable Options Feature Option COP watchdog timer Enabled or disabled External interrupt triggering Edge-sensitive only or edge- and level-sensitive Port A IRQ pin interrupts Enabled or disabled Port pulldown resistors Enabled or disabled STOP instruction mode Stop mode or halt mode Crystal oscillator internal resistor Enabled or disabled EPROM security Enabled or disabled Short oscillator delay counter Enabled or disabled 1.5 Pin Assignments Figure 1-2 shows the MC68HC705J1A pin assignments. 1.5.1 VDD and VSS VDD and VSS are the power supply and ground pins. The MCU operates from a single power supply. Very fast signal transitions occur on the MCU pins, placing high, short-duration current demands on the power supply. To prevent noise problems, take special care as Figure 1-3 shows, by placing the bypass capacitors as close as possible to the MCU. C2 is an optional bulk current bypass capacitor for use in applications that require the port pins to source high current levels. MC68HC705J1A — Rev. 4.0 MOTOROLA Technical Data General Description 25 General Description OSC1 1 20 RESET OSC2 2 19 IRQ/VPP PB5 3 18 PA0 PB4 4 17 PA1 PB3 5 16 PA2 PB2 6 15 PA3 PB1 7 14 PA4 PB0 8 13 PA5 VDD 9 12 PA6 VSS 10 11 PA7 Figure 1-2. Pin Assignments V+ VDD VDD MCU C1 0.1 µF C2 + C2 C1 VSS VSS Figure 1-3. Bypassing Layout Recommendation Technical Data 26 MC68HC705J1A — Rev. 4.0 General Description MOTOROLA General Description Pin Assignments 1.5.2 OSC1 and OSC2 The OSC1 and OSC2 pins are the connections for the on-chip oscillator. The oscillator can be driven by any of these: 1. Crystal (See Figure 1-4 and Figure 1-5.) 2. Ceramic resonator (See Figure 1-6 and Figure 1-7.) 3. Resistor/capacitor (RC) oscillator (Refer to Appendix A. MC68HRC705J1A and Appendix C. MC68HSR705J1A.) 4. External clock signal (See Figure 1-8.) The frequency, fosc, of the oscillator or external clock source is divided by two to produce the internal operating frequency, fop. 1.5.2.1 Crystal Oscillator Figure 1-4 and Figure 1-5 show a typical crystal oscillator circuit for an AT-cut, parallel resonant crystal. Follow the crystal supplier’s recommendations, as the crystal parameters determine the external component values required to provide reliable startup and maximum stability. The load capacitance values used in the oscillator circuit design should include all stray layout capacitances. To minimize output distortion, mount the crystal and capacitors as close as possible to the pins. An internal startup resistor of approximately 2 MΩ is provided between OSC1 and OSC2 for the crystal oscillator as a programmable mask option. NOTE: Use an AT-cut crystal and not an AT-strip crystal because the MCU can overdrive an AT-strip crystal. MC68HC705J1A — Rev. 4.0 MOTOROLA Technical Data General Description 27 General Description VSS MCU C3 XTAL OSC2 OSC1 OSC1 OSC2 C4 XTAL C3 27 pF C4 27 pF VDD C2 C1 VSS Figure 1-4. Crystal Connections with Oscillator Internal Resistor Mask Option VSS C3 MCU R 10 M¾Ω OSC2 OSC1 OSC1 XTAL R OSC2 C4 VDD XTAL C3 27 pF C4 27 pF C2 C1 VSS Figure 1-5. Crystal Connections without Oscillator Internal Resistor Mask Option 1.5.2.2 Ceramic Resonator Oscillator To reduce cost, use a ceramic resonator instead of the crystal. The circuits shown in Figure 1-6 and Figure 1-7 show ceramic resonator circuits. Follow the resonator manufacturer’s recommendations, as the resonator parameters determine the external component values required for maximum stability and reliable starting. The load capacitance values used in the oscillator circuit design should include all stray capacitances. Technical Data 28 MC68HC705J1A — Rev. 4.0 General Description MOTOROLA General Description Pin Assignments Mount the resonator and components as close as possible to the pins for startup stabilization and to minimize output distortion. An internal startup resistor of approximately 2 MΩ is provided between OSC1 and OSC2 as a programmable mask option. VSS CERAMIC RESONATOR C3 27 pF C3 OSC1 CERAMIC RESONATOR OSC2 OSC1 MCU OSC2 C4 C4 27 pF VDD C2 C1 VSS Figure 1-6. Ceramic Resonator Connections with Oscillator Internal Resistor Mask Option VSS C3 CERAMIC RESONATOR R 10 M¾Ω OSC2 OSC1 MCU OSC1 R OSC2 C4 C3 27 pF CERAMIC RESONATOR VDD C4 27 pF C2 C1 VSS Figure 1-7. Ceramic Resonator Connections without Oscillator Internal Resistor Mask Option MC68HC705J1A — Rev. 4.0 MOTOROLA Technical Data General Description 29 General Description 1.5.2.3 RC Oscillator Refer to Appendix A. MC68HRC705J1A and Appendix C. MC68HSR705J1A. 1.5.2.4 External Clock An external clock from another complementary metal-oxide semiconductor (CMOS)-compatible device can be connected to the OSC1 input, with the OSC2 input not connected, as shown in Figure 1-8. This configuration is possible regardless of whether the crystal/ceramic resonator or the RC oscillator is enabled. OSC2 OSC1 MCU EXTERNAL CMOS CLOCK Figure 1-8. External Clock Connections 1.6 RESET Applying a logic 0 to the RESET pin forces the MCU to a known startup state. An internal reset also pulls the RESET pin low. An internal resistor to VDD pulls the RESET pin high. A steering diode between the RESET and VDD pins discharges any RESET pin voltage when power is removed from the MCU. The RESET pin contains an internal Schmitt trigger to improve its noise immunity as an input. Refer to Section 4. Resets and Interrupts for more information. Technical Data 30 MC68HC705J1A — Rev. 4.0 General Description MOTOROLA General Description IRQ/VPP 1.7 IRQ/VPP The external interrupt/programming voltage pin (IRQ/VPP) drives the asynchronous IRQ interrupt function of the CPU. Additionally, it is used to program the user EPROM and mask option register. (See Section 2. Memory and Section 8. External Interrupt Module (IRQ).) The LEVEL bit in the mask option register provides negative edge-sensitive triggering or both negative edge-sensitive and low level-sensitive triggering for the interrupt function. If level-sensitive triggering is selected, the IRQ/VPP input requires an external resistor to VDD for wired-OR operation. If the IRQ/VPP pin is not used, it must be tied to the VDD supply. The IRQ/VPP pin contains an internal Schmitt trigger as part of its input to improve noise immunity. The voltage on this pin should not exceed VDD except when the pin is being used for programming the EPROM. NOTE: The mask option register can enable the PA0–PA3 pins to function as external interrupt pins. 1.8 PA0–PA7 These eight input/output (I/O) lines comprise port A, a general-purpose, bidirectional I/O port. See Section 8. External Interrupt Module (IRQ) for information on PA0–PA3 external interrupts. 1.9 PB0–PB5 These six I/O lines comprise port B, a general-purpose, bidirectional I/O port. MC68HC705J1A — Rev. 4.0 MOTOROLA Technical Data General Description 31 General Description Technical Data 32 MC68HC705J1A — Rev. 4.0 General Description MOTOROLA Technical Data — MC68HC705J1A Section 2. Memory 2.1 Contents 2.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 2.3 Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2.4 Input/Output Register Summary . . . . . . . . . . . . . . . . . . . . . . . .35 2.5 RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 2.6 EPROM/OTPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 2.6.1 EPROM/OTPROM Programming . . . . . . . . . . . . . . . . . . . . . 38 2.6.2 EPROM Programming Register . . . . . . . . . . . . . . . . . . . . . 39 2.6.3 EPROM Erasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 2.7 Mask Option Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 2.8 EPROM Programming Characteristics . . . . . . . . . . . . . . . . . . . 43 2.2 Introduction This section describes the organization of the on-chip memory consisting of: • 1232 bytes of user erasable, programmable read-only memory (EPROM), plus eight bytes for user vectors • 64 bytes of user random-access memory (RAM) MC68HC705J1A — Rev. 4.0 MOTOROLA Technical Data Memory 33 Memory 2.3 Memory Map Port A Data Register (PORTA) Port B Data Register (PORTB) Unimplemented Data Direction Register A (DDRA) Data Direction Register B (DDRB) Unimplemented $0000 ↓ $001F $0020 ↓ $00BF $00C0 ↓ $00FF $0100 ↓ $02FF $0300 ↓ $07CF $07D0 ↓ $07ED $07EE $07EF $07F0 ↓ $07FF Timer Status and Control Register (TSCR) Timer Control Register (TCR) IRQ Status and Control Register (ISCR) I/O Registers 32 Bytes Unimplemented Unimplemented 160 Bytes Pulldown Register Port A (PDRA) Pulldown Register Port B (PDRB) RAM 64 Bytes Unimplemented EPROM Programming Register (EPROG) Unimplemented 512 Bytes Unimplemented EPROM 1232 Bytes Reserved COP Register (COPR)(1) Mask Option Register (MOR) Unimplemented 30 Bytes Reserved Test ROM 2 Bytes Timer Interrupt Vector High Timer Interrupt Vector Low External Interrupt Vector High External Interrupt Vector Low Software Interrupt Vector High Software Interrupt Vector Low Reset Vector High Reset Vector Low Registers and EPROM 16 Bytes (1) $0000 $0001 $0002 $0003 $0004 $0005 $0006 $0007 $0008 $0009 $000A $000B ↓ $000F $0010 $0011 $0012 ↓ $0017 $0018 $0019 ↓ $001E $001F $07F0 $07F1 $07F2 ↓ $07F7 $07F8 $07F9 $07FA $07FB $07FC $07FD $07FE $07FF Writing to bit 0 of $07F0 clears the computer operating properly (COP) watchdog. Figure 2-1. Memory Map Technical Data 34 MC68HC705J1A — Rev. 4.0 Memory MOTOROLA Memory Input/Output Register Summary 2.4 Input/Output Register Summary Addr. $0000 $0001 Register Name Read: Port A Data Register (PORTA) Write: See page 89. Reset: Read: Port B Data Register (PORTB) Write: See page 92. Reset: $0002 Unimplemented $0003 Unimplemented Bit 7 6 5 4 3 2 1 Bit 0 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 PB2 PB1 PB0 Unaffected by reset 0 PB5 $0006 Unimplemented $0007 Unimplemented $0008 Read: Timer Status and Control Register (TSCR) Write: See page 112. Reset: PB4 PB3 Unaffected by reset Read: Data Direction Register A DDRA7 $0004 (DDRA) Write: See page 90. Reset: 0 Read: Data Direction Register B $0005 (DDRB) Write: See page 93. Reset: 0 0 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0 0 0 0 0 0 0 0 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0 0 0 0 0 0 0 0 0 TOIE RTIE RT1 RT0 TOFR RTIFR 0 0 1 1 0 0 0 TOF RTIF 0 0 0 = Unimplemented 0 R = Reserved Figure 2-2. I/O Register Summary (Sheet 1 of 3) MC68HC705J1A — Rev. 4.0 MOTOROLA Technical Data Memory 35 Memory Addr. $0009 $000A Register Name Read: Timer Counter Register (TCR) Write: See page 114. Reset: Read: IRQ Status and Control Register (ISCR) Write: See page 106. Reset: $000B Bit 7 6 5 4 3 2 1 Bit 0 TMR7 TMR6 TMR5 TMR4 TMR3 TMR2 TMR1 TMR0 0 0 0 0 0 0 0 0 0 0 0 IRQF 0 0 0 IRQE R IRQR 1 0 0 0 0 0 0 0 PDIA7 PDIA6 PDIA5 PDIA4 PDIA3 PDIA2 PDIA1 PDIA0 0 0 0 0 0 0 0 0 PDIB5 PDIB4 PDIB3 PDIB2 PDIB1 PDIB0 0 0 0 ELAT MPGM EPGM 0 0 0 Unimplemented ↓ $000F $0010 $0011 Unimplemented Read: Pulldown Register A (PDRA) Write: See page 91. Reset: Read: Pulldown Register B (PDRB) Write: See page 94. Reset: $0012 0 0 0 0 0 0 0 0 0 0 R R R R 0 0 0 0 Unimplemented ↓ $0017 Unimplemented $0018 Read: EPROM Programming Register (EPROG) Write: See page 39. Reset: 0 = Unimplemented R = Reserved Figure 2-2. I/O Register Summary (Sheet 2 of 3) Technical Data 36 MC68HC705J1A — Rev. 4.0 Memory MOTOROLA Memory RAM Addr. Register Name $0019 Unimplemented Bit 7 6 5 4 3 2 1 Bit 0 R R R R R R R R ↓ $001E Unimplemented $001F Reserved Read: COP Register (COPR) Write: See page 99. Reset: $07F0 $07F1 Read: Mask Option Register SOSCD (MOR) Write: See page 41. Reset: COPC 0 EPMSEC OSCRES SWAIT SWPDI PIRQ LEVEL COPEN Unaffected by reset = Unimplemented R = Reserved Figure 2-2. I/O Register Summary (Sheet 3 of 3) 2.5 RAM The 64 addresses from $00C0 to $00FF serve as both the user RAM and the stack RAM. Before processing an interrupt, the central processor unit (CPU) uses five bytes of the stack to save the contents of the CPU registers. During a subroutine call, the CPU uses two bytes of the stack to store the return address. The stack pointer decrements when the CPU stores a byte on the stack and increments when the CPU retrieves a byte from the stack. NOTE: Be careful when using nested subroutines or multiple interrupt levels. The CPU may overwrite data in the RAM during a subroutine or during the interrupt stacking operation. MC68HC705J1A — Rev. 4.0 MOTOROLA Technical Data Memory 37 Memory 2.6 EPROM/OTPROM A microcontroller unit (MCU) with a quartz window has 1240 bytes of erasable, programmable ROM (EPROM). The quartz window allows EPROM erasure with ultraviolet light. NOTE: Keep the quartz window covered with an opaque material except when programming the MCU. Ambient light can affect MCU operation. In an MCU without the quartz window, the EPROM cannot be erased and serves as 1240 bytes of one-time programmable ROM (OTPROM). These addresses are user EPROM/OTPROM locations: • $0300–$07CF • $07F8–$07FF, used for user-defined interrupt and reset vectors The computer operating properly (COP) register (COPR) is an EPROM/OTPROM location at address $07F0. The mask option register (MOR) is an EPROM/OTPROM location at address $07F1. 2.6.1 EPROM/OTPROM Programming The two ways to program the EPROM/OTPROM are: 1. Manipulating the control bits in the EPROM programming register to program the EPROM/OTPROM on a byte-by-byte basis 2. Programming the EPROM/OTPROM with the M68HC705J in-circuit simulator (M68HC705JICS) available from Motorola Technical Data 38 MC68HC705J1A — Rev. 4.0 Memory MOTOROLA Memory EPROM/OTPROM 2.6.2 EPROM Programming Register The EPROM programming register (EPROG) contains the control bits for programming the EPROM/OTPROM. Address: Read: $0018 Bit 7 6 5 4 3 0 0 0 0 0 R R R R 0 0 0 0 Write: Reset: 0 = Unimplemented 2 1 Bit 0 ELAT MPGM EPGM 0 0 0 R = Reserved Figure 2-3. EPROM Programming Register (EPROG) ELAT — EPROM Bus Latch Bit This read/write bit latches the address and data buses for EPROM/OTPROM programming. Clearing the ELAT bit automatically clears the EPGM bit. EPROM/OTPROM data cannot be read while the ELAT bit is set. Reset clears the ELAT bit. 1 = Address and data buses configured for EPROM/OTPROM programming the EPROM 0 = Address and data buses configured for normal operation MPGM — MOR Programming Bit This read/write bit applies programming power from the IRQ/VPP pin to the mask option register. Reset clears MPGM. 1 = Programming voltage applied to MOR 0 = Programming voltage not applied to MOR EPGM — EPROM Programming Bit This read/write bit applies the voltage from the IRQ/VPP pin to the EPROM. To write the EPGM bit, the ELAT bit must be set already. Reset clears EPGM. 1 = Programming voltage (IRQ/VPP pin) applied to EPROM 0 = Programming voltage (IRQ/VPP pin) not applied to EPROM MC68HC705J1A — Rev. 4.0 MOTOROLA Technical Data Memory 39 Memory NOTE: Writing logic 1s to both the ELAT and EPGM bits with a single instruction sets ELAT and clears EPGM. ELAT must be set first by a separate instruction. Bits [7:3] — Reserved Take these steps to program a byte of EPROM/OTPROM: 1. Apply the programming voltage, VPP, to the IRQ/VPP pin. 2. Set the ELAT bit. 3. Write to any EPROM/OTPROM address. 4. Set the EPGM bit and wait for a time, tEPGM. 5. Clear the ELAT bit. 2.6.3 EPROM Erasing The erased state of an EPROM bit is logic 0. Erase the EPROM by exposing it to 15 Ws/cm2 of ultraviolet light with a wave length of 2537 angstroms. Position the ultraviolet light source one inch from the EPROM. Do not use a shortwave filter. 2.7 Mask Option Register The mask option register (MOR) is an EPROM/OTPROM byte that controls these options: • COP watchdog (enable or disable) • External interrupt pin triggering (edge-sensitive only or edge- and level-sensitive) • Port A external interrupts (enable or disable) • Port pulldown resistors (enable or disable) • STOP instruction (stop mode or halt mode) • Crystal oscillator internal resistor (enable or disable) • EPROM security (enable or disable) • Short oscillator delay (enable or disable) Technical Data 40 MC68HC705J1A — Rev. 4.0 Memory MOTOROLA Memory Mask Option Register Take these steps to program the mask option register: 1. Apply the programming voltage, VPP, to the IRQ/VPP pin. 2. Write to the MOR. 3. Set the MPGM bit and wait for a time, tMPGM. 4. Clear the MPGM bit. 5. Reset the MCU. Address: $07F1 Bit 7 6 5 4 3 2 1 Bit 0 SWAIT SWPDI PIRQ LEVEL COPEN Read: SOSCD EPMSEC OSCRES Write: Reset: Unaffected by reset Figure 2-4. Mask Option Register (MOR) SOSCD — Short Oscillator Delay Bit The SOSCD bit controls the oscillator stabilization counter. The normal stabilization delay following reset or exit from stop mode is 4064 tcyc. Setting SOSCD enables a short oscillator stabilization delay. 1 = Short oscillator delay enabled 0 = Short oscillator delay disabled EPMSEC — EPROM Security Bit The EPMSEC bit controls access to the EPROM/OTPROM. 1 = External access to EPROM/OTPROM denied 0 = External access to EPROM/OTPROM not denied OSCRES — Oscillator Internal Resistor Bit The OSCRES bit enables a 2-MΩ internal resistor in the oscillator circuit. 1 = Oscillator internal resistor enabled 0 = Oscillator internal resistor disabled NOTE: Program the OSCRES bit to logic 0 in devices using RC oscillators. MC68HC705J1A — Rev. 4.0 MOTOROLA Technical Data Memory 41 Memory SWAIT — Stop-to-Wait Conversion Bit The SWAIT bit enables halt mode. When the SWAIT bit is set, the CPU interprets the STOP instruction as a WAIT instruction, and the MCU enters halt mode. Halt mode is the same as wait mode, except that an oscillator stabilization delay of 1 to 4064 tcyc occurs after exiting halt mode. 1 = Halt mode enabled 0 = Halt mode not enabled SWPDI — Software Pulldown Inhibit Bit The SWPDI bit inhibits software control of the I/O port pulldown devices. The SWPDI bit overrides the pulldown inhibit bits in the port pulldown inhibit registers. 1 = Software pulldown control inhibited 0 = Software pulldown control not inhibited PIRQ — Port A External Interrupt Bit The PIRQ bit enables the PA0–PA3 pins to function as external interrupt pins. 1 = PA0–PA3 enabled as external interrupt pins 0 = PA0–PA3 not enabled as external interrupt pins LEVEL —External Interrupt Sensitivity Bit The LEVEL bit controls external interrupt triggering sensitivity. 1 = External interrupts triggered by active edges and active levels 0 = External interrupts triggered only by active edges COPEN — COP Enable Bit The COPEN bit enables the COP watchdog. 1 = COP watchdog enabled 0 = COP watchdog disabled Technical Data 42 MC68HC705J1A — Rev. 4.0 Memory MOTOROLA Memory EPROM Programming Characteristics 2.8 EPROM Programming Characteristics Characteristic(1) Symbol Min Typ Max Unit Programming voltage IRQ/VPP VPP 16.0 16.5 17.0 V Programming current IRQ/VPP IPP —¦ 3.0 10.0 mA tEPGM 4 4 — — — — ms Programming time Per array byte MOR tMPGM 1. V DD = 5.0 Vdc ± 10%, V SS = 0 Vdc, TA = –40°C to +105°C MC68HC705J1A — Rev. 4.0 MOTOROLA Technical Data Memory 43 Memory Technical Data 44 MC68HC705J1A — Rev. 4.0 Memory MOTOROLA Technical Data — MC68HC705J1A Section 3. Central Processor Unit (CPU) 3.1 Contents 3.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 3.3 CPU Control Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 3.4 Arithmetic/Logic Unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 3.5 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 3.5.1 Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 3.5.2 Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 3.5.3 Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 3.5.4 Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 3.5.5 Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 3.6 Instruction Set. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 3.6.1 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 3.6.1.1 Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 3.6.1.2 Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 3.6.1.3 Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 3.6.1.4 Extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 3.6.1.5 Indexed, No Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 3.6.1.6 Indexed, 8-Bit Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 3.6.1.7 Indexed, 16-Bit Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 3.6.1.8 Relative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 3.6.2 Instruction Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 3.6.2.1 Register/Memory Instructions . . . . . . . . . . . . . . . . . . . . . 55 3.6.2.2 Read-Modify-Write Instructions . . . . . . . . . . . . . . . . . . . . 56 3.6.2.3 Jump/Branch Instructions . . . . . . . . . . . . . . . . . . . . . . . .57 3.6.2.4 Bit Manipulation Instructions . . . . . . . . . . . . . . . . . . . . . . 59 3.6.2.5 Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 3.7 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 3.8 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 MC68HC705J1A — Rev. 4.0 MOTOROLA Technical Data Central Processor Unit (CPU) 45 Central Processor Unit (CPU) 3.2 Introduction The central processor unit (CPU) consists of a CPU control unit, an arithmetic/logic unit (ALU), and five CPU registers. The CPU control unit fetches and decodes instructions. The ALU executes the instructions. The CPU registers contain data, addresses, and status bits that reflect the results of CPU operations. See Figure 3-1. Features include: • 2.1-MHz bus frequency • 8-bit accumulator • 8-bit index register • 11-bit program counter • 6-bit stack pointer • Condition code register (CCR) with five status flags • 62 instructions • Eight addressing modes • Power-saving stop, wait, halt, and data-retention modes 3.3 CPU Control Unit The CPU control unit fetches and decodes instructions during program operation. The control unit selects the memory locations to read and write and coordinates the timing of all CPU operations. 3.4 Arithmetic/Logic Unit The arithmetic/logic unit (ALU) performs the arithmetic, logic, and manipulation operations decoded from the instruction set by the CPU control unit. The ALU produces the results called for by the program and sets or clears status and control bits in the condition code register (CCR). Technical Data 46 MC68HC705J1A — Rev. 4.0 Central Processor Unit (CPU) MOTOROLA Central Processor Unit (CPU) Arithmetic/Logic Unit ARITHMETIC/LOGIC UNIT CPU CONTROL UNIT 7 6 5 4 3 2 1 0 ACCUMULATOR (A) 7 6 5 4 3 2 1 0 INDEX REGISTER (X) 15 14 13 12 11 10 9 8 7 6 0 0 0 0 1 1 15 14 13 12 11 10 9 8 7 6 0 0 0 0 0 0 0 0 5 4 3 2 1 0 STACK POINTER (SP) 5 4 3 2 1 0 0 PROGRAM COUNTER (PC) 7 6 5 4 3 2 1 0 1 1 1 H I N Z C CONDITION CODE REGISTER (CCR) HALF-CARRY FLAG INTERRUPT MASK NEGATIVE FLAG ZERO FLAG CARRY/BORROW FLAG Figure 3-1. Programming Model MC68HC705J1A — Rev. 4.0 MOTOROLA Technical Data Central Processor Unit (CPU) 47 Central Processor Unit (CPU) 3.5 CPU Registers The M68HC05 CPU contains five registers that control and monitor microcontroller unit (MCU) operation: • Accumulator • Index register • Stack pointer • Program counter • Condition code register CPU registers are not memory mapped. 3.5.1 Accumulator The accumulator (A) is a general-purpose 8-bit register. The CPU uses the accumulator to hold operands and results of ALU operations. Bit 7 6 5 4 3 2 1 Bit 0 Read: Write: Reset: Unaffected by reset Figure 3-2. Accumulator (A) 3.5.2 Index Register In the indexed addressing (X) modes, the CPU uses the byte in the index register to determine the conditional address of the operand. The index register also can serve as a temporary storage location or a counter. Bit 7 6 5 4 3 2 1 Bit 0 Read: Write: Reset: Unaffected by reset Figure 3-3. Index Register (X) Technical Data 48 MC68HC705J1A — Rev. 4.0 Central Processor Unit (CPU) MOTOROLA Central Processor Unit (CPU) CPU Registers 3.5.3 Stack Pointer The stack pointer (SP) is a 16-bit register that contains the address of the next location on the stack. During a reset or after the reset stack pointer instruction (RSP), the stack pointer is preset to $00FF. The address in the stack pointer decrements after a byte is stacked and increments before a byte is unstacked. Read: Bit 15 14 13 12 11 10 9 8 7 6 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 1 1 5 4 3 2 1 Bit 0 1 1 1 1 1 1 Write: Reset: = Unimplemented Figure 3-4. Stack Pointer (SP) The 10 most significant bits of the stack pointer are permanently fixed at 0000000011, so the stack pointer produces addresses from $00C0 to $00FF. If subroutines and interrupts use more than 64 stack locations, the stack pointer wraps around to address $00FF and begins writing over the previously stored data. A subroutine uses two stack locations; an interrupt uses five locations. MC68HC705J1A — Rev. 4.0 MOTOROLA Technical Data Central Processor Unit (CPU) 49 Central Processor Unit (CPU) 3.5.4 Program Counter The program counter (PC) is a 16-bit register that contains the address of the next instruction or operand to be fetched. The five most significant bits of the program counter are ignored and appear as 00000. Normally, the address in the program counter automatically increments to the next sequential memory location every time an instruction or operand is fetched. Jump, branch, and interrupt operations load the program counter with an address other than that of the next sequential location. Bit 15 14 13 12 11 0 0 0 0 0 10 9 8 7 6 5 4 3 2 Bit 0 1 Read: Write: Reset: Loaded with vector from $07FE and $07FF Figure 3-5. Program Counter (PC) 3.5.5 Condition Code Register The condition code register (CCR) is an 8-bit register whose three most significant bits are permanently fixed at 111. The condition code register contains the interrupt mask and four flags that indicate the results of the instruction just executed. Read: Bit 7 6 5 1 1 1 4 3 2 1 Bit 0 H I N Z C U 1 U U U Write: Reset: 1 1 1 = Unimplemented U = Unaffected Figure 3-6. Condition Code Register (CCR) Technical Data 50 MC68HC705J1A — Rev. 4.0 Central Processor Unit (CPU) MOTOROLA Central Processor Unit (CPU) CPU Registers H — Half-Carry Flag The CPU sets the half-carry flag when a carry occurs between bits 3 and 4 of the accumulator during an ADD (add without carry) or ADC (add with carry) operation. The half-carry flag is required for binary-coded decimal (BCD) arithmetic operations. I — Interrupt Mask Bit Setting the interrupt mask disables interrupts. If an interrupt request occurs while the interrupt mask is logic 0, the CPU saves the CPU registers on the stack, sets the interrupt mask, and then fetches the interrupt vector. If an interrupt request occurs while the interrupt mask is logic 1, the interrupt request is latched. Normally, the CPU processes the latched interrupt request as soon as the interrupt mask is cleared again. A return-from-interrupt instruction (RTI) unstacks the CPU registers, restoring the interrupt mask to its cleared state. After any reset, the interrupt mask is set and can be cleared only by a software instruction. N — Negative Flag The CPU sets the negative flag when an ALU operation produces a negative result. Z — Zero Flag The CPU sets the zero flag when an ALU operation produces a result of $00. C — Carry/Borrow Flag The CPU sets the carry/borrow flag when an addition operation produces a carry out of bit 7 of the accumulator or when a subtraction operation requires a borrow. Some logical operations and data manipulation instructions also clear or set the carry/borrow flag. MC68HC705J1A — Rev. 4.0 MOTOROLA Technical Data Central Processor Unit (CPU) 51 Central Processor Unit (CPU) 3.6 Instruction Set The MCU instruction set has 62 instructions and uses eight addressing modes. 3.6.1 Addressing Modes The CPU uses eight addressing modes for flexibility in accessing data. The addressing modes provide eight different ways for the CPU to find the data required to execute an instruction. The eight addressing modes are: • Inherent • Immediate • Direct • Extended • Indexed, no offset • Indexed, 8-bit offset • Indexed, 16-bit offset • Relative 3.6.1.1 Inherent Inherent instructions are those that have no operand, such as return from interrupt (RTI) and stop (STOP). Some of the inherent instructions act on data in the CPU registers, such as set carry flag (SEC) and increment accumulator (INCA). Inherent instructions require no operand address and are one byte long. 3.6.1.2 Immediate Immediate instructions are those that contain a value to be used in an operation with the value in the accumulator or index register. Immediate instructions require no operand address and are two bytes long. The opcode is the first byte, and the immediate data value is the second byte. Technical Data 52 MC68HC705J1A — Rev. 4.0 Central Processor Unit (CPU) MOTOROLA Central Processor Unit (CPU) Instruction Set 3.6.1.3 Direct Direct instructions can access any of the first 256 memory locations with two bytes. The first byte is the opcode, and the second is the low byte of the operand address. In direct addressing, the CPU automatically uses $00 as the high byte of the operand address. 3.6.1.4 Extended Extended instructions use three bytes and can access any address in memory. The first byte is the opcode; the second and third bytes are the high and low bytes of the operand address. When using the Motorola assembler, the programmer does not need to specify whether an instruction is direct or extended. The assembler automatically selects the shortest form of the instruction. 3.6.1.5 Indexed, No Offset Indexed instructions with no offset are 1-byte instructions that can access data with variable addresses within the first 256 memory locations. The index register contains the low byte of the effective address of the operand. The CPU automatically uses $00 as the high byte, so these instructions can address locations $0000–$00FF. Indexed, no offset instructions are often used to move a pointer through a table or to hold the address of a frequently used RAM or input/output (I/O) location. 3.6.1.6 Indexed, 8-Bit Offset Indexed, 8-bit offset instructions are 2-byte instructions that can access data with variable addresses within the first 511 memory locations. The CPU adds the unsigned byte in the index register to the unsigned byte following the opcode. The sum is the effective address of the operand. These instructions can access locations $0000–$01FE. Indexed 8-bit offset instructions are useful for selecting the kth element in an n-element table. The table can begin anywhere within the first 256 memory locations and could extend as far as location 510 ($01FE). MC68HC705J1A — Rev. 4.0 MOTOROLA Technical Data Central Processor Unit (CPU) 53 Central Processor Unit (CPU) The k value is typically in the index register, and the address of the beginning of the table is in the byte following the opcode. 3.6.1.7 Indexed, 16-Bit Offset Indexed, 16-bit offset instructions are 3-byte instructions that can access data with variable addresses at any location in memory. The CPU adds the unsigned byte in the index register to the two unsigned bytes following the opcode. The sum is the effective address of the operand. The first byte after the opcode is the high byte of the 16-bit offset; the second byte is the low byte of the offset. Indexed, 16-bit offset instructions are useful for selecting the kth element in an n-element table anywhere in memory. As with direct and extended addressing, the Motorola assembler determines the shortest form of indexed addressing. 3.6.1.8 Relative Relative addressing is only for branch instructions. If the branch condition is true, the CPU finds the effective branch destination by adding the signed byte following the opcode to the contents of the program counter. If the branch condition is not true, the CPU goes to the next instruction. The offset is a signed, two’s complement byte that gives a branching range of –128 to +127 bytes from the address of the next location after the branch instruction. When using the Motorola assembler, the programmer does not need to calculate the offset because the assembler determines the proper offset and verifies that it is within the span of the branch. Technical Data 54 MC68HC705J1A — Rev. 4.0 Central Processor Unit (CPU) MOTOROLA Central Processor Unit (CPU) Instruction Set 3.6.2 Instruction Types The MCU instructions fall into these five categories: • Register/memory instructions • Read-modify-write instructions • Jump/branch instructions • Bit manipulation instructions • Control instructions 3.6.2.1 Register/Memory Instructions These instructions operate on CPU registers and memory locations. Most of them use two operands. One operand is in either the accumulator or the index register. The CPU finds the other operand in memory. Table 3-1. Register/Memory Instructions Instruction Add memory byte and carry bit to accumulator ADC Add memory byte to accumulator ADD AND memory byte with accumulator AND Bit test accumulator BIT Compare accumulator CMP Compare index register with memory byte CPX EXCLUSIVE OR accumulator with memory byte EOR Load accumulator with memory byte LDA Load index register with memory byte LDX Multiply MUL OR accumulator with memory byte ORA Subtract memory byte and carry bit from accumulator SBC Store accumulator in memory STA Store index register in memory STX Subtract memory byte from accumulator SUB MC68HC705J1A — Rev. 4.0 MOTOROLA Mnemonic Technical Data Central Processor Unit (CPU) 55 Central Processor Unit (CPU) 3.6.2.2 Read-Modify-Write Instructions These instructions read a memory location or a register, modify its contents, and write the modified value back to the memory location or to the register. NOTE: Do not use read-modify-write instructions on registers with write-only bits. Table 3-2. Read-Modify-Write Instructions Instruction Mnemonic Arithmetic shift left (same as LSL) ASL Arithmetic shift right ASR Bit clear BCLR (1) Bit set BSET(1) Clear register CLR Complement (one’s complement) COM Decrement DEC Increment INC Logical shift left (same as ASL) LSL Logical shift right LSR Negate (two’s complement) NEG Rotate left through carry bit ROL Rotate right through carry bit ROR Test for negative or zero TST(2) 1. Unlike other read-modify-write instructions, BCLR and BSET use only direct addressing. 2. TST is an exception to the read-modify-write sequence because it does not write a replacement value. Technical Data 56 MC68HC705J1A — Rev. 4.0 Central Processor Unit (CPU) MOTOROLA Central Processor Unit (CPU) Instruction Set 3.6.2.3 Jump/Branch Instructions Jump instructions allow the CPU to interrupt the normal sequence of the program counter. The unconditional jump instruction (JMP) and the jump-to-subroutine instruction (JSR) have no register operand. Branch instructions allow the CPU to interrupt the normal sequence of the program counter when a test condition is met. If the test condition is not met, the branch is not performed. The BRCLR and BRSET instructions cause a branch based on the state of any readable bit in the first 256 memory locations. These 3-byte instructions use a combination of direct addressing and relative addressing. The direct address of the byte to be tested is in the byte following the opcode. The third byte is the signed offset byte. The CPU finds the effective branch destination by adding the third byte to the program counter if the specified bit tests true. The bit to be tested and its condition (set or clear) is part of the opcode. The span of branching is from –128 to +127 from the address of the next location after the branch instruction. The CPU also transfers the tested bit to the carry/borrow bit of the condition code register. NOTE: Do not use BRCLR or BRSET instructions on registers with write-only bits. MC68HC705J1A — Rev. 4.0 MOTOROLA Technical Data Central Processor Unit (CPU) 57 Central Processor Unit (CPU) Table 3-3. Jump and Branch Instructions Instruction Branch if carry bit clear BCC Branch if carry bit set BCS Branch if equal BEQ Branch if half-carry bit clear BHCC Branch if half-carry bit set BHCS Branch if higher BHI Branch if higher or same BHS Branch if IRQ pin high BIH Branch if IRQ pin low BIL Branch if lower BLO Branch if lower or same BLS Branch if interrupt mask clear BMC Branch if minus BMI Branch if interrupt mask set BMS Branch if not equal BNE Branch if plus BPL Branch always BRA Branch if bit clear Branch never Branch if bit set BRCLR BRN BRSET Branch to subroutine BSR Unconditional jump JMP Jump to subroutine JSR Technical Data 58 Mnemonic MC68HC705J1A — Rev. 4.0 Central Processor Unit (CPU) MOTOROLA Central Processor Unit (CPU) Instruction Set 3.6.2.4 Bit Manipulation Instructions The CPU can set or clear any writable bit in the first 256 bytes of memory, which includes I/O registers and on-chip RAM locations. The CPU can also test and branch based on the state of any bit in any of the first 256 memory locations. Table 3-4. Bit Manipulation Instructions Instruction Bit clear BRCLR Branch if bit set BRSET BSET Do not use bit manipulation instructions on registers with write-only bits. MC68HC705J1A — Rev. 4.0 MOTOROLA BCLR Branch if bit clear Bit set NOTE: Mnemonic Technical Data Central Processor Unit (CPU) 59 Central Processor Unit (CPU) 3.6.2.5 Control Instructions These instructions act on CPU registers and control CPU operation during program execution. Table 3-5. Control Instructions Instruction Clear carry bit CLC Clear interrupt mask CLI No operation NOP Reset stack pointer RSP Return from interrupt RTI Return from subroutine RTS Set carry bit SEC Set interrupt mask SEI Stop oscillator and enable IRQ pin STOP Software interrupt SWI Transfer accumulator to index register TAX Transfer index register to accumulator TXA Stop CPU clock and enable interrupts WAIT Technical Data 60 Mnemonic MC68HC705J1A — Rev. 4.0 Central Processor Unit (CPU) MOTOROLA Central Processor Unit (CPU) Instruction Set Summary 3.7 Instruction Set Summary IMM DIR EXT IX2 IX1 IX ii A9 2 B9 dd 3 C9 hh ll 4 D9 ee ff 5 E9 ff 4 F9 3 IMM DIR EXT IX2 IX1 IX AB ii 2 BB dd 3 CB hh ll 4 DB ee ff 5 EB ff 4 FB 3 — IMM DIR EXT IX2 IX1 IX ii A4 2 B4 dd 3 C4 hh ll 4 D4 ee ff 5 E4 ff 4 F4 3 38 48 58 68 78 dd DIR INH INH IX1 IX DIR INH INH IX1 IX 37 47 57 67 77 dd REL 24 rr 3 11 13 15 17 19 1B 1D 1F dd dd dd dd dd dd dd dd 5 5 5 5 5 5 5 5 Effect on CCR Description H I N Z C ADC #opr ADC opr ADC opr ADC opr,X ADC opr,X ADC ,X ADD #opr ADD opr ADD opr ADD opr,X ADD opr,X ADD ,X AND #opr AND opr AND opr AND opr,X AND opr,X AND ,X ASL opr ASLA ASLX ASL opr,X ASL ,X A ← (A) ∧ (M) Logical AND Arithmetic Shift Left (Same as LSL) C BCC rel Branch if Carry Bit Clear — — — — 0 b7 Arithmetic Shift Right A ← (A) + (M) Add without Carry ASR opr ASRA ASRX ASR opr,X ASR ,X A ← (A) + (M) + (C) Add with Carry — — b0 C b7 — — b0 PC ← (PC) + 2 + rel ? C = 0 Mn ← 0 — — — — — DIR DIR DIR DIR — — — — — DIR DIR DIR DIR (b0) (b1) (b2) (b3) (b4) (b5) (b6) (b7) ff ff Cycles Opcode Operation Address Mode Source Form Operand Table 3-6. Instruction Set Summary (Sheet 1 of 6) 5 3 3 6 5 5 3 3 6 5 BCLR n opr Clear Bit n BCS rel Branch if Carry Bit Set (Same as BLO) PC ← (PC) + 2 + rel ? C = 1 — — — — — REL 25 rr 3 BEQ rel Branch if Equal PC ← (PC) + 2 + rel ? Z = 1 — — — — — REL 27 rr 3 BHCC rel Branch if Half-Carry Bit Clear PC ← (PC) + 2 + rel ? H = 0 — — — — — REL 28 rr 3 BHCS rel Branch if Half-Carry Bit Set PC ← (PC) + 2 + rel ? H = 1 — — — — — REL 29 rr 3 MC68HC705J1A — Rev. 4.0 MOTOROLA Technical Data Central Processor Unit (CPU) 61 Central Processor Unit (CPU) Branch if Higher BHS rel Branch if Higher or Same BIH rel BIL rel Cycles BHI rel H I N Z C Operand Operation Opcode Source Form Address Mode Table 3-6. Instruction Set Summary (Sheet 2 of 6) PC ← (PC) + 2 + rel ? C ∨ Z = 0 — — — — — REL 22 rr 3 Description Effect on CCR PC ← (PC) + 2 + rel ? C = 0 — — — — — REL 24 rr 3 Branch if IRQ Pin High PC ← (PC) + 2 + rel ? IRQ = 1 — — — — — REL 2F rr 3 Branch if IRQ Pin Low PC ← (PC) + 2 + rel ? IRQ = 0 — — — — — REL 2E rr 3 — IMM DIR EXT IX2 IX1 IX ii A5 2 B5 dd 3 C5 hh ll 4 D5 ee ff 5 E5 ff 4 F5 3 — — — — — REL 25 rr 3 PC ← (PC) + 2 + rel ? C ∨ Z = 1 — — — — — REL 23 rr 3 BIT #opr BIT opr BIT opr BIT opr,X BIT opr,X BIT ,X Bit Test Accumulator with Memory Byte BLO rel Branch if Lower (Same as BCS) BLS rel Branch if Lower or Same BMC rel Branch if Interrupt Mask Clear PC ← (PC) + 2 + rel ? I = 0 — — — — — REL 2C rr 3 BMI rel Branch if Minus PC ← (PC) + 2 + rel ? N = 1 — — — — — REL 2B rr 3 BMS rel Branch if Interrupt Mask Set PC ← (PC) + 2 + rel ? I = 1 — — — — — REL 2D rr 3 BNE rel Branch if Not Equal PC ← (PC) + 2 + rel ? Z = 0 — — — — — REL 26 rr 3 BPL rel Branch if Plus PC ← (PC) + 2 + rel ? N = 0 — — — — — REL 2A rr 3 BRA rel Branch Always PC ← (PC) + 2 + rel ? 1 = 1 — — — — — REL 20 rr 3 01 03 05 07 09 0B 0D 0F dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr 5 5 5 5 5 5 5 5 21 rr 3 BRCLR n opr rel Branch if Bit n Clear BRN rel Branch Never BRSET n opr rel Branch if Bit n Set BSET n opr Set Bit n (A) ∧ (M) PC ← (PC) + 2 + rel ? C = 1 PC ← (PC) + 2 + rel ? Mn = 0 PC ← (PC) + 2 + rel ? 1 = 0 PC ← (PC) + 2 + rel ? Mn = 1 Mn ← 1 Technical Data 62 — — — — — — — — — — — DIR DIR DIR DIR DIR DIR DIR DIR (b0) (b1) (b2) (b3) (b4) (b5) (b6) (b7) REL DIR DIR DIR DIR DIR DIR DIR DIR (b0) (b1) (b2) (b3) (b4) (b5) (b6) (b7) 00 02 04 06 08 0A 0C 0E dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr 5 5 5 5 5 5 5 5 DIR DIR DIR DIR — — — — — DIR DIR DIR DIR (b0) (b1) (b2) (b3) (b4) (b5) (b6) (b7) 10 12 14 16 18 1A 1C 1E dd dd dd dd dd dd dd dd 5 5 5 5 5 5 5 5 — — — — MC68HC705J1A — Rev. 4.0 Central Processor Unit (CPU) MOTOROLA Central Processor Unit (CPU) Instruction Set Summary H I N Z C Operand Cycles Operation Opcode Source Form Address Mode Table 3-6. Instruction Set Summary (Sheet 3 of 6) PC ← (PC) + 2; push (PCL) SP ← (SP) – 1; push (PCH) SP ← (SP) – 1 PC ← (PC) + rel — — — — — REL AD rr 6 Description Effect on CCR BSR rel Branch to Subroutine CLC Clear Carry Bit C←0 — — — — 0 INH 98 2 CLI Clear Interrupt Mask I←0 — 0 — — — INH 9A 2 — — 0 1 — DIR INH INH IX1 IX 3F 4F 5F 6F 7F IMM DIR EXT IX2 IX1 IX ii A1 2 B1 dd 3 C1 hh ll 4 D1 ee ff 5 E1 ff 4 F1 3 DIR INH INH IX1 IX 33 43 53 63 73 IMM DIR EXT IX2 IX1 IX ii A3 2 B3 dd 3 C3 hh ll 4 D3 ee ff 5 E3 ff 4 F3 3 DIR INH INH IX1 IX 3A 4A 5A 6A 7A — IMM DIR EXT IX2 IX1 IX ii A8 2 B8 dd 3 C8 hh ll 4 D8 ee ff 5 E8 ff 4 F8 3 — DIR INH INH IX1 IX 3C 4C 5C 6C 7C CLR opr CLRA CLRX CLR opr,X CLR ,X CMP CMP CMP CMP CMP CMP #opr opr opr opr,X opr,X ,X COM opr COMA COMX COM opr,X COM ,X CPX #opr CPX opr CPX opr CPX opr,X CPX opr,X CPX ,X DEC opr DECA DECX DEC opr,X DEC ,X EOR #opr EOR opr EOR opr EOR opr,X EOR opr,X EOR ,X INC opr INCA INCX INC opr,X INC ,X M ← $00 A ← $00 X ← $00 M ← $00 M ← $00 Clear Byte Compare Accumulator with Memory Byte (A) – (M) M ← (M) = $FF – (M) A ← (A) = $FF – (A) Complement Byte (One’s Complement) X ← (X) = $FF – (X) — — 1 M ← (M) = $FF – (M) M ← (M) = $FF – (M) Compare Index Register with Memory Byte M A X M M Decrement Byte EXCLUSIVE OR Accumulator with Memory Byte Increment Byte (X) – (M) ← (M) – 1 ← (A) – 1 ← (X) – 1 ← (M) – 1 ← (M) – 1 A ← (A) ⊕ (M) M ← (M) + 1 A ← (A) + 1 X ← (X) + 1 M ← (M) + 1 M ← (M) + 1 MC68HC705J1A — Rev. 4.0 MOTOROLA — — — — — — — — — — — dd ff dd ff dd ff dd ff 5 3 3 6 5 5 3 3 6 5 5 3 3 6 5 5 3 3 6 5 Technical Data Central Processor Unit (CPU) 63 Central Processor Unit (CPU) JMP JMP JMP JMP JMP opr opr opr,X opr,X ,X JSR opr JSR opr JSR opr,X JSR opr,X JSR ,X LDA LDA LDA LDA LDA LDA #opr opr opr opr,X opr,X ,X LDX LDX LDX LDX LDX LDX #opr opr opr opr,X opr,X ,X LSL opr LSLA LSLX LSL opr,X LSL ,X Unconditional Jump PC ← Jump Address Jump to Subroutine PC ← (PC) + n (n = 1, 2, or 3) Push (PCL); SP ← (SP) – 1 Push (PCH); SP ← (SP) – 1 PC ← Effective Address A ← (M) Load Accumulator with Memory Byte 0 b7 Logical Shift Right MUL Unsigned Multiply NEG opr NEGA NEGX NEG opr,X NEG ,X Negate Byte (Two’s Complement) NOP No Operation C BD dd 5 CD hh ll 6 DD ee ff 7 ED ff 6 FD 5 — IMM DIR EXT IX2 IX1 IX ii A6 2 B6 dd 3 C6 hh ll 4 D6 ee ff 5 E6 ff 4 F6 3 — IMM DIR EXT IX2 IX1 IX AE ii 2 BE dd 3 CE hh ll 4 DE ee ff 5 EE ff 4 FE 3 38 48 58 68 78 dd DIR INH INH IX1 IX DIR INH INH IX1 IX 34 44 54 64 74 dd 0 — — — 0 INH 42 DIR INH INH IX1 IX 30 40 50 60 70 INH 9D IMM DIR EXT IX2 IX1 IX AA ii 2 BA dd 3 CA hh ll 4 DA ee ff 5 EA ff 4 FA 3 — — — — 0 b0 X : A ← (X) × (A) M ← –(M) = $00 – (M) A ← –(A) = $00 – (A) X ← –(X) = $00 – (X) M ← –(M) = $00 – (M) M ← –(M) = $00 – (M) — — — — — — — Logical OR Accumulator with Memory A ← (A) ∨ (M) Technical Data 64 — — — — — DIR EXT IX2 IX1 IX b0 0 b7 BC dd 2 CC hh ll 3 DC ee ff 4 EC ff 3 FC 2 — — C Logical Shift Left (Same as ASL) — — — — — DIR EXT IX2 IX1 IX — — X ← (M) Load Index Register with Memory Byte Cycles H I N Z C LSR opr LSRA LSRX LSR opr,X LSR ,X ORA #opr ORA opr ORA opr ORA opr,X ORA opr,X ORA ,X Description Operand Operation Effect on CCR Opcode Source Form Address Mode Table 3-6. Instruction Set Summary (Sheet 4 of 6) — — — ff ff 5 3 3 6 5 5 3 3 6 5 11 dd ff 5 3 3 6 5 2 MC68HC705J1A — Rev. 4.0 Central Processor Unit (CPU) MOTOROLA Central Processor Unit (CPU) Instruction Set Summary H I N Z C C Rotate Byte Left through Carry Bit — — b7 b0 DIR INH INH IX1 IX 39 49 59 69 79 dd DIR INH INH IX1 IX 36 46 56 66 76 dd ff Cycles Description Operand ROL opr ROLA ROLX ROL opr,X ROL ,X Operation Effect on CCR Opcode Source Form Address Mode Table 3-6. Instruction Set Summary (Sheet 5 of 6) 5 3 3 6 5 5 3 3 6 5 ROR opr RORA RORX ROR opr,X ROR ,X Rotate Byte Right through Carry Bit RSP Reset Stack Pointer SP ← $00FF — — — — — INH 9C 2 RTI Return from Interrupt SP ← (SP) + 1; Pull (CCR) SP ← (SP) + 1; Pull (A) SP ← (SP) + 1; Pull (X) SP ← (SP) + 1; Pull (PCH) SP ← (SP) + 1; Pull (PCL) INH 80 9 RTS Return from Subroutine SP ← (SP) + 1; Pull (PCH) SP ← (SP) + 1; Pull (PCL) — — — — — INH 81 6 IMM DIR EXT IX2 IX1 IX ii A2 2 B2 dd 3 C2 hh ll 4 D2 ee ff 5 E2 ff 4 F2 3 C b7 — — b0 ff SBC #opr SBC opr SBC opr SBC opr,X SBC opr,X SBC ,X Subtract Memory Byte and Carry Bit from Accumulator SEC Set Carry Bit C←1 — — — — 1 INH 99 2 SEI Set Interrupt Mask I←1 — 1 — — — INH 9B 2 — DIR EXT IX2 IX1 IX B7 dd 4 C7 hh ll 5 D7 ee ff 6 E7 ff 5 F7 4 — 0 — — — INH 8E — DIR EXT IX2 IX1 IX BF dd 4 CF hh ll 5 DF ee ff 6 EF ff 5 FF 4 IMM DIR EXT IX2 IX1 IX ii A0 2 B0 dd 3 C0 hh ll 4 D0 ee ff 5 E0 ff 4 F0 3 STA opr STA opr STA opr,X STA opr,X STA ,X Store Accumulator in Memory STOP Stop Oscillator and Enable IRQ Pin STX STX STX STX STX opr opr opr,X opr,X ,X SUB #opr SUB opr SUB opr SUB opr,X SUB opr,X SUB ,X A ← (A) – (M) – (C) M ← (A) M ← (X) Store Index Register In Memory Subtract Memory Byte from Accumulator A ← (A) – (M) MC68HC705J1A — Rev. 4.0 MOTOROLA — — — — — — — — 2 Technical Data Central Processor Unit (CPU) 65 Central Processor Unit (CPU) H I N Z C PC ← (PC) + 1; Push (PCL) SP ← (SP) – 1; Push (PCH) SP ← (SP) – 1; Push (X) SP ← (SP) – 1; Push (A) — 1 — — — SP ← (SP) – 1; Push (CCR) SP ← (SP) – 1; I ← 1 PCH ← Interrupt Vector High Byte PCL ← Interrupt Vector Low Byte SWI Software Interrupt TAX Transfer Accumulator to Index Register TST opr TSTA TSTX TST opr,X TST ,X Test Memory Byte for Negative or Zero TXA Transfer Index Register to Accumulator WAIT Stop CPU Clock and Enable Interrupts A C CCR dd dd rr DIR ee ff EXT ff H hh ll I ii IMM INH IX IX1 IX2 M N n Accumulator Carry/borrow flag Condition code register Direct address of operand Direct address of operand and relative offset of branch instruction Direct addressing mode High and low bytes of offset in indexed, 16-bit offset addressing Extended addressing mode Offset byte in indexed, 8-bit offset addressing Half-carry flag High and low bytes of operand address in extended addressing Interrupt mask Immediate operand byte Immediate addressing mode Inherent addressing mode Indexed, no offset addressing mode Indexed, 8-bit offset addressing mode Indexed, 16-bit offset addressing mode Memory location Negative flag Any bit X ← (A) (M) – $00 A ← (X) — — — — — — — — — — — — — — — opr PC PCH PCL REL rel rr SP X Z # ∧ ∨ ⊕ () –( ) ← ? : — — — INH 83 10 INH 97 2 DIR INH INH IX1 IX 3D 4D 5D 6D 7D INH 9F 2 INH 8F 2 dd ff Cycles Description Opcode Operation Effect on CCR Address Mode Source Form Operand Table 3-6. Instruction Set Summary (Sheet 6 of 6) 4 3 3 5 4 Operand (one or two bytes) Program counter Program counter high byte Program counter low byte Relative addressing mode Relative program counter offset byte Relative program counter offset byte Stack pointer Index register Zero flag Immediate value Logical AND Logical OR Logical EXCLUSIVE OR Contents of Negation (two’s complement) Loaded with If Concatenated with Set or cleared Not affected 3.8 Opcode Map See Table 3-7. Technical Data 66 MC68HC705J1A — Rev. 4.0 Central Processor Unit (CPU) MOTOROLA MC68HC705J1A — Rev. 4.0 MOTOROLA Table 3-7. Opcode Map Bit Manipulation MSB LSB 0 1 2 3 4 Central Processor Unit (CPU) 5 6 7 8 9 A B C E F Read-Modify-Write Control Register/Memory DIR REL DIR INH INH IX1 IX INH INH IMM DIR EXT IX2 IX1 IX 0 1 2 3 4 5 6 7 8 9 A B C D E F 67 Technical Data 5 BRSET0 3 DIR 5 BRCLR0 3 DIR 5 BRSET1 3 DIR 5 BRCLR1 3 DIR 5 BRSET2 3 DIR 5 BRCLR2 3 DIR 5 BRSET3 3 DIR 5 BRCLR3 3 DIR 5 BRSET4 3 DIR 5 BRCLR4 3 DIR 5 BRSET5 3 DIR 5 BRCLR5 3 DIR 5 BRSET6 3 DIR 5 BRCLR6 3 DIR 5 BRSET7 3 DIR 5 BRCLR7 3 DIR 5 BSET0 DIR 5 BCLR0 2 DIR 5 BSET1 2 DIR 5 BCLR1 2 DIR 5 BSET2 2 DIR 5 BCLR2 2 DIR 5 BSET3 2 DIR 5 BCLR3 2 DIR 5 BSET4 2 DIR 5 BCLR4 2 DIR 5 BSET5 2 DIR 5 BCLR5 2 DIR 5 BSET6 2 DIR 5 BCLR6 2 DIR 5 BSET7 2 DIR 5 BCLR7 2 DIR 2 INH = Inherent IMM = Immediate DIR = Direct EXT = Extended 5 3 NEG BRA DIR REL 2 3 BRN 2 REL 3 BHI 2 REL 5 3 COM BLS DIR 2 REL 2 5 3 LSR BCC DIR 2 REL 2 3 BCS/BLO 2 REL 5 3 ROR BNE DIR 2 REL 2 5 3 ASR BEQ DIR 2 REL 2 5 3 ASL/LSL BHCC DIR 2 REL 2 5 3 ROL BHCS DIR 2 REL 2 5 3 DEC BPL DIR 2 REL 2 3 BMI 2 REL 5 3 INC BMC DIR 2 REL 2 4 3 TST BMS DIR 2 REL 2 3 BIL 2 REL 5 3 CLR BIH DIR 2 REL 2 2 1 9 RTI INH 6 RTS 1 INH 5 6 3 3 NEG NEG NEGX NEGA IX 1 IX1 1 INH 2 INH 1 2 2 11 MUL 1 INH 10 5 6 3 3 SWI COM COM COMX COMA INH IX 1 IX1 1 INH 2 1 INH 1 5 6 3 3 LSR LSR LSRX LSRA IX IX1 1 INH 2 1 INH 1 2 2 2 2 6 3 3 ROR RORX RORA IX1 INH 2 1 INH 1 6 3 3 ASR ASRX ASRA IX1 INH 2 1 INH 1 6 3 3 ASLA/LSLA ASLX/LSLX ASL/LSL IX1 INH 2 1 INH 1 6 3 3 ROL ROLX ROLA IX1 INH 2 1 INH 1 6 3 3 DEC DECX DECA IX1 INH 2 1 INH 1 5 ROR 1 2 IX 5 ASR 1 IX 5 ASL/LSL 1 IX 5 ROL 1 IX 5 DEC 1 IX 1 1 1 1 1 5 6 3 3 INC INC INCX INCA IX IX1 1 INH 2 INH 1 4 5 3 3 TST TST TSTX TSTA IX IX1 1 INH 2 1 INH 1 1 1 1 2 TAX INH 2 CLC INH 2 SEC INH 2 CLI INH 2 SEI INH 2 RSP INH 2 NOP INH 2 STOP 1 INH 2 2 5 6 3 3 TXA WAIT CLR CLR CLRX CLRA INH INH 1 IX 1 IX1 1 INH 2 1 INH 1 REL = Relative IX = Indexed, No Offset IX1 = Indexed, 8-Bit Offset IX2 = Indexed, 16-Bit Offset 2 SUB IMM 2 2 CMP IMM 2 2 SBC IMM 2 2 CPX IMM 2 2 AND IMM 2 2 BIT IMM 2 2 LDA IMM 2 2 2 EOR IMM 2 2 ADC 2 IMM 2 2 ORA 2 IMM 2 2 ADD 2 IMM 2 2 2 6 BSR 2 REL 2 2 LDX 2 IMM 2 2 MSB LSB LSB of Opcode in Hexadecimal 0 3 SUB DIR 3 3 CMP DIR 3 3 SBC DIR 3 3 CPX DIR 3 3 AND DIR 3 3 BIT DIR 3 3 LDA DIR 3 4 STA DIR 3 3 EOR DIR 3 3 ADC DIR 3 3 ORA DIR 3 3 ADD DIR 3 2 JMP DIR 3 5 JSR DIR 3 3 LDX DIR 3 4 STX DIR 3 0 4 SUB EXT 3 4 CMP EXT 3 4 SBC EXT 3 4 CPX EXT 3 4 AND EXT 3 4 BIT EXT 3 4 LDA EXT 3 5 STA EXT 3 4 EOR EXT 3 4 ADC EXT 3 4 ORA EXT 3 4 ADD EXT 3 3 JMP EXT 3 6 JSR EXT 3 4 LDX EXT 3 5 STX EXT 3 5 SUB IX2 2 5 CMP IX2 2 5 SBC IX2 2 5 CPX IX2 2 5 AND IX2 2 5 BIT IX2 2 5 LDA IX2 2 6 STA IX2 2 5 EOR IX2 2 5 ADC IX2 2 5 ORA IX2 2 5 ADD IX2 2 4 JMP IX2 2 7 JSR IX2 2 5 LDX IX2 2 6 STX IX2 2 4 SUB IX1 4 CMP IX1 4 SBC IX1 4 CPX IX1 4 AND IX1 4 BIT IX1 4 LDA IX1 5 STA IX1 4 EOR IX1 4 ADC IX1 4 ORA IX1 4 ADD IX1 3 JMP IX1 6 JSR IX1 4 LDX IX1 5 STX IX1 MSB LSB 3 SUB 1 1 CMP 1 IX 3 2 SBC 1 IX 3 3 CPX 1 IX 3 4 AND 1 IX 3 5 BIT 1 IX 3 LDA 1 6 IX 4 7 STA 1 IX 3 8 EOR 1 IX 3 9 ADC 1 IX 3 A ORA 1 IX 3 B ADD 1 IX 2 JMP 1 C IX 5 D JSR 1 IX 3 E LDX 1 IX 4 F STX 1 MSB of Opcode in Hexadecimal 5 Number of Cycles BRSET0 Opcode Mnemonic 3 DIR Number of Bytes/Addressing Mode 0 IX 3 IX Central Processor Unit (CPU) Opcode Map D Branch DIR Central Processor Unit (CPU) Technical Data 68 MC68HC705J1A — Rev. 4.0 Central Processor Unit (CPU) MOTOROLA Technical Data — MC68HC705J1A Section 4. Resets and Interrupts 4.1 Contents 4.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 4.3 Resets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 4.3.1 Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 4.3.2 External Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 4.3.3 COP Watchdog Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 4.3.4 Illegal Address Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 4.4 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 4.4.1 Software Interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 4.4.2 External Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 4.4.3 Timer Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 4.4.3.1 Real-Time Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 4.4.3.2 Timer Overflow Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . 76 4.4.4 Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 4.2 Introduction Reset initializes the microcontroller unit (MCU) by returning the program counter to a known address and by forcing control and status bits to known states. Interrupts temporarily change the sequence of program execution to respond to events that occur during processing. MC68HC705J1A — Rev. 4.0 MOTOROLA Technical Data Resets and Interrupts 69 Resets and Interrupts 4.3 Resets A reset immediately stops the operation of the instruction being executed, initializes certain control and status bits, and loads the program counter with a user-defined reset vector address. These sources can generate a reset: • Power-on reset (POR) circuit • RESET pin • Computer operating properly (COP) watchdog • Illegal address ILLEGAL ADDRESS COP WATCHDOG VDD POWER-ON RESET S D RESET PIN INTERNAL CLOCK Q RST TO CPU AND PERIPHERAL MODULES CK RESET LATCH Figure 4-1. Reset Sources Technical Data 70 MC68HC705J1A — Rev. 4.0 Resets and Interrupts MOTOROLA Resets and Interrupts Resets 4.3.1 Power-On Reset A positive transition on the VDD pin generates a power-on reset. NOTE: The power-on reset is strictly for power-up conditions and cannot be used to detect drops in power supply voltage. A 4064-tcyc (internal clock cycle) delay after the oscillator becomes active allows the clock generator to stabilize. If any reset source is active at the end of this delay, the MCU remains in the reset condition until all reset sources are inactive. VDD OSCILLATOR STABILIZATION DELAY (NOTE 1) OSC1 PIN INTERNAL CLOCK INTERNAL ADDRESS BUS $07FE $07FE $07FE $07FE $07FE INTERNAL DATA BUS $07FE NEW PCH $07FF NEW PCL Notes: 1. Power-on reset threshold is typically between 1 V and 2 V. 2. Internal clock, internal address bus, and internal data bus are not available externally. Figure 4-2. Power-On Reset Timing MC68HC705J1A — Rev. 4.0 MOTOROLA Technical Data Resets and Interrupts 71 Resets and Interrupts 4.3.2 External Reset A logic 0 applied to the RESET pin for 1 1/2 tcyc generates an external reset. A Schmitt trigger senses the logic level at the RESET pin. INTERNAL CLOCK INTERNAL ADDRESS BUS $07FE $07FE $07FE $07FE NEW PCH INTERNAL DATA BUS $07FF NEW PC NEW PCL NEW PC OP CODE DUMMY tRL RESET Notes: 1. Internal clock, internal address bus, and internal data bus are not available externally. 2. The next rising edge of the internal clock after the rising edge of RESET initiates the reset sequence. Figure 4-3. External Reset Timing Table 4-1. External Reset Timing Characteristic RESET pulse width Symbol Min Max Unit tRL 1.5 — tcyc 4.3.3 COP Watchdog Reset A timeout of the COP watchdog generates a COP reset. The COP watchdog is part of a software error detection system and must be cleared periodically to start a new timeout period. To clear the COP watchdog and prevent a COP reset, write a logic 0 to bit 0 (COPC) of the COP register at location $07F0. 4.3.4 Illegal Address Reset An opcode fetch from an address not in random-access memory (RAM) or erasable, programmable read-only memory (EPROM) generates a reset. Technical Data 72 MC68HC705J1A — Rev. 4.0 Resets and Interrupts MOTOROLA Resets and Interrupts Interrupts 4.4 Interrupts These sources can generate interrupts: • Software interrupt (SWI) instruction • External interrupt pins: – IRQ/VPP – PA0–PA3 • Timer: – Real-time interrupt flag (RTIF) – Timer overflow flag (TOF) An interrupt temporarily stops the program sequence to process a particular event. An interrupt does not stop the operation of the instruction being executed, but takes effect when the current instruction completes its execution. Interrupt processing automatically saves the CPU registers on the stack and loads the program counter with a user-defined interrupt vector address. 4.4.1 Software Interrupt The software interrupt (SWI) instruction causes a non-maskable interrupt. 4.4.2 External Interrupt An interrupt signal on the IRQ/VPP pin latches an external interrupt request. When the CPU completes its current instruction, it tests the IRQ latch. If the IRQ latch is set, the CPU then tests the I bit in the condition code register. If the I bit is clear, the CPU then begins the interrupt sequence. MC68HC705J1A — Rev. 4.0 MOTOROLA Technical Data Resets and Interrupts 73 Resets and Interrupts The CPU clears the IRQ latch during interrupt processing, so that another interrupt signal on the IRQ/VPP pin can latch another interrupt request during the interrupt service routine. As soon as the I bit is cleared during the return from interrupt, the CPU can recognize the new interrupt request. Figure 4-4 shows the IRQ/VPP pin interrupt logic. TO BIH & BIL INSTRUCTION PROCESSING IRQ LEVEL-SENSITIVE TRIGGER (MOR LEVEL BIT) IRQF VDD EXTERNAL INTERRUPT REQUEST D IRQ Q LATCH CK PA3 PA2 PA1 PA0 IRQE CLR PIRQ (MOR) RESET IRQ VECTOR FETCH IRQR Figure 4-4. External Interrupt Logic Setting the I bit in the condition code register disables external interrupts. The port A external interrupt bit (PIRQ) in the mask option register enables pins PA0–PA3 to function as external interrupt pins. The external interrupt sensitivity bit (LEVEL) in the mask option register controls interrupt triggering sensitivity of external interrupt pins. The IRQ/VPP pin can be negative-edge triggered only or negative-edge and low-level triggered. Port A external interrupt pins can be positive-edge triggered only or both positive-edge and high-level triggered. The level-sensitive triggering option allows multiple external interrupt sources to be wire-ORed to an external interrupt pin. An external interrupt request, shown in Figure 4-5, is latched as long as any source is holding an external interrupt pin low. Technical Data 74 MC68HC705J1A — Rev. 4.0 Resets and Interrupts MOTOROLA Resets and Interrupts Interrupts tILIL IRQ PIN IRQ1 . tILIH tILIH . . IRQn IRQ (INTERNAL) Figure 4-5. External Interrupt Timing Table 4-2. External Interrupt Timing (VDD = 5.0 Vdc)(1) Characteristic Symbol Min Max Unit Interrupt pulse width low (edge-triggered) tILIH 125 — ns Interrupt pulse period tILIL Note(2) — tcyc 1. V DD = 5.0 Vdc ±10%, VSS = 0 Vdc, TA = –40°C to +105°C, unless otherwise noted 2. The minimum, tILIL, should not be less than the number of interrupt service routine cycles plus 19 tcyc. Table 4-3. External Interrupt Timing (VDD = 3.3 Vdc)(1) Characteristic Symbol Min Max Unit Interrupt pulse width low (edge-triggered) tILIH 250 — ns Interrupt pulse period tILIL Note(2) — tcyc 1. V DD = 3.3 Vdc ±10%, VSS = 0 Vdc, TA = –40°C to +105°C, unless otherwise noted 2. The minimum, tILIL, should not be less than the number of interrupt service routine cycles plus 19 tcyc. MC68HC705J1A — Rev. 4.0 MOTOROLA Technical Data Resets and Interrupts 75 Resets and Interrupts 4.4.3 Timer Interrupts The timer can generate these interrupt requests: • Real time • Timer overflow Setting the I bit in the condition code register disables timer interrupts. 4.4.3.1 Real-Time Interrupt A real-time interrupt occurs if the real-time interrupt flag, RTIF, becomes set while the real-time interrupt enable bit, RTIE, is also set. RTIF and RTIE are in the timer status and control register. 4.4.3.2 Timer Overflow Interrupt A timer overflow interrupt request occurs if the timer overflow flag, TOF, becomes set while the timer overflow interrupt enable bit, TOIE, is also set. TOF and TOIE are in the timer status and control register. 4.4.4 Interrupt Processing The CPU takes these actions to begin servicing an interrupt: • Stores the CPU registers on the stack in the order shown in Figure 4-6 • Sets the I bit in the condition code register to prevent further interrupts • Loads the program counter with the contents of the appropriate interrupt vector locations: – $07FC and $07FD (software interrupt vector) – $07FA and $07FB (external interrupt vector) – $07F8 and $07F9 (timer interrupt vector) The return-from-interrupt (RTI) instruction causes the CPU to recover the CPU registers from the stack as shown in Figure 4-6. Technical Data 76 MC68HC705J1A — Rev. 4.0 Resets and Interrupts MOTOROLA Resets and Interrupts Interrupts $00C0 (BOTTOM OF STACK) $00C1 $00C2 UNSTACKING ORDER • • • • • • 5 1 4 2 ACCUMULATOR 3 3 INDEX REGISTER 2 4 PROGRAM COUNTER (HIGH BYTE) 1 5 PROGRAM COUNTER (LOW BYTE) CONDITION CODE REGISTER STACKING ORDER • • • • • • $00FD $00FE $00FF (TOP OF STACK) Figure 4-6. Interrupt Stacking Order Table 4-4. Reset/Interrupt Vector Addresses Function Source Local Mask Global Mask Priority (1 = Highest) Vector Address Reset Power-on RESET pin COP watchdog(1) illegal address None None 1 $07FE–$07FF Software interrupt (SWI) User code None None Same priority as instruction $07FC–$07FD External interrupt IRQ/VPP pin IRQE I bit 2 $07FA–$07FB Timer interrupts RTIF bit TOF bit RTIE bit TOIE bit I bit 3 $07F8–$07F9 1. The COP watchdog is programmable in the mask option register. MC68HC705J1A — Rev. 4.0 MOTOROLA Technical Data Resets and Interrupts 77 Resets and Interrupts FROM RESET YES I BIT SET? NO EXTERNAL INTERRUPT? YES CLEAR IRQ LATCH NO TIMER INTERRUPT? YES STACK PC, X, A, CCR SET I BIT LOAD PC WITH INTERRUPT VECTOR NO FETCH NEXT INSTRUCTION SWI INSTRUCTION? YES NO RTI INSTRUCTION? YES NO UNSTACK CCR, A, X, PC EXECUTE INSTRUCTION Figure 4-7. Interrupt Flowchart Technical Data 78 MC68HC705J1A — Rev. 4.0 Resets and Interrupts MOTOROLA Technical Data — MC68HC705J1A Section 5. Low-Power Modes 5.1 Contents 5.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 5.3 Exiting Stop and Wait Modes . . . . . . . . . . . . . . . . . . . . . . . . . . 80 5.4 Effects of Stop and Wait Modes . . . . . . . . . . . . . . . . . . . . . . . .81 5.4.1 Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 5.4.2 CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 5.4.3 COP Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 5.4.4 Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 5.4.5 EPROM/OTPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 5.4.6 Data-Retention Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 5.5 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 5.2 Introduction The microcontroller unit (MCU) can enter these low-power standby modes: • Stop mode — The STOP instruction puts the MCU in its lowest power-consumption mode. • Wait mode — The WAIT instruction puts the MCU in an intermediate power-consumption mode. • Halt mode — Halt mode is identical to wait mode, except that an oscillator stabilization delay of 1 to 4064 internal clock cycles occurs when the MCU exits halt mode. The stop-to-wait conversion bit, SWAIT, in the mask option register, enables halt mode. MC68HC705J1A — Rev. 4.0 MOTOROLA Technical Data Low-Power Modes 79 Low-Power Modes Enabling halt mode prevents the computer operating properly (COP) watchdog from being inadvertently turned off by a STOP instruction. • Data-retention mode — In data-retention mode, the MCU retains RAM contents and CPU register contents at VDD voltages as low as 2.0 Vdc. The data-retention feature allows the MCU to remain in a low power-consumption state during which it retains data, but the CPU cannot execute instructions. 5.3 Exiting Stop and Wait Modes The events described in this subsection bring the MCU out of stop mode and load the program counter with the reset vector or with an interrupt vector. Exiting stop mode: • External reset — A logic 0 on the RESET pin resets the MCU, starts the CPU clock, and loads the program counter with the contents of locations $07FE and $07FF. • External interrupt — A high-to-low transition on the IRQ/VPP pin or a low-to-high transition on an enabled port A external interrupt pin starts the CPU clock and loads the program counter with the contents of locations $07FA and $07FB. Exiting wait mode: • External reset — A logic 0 on the RESET pin resets the MCU, starts the CPU clock, and loads the program counter with the contents of locations $07FE and $07FF. • External interrupt — A high-to-low transition on the IRQ/VPP pin or a low-to-high transition on an enabled port A external interrupt pin starts the CPU clock and loads the program counter with the contents of locations $07FA and $07FB. Technical Data 80 MC68HC705J1A — Rev. 4.0 Low-Power Modes MOTOROLA Low-Power Modes Effects of Stop and Wait Modes • COP watchdog reset — A timeout of the COP watchdog resets the MCU, starts the CPU clock, and loads the program counter with the contents of locations $07FE and $07FF. Software can enable timer interrupts so that the MCU periodically can exit wait mode to reset the COP watchdog. • Timer interrupt — Real-time interrupt requests and timer overflow interrupt requests start the MCU clock and load the program counter with the contents of locations $07F8 and $07F9. 5.4 Effects of Stop and Wait Modes The STOP and WAIT instructions have the effects described in this subsection on MCU modules. 5.4.1 Clock Generation The STOP instruction: The STOP instruction disables the internal oscillator, stopping the CPU clock and all peripheral clocks. After exiting stop mode, the CPU clock and all enabled peripheral clocks begin running after the oscillator stabilization delay. NOTE: The oscillator stabilization delay holds the MCU in reset for the first 4064 internal clock cycles. The WAIT instruction: The WAIT instruction disables the CPU clock. After exiting wait mode, the CPU clock and all enabled peripheral clocks immediately begin running. MC68HC705J1A — Rev. 4.0 MOTOROLA Technical Data Low-Power Modes 81 Low-Power Modes 5.4.2 CPU The STOP instruction: • Clears the interrupt mask (I bit) in the condition code register, enabling external interrupts • Disables the CPU clock After exiting stop mode, the CPU clock begins running after the oscillator stabilization delay. After exit from stop mode by external interrupt, the I bit remains clear. After exit from stop mode by reset, the I bit is set. The WAIT instruction: • Clears the interrupt mask (I bit) in the condition code register, enabling interrupts • Disables the CPU clock After exit from wait mode by interrupt, the I bit remains clear. After exit from wait mode by reset, the I bit is set. 5.4.3 COP Watchdog The STOP instruction: NOTE: • Clears the COP watchdog counter • Disables the COP watchdog clock To prevent the STOP instruction from disabling the COP watchdog, program the stop-to-wait conversion bit (SWAIT) in the mask option register to logic 1. After exit from stop mode by external interrupt, the COP watchdog counter immediately begins counting from $0000 and continues counting throughout the oscillator stabilization delay. NOTE: Immediately after exiting stop mode by external interrupt, service the COP to ensure a full COP timeout period. Technical Data 82 MC68HC705J1A — Rev. 4.0 Low-Power Modes MOTOROLA Low-Power Modes Effects of Stop and Wait Modes After exit from stop mode by reset: • The COP watchdog counter immediately begins counting from $0000. • The COP watchdog counter is cleared at the end of the oscillator stabilization delay and begins counting from $0000 again. The WAIT instruction: The WAIT instruction has no effect on the COP watchdog. NOTE: To prevent a COP timeout during wait mode, exit wait mode periodically to service the COP. 5.4.4 Timer The STOP instruction: • Clears the RTIE, TOFE, RTIF, and TOF bits in the timer status and control register, disabling timer interrupt requests and removing any pending timer interrupt requests • Disables the clock to the timer After exiting stop mode by external interrupt, the timer immediately resumes counting from the last value before the STOP instruction and continues counting throughout the oscillator stabilization delay. After exiting stop mode by reset and after the oscillator stabilization delay, the timer resumes operation from its reset state. The WAIT instruction: The WAIT instruction has no effect on the timer. MC68HC705J1A — Rev. 4.0 MOTOROLA Technical Data Low-Power Modes 83 Low-Power Modes 5.4.5 EPROM/OTPROM The STOP instruction: The STOP instruction during erasable, programmable read-only memory (EPROM) programming clears the EPGM bit in the EPROM programming register, removing the programming voltage from the EPROM. The WAIT instruction: The WAIT instruction has no effect on EPROM/one-time programmable read-only memory (OTPROM) operation. 5.4.6 Data-Retention Mode In data-retention mode, the MCU retains random-access memory (RAM) contents and CPU register contents at VDD voltages as low as 2.0 Vdc. The data-retention feature allows the MCU to remain in a low power-consumption state during which it retains data, but the CPU cannot execute instructions. To put the MCU in data-retention mode: 1. Drive the RESET pin to logic 0. 2. Lower the VDD voltage. The RESET pin must remain low continuously during data-retention mode. To take the MCU out of data-retention mode: 1. Return VDD to normal operating voltage. 2. Return the RESET pin to logic 1. Technical Data 84 MC68HC705J1A — Rev. 4.0 Low-Power Modes MOTOROLA Low-Power Modes Timing 5.5 Timing OSC (NOTE 1) tRL RESET IRQ/VPP (NOTE 2) tILIH OSCILLATOR STABILIZATION DELAY IRQ/VPP (NOTE 3) INTERNAL CLOCK INTERNAL ADDRESS BUS $07FE (NOTE 4) $07FE $07FE Notes: 1. Internal clocking from OSC1 pin 2. Edge-triggered external interrupt mask option 3. Edge- and level-triggered external interrupt mask option 4. Reset vector shown as example $07FE $07FE $07FF RESET OR INTERRUPT VECTOR FETCH Figure 5-1. Stop Mode Recovery Timing MC68HC705J1A — Rev. 4.0 MOTOROLA Technical Data Low-Power Modes 85 Low-Power Modes STOP SWAIT BIT SET? YES HALT WAIT CLEAR I BIT IN CCR SET IRQE BIT IN ISCR TURN OFF CPU CLOCK TIMER CLOCK ACTIVE CLEAR I BIT IN CCR SET IRQE BIT IN ISCR TURN OFF CPU CLOCK TIMER CLOCK ACTIVE NO CLEAR I BIT IN CCR SET IRQE BIT IN ISCR CLEAR TOF, RTIF, TOIE, AND RTIE BITS IN TSCR TURN OFF INTERNAL OSCILLATOR YES EXTERNAL RESET? YES EXTERNAL RESET? YES NO EXTERNAL RESET? NO NO YES EXTERNAL INTERRUPT? YES EXTERNAL INTERRUPT? YES NO EXTERNAL INTERRUPT? NO NO YES TIMER INTERRUPT? TURN ON INTERNAL OSCILLATOR RESET STABILIZATION TIMER YES COP RESET? NO TIMER INTERRUPT? NO NO YES END OF STABILIZATION DELAY? YES YES COP RESET? NO NO TURN ON CPU CLOCK 1. LOAD PC WITH RESET VECTOR OR 2. SERVICE INTERRUPT a. SAVE CPU REGISTERS ON STACK b. SET I BIT IN CCR c. LOAD PC WITH INTERRUPT VECTOR Figure 5-2. Stop/Halt/Wait Flowchart Technical Data 86 MC68HC705J1A — Rev. 4.0 Low-Power Modes MOTOROLA Technical Data — MC68HC705J1A Section 6. Parallel Input/Output (I/O) Ports 6.1 Contents 6.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 6.3 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 6.3.1 Port A Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 6.3.2 Data Direction Register A. . . . . . . . . . . . . . . . . . . . . . . . . . . 90 6.3.3 Pulldown Register A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 6.3.4 Port A LED Drive Capability . . . . . . . . . . . . . . . . . . . . . . . . . 92 6.3.5 Port A I/O Pin Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 6.4 Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 6.4.1 Port B Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 6.4.2 Data Direction Register B. . . . . . . . . . . . . . . . . . . . . . . . . . . 93 6.4.3 Pulldown Register B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 6.5 5.0-Volt I/O Port Electrical Characteristics . . . . . . . . . . . . . . . . 95 6.6 3.3-Volt I/O Port Electrical Characteristics . . . . . . . . . . . . . . . . 95 6.2 Introduction Fourteen bidirectional pins form one 8-bit input/output (I/O) port and one 6-bit I/O port. All the bidirectional port pins are programmable as inputs or outputs. NOTE: Connect any unused I/O pins to an appropriate logic level, either VDD or VSS. Although the I/O ports do not require termination for proper operation, termination reduces excess current consumption and the possibility of electrostatic damage. MC68HC705J1A — Rev. 4.0 MOTOROLA Technical Data Parallel Input/Output (I/O) Ports 87 Parallel Input/Output (I/O) Ports Addr. $0000 $0001 Register Name Read: Port A Data Register (PORTA) Write: See page 89. Reset: Read: Port B Data Register (PORTB) Write: See page 92. Reset: Bit 7 6 5 4 3 2 1 Bit 0 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 PB2 PB1 PB0 Unaffected by reset 0 PB5 $0010 $0011 Read: Pulldown Register A (PDRA) Write: See page 91. Reset: Read: Pulldown Register B (PDRB) Write: See page 94. Reset: PB4 PB3 Unaffected by reset Read: Data Direction Register A DDRA7 $0004 (DDRA) Write: See page 90. Reset: 0 Read: Data Direction Register B $0005 (DDRB) Write: See page 93. Reset: 0 0 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0 0 0 0 0 0 0 0 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0 0 0 0 0 0 0 0 0 0 PDIA7 PDIA6 PDIA5 PDIA4 PDIA3 PDIA2 PDIA1 PDIA0 0 0 0 0 0 0 0 0 PDIB5 PDIB4 PDIB3 PDIB2 PDIB1 PDIB0 0 0 0 0 0 0 = Unimplemented Figure 6-1. Parallel I/O Port Register Summary Technical Data 88 MC68HC705J1A — Rev. 4.0 Parallel Input/Output (I/O) Ports MOTOROLA Parallel Input/Output (I/O) Ports Port A 6.3 Port A Port A is an 8-bit bidirectional port. 6.3.1 Port A Data Register The port A data register (PORTA) contains a latch for each port A pin. Address: $0000 Bit 7 6 5 4 3 2 1 Bit 0 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 Read: Write: Reset: Unaffected by reset Figure 6-2. Port A Data Register (PORTA) PA[7:0] — Port A Data Bits These read/write bits are software programmable. Data direction of each port A pin is under the control of the corresponding bit in data direction register A. Reset has no effect on port A data. MC68HC705J1A — Rev. 4.0 MOTOROLA Technical Data Parallel Input/Output (I/O) Ports 89 Parallel Input/Output (I/O) Ports 6.3.2 Data Direction Register A Data direction register A (DDRA) determines whether each port A pin is an input or an output. Address: $0004 Bit 7 6 5 4 3 2 1 Bit 0 DDRA7 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0 0 0 0 0 0 0 0 0 Read: Write: Reset: Figure 6-3. Data Direction Register A (DDRA) DDRA[7:0] — Data Direction Register A Bits These read/write bits control port A data direction. Reset clears DDRA[7:0], configuring all port A pins as inputs. 1 = Corresponding port A pin configured as output 0 = Corresponding port A pin configured as input NOTE: Avoid glitches on port A pins by writing to the port A data register before changing data direction register A bits from 0 to 1. Figure 6-4 shows the I/O logic of port A. READ DDRA WRITE DDRA INTERNAL DATA BUS DDRAx WRITE PORTA 10-mA SINK CAPABILITY (PINS PA4–PA7 ONLY) PAx PAx (PA0–PA3 TO IRQ MODULE) READ PORTA WRITE PDRA 100-µA PULLDOWN PDRAx RESET SWPDI Figure 6-4. Port A I/O Circuitry Technical Data 90 MC68HC705J1A — Rev. 4.0 Parallel Input/Output (I/O) Ports MOTOROLA Parallel Input/Output (I/O) Ports Port A Writing a logic 1 to a DDRA bit enables the output buffer for the corresponding port A pin; a logic 0 disables the output buffer. When bit DDRAx is a logic 1, reading address $0000 reads the PAx data latch. When bit DDRAx is a logic 0, reading address $0000 reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data direction bit. Table 6-1 summarizes the operation of the port A pins. Table 6-1. Port A Pin Operation Accesses to Data Bit Data Direction Bit I/O Pin Mode 0 1 Read Write Input, high-impedance Pin Latch(1) Output Latch Latch 1. Writing affects the data register but does not affect input. 6.3.3 Pulldown Register A Pulldown register A (PDRA) inhibits the pulldown devices on port A pins programmed as inputs. NOTE: If the SWPDI bit in the mask option register is programmed to logic 1, reset initializes all port A pins as inputs with disabled pulldown devices. Address: $0010 Bit 7 6 5 4 3 2 1 Bit 0 Write: PDIA7 PDIA6 PDIA5 PDIA4 PDIA3 PDIA2 PDIA1 PDIA0 Reset: 0 0 0 0 0 0 0 0 Read: = Unimplemented Figure 6-5. Pulldown Register A (PDRA) PDIA[7:0] — Pulldown Inhibit A Bits PDIA[7:0] disable the port A pulldown devices. Reset clears PDIA[7:0]. 1 = Corresponding port A pulldown device disabled 0 = Corresponding port A pulldown device not disabled MC68HC705J1A — Rev. 4.0 MOTOROLA Technical Data Parallel Input/Output (I/O) Ports 91 Parallel Input/Output (I/O) Ports 6.3.4 Port A LED Drive Capability The outputs for the upper four bits of port A (PA4–PA7) can drive light-emitting diodes (LEDs). PA4–PA7 can sink approximately 10 mA of current to VSS. 6.3.5 Port A I/O Pin Interrupts If the PIRQ bit in the mask option register is programmed to logic 1, PA0–PA3 pins function as external interrupt pins. See Section 8. External Interrupt Module (IRQ). 6.4 Port B Port B is a 6-bit bidirectional port. 6.4.1 Port B Data Register The port B data register (PORTB) contains a latch for each port B pin. Address: Read: $0001 Bit 7 6 0 0 5 4 3 2 1 Bit 0 PB5 PB4 PB3 PB2 PB1 PB0 Write: Reset: Unaffected by reset = Unimplemented Figure 6-6. Port B Data Register (PORTB) PB[5:0] — Port B Data Bits These read/write bits are software programmable. Data direction of each port B pin is under the control of the corresponding bit in data direction register B. Reset has no effect on port B data. Technical Data 92 MC68HC705J1A — Rev. 4.0 Parallel Input/Output (I/O) Ports MOTOROLA Parallel Input/Output (I/O) Ports Port B 6.4.2 Data Direction Register B Data direction register B (DDRB) determines whether each port B pin is an input or an output. Address: Read: $0005 Bit 7 6 0 0 5 4 3 2 1 Bit 0 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0 0 0 0 0 0 0 Write: Reset: 0 0 = Unimplemented Figure 6-7. Data Direction Register B (DDRB) DDRB[5:0] — Data Direction Register B Bits These read/write bits control port B data direction. Reset clears DDRB[5:0], configuring all port B pins as inputs. 1 = Corresponding port B pin configured as output 0 = Corresponding port B pin configured as input NOTE: Avoid glitches on port B pins by writing to the port B data register before changing data direction register B bits from 0 to 1. Figure 6-8 shows the I/O logic of port B. READ DDRB WRITE DDRB INTERNAL DATA BUS DDRBx WRITE PORTB PBx PBx READ PORTB WRITE PDRB 100-µA PULLDOWN PDRBx RESET SWPDI Figure 6-8. Port B I/O Circuitry MC68HC705J1A — Rev. 4.0 MOTOROLA Technical Data Parallel Input/Output (I/O) Ports 93 Parallel Input/Output (I/O) Ports Writing a logic 1 to a DDRB bit enables the output buffer for the corresponding port B pin; a logic 0 disables the output buffer. When bit DDRBx is a logic 1, reading address $0001 reads the PBx data latch. When bit DDRBx is a logic 0, reading address $0001 reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data direction bit. Table 6-2 summarizes the operation of the port B pins. Table 6-2. Port B Pin Operation Data Direction Bit Accesses to Data Bit I/O Pin Mode Read Write 0 Input, high-impedance Pin Latch(1) 1 Output Latch Latch 1. Writing affects the data register, but does not affect input. 6.4.3 Pulldown Register B Pulldown register B (PDRB) inhibits the pulldown devices on port B pins programmed as inputs. NOTE: If the SWPDI bit in the mask option register is programmed to logic 1, reset initializes all port B pins as inputs with disabled pulldown devices. Address: $0011 Bit 7 6 5 4 3 2 1 Bit 0 Write: PDIB5 PDIB4 PDIB3 PDIB2 PDIB1 PDIB0 Reset: 0 0 0 0 0 0 Read: = Unimplemented Figure 6-9. Pulldown Register B (PDRB) PDIB[7:0] — Pulldown Inhibit B Bits PDIB[7:0] disable the port B pulldown devices. Reset clears PDIB[7:0]. 1 = Corresponding port B pulldown device disabled 0 = Corresponding port B pulldown device not disabled Technical Data 94 MC68HC705J1A — Rev. 4.0 Parallel Input/Output (I/O) Ports MOTOROLA Parallel Input/Output (I/O) Ports 5.0-Volt I/O Port Electrical Characteristics 6.5 5.0-Volt I/O Port Electrical Characteristics Characteristic(1) Symbol Min Typ(2) Max Unit Current drain per pin excluding PA4–PA7 I — 25 — mA Output high voltage (ILoad = –0.8 mA) PA0–PA7, PB0–PB5 VOH VDD –0.8 — — V VOL — — — — 0.4 0.4 V Input high voltage PA0–PA7, PB0–PB5 VIH 0.7 x VDD — VDD V Input low voltage PA0–PA7, PB0–PB5 VIL VSS — 0.2 x VDD V I/O ports hi-z leakage current PA0–PA7, PB0–PB5 (without individual pulldown activated) IIL — 0.2 ±1 µA Input pulldown current PA0–PA7, PB0–PB5 (with individual pulldown activated) IIL 35 80 200 µA Symbol Min Typ(2) Max Unit Current drain per pin excluding PA4–PA7 I — 25 — mA Output high voltage (ILoad = –0.2 mA) PA0–PA7, PB0–PB5 VOH VDD –0.3 — — V Output low voltage (ILoad = 0.4 mA) PA0–PA3, PB0–PB5 (ILoad = 5.0 mA) PA4–PA7 VOL — — — — 0.3 0.3 V Input high voltage PA0–PA7, PB0–PB5 VIH 0.7 x VDD — VDD V Input low voltage PA0–PA7, PB0–PB5 VIL VSS — 0.2 x VDD V I/O ports hi-z leakage current PA0–PA7, PB0–PB5 (without individual pulldown activated) IIL — 0.1 ±1 µA Input pulldown current PA0–PA7, PB0–PB5 (with individual pulldown activated) IIL 12 30 100 µA Output low voltage (ILoad = 1.6 mA) PA0–PA3, PB0–PB5 (ILoad = 10.0 mA) PA4–PA7 1. V DD = 5.0 Vdc ± 10%, V SS = 0 Vdc, TA = –40°C to +105°C, unless otherwise noted 2. Typical values reflect average measurements at midpoint of voltage range, 25°C. 6.6 3.3-Volt I/O Port Electrical Characteristics Characteristic(1) 1. V DD = 3.3 Vdc ± 10%, V SS= 0 Vdc, TA = –40°C to +105°C, unless otherwise noted 2. Typical values reflect average measurements at midpoint of voltage range, 25°C. MC68HC705J1A — Rev. 4.0 MOTOROLA Technical Data Parallel Input/Output (I/O) Ports 95 Parallel Input/Output (I/O) Ports Technical Data 96 MC68HC705J1A — Rev. 4.0 Parallel Input/Output (I/O) Ports MOTOROLA Technical Data — MC68HC705J1A Section 7. Computer Operating Properly (COP) Module 7.1 Contents 7.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 7.3 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 7.3.1 COP Watchdog Timeout . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 7.3.2 COP Watchdog Timeout Period . . . . . . . . . . . . . . . . . . . . . . 98 7.3.3 Clearing the COP Watchdog . . . . . . . . . . . . . . . . . . . . . . . .98 7.4 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 7.5 COP Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99 7.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 7.6.1 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100 7.6.2 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100 7.2 Introduction The computer operating properly (COP) watchdog resets the microcontroller (MCU) in case of software failure. Software that is operating properly periodically services the COP watchdog and prevents COP reset. The COP watchdog function is programmable by the COPEN bit in the mask option register. Features include: • Protection from runaway software • Wait and halt mode operation MC68HC705J1A — Rev. 4.0 MOTOROLA Technical Data Computer Operating Properly (COP) Module 97 Computer Operating Properly (COP) Module 7.3 Operation Operation of the COP is described in this subsection. 7.3.1 COP Watchdog Timeout Four counter stages at the end of the timer make up the COP watchdog. The COP resets the MCU if the timeout period occurs before the COP watchdog timer is cleared by application software and the IRQ/VPP pin voltage is between VSS and VDD. Periodically clearing the counter starts a new timeout period and prevents COP reset. A COP watchdog timeout indicates that the software is not executing instructions in the correct sequence. NOTE: The internal clock drives the COP watchdog. Therefore, the COP watchdog cannot generate a reset for errors that cause the internal clock to stop. The COP watchdog depends on a power supply voltage at or above a minimum specification and is not guaranteed to protect against brownout. 7.3.2 COP Watchdog Timeout Period The COP watchdog timer function is implemented by dividing the output of the real-time interrupt circuit (RTI) by eight. The RTI select bits in the timer status and control register control RTI output, and the selected output drives the COP watchdog. See timer status and control register in Section 9. Multifunction Timer Module. NOTE: The minimum COP timeout period is seven times the RTI period. The COP is cleared asynchronously with the value in the RTI divider; hence, the COP timeout period will vary between 7x and 8x the RTI period. 7.3.3 Clearing the COP Watchdog To clear the COP watchdog and prevent a COP reset, write a logic 0 to bit 0 (COPC) of the COP register at location $07F0 (see Figure 7-1). Technical Data 98 MC68HC705J1A — Rev. 4.0 Computer Operating Properly (COP) Module MOTOROLA Computer Operating Properly (COP) Module Interrupts Clearing the COP bit disables the COP watchdog timer regardless of the IRQ/VPP pin voltage. If the main program executes within the COP timeout period, the clearing routine should be executed only once. If the main program takes longer than the COP timeout period, the clearing routine must be executed more than once. NOTE: Place the clearing routine in the main program and not in an interrupt routine. Clearing the COP watchdog in an interrupt routine might prevent COP watchdog timeouts even though the main program is not operating properly. 7.4 Interrupts The COP watchdog does not generate interrupts. 7.5 COP Register The COP register (COPR) is a write-only register that returns the contents of EPROM location $07F0 when read. Address: $07F0 Bit 7 6 5 4 3 2 1 Bit 0 Read: Write: COPC Reset: 0 = Unimplemented Figure 7-1. COP Register (COPR) COPC — COP Clear Bit This write-only bit resets the COP watchdog. Reading address $07F0 returns undefined results. MC68HC705J1A — Rev. 4.0 MOTOROLA Technical Data Computer Operating Properly (COP) Module 99 Computer Operating Properly (COP) Module 7.6 Low-Power Modes The STOP and WAIT instructions have these effects on the COP watchdog. 7.6.1 Stop Mode The STOP instruction clears the COP watchdog counter and disables the clock to the COP watchdog. NOTE: To prevent the STOP instruction from disabling the COP watchdog, program the stop-to-wait conversion bit (SWAIT) in the mask option register to logic 1. Upon exit from stop mode by external reset: • The counter begins counting from $0000. • The counter is cleared again after the oscillator stabilization delay and begins counting from $0000 again. Upon exit from stop mode by external interrupt: NOTE: • The counter begins counting from $0000. • The counter is not cleared again after the oscillator stabilization delay and continues counting throughout the oscillator stabilization delay. Immediately after exiting stop mode by external interrupt, service the COP to ensure a full COP timeout period. 7.6.2 Wait Mode The WAIT instruction has no effect on the COP watchdog. NOTE: To prevent a COP timeout during wait mode, exit wait mode periodically to service the COP. Technical Data 100 MC68HC705J1A — Rev. 4.0 Computer Operating Properly (COP) Module MOTOROLA Technical Data — MC68HC705J1A Section 8. External Interrupt Module (IRQ) 8.1 Contents 8.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 8.3 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 8.3.1 IRQ/VPP Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 8.3.2 Optional External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . 104 8.4 IRQ Status and Control Register . . . . . . . . . . . . . . . . . . . . . . 106 8.5 External Interrupt Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 8.5.1 5.0-Volt External Interrupt Timing Characteristics . . . . . . . 107 8.5.2 3.3-Volt External Interrupt Timing Characteristics . . . . . . . 107 8.2 Introduction The external interrupt (IRQ) module provides asynchronous external interrupts to the CPU. These sources can generate external interrupts: • IRQ/VPP pin • PA0–PA3 pins Features include: • Dedicated external interrupt pin (IRQ/VPP) • Selectable interrupt on four input/output (I/O) pins (PA0–PA3) • Programmable edge-only or edge- and level-interrupt sensitivity MC68HC705J1A — Rev. 4.0 MOTOROLA Technical Data External Interrupt Module (IRQ) 101 External Interrupt Module (IRQ) 8.3 Operation The interrupt request/programming voltage pin (IRQ/VPP) and port A pins 0–3 (PA0–PA3) provide external interrupts. The PIRQ bit in the mask option register (MOR) enables PA0–PA3 as IRQ interrupt sources, which are combined into a single ORing function to be latched by the IRQ latch. Figure 8-1 shows the structure of the IRQ module. After completing its current instruction, the CPU tests the IRQ latch. If the IRQ latch is set, the CPU then tests the I bit in the condition code register and the IRQE bit in the IRQ status and control register. If the I bit is clear and the IRQE bit is set, the CPU then begins the interrupt sequence. This interrupt is serviced by the interrupt service routine located at $07FA and $07FB. The CPU clears the IRQ latch while it fetches the interrupt vector, so that another external interrupt request can be latched during the interrupt service routine. As soon as the I bit is cleared during the return from interrupt, the CPU can recognize the new interrupt request. Figure 8-2 shows the sequence of events caused by an interrupt. TO BIH & BIL INSTRUCTION PROCESSING IRQ LEVEL-SENSITIVE TRIGGER (MOR LEVEL BIT) IRQF VDD EXTERNAL INTERRUPT REQUEST D IRQ Q LATCH CK PA3 PA2 PA1 PA0 IRQE CLR PIRQ (MOR) RESET IRQ VECTOR FETCH IRQR Figure 8-1. IRQ Module Block Diagram Technical Data 102 MC68HC705J1A — Rev. 4.0 External Interrupt Module (IRQ) MOTOROLA External Interrupt Module (IRQ) Operation FROM RESET YES I BIT SET? NO EXTERNAL INTERRUPT? YES CLEAR IRQ LATCH NO TIMER INTERRUPT? YES STACK PCL, PCH, X, A, CCR SET I BIT LOAD PC WITH INTERRUPT VECTOR NO FETCH NEXT INSTRUCTION SWI INSTRUCTION? YES NO RTI INSTRUCTION? NO YES UNSTACK CCR, A, X, PCH, PCL EXECUTE INSTRUCTION Figure 8-2. Interrupt Flowchart MC68HC705J1A — Rev. 4.0 MOTOROLA Technical Data External Interrupt Module (IRQ) 103 External Interrupt Module (IRQ) 8.3.1 IRQ/VPP Pin An interrupt signal on the IRQ/VPP pin latches an external interrupt request. The LEVEL bit in the mask option register provides negative edge-sensitive triggering or both negative edge-sensitive and low level-sensitive triggering for the interrupt function. If edge- and level-sensitive triggering is selected, a falling edge or a low level on the IRQ/VPP pin latches an external interrupt request. Edge- and level-sensitive triggering allows the use of multiple wired-OR external interrupt sources. An external interrupt request is latched as long as any source is holding the IRQ/VPP pin low. If level-sensitive triggering is selected, the IRQ/VPP input requires an external resistor to VDD for wired-OR operation. If the IRQ/VPP pin is not used, it must be tied to the VDD supply. If edge-sensitive-only triggering is selected, a falling edge on the IRQ/VPP pin latches an external interrupt request. A subsequent external interrupt request can be latched only after the voltage level on the IRQ/VPP pin returns to logic 1 and then falls again to logic 0. The IRQ/VPP pin contains an internal Schmitt trigger as part of its input to improve noise immunity. The voltage on this pin can affect the mode of operation and should not exceed VDD. 8.3.2 Optional External Interrupts The inputs for the lower four bits of port A (PA0–PA3) can be connected to the IRQ pin input of the CPU if enabled by the PIRQ bit in the mask option register. This capability allows keyboard scan applications where the transitions or levels on the I/O pins will behave the same as the IRQ/VPP pin except for the inverted phase (logic 1, rising edge). The active state of the IRQ/VPP pin is a logic 0 (falling edge). The PA0–PA3 pins are selected as a group to function as IRQ interrupts and are enabled by the IRQE bit in the IRQ status and control register. The PA0–PA3 pins can be positive-edge triggered only or positive-edge and high-level triggered. Technical Data 104 MC68HC705J1A — Rev. 4.0 External Interrupt Module (IRQ) MOTOROLA External Interrupt Module (IRQ) Operation If edge- and level-sensitive triggering is selected, a rising edge or a high level on a PA0–PA3 pin latches an external interrupt request. Edge- and level-sensitive triggering allows the use of multiple wired-OR external interrupt sources. As long as any source is holding a PA0–PA3 pin high, an external interrupt request is latched, and the CPU continues to execute the interrupt service routine. If edge-sensitive only triggering is selected, a rising edge on a PA0–PA3 pin latches an external interrupt request. A subsequent external interrupt request can be latched only after the voltage level of the previous interrupt signal returns to logic 0 and then rises again to logic 1. NOTE: The branch if interrupt pin is high (BIH) and branch if interrupt pin is low (BIL) instructions apply only to the level on the IRQ/VPP pin itself and not to the output of the logic OR function with the PA0–PA3 pins. The state of the individual port A pins can be checked by reading the appropriate port A pins as inputs. Enabled PA0–PA3 pins cause an IRQ interrupt regardless of whether these pins are configured as inputs or outputs. The IRQ pin has an internal Schmitt trigger. The optional external interrupts (PA0–PA3) do not have internal Schmitt triggers. The interrupt mask bit (I) in the condition code register (CCR) disables all maskable interrupt requests, including external interrupt requests. MC68HC705J1A — Rev. 4.0 MOTOROLA Technical Data External Interrupt Module (IRQ) 105 External Interrupt Module (IRQ) 8.4 IRQ Status and Control Register The IRQ status and control register (ISCR) controls and monitors operation of the IRQ module. All unused bits in the ISCR read as logic 0s. The IRQF bit is cleared and the IRQE bit is set by reset. Address: $000A Bit 7 Read: 6 5 4 3 2 1 Bit 0 0 0 0 IRQF 0 0 0 IRQE R Write: Reset: 1 0 0 IRQR 0 = Unimplemented 0 0 0 0 R = Reserved Figure 8-3. IRQ Status and Control Register (ISCR) IRQR — Interrupt Request Reset Bit This write-only bit clears the external interrupt request flag. 1 = Clears external interrupt and IRQF bit 0 = No effect on external interrupt and IRQF bit IRQF — External Interrupt Request Flag The external interrupt request flag is a clearable, read-only bit that is set when an external interrupt request is pending. Reset clears the IRQF bit. 1 = External interrupt request pending 0 = No external interrupt request pending IRQE — External Interrupt Request Enable Bit This read/write bit enables external interrupts. Reset sets the IRQE bit. 1 = External interrupt requests enabled 0 = External interrupt requests disabled The STOP and WAIT instructions set the IRQE bit so that an external interrupt can bring the MCU out of these low-power modes. In addition, reset sets the I bit which masks all interrupt sources. Technical Data 106 MC68HC705J1A — Rev. 4.0 External Interrupt Module (IRQ) MOTOROLA External Interrupt Module (IRQ) External Interrupt Timing 8.5 External Interrupt Timing tILIL tILIH IRQ PIN tILIH IRQ1 . . . IRQn IRQ (INTERNAL) Figure 8-4. External Interrupt Timing 8.5.1 5.0-Volt External Interrupt Timing Characteristics Characteristic(1) Symbol Min Max Unit IRQ interrupt pulse width low (edge-triggered) tILIH 1.5 — tcyc(2) IRQ interrupt pulse width (edge- and level-triggered) tILIH 1.5 Note(3) tcyc PA0–PA3 interrupt pulse width high (edge-triggered) tILIL 1.5 — tcyc PA0–PA3 interrupt pulse width high (edge- and level-triggered) tILIH 1.5 Note(3) tcyc 1. V DD = 5.0 Vdc ± 10%, V SS = 0 Vdc, TA = –40°C to +105°C, unless otherwise noted 2. tcyc = 1/fop; fop = fosc/2. 3. The minimum, tILIL, should not be less than the number of interrupt service routine cycles plus 19 tcyc. 8.5.2 3.3-Volt External Interrupt Timing Characteristics Characteristic(1) Symbol Min Max Unit IRQ interrupt pulse width low (edge-triggered) tILIH 1.5 — tcyc(2) IRQ interrupt pulse width (edge- and level-triggered) tILIH 1.5 Note(3) tcyc PA0–PA3 interrupt pulse width high (edge-triggered) tILIL 1.5 — tcyc PA0–PA3 interrupt pulse width high (edge- and level-triggered) tILIH 1.5 Note(3) tcyc 1. V DD = 3.3 Vdc ± 10%, V SS = 0 Vdc, TA = –40°C to +105°C, unless otherwise noted 2. tcyc = 1/fop; fop = fosc/2. 3. The minimum, tILIL, should not be less than the number of interrupt service routine cycles plus 19 tcyc. MC68HC705J1A — Rev. 4.0 MOTOROLA Technical Data External Interrupt Module (IRQ) 107 External Interrupt Module (IRQ) Technical Data 108 MC68HC705J1A — Rev. 4.0 External Interrupt Module (IRQ) MOTOROLA Technical Data — MC68HC705J1A Section 9. Multifunction Timer Module 9.1 Contents 9.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 9.3 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 9.4 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 9.5 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 9.5.1 Timer Status and Control Register . . . . . . . . . . . . . . . . . . .112 9.5.2 Timer Counter Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 9.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 9.6.1 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115 9.6.2 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115 9.2 Introduction The multifunction timer provides a timing reference with programmable real-time interrupt (RTI) capability. Figure 9-1 shows the timer organization. Features include: • Timer overflow • Four selectable interrupt rates • Computer operating properly (COP) watchdog timer MC68HC705J1A — Rev. 4.0 MOTOROLA Technical Data Multifunction Timer Module 109 Multifunction Timer Module RESET OVERFLOW ÷ 4 TIMER COUNTER REGISTER INTERNAL CLOCK (XTAL ÷ 2) BITS [0:7] OF 15-STAGE RIPPLE COUNTER INTERNAL DATA BUS RESET RTIFR TOFR RTIE TOIE RTIF TOF INTERRUPT REQUEST RT0 RT1 TIMER STATUS/CONTROL REGISTER RESET CLEAR COP TIMER RTI RATE SELECT ÷ 2 ÷ 2 ÷ 2 ÷ 2 ÷ 2 ÷ 2 ÷ 2 BITS [8:14] OF 15-STAGE RIPPLE COUNTER ÷ 8 S Q COP RESET R RESET Figure 9-1. Multifunction Timer Block Diagram Technical Data 110 MC68HC705J1A — Rev. 4.0 Multifunction Timer Module MOTOROLA Multifunction Timer Module Operation Addr. $0008 $0009 Register Name Read: Timer Status and Control Register (TSCR) Write: See page 112. Reset: Timer Counter Register Read: (TCR) Write: See page 114. Reset: Bit 7 6 TOF RTIF 5 4 TOIE RTIE 3 2 0 0 TOFR RTIFR 1 Bit 0 RT1 RT0 0 0 0 0 0 0 1 1 TMR7 TMR6 TMR5 TMR4 TMR3 TMR2 TMR1 TMR0 0 0 0 0 0 0 0 0 = Unimplemented Figure 9-2. I/O Register Summary 9.3 Operation A 15-stage ripple counter, preceded by a prescaler that divides the internal clock signal by four, provides the timing reference for the timer functions. The value of the first eight timer stages can be read at any time by accessing the timer counter register at address $0009. A timer overflow function at the eighth stage allows a timer interrupt every 1024 internal clock cycles. The next four stages lead to the real-time interrupt (RTI) circuit. The RT1 and RT0 bits in the timer status and control register at address $0008 allow a timer interrupt every 16,384, 32,768, 65,536, or 131,072 clock cycles. The last four stages drive the selectable COP system. For information on the COP, refer to the Section 7. Computer Operating Properly (COP) Module. MC68HC705J1A — Rev. 4.0 MOTOROLA Technical Data Multifunction Timer Module 111 Multifunction Timer Module 9.4 Interrupts These timer sources can generate interrupts: • Timer overflow flag (TOF) — The TOF bit is set when the first eight stages of the counter roll over from $FF to $00. The timer overflow interrupt enable bit, TOIE, enables TOF interrupt requests. • Real-time interrupt flag (RTIF) — The RTIF bit is set when the selected RTI output becomes active. The real-time interrupt enable bit, RTIE, enables RTIF interrupt requests. 9.5 I/O Registers These registers control and monitor the timer operation: • Timer status and control register (TSCR) • Timer counter register (TCR) 9.5.1 Timer Status and Control Register The read/write timer status and control register (TSCR) performs these functions: • Flags timer interrupts • Enables timer interrupts • Resets timer interrupt flags • Selects real-time interrupt rates Address: Read: $0008 Bit 7 6 TOF RTIF 5 4 TOIE RTIE Write: Reset: 0 0 0 0 3 2 0 0 TOFR RTIFR 0 0 1 Bit 0 RT1 RT0 1 1 = Unimplemented Figure 9-3. Timer Status and Control Register (TSCR) Technical Data 112 MC68HC705J1A — Rev. 4.0 Multifunction Timer Module MOTOROLA Multifunction Timer Module I/O Registers TOF — Timer Overflow Flag This read-only flag becomes set when the first eight stages of the counter roll over from $FF to $00. TOF generates a timer overflow interrupt request if TOIE is also set. Clear TOF by writing a logic 1 to the TOFR bit. Writing to TOF has no effect. Reset clears TOF. RTIF — Real-Time Interrupt Flag This read-only flag becomes set when the selected RTI output becomes active. RTIF generates a real-time interrupt request if RTIE is also set. Clear RTIF by writing a logic 1 to the RTIFR bit. Writing to RTIF has no effect. Reset clears RTIF. TOIE — Timer Overflow Interrupt Enable Bit This read/write bit enables timer overflow interrupts. Reset clears TOIE. 1 = Timer overflow interrupts enabled 0 = Timer overflow interrupts disabled RTIE — Real-Time Interrupt Enable Bit This read/write bit enables real-time interrupts. Reset clears RTIE. 1 = Real-time interrupts enabled 0 = Real-time interrupts disabled TOFR — Timer Overflow Flag Reset Bit Writing a logic 1 to this write-only bit clears the TOF bit. TOFR always reads as logic 0. Reset clears TOFR. RTIFR — Real-Time Interrupt Flag Reset Bit Writing a logic 1 to this write-only bit clears the RTIF bit. RTIFR always reads as logic 0. Reset clears RTIFR. RT1 and RT0 — Real-Time Interrupt Select Bits These read/write bits select one of four real-time interrupt rates, as shown in Table 9-1. Because the selected RTI output drives the COP watchdog, changing the real-time interrupt rate also changes the counting rate of the COP watchdog. Reset sets RT1 and RT0. NOTE: Changing RT1 and RT0 when a COP timeout is imminent can cause a real-time interrupt request to be missed or an additional real-time MC68HC705J1A — Rev. 4.0 MOTOROLA Technical Data Multifunction Timer Module 113 Multifunction Timer Module interrupt request to be generated. To prevent this occurrence, clear the COP timer before changing RT1 and RT0. Table 9-1. Real-Time Interrupt Rate Selection RT1:RT0 Number of Cycles to RTI RTI Period(1) Number of Cycles to COP Reset COP Timeout Period(1) 00 214 = 16,384 8.2 ms 217 = 131,072 65.5 ms 01 215 = 32,768 16.4 ms 218 = 262,144 131.1 ms 10 216 = 65,536 32.8 ms 219 = 524,288 262.1 ms 11 217 = 131,072 65.5 ms 220 = 1,048,576 524.3 ms 1. At 2-MHz bus, 4-MHz XTAL, 0.5 µs per cycle 9.5.2 Timer Counter Register A 15-stage ripple counter is the core of the timer. The value of the first eight stages is readable at any time from the read-only timer counter register (TCR) shown in Figure 9-4. Address: Read: $0009 Bit 7 6 5 4 3 2 1 Bit 0 TMR7 TMR6 TMR5 TMR4 TMR3 TMR2 TMR1 TMR0 0 0 0 0 0 0 0 0 Write: Reset: = Unimplemented Figure 9-4. Timer Counter Register (TCR) Power-on clears the entire counter chain and the internal clock begins clocking the counter. After 4064 cycles (or 16 cycles if the SOSCD bit in the mask option register is set), the power-on reset circuit is released, clearing the counter again and allowing the MCU to come out of reset. A timer overflow function at the eighth counter stage allows a timer interrupt every 1024 internal clock cycles. Technical Data 114 MC68HC705J1A — Rev. 4.0 Multifunction Timer Module MOTOROLA Multifunction Timer Module Low-Power Modes 9.6 Low-Power Modes The STOP and WAIT instructions put the MCU in low power-consumption standby states. 9.6.1 Stop Mode The STOP instruction has these effects on the timer: • Clears the timer counter • Clears interrupt flags (TOF and RTIF) and interrupt enable bits (TOFE and RTIE) in TSCR, removing any pending timer interrupt requests and disabling further timer interrupts. 9.6.2 Wait Mode The timer remains active after a WAIT instruction. Any enabled timer interrupt request can bring the MCU out of wait mode. MC68HC705J1A — Rev. 4.0 MOTOROLA Technical Data Multifunction Timer Module 115 Multifunction Timer Module Technical Data 116 MC68HC705J1A — Rev. 4.0 Multifunction Timer Module MOTOROLA Technical Data — MC68HC705J1A Section 10. Electrical Specifications 10.1 Contents 10.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 10.3 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 10.4 Operating Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . 119 10.5 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 10.6 Power Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 10.7 5.0-Volt DC Electrical Characteristics. . . . . . . . . . . . . . . . . . .121 10.8 3.3-Volt DC Electrical Characteristics . . . . . . . . . . . . . . . . . . 122 10.9 Driver Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 10.10 Typical Supply Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 10.11 EPROM Programming Characteristics . . . . . . . . . . . . . . . . . . 126 10.12 5.0-Volt Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 10.13 3.3-Volt Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 10.2 Introduction This section contains electrical and timing specifications. MC68HC705J1A — Rev. 4.0 MOTOROLA Technical Data Electrical Specifications 117 Electrical Specifications 10.3 Maximum Ratings Maximum ratings are the extreme limits to which the MCU can be exposed without permanently damaging it. The MCU contains circuitry to protect the inputs against damage from high static voltages; however, do not apply voltages higher than those shown in the table here. Keep VIn and VOut within the range VSS ≤ (VIn or VOut) ≤ VDD. Connect unused inputs to the appropriate voltage level, either VSS or VDD. Rating(1) Symbol Value Unit VDD –0.3 to +7.0 V I 25 mA Input voltage VIn VSS – 0.3 to VDD + 0.3 V IRQ/VPP pin VPP VSS – 0.3 to 2 x VDD + 0.3 V Storage temperature range TSTG –65 to +150 °C Supply voltage Current drain per pin (excluding VDD, VSS, and PA4–PA7) 1. Voltages are referenced to VSS. NOTE: This device is not guaranteed to operate properly at the maximum ratings. Refer to 10.7 5.0-Volt DC Electrical Characteristics and 10.8 3.3-Volt DC Electrical Characteristics for guaranteed operating conditions. Technical Data 118 MC68HC705J1A — Rev. 4.0 Electrical Specifications MOTOROLA Electrical Specifications Operating Temperature Range 10.4 Operating Temperature Range Symbol Value (TL to TH) Unit MC68HC705J1AP(1), DW(2), S(3) TA 0 to 70 °C MC68HC705J1AC(4)P, CDW, CS TA –40 to +85 °C MC68HC705J1AV(5)P, VDW, VS TA –40 to +105 °C Package Type 1. P = plastic dual in-line package (PDIP) 2. DW = small outline integrated circuit (SOIC) 3. S = ceramic DIP (cerdip) 4. C = extended temperature range 5. V = automotive temperature range 10.5 Thermal Characteristics Characteristic Thermal resistance MC68HC705J1AP(1) MC68HC705J1ADW (2) MC68HC705J1AS(3) Symbol Value Unit θJA 60 °C/W 1. P = plastic dual in-line package (PDIP) 2. DW = small outline integrated circuit (SOIC) 3. S = ceramic DIP (cerdip) MC68HC705J1A — Rev. 4.0 MOTOROLA Technical Data Electrical Specifications 119 Electrical Specifications 10.6 Power Considerations The average chip junction temperature, TJ, in °C can be obtained from: TJ = TA + (PD x θJA) (1) Where: TA = ambient temperature in °C θJA = package thermal resistance, junction to ambient in °C/W PD = PINT + PI/O PINT = ICC × VCC = chip internal power dissipation PI/O = power dissipation on input and output pins (user-determined) For most applications, PI/O < PINT and can be neglected. Ignoring PI/O, the relationship between PD and TJ is approximately: K PD = (2) TJ + 273°C Solving equations (1) and (2) for K gives: = PD x (TA + 273°C) + θJA x (PD)2 (3) where K is a constant pertaining to the particular part. K can be determined from equation (3) by measuring PD (at equilibrium) for a known TA. Using this value of K, the values of PD and TJ can be obtained by solving equations (1) and (2) iteratively for any value of TA. Technical Data 120 MC68HC705J1A — Rev. 4.0 Electrical Specifications MOTOROLA Electrical Specifications 5.0-Volt DC Electrical Characteristics 10.7 5.0-Volt DC Electrical Characteristics Characteristic(1) Symbol Min Typ(2) Max Unit VOL VOH — VDD – 0.1 — — 0.1 — V Output high voltage (ILoad = –0.8 mA) PA0–PA7, PB0–PB5 VOH VDD – 0.8 — — V Output low voltage (ILoad = 1.6 mA) PA0–PA3, PB0–PB5 (ILoad = 10.0 mA) PA4–PA7 VOL — — 0.4 0.4 V Input high voltage PA0–PA7, PB0–PB5, IRQ/VPP, RESET, OSC1 VIH 0.7 × VDD — VDD V Input low voltage PA0–PA7, PB0–PB5, IRQ/VPP, RESET, OSC1 VIL VSS — 0.2 × VDD V — — 3.5 0.45 6.0 2.75 mA mA — — 0.2 2.0 10 20 µA µA IIL — 0.2 ±1 µA IIL 35 80 200 µA IIL –15 –35 –85 µA IIn — 0.2 ±1 µA COut CIn — — — — 12 8 pF Rosc 1.0 2.0 3.0 MΩ Output voltage ILoad = 10.0 µA ILoad = –10.0 µA Supply current Run mode (3) Wait mode(4) Stop mode(5) 25°C –40 to 105°C I/O ports hi-z leakage current PA0–PA7, PB0–PB5 (without individual pulldown activated) Input pulldown current PA0–PA7, PB0–PB5 (with individual pulldown activated) Input pullup current RESET Input current(6) RESET, IRQ/VPP, OSC1 Capacitance Ports (as inputs or outputs) RESET, IRQ/VPP, OSC1, OSC2 Crystal/ceramic resonator oscillator mode internal resistor OSC1 to OSC2(7) IDD 1. V DD = 5.0 Vdc ± 10%, V SS = 0 Vdc, TA = –40°C to +105°C, unless otherwise noted 2. Typical values at midpoint of voltage range, 25°C only 3. Run mode IDD is measured using external square wave clock source (fosc = 4.2 MHz); all inputs 0.2 V from rail; no dc loads; less than 50 pF on all outputs; CL = 20 pF on OSC2 4. Wait mode IDD: only timer system active. Wait mode is affected linearly by OSC2 capacitance. Wait mode is measured with all ports configured as inputs; VIL = 0.2 V; VIH = VDD – 0.2 V. Wait mode IDD is measured using external square wave clock source (fosc = 4.2 MHz); all inputs 0.2 V from rail; no dc loads; less than 50 pF on all outputs; CL = 20 pF on OSC2. 5. Stop mode IDD is measured with OSC1 = VSS. Stop mode IDD is measured with all ports configured as inputs; VIL = 0.2 V; VIH = V DD – 0.2 V 6. Only input high current rated to +1 µA on RESET. 7. The Rosc value selected for RC oscillator versions of this device is unspecified. See Appendix C. MC68HSR705J1A for additional information. MC68HC705J1A — Rev. 4.0 MOTOROLA Technical Data Electrical Specifications 121 Electrical Specifications 10.8 3.3-Volt DC Electrical Characteristics Characteristic(1) Symbol Min Typ(2) Max Unit VOL VOH — VDD– 0.1 — — 0.1 — V Output high voltage (ILoad = –0.2 mA) PA0–PA7, PB0–PB5 VOH VDD – 0.3 — — V Output low voltage (ILoad = 0.4 mA) PA0–PA3, PB0–PB5 (ILoad = 5.0 mA) PA4–PA7 VOL — — 0.3 0.3 V Input high voltage PA0–PA7, PB0–PB5, IRQ/VPP, RESET, OSC1 VIH 0.7 × VDD — VDD V Input low voltage PA0–PA7, PB0–PB5, IRQ/VPP, RESET, OSC1 VIL VSS — 0.2 × VDD V — — 1.2 0.25 4.0 1.5 mA mA — — 0.1 1.0 5 10 µA µA IIL — 0.1 ±1 µA IIL 12 30 100 µA IIL –10 –25 –45 µA IIn — 0.1 ±1 µA COut CIn — — — — 12 8 pF Rosc 1.0 2.0 3.0 MΩ Output voltage ILoad = 10.0 µA ILoad = –10.0 µA Supply current Run Mode (3) Wait Mode(4) Stop Mode(5) 25°C –40 to 105°C I/O ports hi-z leakage current PA0–PA7, PB0–PB5 (without individual pulldown activated) Input pulldown current PA0–PA7, PB0–PB5 (with individual pulldown activated) Input pullup current RESET Input current(6) RESET, IRQ/VPP, OSC1 Capacitance Ports (as inputs or outputs) RESET, IRQ/VPP, OSC1, OSC2 Crystal/ceramic resonator oscillator mode internal resistor OSC1 to OSC2(7) IDD 1. V DD = 3.3 Vdc ± 10%, V SS = 0 Vdc, TA = –40°C to +105°C, unless otherwise noted 2. Typical values at midpoint of voltage range, 25°C only 3. Run mode IDD is measured using external square wave clock source (fosc = 2.0 MHz); all inputs 0.2 V from rail; no dc loads; less than 50 pF on all outputs; CL = 20 pF on OSC2 4. Wait mode IDD: only timer system active. Wait mode is affected linearly by OSC2 capacitance. Wait mode is measured with all ports configured as inputs; VIL = 0.2 V; VIH = VDD – 0.2 V. Wait mode IDD is measured using external square wave clock source (fosc = 2.0 MHz); all inputs 0.2 V from rail; no dc loads; less than 50 pF on all outputs; CL = 20 pF on OSC2. 5. Stop mode IDD is measured with OSC1 = VSS. Stop mode IDD is measured with all ports configured as inputs; VIL = 0.2 V; VIH = V DD – 0.2 V 6. Only input high current rated to +1 µA on RESET. 7. The R osc value selected for RC oscillator versions of this device is unspecified. See Appendix C. MC68HSR705J1A for additional information. Technical Data 122 MC68HC705J1A — Rev. 4.0 Electrical Specifications MOTOROLA Electrical Specifications Driver Characteristics 10.9 Driver Characteristics L PR °C NOM INA −40 °C 300 mV 100 mV 0 −1.0 mA −2.0 mA −3.0 mA −4.0 mA −5.0 mA 0 V DD = 3.3 V SE 100 mV OT E 200 mV VDD = 5.0 V EN 200 mV 0 400 mV 2 300 mV 500 mV 25 ° C −4 25 ° 400 mV 105 600 mV CN 500 mV 700 mV VDD - VOH 600 mV 85 ° C OCE SSIN G OM INA 85 0° °C LP C RO CE SS I NG °C 105 SE EN 700 mV VDD - VOH 800 mV OT E1 800 mV 0 −1.0 mA −2.0 mA −3.0 mA −4.0 mA −5.0 mA IOH IOH Notes: 1. At VDD = 5.0 V, devices are specified and tested for (VDD – VOH) ≤ 800 mV @ IOH = –0.8 mA. 2. At VDD = 3.3 V, devices are specified and tested for (VDD – VOH) ≤ 300 mV @ IOH = –0.2 mA. Figure 10-1. PA0–PA7, PB0–PB5 Typical High-Side Driver Characteristics 25°C NOMINAL PROCESSING SEE NOTE 2 °C –40 85 ° C °C 300 mV 250 mV VOL 250 mV VOL 105 °C 350 mV –4 0 300 mV 85 ° C 105 °C 400 mV 350 mV 200 mV 150 mV 200 mV 150 mV 100 mV VDD = 5.0 V 50 mV 0 25°C NOMINAL PROCESSING SEE NOTE 2 400 mV 100 mV VDD = 3.3 V 50 mV 0 2.0 mA 4.0 mA 6.0 mA 8.0 mA 10.0 mA 0 0 IOL 2.0 mA 4.0 mA 6.0 mA 8.0 mA 10.0 mA IOL Notes: 1. At V DD = 5.0 V, devices are specified and tested for VOL ≤ 400 mV @ IOL = 1.6 mA. 2. At V DD = 3.3 V, devices are specified and tested for VOL ≤ 300 mV @ IOL = 0.4 mA. Figure 10-2. PA0–PA3, PB0–PB5 Typical Low-Side Driver Characteristics MC68HC705J1A — Rev. 4.0 MOTOROLA Technical Data Electrical Specifications 123 Electrical Specifications °C 700 mV 105 NO M INA L NO T E2 °C 400 mV 25 300 mV 300 mV 200 mV 200 mV VDD = 5.0 V V DD = 3.3 V 100 mV 0 SEE °C 25 400 mV 500 mV VOL NO SEE VOL 500 mV 600 mV NO MI TE 1 600 mV 105 °C 85 700 mV 85 ° C PR OC E SS −40 ING °C 800 mV °C NA LP RO CE −4 SS 0 °C IN G 800 mV 100 mV 0 10 mA 20 mA 30 mA 40 mA 50 mA 0 IOL 0 10 mA 20 mA 30 mA 40 mA 50 mA IOL Notes: 1. At VDD = 5.0 V, devices are specified and tested for V OL ≤ 400 mV @ IOL = 10.0 mA. 2. At VDD = 3.3 V, devices are specified and tested for V OL ≤ 300 mV @ IOL = 5.0 mA. Figure 10-3. PA4–PA7 Typical Low-Side Driver Characteristics Technical Data 124 MC68HC705J1A — Rev. 4.0 Electrical Specifications MOTOROLA Electrical Specifications Typical Supply Currents 10.10 Typical Supply Currents 6.0 mA SEE NOTE 1 SUPPLY CURRENT (IDD) 5.0 mA SEE NOTE 2 4.0 mA 5.5 V 3.0 mA 4.5 V 2.0 mA 3.6 V 1.0 mA 3.0 V 0 0 1.0 MHz 2.0 MHz INTERNAL OPERATING FREQUENCY (fOP) Notes: 1. At VDD = 5.0 V, devices are specified and tested for IDD ≤ 6.0 mA @ fOP = 2.1 MHz. 2. At VDD = 3.3 V, devices are specified and tested for IDD ≤ 4.0 mA @ fOP = 1.0 MHz. Figure 10-4. Typical Operating IDD (25°C) SEE NOTE 2 SEE NOTE 1 700 µA 600 µA SUPPLY CURRENT (IDD) 5.5 V 500 µA 4.5 V 400 µA 300 µA 3.6 V 3.0 V 200 µA 100 µA 0 0 1.0 MHz 2.0 MHz INTERNAL OPERATING FREQUENCY (fOP) Notes: 1. At VDD = 5.0 V, devices are specified and tested for IDD ≤ 2.75 mA @ fOP = 2.1 MHz. 2. At VDD = 3.3 V, devices are specified and tested for IDD ≤ 1.5 mA @ fOP = 1.0 MHz. Figure 10-5. Typical Wait Mode IDD (25°C) MC68HC705J1A — Rev. 4.0 MOTOROLA Technical Data Electrical Specifications 125 Electrical Specifications 10.11 EPROM Programming Characteristics Characteristic(1) Symbol Min Typ Max Unit Programming voltage IRQ/VPP VPP 16.0 16.5 17.0 V Programming current IRQ/VPP IPP — 3.0 10.0 mA tEPGM tMPGM 4 4 — — — — ms Symbol Min Max Unit Oscillator frequency Crystal oscillator option External clock source fosc — dc 4.2 4.2 MHz Internal operating frequency (fosc ÷ 2) Crystal oscillator External clock fop — dc 2.1 2.1 MHz Cycle time (1 ÷ fOP) tcyc 476 — ns RESET pulse width low tRL 1.5 — tcyc IRQ interrupt pulse width low (edge-triggered) tILIH 1.5 — tcyc IRQ interrupt pulse width low (edge- and level-triggered) tILIL 1.5 Note(2) tcyc PA0–PA3 interrupt pulse width high (edge-triggered) tIHIL 1.5 — tcyc PA0–PA3 interrupt pulse width (edge- and level-triggered) tIHIH 1.5 Note(2) tcyc tOH, tOL 200 — ns Programming time Per array byte MOR 1. V DD = 5.0 Vdc ± 10%, V SS = 0 Vdc, T = –40°C to +105°C, unless otherwise noted A 10.12 5.0-Volt Control Timing Characteristic(1) OSC1 pulse width 1. VDD = 5.0 Vdc ± 10%, V SS = 0 Vdc, T = –40°C to +105°C, unless otherwise noted A 2. The maximum width, tILIL or tILIH, should not be more than the number of cycles it takes to execute the interrupt service routine plus 19 tcyc or the interrupt service routine will be re-entered. Technical Data 126 MC68HC705J1A — Rev. 4.0 Electrical Specifications MOTOROLA Electrical Specifications 3.3-Volt Control Timing 10.13 3.3-Volt Control Timing Characteristic(1) Symbol Min Max Unit Oscillator frequency Crystal oscillator option External clock source fosc — dc 2.0 2.0 MHz Internal operating frequency (fosc ÷ 2) Crystal oscillator External clock fop — dc 1.0 1.0 MHz Cycle time (1 ÷ fOP) tcyc 1000 — ns RESET pulse width low tRL 1.5 — tcyc IRQ interrupt pulse width low (edge-triggered) tILIH 1.5 — tcyc IRQ interrupt pulse width low (edge- and level-triggered) tILIL 1.5 Note(2) tcyc PA0–PA3 interrupt pulse width high (edge-triggered) tIHIL 1.5 — tcyc PA0–PA3 interrupt pulse width (edge- and level-triggered) tIHIH 1.5 Note(2) tcyc tOH, tOL 400 — ns OSC1 pulse width 1. VDD = 3.3 Vdc ± 10%, V SS = 0 Vdc, T = –40°C to +105°C, unless otherwise noted A 2. The maximum width, tILIL or tILIH, should not be more than the number of cycles it takes to execute the interrupt service routine plus 19 tcyc or the interrupt service routine will be re-entered. MC68HC705J1A — Rev. 4.0 MOTOROLA Technical Data Electrical Specifications 127 Electrical Specifications tILIL tILIH IRQ PIN tILIH IRQ1 . . . IRQn IRQ (INTERNAL) Figure 10-6. External Interrupt Timing OSC (NOTE 1) tRL RESET tILIH IRQ (NOTE 2) 4064 tcyc IRQ (NOTE 3) INTERNAL CLOCK INTERNAL ADDRESS BUS 07FE (NOTE 4) 07FE 07FE 07FE Notes: 1. Internal clocking from OSC1 pin 2. Edge-triggered external interrupt mask option 3. Edge- and level-triggered external interrupt mask option 4. Reset vector shown as example 07FE 07FF RESET OR INTERRUPT VECTOR FETCH Figure 10-7. Stop Mode Recovery Timing Technical Data 128 MC68HC705J1A — Rev. 4.0 Electrical Specifications MOTOROLA Electrical Specifications 3.3-Volt Control Timing VDD (NOTE 1) 4064 tcyc OSC1 PIN INTERNAL CLOCK INTERNAL ADDRESS BUS 07FE 07FE 07FE 07FE 07FE 07FE INTERNAL DATA BUS 07FF NEW PCH NEW PCL Notes: 1. Power-on reset threshold is typically between 1 V and 2 V. 2. Internal clock, internal address bus, and internal data bus are not available externally. Figure 10-8. Power-On Reset Timing INTERNAL CLOCK INTERNAL ADDRESS BUS 07FE INTERNAL DATA BUS 07FE 07FE 07FE NEW PCH 07FF NEW PCL NEW PC DUMMY NEW PC OP CODE tRL Notes: 1. Internal clock, internal address bus, and internal data bus are not available externally. 2. The next rising edge of the internal clock after the rising edge of RESET initiates the reset sequence. Figure 10-9. External Reset Timing MC68HC705J1A — Rev. 4.0 MOTOROLA Technical Data Electrical Specifications 129 Electrical Specifications Technical Data 130 MC68HC705J1A — Rev. 4.0 Electrical Specifications MOTOROLA Technical Data — MC68HC705J1A Section 11. Mechanical Specifications 11.1 Contents 11.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 11.3 Plastic Dual In-Line Package (Case 738) . . . . . . . . . . . . . . . . 132 11.4 Small Outline Integrated Circuit (Case 751) . . . . . . . . . . . . . .132 11.5 Ceramic Dual In-Line Package (Case 732) . . . . . . . . . . . . . . 133 11.2 Introduction The MC68HC705J1A, the resistor-capacitor (RC) oscillator, and high-speed option devices described in Appendix A. MC68HRC705J1A, Appendix B. MC68HSC705J1A, and Appendix C. MC68HSR705J1A are available in the following packages: • 738-03 — plastic dual in-line package (PDIP) • 751D-04 — small outline integrated circuit (SOIC) • 732-03 — ceramic DIP (cerdip) (windowed) MC68HC705J1A — Rev. 4.0 MOTOROLA Technical Data Mechanical Specifications 131 Mechanical Specifications 11.3 Plastic Dual In-Line Package (Case 738) -A20 11 1 10 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. B C -T- L K SEATING PLANE M E G N F J 20 PL 0.25 (0.010) D 20 PL 0.25 (0.010) M T A M M T B M DIM A B C D E F G J K L M N INCHES MIN MAX 1.010 1.070 0.240 0.260 0.150 0.180 0.015 0.022 0.050 BSC 0.050 0.070 0.100 BSC 0.008 0.015 0.110 0.140 0.300 BSC 15° 0° 0.020 0.040 MILLIMETERS MIN MAX 25.66 27.17 6.10 6.60 3.81 4.57 0.39 0.55 1.27 BSC 1.27 1.77 2.54 BSC 0.21 0.38 2.80 3.55 7.62 BSC 0° 15° 0.51 1.01 11.4 Small Outline Integrated Circuit (Case 751) -A20 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.150 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF D DIMENSION AT MAXIMUM MATERIAL CONDITION. 11 -B- P 10 PL 0.010 (0.25) 1 M B M 10 D 20 PL 0.010 (0.25) M T A S B S J F R X 45° C -TG 18 PL K SEATING PLANE M Technical Data 132 DIM A B C D F G J K M P R MILLIMETERS MIN MAX 12.65 12.95 7.40 7.60 2.35 2.65 0.35 0.49 0.50 0.90 1.27 BSC 0.25 0.32 0.10 0.25 0° 7° 10.05 10.55 0.25 0.75 INCHES MIN MAX 0.499 0.510 0.292 0.299 0.093 0.104 0.014 0.019 0.020 0.035 0.050 BSC 0.010 0.012 0.004 0.009 0° 7° 0.395 0.415 0.010 0.029 MC68HC705J1A — Rev. 4.0 Mechanical Specifications MOTOROLA Mechanical Specifications Ceramic Dual In-Line Package (Case 732) 11.5 Ceramic Dual In-Line Package (Case 732) 20 11 1 10 NOTES: 1. LEADS WITHIN 0.010 DIAMETER, TRUE POSITION AT SEATING PLANE, AT MAXIMUM MATERIAL CONDITION. 2. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 3. DIMENSIONS A AND B INCLUDE MENISCUS. B A L C F N H D G K J M DIM A B C D F G H J K L M N INCHES MIN MAX 0.940 0.990 0.260 0.295 0.150 0.200 0.015 0.022 0.055 0.065 0.100 BSC 0.020 0.050 0.008 0.012 0.125 0.160 0.300 BSC 0_ 15_ 0.010 0.040 SEATING PLANE MC68HC705J1A — Rev. 4.0 MOTOROLA Technical Data Mechanical Specifications 133 Mechanical Specifications Technical Data 134 MC68HC705J1A — Rev. 4.0 Mechanical Specifications MOTOROLA Technical Data — MC68HC705J1A Section 11. Section 12. Ordering Information 12.1 Contents 12.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 12.3 MCU Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 12.2 Introduction This section contains ordering information for the available package types. 12.3 MCU Order Numbers Table 12-1 lists the MC order numbers. Table 12-1. Order Numbers Package Type Case Outline Pin Count Operating Temperature Order Number(1) MC68HC705J1AP(2) MC68HC705J1AC (3)P MC68HC705J1AV(4)P PDIP 738-03 20 0 to 70°C –40 to +85°C –40 to +105°C SOIC 751D-04 20 0 to 70°C –40 to +85°C –40 to +105°C MC68HC705J1ADW (5) MC68HC705J1ACDW MC68HC705J1AVDW Cerdip 732-03 20 0 to 70°C –40 to +85°C –40 to +105°C MC68HC705J1AS(6) MC68HC705J1ACS MC68HC705J1AVS 1. Refer to Appendix A. MC68HRC705J1A, Appendix B. MC68HSC705J1A, and Appendix C. MC68HSR705J1A for ordering information on optional high-speed and resistor-capacitor oscillator devices. 2. P = Plastic dual in-line package (PDIP) 3. C = Extended temperature range 4. V = Automotive temperature range 5. DW = Small outline integrated circuit (SOIC) 6. S = Ceramic dual in-line package (cerdip) MC68HC705J1A — Rev. 4.0 MOTOROLA Technical Data 135 Ordering Information Technical Data 136 MC68HC705J1A — Rev. 4.0 Ordering Information MOTOROLA Technical Data — MC68HC705J1A Appendix A. MC68HRC705J1A A.1 Contents A.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 A.3 RC Oscillator Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 A.4 Typical Internal Operating Frequency for RC Oscillator Option. . . . . . . . . . . . . . . . . . . . . . . . . . . 139 A.5 Package Types and Order Numbers . . . . . . . . . . . . . . . . . . . 140 A.2 Introduction This appendix introduces the MC68HRC705J1A, a resistor-capacitor (RC) oscillator mask option version of the MC68HC705J1A. All of the information in this document applies to the MC68HRC705J1A with the exceptions given in this appendix. MC68HC705J1A — Rev. 4.0 MOTOROLA Technical Data MC68HRC705J1A 137 MC68HRC705J1A A.3 RC Oscillator Connections For greater cost reduction, the RC oscillator mask option allows the configuration shown in Figure A-1 to drive the on-chip oscillator. Mount the RC components as close as possible to the pins for startup stabilization and to minimize output distortion. OSC1 R OSC2 R OSC2 OSC1 MCU VDD C2 C1 VSS Figure A-1. RC Oscillator Connections NOTE: The optional internal resistor is not recommended for configurations that use the RC oscillator connections as shown in Figure A-1. For such configurations, the oscillator internal resistor (OSCRES) bit of the mask option register should be programmed to a logic 0. Technical Data 138 MC68HC705J1A — Rev. 4.0 MC68HRC705J1A MOTOROLA MC68HRC705J1A Typical Internal Operating Frequency for RC Oscillator Option A.4 Typical Internal Operating Frequency for RC Oscillator Option Figure A-2 shows typical internal operating frequencies at 25°C for the RC oscillator option. NOTE: Tolerance for resistance is ±50%. When selecting resistor size, consider the tolerance to ensure that the resulting oscillator frequency does not exceed the maximum operating frequency. 10 FREQUENCY (MHz) 1 3.0 V 3.6 V 4.5 V 5.0 V 5.5 V 0.1 0.01 1 10 100 1000 10000 RESISTANCE (kΩ) Figure A-2. Typical Internal Operating Frequency for Various VDD at 25°C — RC Oscillator Option Only MC68HC705J1A — Rev. 4.0 MOTOROLA Technical Data MC68HRC705J1A 139 MC68HRC705J1A A.5 Package Types and Order Numbers Table A-1. MC68HRC705J1A (RC Oscillator Option) Order Numbers Package Type PDIP Case Outline 738-03 Pin Count Operating Temperature 20 0 to 70°C –40 to +85°C –40 to +105°C MC68HRC705J1AP(2) MC68HRC705J1AC (3)P MC68HRC705J1AV(4)P MC68HRC705J1ADW (5) MC68HRC705J1ACDW MC68HRC705J1AVDW MC68HRC705J1AS(6) MC68HRC705J1ACS MC68HRC705J1AVS SOIC 751D-04 20 0 to 70°C –40 to +85°C –40 to +105°C Cerdip 732-03 20 0 to 70°C –40 to +85°C –40 to +105°C Order Number(1) 1. Refer to Section 12. Ordering Information for standard part ordering information. 2. P = plastic dual in-line package (PDIP) 3. C = extended temperature range 4. V = automotive temperature range 5. DW = small outline integrated circuit (SOIC) 6. S = ceramic dual in-line package (cerdip) Technical Data 140 MC68HC705J1A — Rev. 4.0 MC68HRC705J1A MOTOROLA Technical Data — MC68HC705J1A Appendix B. MC68HSC705J1A B.1 Contents B.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 B.3 5.0-Volt DC Electrical Characteristics. . . . . . . . . . . . . . . . . . .142 B.4 3.3-Volt DC Electrical Characteristics. . . . . . . . . . . . . . . . . . .142 B.5 Typical Supply Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 B.6 Package Types and Order Numbers . . . . . . . . . . . . . . . . . . . 144 B.2 Introduction This appendix introduces the MC68HSC705J1A, a high-speed version of the MC68HC705J1A. All of the information in this document applies to the MC68HSC705J1A with the exceptions given in this appendix. MC68HC705J1A — Rev. 4.0 MOTOROLA Technical Data MC68HSC705J1A 141 MC68HSC705J1A B.3 5.0-Volt DC Electrical Characteristics Characteristic Symbol Min Typ Max Unit IDD — 4.25 0.57 7.0 3.25 mA Symbol Min Typ Max Unit IDD — 1.4 0.28 4.25 1.75 mA Supply current (fOP = 4.0 MHz) Run Wait B.4 3.3-Volt DC Electrical Characteristics Characteristic Supply current (fOP = 2.1 MHz) Run Wait B.5 Typical Supply Currents 7.0 mA SEE NOTE 1 6.0 mA 5.5 V SUPPLY CURRENT (IDD) 5.0 mA SEE NOTE 2 4.0 mA 4.5 V 3.0 mA 2.0 mA 3.6 V 3.0 V 1.0 mA 0 0 1.0 MHz 2.0 MHz 3.0 MHz 4.0 MHz INTERNAL OPERATING FREQUENCY (fOP) Notes: 1. At V DD = 5.0 V, high-speed devices are specified and tested for IDD ≤ 7.0 mA @ fOP = 4.0 MHz. 2. At V DD = 3.3 V, high-speed devices are specified and tested for IDD ≤ 4.25 mA @ fOP = 2.1 MHz. Figure B-1. Typical High-Speed Operating IDD (25°C) Technical Data 142 MC68HC705J1A — Rev. 4.0 MC68HSC705J1A MOTOROLA MC68HSC705J1A Typical Supply Currents SEE NOTE 1 SEE NOTE 2 700 µA 5.5 V SUPPLY CURRENT (IDD) 600 µA 4.5 V 500 µA 400 µA 3.6 V 300 µA 3.0 V 200 µA 100 µA 0 0 1.0 MHz 2.0 MHz 3.0 MHz 4.0 MHz INTERNAL OPERATING FREQUENCY (fOP) Notes: 1. At VDD = 5.0 V, high-speed devices are specified and tested for IDD ≤ 3.25 mA @ fOP = 4.0 MHz. 2. At VDD = 3.3 V, high-speed devices are specified and tested for IDD ≤ 1.75 mA @ fOP = 2.1 MHz. Figure B-2. Typical High-Speed Wait Mode IDD (25°C) MC68HC705J1A — Rev. 4.0 MOTOROLA Technical Data MC68HSC705J1A 143 MC68HSC705J1A B.6 Package Types and Order Numbers Table B-1. MC68HSC705J1A (High Speed) Order Numbers Package Type Case Outline Pin Count Operating Temperature PDIP 738-03 20 0 to 70°C –40 to +85°C MC68HSC705J1AP(2) MC68HSC705J1AC(3)P SOIC 751D-04 20 0 to 70°C –40 to +85°C MC68HSC705J1ADW (4) MC68HSC705J1ACDW Cerdip 732-03 20 0 to 70°C –40 to +85°C MC68HSC705J1AS(5) MC68HSC705J1ACS Order Number(1) 1. Refer to Section 12. Ordering Information for standard part ordering information. 2. P = plastic dual in-line package (PDIP) 3. C = extended temperature range 4. DW = small outline integrated circuit (SOIC) 5. S = ceramic dual in-line package (cerdip) Technical Data 144 MC68HC705J1A — Rev. 4.0 MC68HSC705J1A MOTOROLA Technical Data — MC68HC705J1A Appendix C. MC68HSR705J1A C.1 Contents C.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 C.3 RC Oscillator Connections (External Resistor). . . . . . . . . . . . 145 C.4 Typical Internal Operating Frequency at 25°C for High-Speed RC Oscillator Option. . . . . . . . . . . . . . . . . 146 C.5 RC Oscillator Connections (No External Resistor) . . . . . . . . .147 C.6 Typical Internal Operating Frequency versus Temperature (No External Resistor) . . . . . . . . . . . . . . . . . . . . . . . . . . . .148 C.7 Package Types and Order Numbers . . . . . . . . . . . . . . . . . . . 149 C.2 Introduction This appendix introduces the MC68HSR705J1A, a high-speed version of the MC68HRC705J1A. All of the information in this document applies to the MC68HSR705J1A with the exceptions given in this appendix. C.3 RC Oscillator Connections (External Resistor) Refer to Appendix A. MC68HRC705J1A for a description of the resistor-capacitor (RC) oscillator connections with external resistor. MC68HC705J1A — Rev. 4.0 MOTOROLA Technical Data MC68HSR705J1A 145 MC68HSR705J1A C.4 Typical Internal Operating Frequency at 25°C for High-Speed RC Oscillator Option 10 3.0 V 3.6 V FREQUENCY (MHz) 4.5 V 5.0 V 5.5 V 1 10 1 100 RESISTANCE (kΩ) Figure C-1. Typical Internal Operating Frequency at 25°C for High-Speed RC Oscillator Option For lower frequency operation characteristics, refer to Appendix A. MC68HRC705J1A. NOTE: Tolerance for resistance is ±50 percent. When selecting resistor size, consider the tolerance to ensure that resulting oscillator frequency does not exceed the maximum operating frequency. Technical Data 146 MC68HC705J1A — Rev. 4.0 MC68HSR705J1A MOTOROLA MC68HSR705J1A RC Oscillator Connections (No External Resistor) C.5 RC Oscillator Connections (No External Resistor) For maximum cost reduction, the RC oscillator mask connections shown in Figure C-2 allow the on-chip oscillator to be driven with no external components. This can be accomplished by programming the oscillator internal resistor (OSCRES) bit in the mask option register to a logic 1. When programming the OSCRES bit for the MC68HSR705J1A, an internal resistor is selected which yields typical internal oscillator frequencies as shown in Figure C-3. The internal resistance for this device is different than the resistance of the selectable internal resistor on the MC68HC705J1A and the MC68HSC705J1A devices. NOTE: This option is not available on the ROM version of this device (MC68HC05J1A). OSC1 R OSC2 OSC2 OSC1 MCU VDD C2 EXTERNAL CONNECTIONS LEFT OPEN C1 VSS Figure C-2. RC Oscillator Connections (No External Resistor) MC68HC705J1A — Rev. 4.0 MOTOROLA Technical Data MC68HSR705J1A 147 MC68HSR705J1A C.6 Typical Internal Operating Frequency versus Temperature (No External Resistor) 3.00 FREQUENCY (MHz) 2.50 2.00 3.0 V 3.6 V 4.5 V 5.0 V 1.50 5.5 V 1.00 0.50 0.00 –50 0 50 100 150 TEMPERATURE (°C) Figure C-3. Typical Internal Operating Frequency versus Temperature (OSCRES Bit = 1) NOTE: Due to process variations, operating voltages, and temperature requirements, the internal resistance and tolerance are unspecified. Typically for a given voltage and temperature, the frequency should not vary more than ±500 kHz. However, this data is not guaranteed. It is the user’s responsibility to ensure that the resulting internal operating frequency meets the user’s requirements. Technical Data 148 MC68HC705J1A — Rev. 4.0 MC68HSR705J1A MOTOROLA MC68HSR705J1A Package Types and Order Numbers C.7 Package Types and Order Numbers Table C-1. MC68HSR705J1A (High-Speed RC Oscillator Option) Order Numbers(1) Package Type Case Outline Pin Count Operating Temperature PDIP 738-03 20 0 to 70°C –40 to +85°C MC68HSR705J1AP(2) MC68HSR705J1AC(3)P SOIC 751D-04 20 0 to 70°C –40 to +85°C MC68HSR705J1ADW (4) MC68HSR705J1ACDW Cerdip 732-03 20 0 to 70°C –40 to +85°C MC68HSR705J1AS(5) MC68HSR705J1ACS Order Number 1. Refer to Section 12. Ordering Information for standard part ordering information. 2. P = plastic dual in-line package (PDIP) 3. C = extended temperature range 4. DW = small outline integrated circuit (SOIC) 5. S = ceramic dual in-line package (cerdip) MC68HC705J1A — Rev. 4.0 MOTOROLA Technical Data MC68HSR705J1A 149 MC68HSR705J1A Technical Data 150 MC68HC705J1A — Rev. 4.0 MC68HSR705J1A MOTOROLA Technical Data — MC68HC705J1A Index A accumulator register (A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 B block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 brownout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 C C bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 central processor unit (CPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 computer operating properly (COP) module . . . . . . . . . . . . . . . . . . . 97 condition code register (CCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 COP watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 COP in stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 COP in wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 COP register (COPR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 COP reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 programmable option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 COPEN bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 instruction types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 opcode map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 MC68HC705J1A — Rev. 4.0 MOTOROLA Technical Data Index 151 Index CPU registers accumulator register (A). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . index register (X) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . program counter register (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . stack pointer register (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 48 50 49 D data direction registers data direction register A (DDRA) . . . . . . . . . . . . . . . . . . . . . . . . . 90 data direction register B (DDRB) . . . . . . . . . . . . . . . . . . . . . . . . . 93 data-retention mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 E ELAT bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126, 127 DC electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . 121, 122 driver characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 MC68HSC705J1A (high-speed option) . . . . . . . . . . . . . . . . . . . 142 MC68HSR705J1A (high-speed RC oscillator option) . . . . . . . . 145 operating temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 power considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 thermal resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 typical supply currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 electrostatic damage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 EPGM bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 EPMSEC bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 EPROM EPROM security programmable option . . . . . . . . . . . . . . . . . . . . 25 EPROM/OTPROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 erasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38, 40 programming characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 programming register (EPROG). . . . . . . . . . . . . . . . . . . . . . . . . . 39 Technical Data 152 MC68HC705J1A — Rev. 4.0 Index MOTOROLA Index external interrupt module (IRQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 external interrupt pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 external reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 G general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 H H bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 I I bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 index register (X) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 instruction types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 opcode map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 instruction types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 interrupts external interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73, 74 external interrupt logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 external interrupt module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 external interrupt timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75, 107 external interrupt vector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 interrupt flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78, 103 interrupt processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 interrupt sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 interrupt stacking order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 IRQ module block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 IRQ status and control register (ISCR) . . . . . . . . . . . . . . . . . . . 106 IRQ/VPP pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101, 104 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 optional external interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 pin sensitivity selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 pin triggering option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 port A external interrupts programmable option. . . . . . . . . . . . . . 25 MC68HC705J1A — Rev. 4.0 MOTOROLA Technical Data Index 153 Index real-time interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 reset/interrupt vector addresses. . . . . . . . . . . . . . . . . . . . . . . . . . 77 software interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 software interrupt vector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 sources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 timer interrupt vector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 timer interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76, 112 timer overflow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 IRQ latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 IRQ/VPP pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31, 98, 104 IRQE bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 IRQF bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 IRQR bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 J junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 L LEVEL bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 COP timeout period . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 data-retention mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80, 84 effects on clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 effects on COP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 effects on CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 effects on EPROM/OTPROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 effects on timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 exiting stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 exiting wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 flowchart (STOP/HALT/WAIT) . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 STOP instruction flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79, 82 stop recovery timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 timing of stop mode recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 wait mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Technical Data 154 MC68HC705J1A — Rev. 4.0 Index MOTOROLA Index M mask option register (MOR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 MC68HC705J1A features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 MC68HRC705J1A (RC oscillator option) . . . . . . . . . . . . . . . . . . . . 137 operating frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 order numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 package types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 RC oscillator connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 MC68HSC705J1A (high-speed option) . . . . . . . . . . . . . . . . . . . . . . 141 DC electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 order numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 package types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 typical operating current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 typical wait mode current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 MC68HSR705J1A (high-speed RC oscillator option) . . . . . . . . . . . 145 operating frequencies (with OSCRES bit set) . . . . . . . . . . . . . . 148 operating frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 order numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 package types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 RC oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 RC oscillator connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 mechanical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 EPROM/OTPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 EPROM/OTPROM programming . . . . . . . . . . . . . . . . . . . . . . . . . 38 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 I/O register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 mask option register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 MPGM bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 multifunction timer module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 N N bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 MC68HC705J1A — Rev. 4.0 MOTOROLA Technical Data Index 155 Index O opcode map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 options (mask) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 options (programmable) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 ordering information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 MC68HRC705J1A (RC oscillator option) . . . . . . . . . . . . . . . . . . 140 MC68HSC705J1A (high-speed option) . . . . . . . . . . . . . . . . . . . 144 MC68HSR705J1A (high-speed RC oscillator option) . . . . . . . . 149 order numbers . . . . . . . . . . . . . . . . . . . . . . . . . . 135, 140, 144, 149 OSC1 pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 OSC2 pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 oscillator crystal oscillator internal resistor option . . . . . . . . . . . . . . . . . . . . 25 delay counter programmable option. . . . . . . . . . . . . . . . . . . . . . . 25 on-chip oscillator stabilization delay. . . . . . . . . . . . . . . . . . . . . . . 71 pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 OSCRES bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 P PA0–PA3 pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 package types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 parallel input/output (I/O) ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 pin assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 PIRQ bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . port A data direction register (DDRA) . . . . . . . . . . . . . . . . . . . . . . . . . . . data register (PORTA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O pin interrupts (PA0–PA3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . LED drive capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pin operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pulldown register (PDRA). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . port B data direction register (DDRB) . . . . . . . . . . . . . . . . . . . . . . . . . . . electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Technical Data 156 42 90 89 95 90 92 92 91 31 91 93 95 MC68HC705J1A — Rev. 4.0 Index MOTOROLA Index I/O circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 pin operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 port B data register (PORTB). . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 pulldown register (PDRB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 power dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 power-on reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 program counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 programmable options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 programming model (CPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 pulldown register A (PDRA). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 pulldown register B (PDRB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 pulldown resistors programmable option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 R RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 stack RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 registers CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 I/O register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 parallel I/O port register summary . . . . . . . . . . . . . . . . . . . . . . . . 88 RESET pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30, 72 resets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 COP register (COPR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 COP watchdog reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 external reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 external reset timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 illegal address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 power-on reset (POR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 power-on reset timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 reset sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 reset/interrupt vector addresses. . . . . . . . . . . . . . . . . . . . . . . . . . 77 resistors (pulldown) programmable option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 RT1, RT0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 MC68HC705J1A — Rev. 4.0 MOTOROLA Technical Data Index 157 Index RTIE bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 RTIF bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 RTIFR bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 S Schmitt trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31, 104, 105 SOSCD bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 stack pointer register (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 STOP instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81, 100, 106 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82, 100 effect on COP watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 effects on timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 STOP instruction flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 stop recovery timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 stop/halt mode programmable option . . . . . . . . . . . . . . . . . . . . . . . . 25 SWAIT bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 SWPDI bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 T thermal resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 timer block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 I/O registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76, 112 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 timer counter register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 timer interrupt vector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 timer status and control register (TSCR) . . . . . . . . . . . . . . . . . . 112 TOF bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 TOFR bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 TOIE bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Technical Data 158 MC68HC705J1A — Rev. 4.0 Index MOTOROLA Index V VDD pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 VSS pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 W WAIT instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81, 100, 106 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 effects on timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Z Z bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 MC68HC705J1A — Rev. 4.0 MOTOROLA Technical Data Index 159 Index Technical Data 160 MC68HC705J1A — Rev. 4.0 Index MOTOROLA HOW TO REACH US: USA/EUROPE/LOCATIONS NOT LISTED: Motorola Literature Distribution; P.O. Box 5405, Denver, Colorado 80217 1-303-675-2140 or 1-800-441-2447 JAPAN: Motorola Japan Ltd.; SPS, Technical Information Center, 3-20-1, Minami-Azabu Minato-ku, Tokyo 106-8573 Japan 81-3-3440-3569 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre, 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong 852-26668334 TECHNICAL INFORMATION CENTER: 1-800-521-6274 Information in this document is provided solely to enable system and software implementers to use Motorola products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any HOME PAGE: http://www.motorola.com/semiconductors liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and the Stylized M Logo are registered in the U.S. Patent and Trademark Office. digital dna is a trademark of Motorola, Inc. All other product or service names are the property of their respective owners. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. © Motorola, Inc. 2002 MC68HC705J1A/D