OKI ML7000-02 Single rail codec Datasheet

E2U0062-18-84
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This version: Aug. 1998
ML7000-01/02/03/ML7001-01/02/03
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¡ Semiconductor
ML7000-01/02/03
ML7001-01/02/03
¡ Semiconductor
Single Rail CODEC
GENERAL DESCRIPTION
The ML7000/ML7001 are single-channel CMOS CODEC LSI devices for voice signals ranging
from 300 to 3400 Hz with filters for A/D and D/A conversion.
Designed especially for a single-power supply and low-power applications, the devices are
optimized for ISDN terminals, digital wireless systems, and digital PBXs.
The devices use the same transmission clocks as those used in the MSM7507.
With the differential analog signal outputs which can drive 60 W load, the devices can directly
drive a handset receiver.
FEATURES
• Single power supply: +5 V (ML7000-xx)
+3 V (ML7001-xx)
• Low power consumption
Operating mode:
25 mW Typ. VDD = 5.0 V (ML7000-xx)
20 mW Typ. VDD = 3.0 V (ML7001-xx)
Power-down mode: 0.05 mW Typ. VDD = 5.0 V (ML7000-xx)
0.03 mW Typ. VDD = 3.0 V (ML7001-xx)
• Conforms to ITU-T Companding law
ML7000-01/ML7001-01: m/A-law pin selectable
ML7000-02/ML7001-02: m-law
ML7000-03/ML7001-03: A-law
• Transmission characteristics conform to ITU-T G.714
• Short frame sync timing operation
• Built-in PLL eliminates a master clock
• Serial data rate: 64/96/128/192/200/256/384/512/
768/1024/1536/1544/2048 kHz
• Adjustable transmit gain
• Adjustable receive gain
• Built-in reference voltage supply
• Package options:
24-pin plastic SOP (SOP24-P-430-1.27-K) (Product name: ML7000-01MA/ML7001-01MA)
(Product name: ML7000-02MA/ML7001-02MA)
(Product name: ML7000-03MA/ML7001-03MA)
20-pin plastic SSOP (SSOP20-P-250-0.95-K) (Product name: ML7000-01MB/ML7001-01MB)
(Product name: ML7000-02MB/ML7001-02MB)
(Product name: ML7000-03MB/ML7001-03MB)
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ML7000-01/02/03/ML7001-01/02/03
BLOCK DIAGRAM
AIN–
AIN+
–
+
RC
LPF
8th
BPF
PCMOUT
A/D
CONV.
TCONT
AUTO
ZERO
PLL
GSX
XSYNC
BCLK
SGC
SG
SG
GEN
VR
GEN
VFRO
–
+
5th
LPF
RTIM
RSYNC
(ALAW)
D/A
CONV.
RCONT
PCMIN
PWI
AOUT–
–
+
PWD
AOUT+
–
+
PWD
Logic
PDN
VDD
AG
DG
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PIN CONFIGURATION (TOP VIEW)
SG 1
24 SGC
SG 1
20 SGC
AOUT+ 2
23 AIN+
AOUT+ 2
19 AIN+
AOUT– 3
22 AIN–
AOUT– 3
18 AIN–
NC 4
21 GSX
PWI 4
17 GSX
PWI 5
20 NC
VFRO 5
16 NC
VFRO 6
19 NC
VDD 6
15 (ALAW)*
18 (ALAW)*
DG 7
14 AG
NC 7
VDD 8
17 NC
PDN 8
DG 9
16 AG
RSYNC 9
12 XSYNC
15 BCLK
PCMIN 10
11 PCMOUT
PDN 10
RSYNC 11
14 XSYNC
PCMIN 12
13 PCMOUT
13 BCLK
20-Pin Plastic SSOP
24-Pin Plastic SOP
* The ALAW pin is only supported by the ML7000-01MA/ML7000-01MB/ML7001-01MA/
ML7001-01MB.
NC : No connect pin
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PIN FUNCTIONAL DESCRIPTION
AIN+, AIN–, GSX
Transmit analog input and transmit level adjustment.
AIN+ is a non-inverting input to the op-amp; AIN– is an inverting input to the op-amp; GSX is
connected to the output of the op-amp.
The level adjustment should be performed using any of the methods shown below. During
power-saving and power-down modes, the GSX output is at AG voltage.
C1
R2
Analog input
R1
C2
AIN+
AIN–
GSX
Analog input
R5
GSX
AIN–
AIN+
SG
R4
R3
–
+
+
–
R1 : variable
R2 > 20 kW
C1 > 1/(2 ¥ 3.14 ¥ 30 ¥ R1)
R3 > 20 kW
R4 > 20 kW
R5 > 50 kW
C2 > 1/ (2 ¥ 3.14 ¥ 30 ¥ R5)
SG
AG
Analog ground.
VFRO
Receive filter output.
The output signal has an amplitude of 2.4 VPP for ML7000-xx and 2.0 VPP for ML7001-xx above
and below the signal ground voltage (SG) when the digital signal of +3 dBm0 is input to PCMIN
and can drive a load of 20 kW or more.
For driving a load of less than 20 kW, connect a resistor of 20 kW or more between the pins VFRO
and PWI.
During power-saving or power-down mode, the VFRO output is at an SG level.
When adjusting the receive signal on the basis of frequency characteristics, refer to the Frequency
Characteristics Adjustment Circuit.
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PWI, AOUT+, AOUT–
PWI is connected to the inverting input of the receive driver.
The receive driver output is connected to the AOUT– pin. Therefore, the receive level can be
adjusted with the pins VFRO, PWI, and AOUT–. During power-saving or power down-mode,
the outputs of AOUT+ and AOUT– are in a high impedance state. The output of AOUT+ is
inverted with respect to the output of AOUT–. Since these outputs provide differential drive of
an impedance of 1.2 kW, they can directly be connected to a handset using a piezoelectric
earphone or a line transformer. Refer to the application example.
VI
Receive filter
VFRO
PWI
SG
–
+
SG
–
+
R6 > 20 kW
ZL > 1.2 kW
R7
AOUT–
20 kW
20 kW
R6
Gain = VO/VI = 2 5 R7/R6 £ 2
VO ZL
AOUT+
VDD
Power supply for +5 V (ML7000-xx) or +3 V (ML7001-xx)
PCMIN
PCM data input.
A serial PCM data input to this pin is converted to an analog signal in synchronization with the
RSYNC signal and BCLK signal.
The data rate of PCM is equal to the frequency of the BCLK signal.
PCM signal is shifted in at the falling edge of the BCLK signal and latched into the internal
register when shifted by eight bits.
The start of the PCM data (MSD) is identified at the rising edge of RSYNC.
BCLK
Shift clock signal input for the PCMIN and PCMOUT signals.
The frequency, equal to the data rate, is 64, 96, 128, 192, 256, 384, 512, 768, 1024, 1536, 1544, or 2048
kHz. Setting this signal to logic "1" or "0" drives both transmit and receive circuits to the power
saving state.
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ML7000-01/02/03/ML7001-01/02/03
RSYNC
Receive synchronizing signal input.
Eight required bits are selected from serial PCM signals on the PCMIN pin by the receive
synchronizing signal.
Signals in the receive section are synchronized by this synchronizing signal. This signal must be
synchronized in phase with the BCLK. The frequency should be 8 kHz ±50 ppm to guarantee the
AC characteristics which are mainly the frequency characteristics of the receive section.
However, if the frequency characteristic of an applied system is not specified exactly, this device
can operate in the range of 6 to 9 kHz, but the electrical characteristics in this specification are not
guaranteed.
XSYNC
Transmit synchronizing signal input.
The PCM output signal from the PCMOUT pin is output in synchronization with this signal. This
synchronizing signal triggers the PLL and synchronizes all timing signals of the transmit section.
This synchronizing signal must be synchronized in phase with BCLK.
The frequency should be 8 kHz ±50 ppm to guarantee the AC characteristics which are mainly
the frequency characteristics of the transmit section. However, if the frequency characteristic of
an applied system is not specified exactly, this device operates in the range of 6 to 9 kHz, but the
electrical characteristics in this specification are not guaranteed.
Setting this signal to logic "1" or "0" drives both transmit and receive circuits to the power saving
state.
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DG
Ground for the digital signal circuits.
This ground is separate from the analog signal ground AG. The DG pin must be connected to the
AG pin on the printed circuit board to make a common analog ground AG.
PDN
Power down control signal.
A logic "0" level drives both transmit and receive circuits to a power down state.
PCMOUT
PCM signal output.
Synchronizing with the rising edge of the BCLK signal, the PCM output signal is output from
MSD in a sequential order.
MSD may be output at the rising edge of the XSYNC signal, based on the timing between BCLK
and XSYNC.
This pin is in a high impedance state except during 8-bit PCM output. It is also in a high
impedance state during power saving or power down mode.
A pull-up resistor must be connected to this pin because its output is configured as an open drain.
This device is compatible with the ITU-T recommendation on coding law and output coding
format.
The ML7000-03 (A-law) and ML7001-03 (A-law) output the character signal, inverting the even
bits.
PCMIN/PCMOUT
Input/Output Level
+Full scale
ML7000-02 (m-law)
ML7000-03 (A-law)
ML7001-02 (m-law)
ML7001-03 (A-law)
MSD
LSD
MSD
LSD
1
0
0
0
0
0
0
0
1
0
1
0
1
0
1
0
+0
1
1
1
1
1
1
1
1
1
1
0
1
0
1
0
1
–0
0
1
1
1
1
1
1
1
0
1
0
1
0
1
0
1
–Full scale
0
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
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ML7000-01/02/03/ML7001-01/02/03
SG
Signal ground voltage output.
The output voltage is 1/2 of the power supply voltage.
The output drive current capability is ±300 mA for ML7000-xx and ±200 mA for ML7001-xx.
This pin provides the SG level for CODEC peripherals.
This output voltage level is undefined during power-saving or power-down mode.
SGC
Used to generate the signal ground voltage level by connecting a bypass capacitor.
Connect a 0.1 mF capacitor with excellent high frequency characteristics between the AG pin and
the SGC pin.
ALAW
Control signal input of the companding law selection.
Only the ML7000-01MA/ML7000-01MB/ML7001-01MA/ML7001-01MB have this pin. The
CODEC will operate in the m-law when this pin is at a logic "0" level and the CODEC will operate
in the A-law when this pin is at a logic "1" level. The CODEC operates in the m-law if the pin is
left open, since the pin is internally pulled down.
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ML7000-01/02/03/ML7001-01/02/03
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Condition
Rating
Unit
Power Supply Voltage
VDD
Analog Input Voltage
VAIN
—
–0.3 to +7
V
—
–0.3 to VDD + 0.3
V
Digital Input Voltage
VDIN
—
–0.3 to VDD + 0.3
V
RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Condition
Power Supply Voltage
VDD
—
Operating Temperature
Ta
—
Analog Input Voltage
VAIN
High Level Input Voltage
VIH
Low Level Input Voltage
VIL
Connect AIN– and GSX
XSYNC, RSYNC, BCLK,
PCMIN, PDN, ALAW
Min.
Typ.
Max.
4.75
5.00
5.25
2.70
3.00
3.30
–30
+25
+85
—
—
2.4
—
—
1.2
2.2
—
VDD
0.45¥VDD
—
VDD
0
—
0.8
0
—
0.16¥VDD
Unit
V
°C
VPP
V
V
64, 96, 128, 192, 200, 256,
Clock Frequency
FC
384, 512, 768, 1024, 1536,
BCLK
kHz
1544, 2048
8.0
9.0
6.0
8.0
10.0
FS
Clock Duty Ratio
DC
BCLK
40
50
60
%
Digital Input Rise Time
tlr
XSYNC, RSYNC, BCLK,
—
—
50
ns
Digital Input Fall Time
Transmit Sync Pulse Setting Time
XSYNC Setup Time
XSYNC Hold Time
Receive Sync Pulse Setting Time
XSYNC, RSYNC (–40 to +75 °C)
6.0
Sync Pulse Frequency
kHz
tlf
PCMIN, PDN
—
—
50
ns
tCX
BCLKÆXSYNC, See Fig. 1
50
—
—
ns
tXC
XSYNCÆBCLK, See Fig. 1
tXS
tXH
50
—
—
ns
—
50
—
—
ns
—
50
—
—
ns
tCR
BCLKÆRSYNC, See Fig. 1
50
—
—
ns
tRC
RSYNCÆBCLK, See Fig. 1
50
—
—
ns
RSYNC Setup Time
tRS
—
50
—
—
ns
RSYNC Hold Time
tRH
—
50
—
—
ns
PCMIN Setup Time
tDS
—
50
—
—
ns
PCMIN Hold Time
tDH
—
50
—
—
ns
0.5
—
—
kW
—
—
100
pF
Digital Output Load
RDL
CDL
Analog Input Allowable DC Offset
Voff
Allowable Jitter Width
—
Pull-up resistor
—
Transmit gain stage, Gain = 0 dB
–10
—
+10
mV
Transmit gain stage, Gain = +20 dB
–100
—
+100
mV
—
—
1000
ns
XSYNC, RSYNC, BCLK
Values above the dotted line are for ML7000-xx; those below, for ML7001-xx.
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ML7000-01/02/03/ML7001-01/02/03
ELECTRICAL CHARACTERISTICS
DC and Digital Interface Characteristics
(ML7001-xx: VDD = 2.7 V to 3.3 V, Ta = –30 to +85°C)
(ML7000-xx: VDD = +5.0 V ±5%, Ta = –30 to +85°C)
Parameter
Symbol
IDD1
Power Supply Current
IDD2
IDD3
Condition
VDD = 5.0 V
—
5.0
12.0
VDD = 3.0 V
—
6.5
10.0
Power-saving mode, PDN = 1,
—
1.5
4.0
XSYNC Æ OFF
—
2.0
8.0
—
0.01
0.05
Power-down mode, PDN = 0,
BCLK OFF
—
Low Level Input Voltage
VIL
—
High Level Input Leakage Current
IIH
—
IIH2
IIL
Digital Output Low Voltage
VOL
Max.
No signal
VIH
High Level Input Leakage Current
Typ.
Operating mode
High Level Input Voltage
Low Level Input Leakage Current
Min.
ALAW
—
Pull-up resistor = 500 W
Unit
mA
mA
mA
2.2
—
VDD
0.45¥VDD
—
VDD
0.0
—
0.8
0.0
—
0.16¥VDD
—
—
2.0
—
—
30.0
mA
—
—
0.5
mA
V
V
mA
0.0
0.2
0.4
V
Digital Output Leakage Current
IO
—
—
—
10
mA
Input Capacitance
CIN
—
—
5
—
pF
Values above the dotted line are for ML7000-xx; those below, for ML7001-xx.
10/19
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ML7000-01/02/03/ML7001-01/02/03
Transmit Analog Interface Characteristics
(ML7001-xx: VDD = 2.7 V to 3.3 V, Ta = –30 to +85°C)
(ML7000-xx: VDD = +5.0 V ±5%, Ta = –30 to +85°C)
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
Input Resistance
RINX
AIN+, AIN–
10
—
—
MW
Output Load Resistance
RLGX
GSX with respect to SG
20
—
—
kW
Output Load Capacitance
CLGX
pF
Output Amplitude
VOGX
Offset Voltage
VOSGX
Gain = 1
—
—
30
–1.2
—
+1.2
–0.7
—
+0.7
–20
—
+20
V0p
mV
Values above the dotted line are for ML7000-xx; those below, for ML7001-xx.
Receive Analog Interface Characteristics
(ML7001-xx: VDD = 2.7 V to 3.3 V, Ta = –30 to +85°C)
(ML7000-xx: VDD = +5.0 V ±5%, Ta = –30 to +85°C)
Parameter
Input Resistance
Symbol
RLVF
Output Load Resistance
Output Load Capacitance
Condition
RINPW PWI
RLAO
VFRO with respect to SG
AOUT+, AOUT– (each) with
respect to SG
Typ.
Max.
Unit
10
—
—
MW
20
—
—
kW
0.6
—
—
kW
CLVF
VFRO
—
—
30
pF
CLAO
AOUT+, AOUT–
—
—
50
pF
VOVF
Output Amplitude
VOAO
VFRO, RL = 20 kW with
–1.2
—
+1.2
respect to SG
–1.0
—
+1.0
AOUT+, AOUT–, RL = 0.6 kW
–1.3
—
+1.3
with respect to SG
–1.0
—
+1.0
–100
—
+100
mV
–100
—
+100
mV
VOSVF VFRO with respect to SG
Offset Voltage
Min.
VOSAO
AOUT+, AOUT–, Gain = 1 with
respect to SG
V0p
Values above the dotted line are for ML7000-xx; those below, for ML7001-xx.
11/19
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ML7000-01/02/03/ML7001-01/02/03
AC Characteristics
Parameter
Transmit Frequency Response
Receive Frequency Response
(ML7001-xx: FS = 8 kHz, VDD = 2.7 V to 3.3 V, Ta = –30 to +85°C)
(ML7000-xx: FS = 8 kHz, VDD = +5.0 V ±5%, Ta = –30 to +85°C)
Loss T1
Freq.
(Hz)
60
Loss T2
300
Loss T3
1020
Loss T4
2020
Loss T5
3000
Symbol
Typ.
Max.
20
26
—
–0.15
+0.07
+0.2
Reference
0
–0.15
–0.04
+0.2
–0.15
+0.07
+0.2
Loss T6
3400
0
0.4
0.8
300
–0.15
–0.03
+0.2
Loss R2
1020
Loss R3
2020
Loss R4
Loss R5
0.00
+0.2
3000
–0.15
+0.05
+0.2
3400
0
0.54
0.8
0
SD T1
3
35
43
—
SD T2
0
35
41
—
SD T3
–30
35.0
38.0
—
1020
*1
–40
SD T5
–45
SD R1
3
SD R2
0
SD R3
Receive Signal to Distortion Ratio
–30
1020
SD R4
*1
–40
SD R5
–45
GT T1
3
GT T2
–10
GT T3
1020
34.0
38.0
—
26.0
31.0
—
26.0
30.0
—
24.0
25.0
—
—
25.0
—
36
43
—
36
41
—
36.0
40.0
—
35.0
40.0
—
25.0
32.0
—
26.0
32.0
—
25.0
27.0
—
—
27.0
—
+0.01
+0.3
–0.3
–40
–0.3
–0.05
+0.3
–50
–0.6
–0.05
+0.6
GT T5
–55
–1.2
–0.08
+1.2
GT R1
3
–0.3
–0.06
+0.3
–0.3
+0.08
+0.3
GT R4
–50
–0.6
+0.12
+0.6
GT R5
–55
–1.2
+0.15
+1.2
1020
dB
dB
dB
dB
Reference
–10
–40
GT R3
dB
Reference
GT T4
GT R2
Unit
Reference
–0.15
SD T4
Receive Gain Tracking
Min.
Loss R1
Transmit Signal to Distortion Ratio
Transmit Gain Tracking
Level Condition
(dBm0)
dB
*1 Psophometric filter is used.
Values above the dotted line are for ML7000-xx; those below, for ML7001-xx.
12/19
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ML7000-01/02/03/ML7001-01/02/03
AC Characteristics (Continued)
Parameter
(ML7001-xx: FS = 8 kHz, VDD = 2.7 V to 3.3 V, Ta = –30 to +85°C)
(ML7000-xx: FS = 8 kHz, VDD = +5.0 V ±5%, Ta = –30 to +85°C)
Symbol
Freq.
(Hz)
Nidle T
—
Idle Channel Noise
Nidle R
—
Level Condition
(dBm0)
AIN = SG
—
*1 *2
—
*1 *2
VDD = 5.0 V,
Ta = 25°C
AV T
1020
0
Absolute Level (Initial Difference)
AV R
VDD = 3.0 V,
Ta = 25°C
*3
Min.
Typ.
Max.
—
–73.0
–66.0
—
–69.5
–65.0
—
–78.0
–71.0
—
–75.0
–65.0
0.58
0.6007
0.622
0.338
0.35
0.362
0.58
0.6007
0.622
0.483
0.5
0.518
*3
–0.2
—
0.2
(Deviation of Temperature and Power) AV Rt VDD = 2.7 to 3.3 V, Ta = –30 to 85°C *3
–0.2
—
0.2
—
—
0.6
Absolute Level
AV Tt VDD = 5 V ±5%, Ta = –30 to 85°C
Unit
dBm0p
Vrms
dB
A to A
Absolute Delay
Td
1020
0
BCLK
ms
= 64 kHz
Transmit Group Delay
Receive Group Delay
Crosstalk Attenuation
*1
*2
*3
*4
tGD T1
500
—
0.19
0.75
tGD T2
600
—
0.11
0.35
tGD T3
1000
—
0.02
0.125
tGD T4
2600
—
0.05
0.125
0
*4
tGD T5
2800
—
0.07
0.75
tGD R1
500
—
0.00
0.75
tGD R2
600
—
0.00
0.35
tGD R3
1000
—
0.00
0.125
tGD R4
2600
—
0.09
0.125
tGD R5
2800
CR T
CR R
1020
0
0
*4
—
0.12
0.75
TRANS Æ RECV
—
–85
–75
RECV Æ TRANS
—
–76
–70
ms
ms
dB
Psophometric filter is used.
Input "0" code to PCMIN.
AVR is defined at VFRO output.
With respect to minimum value of the group delay distortion.
Values above the dotted line are for ML7000-xx; those below, for ML7001-xx.
13/19
¡ Semiconductor
ML7000-01/02/03/ML7001-01/02/03
AC Characteristics (Continued)
(ML7001-xx: FS = 8 kHz, VDD = 2.7 V to 3.3 V, Ta = –30 to +85°C)
(ML7000-xx: FS = 8 kHz, VDD = +5.0 V ±5%, Ta = –30 to +85°C)
Parameter
Discrimination
Out-of-band Spurious
Intermodulation Distortion
Power Supply Noise Rejection Ratio
Digital Output Delay Time
Freq.
Level Condition
(Hz)
(dBm0)
0 to
4.6 kHz to
DIS
0
4000 Hz
72 kHz
Symbol
S
IMD
300 to
3400
fa = 470
fd = 320
PSR T
0 to
PSR R
50 kHz
0
–4
50 mVPP
4.6 kHz to
100 kHz
2fa – fb
Measured
inband *5
Min.
Typ.
Max.
Unit
30
32
—
dB
—
–37.5
–35
dBm0
—
–52
–35
dBm0
—
30
—
dB
tXD1
CL = 100 pF + 1 LSTTL
20
—
200
tXD2
Pull-up resistor = 500 W
20
—
200
ns
*5 Measured under idle channel noise.
14/19
¡ Semiconductor
ML7000-01/02/03/ML7001-01/02/03
TIMING DIAGRAM
PCM Data Input/Output Timing
Transmit Timing
BCLK
1
2
3
4
5
6
7
8
9
10
11
12
9
10
11
12
tXS tXH
XSYNC
tCX
tXC
tXD1
PCMOUT
tXD2
D2
MSD
D3
D4
D5
D6
D7
D8
7
8
Receive Timing
BCLK
1
2
3
4
5
6
tRS tRH
RSYNC
tCR
tRC
tDS
PCMIN
MSD
D2
D3
tDH
D4
D5
D6
D7
D8
Figure 1 Basic Timing
15/19
¡ Semiconductor
ML7000-01/02/03/ML7001-01/02/03
APPLICATION CIRCUIT
+ 5V
ML7000-01
0.1 mF 51 kW
AIN–
600:600
600 W
1 kW
PCMOUT
PCM signal output
XSYNC
8 kHz SYNC signal input
RSYNC
BCLK
PCMIN
PCM shift clock input
PCM signal input
GSX
AIN+
SG
600:600 300 W
AOUT+
Control of companding law
1: A-law
0: m-law
ALAW
300 W
AOUT–
PWI
VFRO
51 kW 0.1 mF
SGC
DG
AG
10 mF
0V
Power down control input
1: Normal operation
0: Power down
1 mF
+
+5 V
PDN
VDD
0 to 20 W
+3 V
ML7001-01
0.1 mF 51 kW
AIN–
600:600
600 W
PCMOUT
1 kW
PCM signal output
XSYNC
8 kHz SYNC signal input
RSYNC
BCLK
PCMIN
PCM shift clock input
PCM signal input
GSX
AIN+
SG
600:600 300 W
AOUT+
ALAW
300 W
AOUT–
Control of companding law
1: A-law
0: m-law
PWI
VFRO
51 kW 0.1 mF
SGC
DG
AG
10 mF
0V
+
+3 V
0 to 20 W
PDN
Power down control input
1: Normal operation
0: Power down
1 mF
VDD
16/19
¡ Semiconductor
ML7000-01/02/03/ML7001-01/02/03
NOTES ON USE
• To ensure proper electrical characteristics, use bypass capacitors with excellent high frequency
characteristics for the power supply and keep them as close as possible to the device pins.
• Connect the AG pin and the DG pin as closely as possible. Connect to the system ground with
low impedance.
• Mount the device directly on the board when mounted on PCBs. Do not use IC sockets. If the
use of IC socket is unavoidable, use the short lead type socket.
• When mounted on a frame, use electromagnetic shielding if any electromagnetic wave
sources such as power supply transformers surrounds the device.
• Keep the voltage on the VDD pin not lower than –0.3 V even instantaneously to avoid latchup that may otherwise occur when power is turned on.
• Use a low noise (particularly, low level type of high frequency spike noise or pulse noise)
power supply to avoid erroneous operation and the degradation of the characteristics of these
devices.
17/19
¡ Semiconductor
ML7000-01/02/03/ML7001-01/02/03
PACKAGE DIMENSIONS
(Unit : mm)
SOP24-P-430-1.27-K
Mirror finish
Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
Epoxy resin
42 alloy
Solder plating
5 mm or more
0.58 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
18/19
¡ Semiconductor
ML7000-01/02/03/ML7001-01/02/03
(Unit : mm)
SSOP20-P-250-0.95-K
Mirror finish
Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
Epoxy resin
42 alloy
Solder plating
5 mm or more
0.18 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
19/19
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