AVAGO ADNS-5060 Self-adjusting frame rate for optimum performance Datasheet

ADNS-5060
Optical Mouse Sensor
Data Sheet
Description
Features
The ADNS-5060 is a mainstream, small form factor optical
mouse sensor. It is used to implement a non mechanical
tracking engine for computer mice.
• Small form factor, pin-to-pin compatible with
ADNS-26x0
It is based on optical navigation technology, which
measures changes in position by optically acquiring
sequential surface images (frames) and mathematically
determining the direction and magnitude of movement.
• Built-in LED driver for simpler circuitry
The sensor is housed in an 8-pin staggered dual
inline package (DIP). It is designed for use with the
HDNS-2100 round lens or HDNS-2100#001 trim lens,
HLMP-ED80-xx000, and the HDNS-2200 LED Clip,
providing an optical mouse solution that is compact
and affordable. There are no moving parts, so precision
optical alignment is not required, thereby facilitating high
volume assembly.
• Internal oscillator – no clock input needed
The output format is a two wire serial port. The current X
and Y information are available in registers accessed via
the serial port.
• Register-to-register compatible with ADNS-26x0
• High speed motion detection up to 30ips and 8g
• Self-adjusting frame rate for optimum performance
• Default 1050cpi resolution, adjustable from 150 to
1350cpi via 150cpi step
• Operating voltage: 5V nominal
• Two-wire serial interface
Applications
• Optical Mice
• Optical trackballs
• Integrated input devices
The ADNS-5060 is capable of high-speed motion detection
– up to 30ips and 8g. In addition, it has an on-chip
oscillator and built-in LED driver to minimize external
components. Frame rate is also adjusted internally.
CAUTION: It is advised that normal static precautions be taken in handling and assembly
of this component to prevent damage and/or degradation which may be induced by ESD.
Theory of Operation
The ADNS-5060 is based on Optical Navigation Technology, which measures changes in position by optically
acquiring sequential surface images (frames) and mathematically determining the direction and magnitude of
movement.
The IAS acquires microscopic surface images via the lens
and illumination system. These images are processed
by the DSP to determine the direction and distance of
motion. The DSP calculates the Δx and Δy relative displacement values.
The ADNS-5060 contains an Image Acquisition System
(IAS), a Digital Signal Processor (DSP), and a two wire serial
port.
An external microcontroller reads the Δx and Δy information from the sensor serial port. The microcontroller then
translates the data into PS2 or USB signals before sending
them to the host PC.
Pinout of ADNS-5060 Optical Mouse Sensor
Name
Description
1
NC
No Connect
I/O type
2
NC
No Connect
3
SDIO
Serial Port Data
I/O
4
SCLK
Serial Port Clock
I
5
LED_CNTL
Digital Shutter Signal Out
O
6
GND
System Ground
Ground
7
VDD5
5V DC Input
Power
8
REFA
Internal Reference
O
LED_CNTL
5
GND
6
VDD5
7
REFA
8
A5060 XYYWWZ
Pin
Figure 1. Package outline drawing (top view)
4
SCLK
3
SDIO
2
NC
1
NC
Figure 2. Package outline drawing
Overview of Optical Mouse Sensor Assembly
Avago Technologies provides an IGES file drawing describing the base plate molding features for lens and PCB
alignment.
The ADNS-5060 sensor is designed for mounting on a
through-hole PCB, looking down. There is an aperture
stop and features on the package that align to the lens.
The HDNS-2100/2100#001 lens provides optics for the
imaging of the surface as well as illumination of the
Figure 3. Recommended PCB mechanical cutouts and spacing
surface at the optimum angle. Features on the lens align it
to the sensor, base plate, and clip with the LED.
The HDNS-2200 clip holds the LED in relation to the lens.
The LED must be inserted into the clip and the LED’s leads
formed prior to loading on the PCB.
The HLMP-ED80 LED is recommended for illumination.
Figure 4. 2D Assembly drawing of ADNS-5060 (top and side view)
Clip
(HDNS-2200#001)
Sensor
LED
(HLMP-ED80)
Customer supplied
PCB
Lens
(HDNS-2100/
HDNS-2100#001)
Customer supplied
base plate with
recommended
alignment features
per IGES drawing
Figure 5. Exploded view drawing
PCB Assembly Considerations
Design considerations for improved ESD Performance
1. Insert the sensor and all other electrical components
into PCB.
For improved electrostatic discharge performance, typical
system creepage and clearance distance are shown in the
table below.
2. Insert the LED into the assembly clip and bend the
leads 90 degrees.
3. Insert the LED clip assembly into PCB.
4. Wave solder the entire assembly in a no-wash solder
process utilizing solder fixture. The solder fixture is
needed to protect the sensor during the solder process.
It also sets the correct sensor-to-PCB distance as the
lead shoulders do not normally rest on the PCB surface.
The fixture should be designed to expose the sensor
leads to solder while shielding the optical aperture
from direct solder contact.
5. Place the lens onto the base plate.
6. Remove the protective kapton tape from optical
aperture of the sensor. Care must be taken to keep
contaminants from entering the aperture. Recommend
not to place the PCB facing up during the entire mouse
assembly process. Recommend to hold the PCB first
vertically for the kapton removal process.
7. Insert PCB assembly over the lens onto the base plate
aligning post to retain PCB assembly. The sensor
aperture ring should self-align to the lens.
8. The optical position reference for the PCB is set by the
base plate and lens. Note that the PCB motion due to
button presses must be minimized to maintain optical
alignment.
9. Install mouse top case. There MUST be a feature in the top
case to press down onto the PCB assembly to ensure all
components are interlocked to correct vertical height.
SERIAL
PORT
IMAGE
PROCESSOR
LED _CNTL
LED
CONTROL
VOLTAGE REGULATOR
AND POWER CONTROL
SERIAL SCLK
PORT SDIO
REFA VOLTAGE
REFERENCE
VDD5 5 VOLT
GND POWER
Figure 6. Block diagram of ADNS-5060 optical mouse sensor
Assumption: Base plate construction as per the Avago
Technologies supplied IGES file and HDNS-2100/2100#001
lens.
Typical Distance
HDNS-2100
round lens
HDNS-2100#001
trim lens
Creepage (mm)
40.5
17.9
Clearance (mm)
32.6
9.2
Note that the lens material is polycarbonate and therefore, cyanoacrylate
based adhesives or other adhesives that may damage the lens should
NOT be used.
33R
33R
GND1
GND1
GND1
33pF
VCC1
33pF
RΩ
7 Vpp
QB
QA
10
6MHz
(Optional)
VS S 6
P0.1 2
P0.2 3
P0.3 4
P0.7 15
P0.6 16
9
R
Buttons
M
L
GN D1
4.7uF
GN D1
GN D1
0.1uF
10nF
GN D1
P0.5 17
XTALIN
USB MC U
11
VDD
VCC 1
22uH
XT ALOUT
1 P0.0
14 P1.1
5 P1.0
8 Vreg
12 D-
GN D1 13 D+
ZLED
VDD
GND
1.3KΩ
0.1 uF
10uF/16V
22uH
Figure 7a. Schematic Diagram for Interface between ADNS-5060 and Microcontroller (compatible with A26x0 sensors)
SHL D
GND
D-
D+
VDD
10nF
VC C
VCC 1
4 SC LK
3 SD IO
6 GND
7
VDD5
A5060
REFA 8
NC 2
NC 1
LE D_CNTL 5
Internal
Image
Se nsor
2.2uF
GN D1
1KΩ
100KΩ
2N3906
HLMP-E D80-xx000
(R ecommended: B in P)
32Ω
33R
33R
GND1
GND1
33pF
VC C1
GND1
33pF
ZLED
QB
VDD
RΩ
QA
GND
1.3KΩ
GND1
VS S 6
P0.1 2
P0.2 3
P0.3 4
P0.7 15
P0.6 16
P0.5 17
4.7µF
22uH
6MHz
(Optional)
XTALIN
9
USB MC U
XT ALOUT
10
1 P0.0
14 P1.1
5 P1.0
8 Vreg
12 D-
13 D+
7 Vpp
11
VDD
VCC1
10uF/16V
22uH
R
Buttons
M
L
GN D1
GND1
7
VDD5
4 SC LK
3 SD IO
6 GND
10nF
GN D1
0.1µF
GN D1
Figure 7b. Schematic Diagram for Interface between ADNS-5060 and Microcontroller (using internal LED driver)
SH LD
GND
D-
D+
VDD
0.1 µF
10nF
VC C
VC C1
A5060
5
RE FA 8
NC 2
GND1
2.2µF
HLMP-E D80-XX 000
(R ecommended: B in P)
NC 1
LE D_CNTL
Internal
Image
Se nsor
Regulatory Requirements
• Passes FCC B and worldwide analogous emission limits when assembled into a mouse with shielded cable and
following Avago Technologies recommendations.
• Passes IEC-1000-4-3 radiated susceptibility level when assembled into a mouse with shielded cable and following
Avago Technologies recommendations.
• Passes EN61000-4-4/IEC801-4 EFT tests when assembled into a mouse with shielded cable and following Avago
Technologies recommendations.
• UL flammability level UL94 HB.
• Provides sufficient ESD creepage/clearance distance to avoid discharge up to 15kV when assembled into a mouse
using HDNS-2100 round lens according to usage instructions above.
Absolute Maximum Ratings
Parameter
Symbol
Minimum
Maximum
Units
Storage Temperature
TS
-40
85
°C
Operating Temperature
TA
-15
55
°C
260
°C
5.5
V
2
kV
All pins, human body model MIL 883 Method 3015
Lead Solder Temp
Supply Voltage
VDD
-0.5
ESD
Notes
For 10 seconds, 1.6mm below seating plane.
Input Voltage
VIN
-0.5
VDD+0.5
V
SDIO, SCLK, LED_CNTL
Input Voltage
VIN
-0.5
3.6
V
REFA
10
Recommended Operating Conditions
Parameter
Symbol
Minimum
Operating Temperature
TA
0
Power supply voltage
VDD
4.10
Power supply rise time
Typical
Maximum Units
Notes
40
°C
5.5
V
VRT
100
ms
Supply noise
VN
100
mV
Peak to peak within 0-50 MHz bandwidth
Serial Port Clock
Frequency
fSCLK
3
MHz
550% duty cycle.
Distance from lens
reference plane to surface
Z
2.5
mm
Results in ±0.1 mm DOF, (See Figure 8)
Speed
S
Acceleration
A
SDIO read hold time
tHOLD
100
ns
Hold time for valid data (Refer to Figure 20)
SDIO serial write-write
time
tSWW
100
us
Time between two write commands.
(Refer to Figure 22)
SDIO serial write-read
time
tSWR
100
us
Time between write and read operation.
(Refer to Figure 23)
SDIO serial read-write
time
tSRW
250
ns
Time between read and write operation.
(Refer to Figure 24)
SDIO serial read-read
time
tSRR
250
ns
Time between two read commands.
(Refer to Figure 24)
SPI Read Address-Data
Delay
tSRAD
4
us
From rising SCLK for last bit of the address
byte, to falling SCLK for first bit of data
being read. (Refer to Figure 24)
Data delay after PD
deactivated
tCOMPUTE 3.1
ms
After tCOMPUTE, all registers contain data
from first image after wakeup from
Power-Down mode. Note that an additional
75 frames for AGC stabilization may be
required if mouse movement occurred
while Power Down. (refer to Figure 9)
SDIO write setup time
tsetup
ns
Data valid time before the rising of SCLK.
(refer to Figure 17)
2.3
2.4
30
in/sec
8
60
ADNS-5060
HDNS-2100
Z
OBJECT SURFACE
Figure 8. Distance from Lens Reference Plane to Surface
11
5.0
g
AC Electrical Specifications
Electrical Characteristics over recommended operating conditions. Typical values at 25°C, VDD=5.0 V
Parameter
Symbol
Min.
Power Down (PD)
tPD
1.33
Power Up after PowerDown mode deactivated
tPUPD
Power Up from VDD ↑
tPU
Rise and Fall Times:
SDIO
tr
Units
Notes
us
32 clock cycle minimum after setting bit 6 in
the Configuration register.
(refer to Figure 11)
50
ms
From Power-Down mode deactivation to
accurate reports 610 us + 75 frames
(refer to Figure 9)
40
ms
From VDD valid to accurate reports
610 us + 50 frames
30
ns
CL = 30 pF (the rise time is between
10% to 90%)
tf
16
ns
CL = 30 pF (the fall time is between
10% to 90%)
Serial Port transaction
timer
tSPTT
90
ms
Serial port will reset if current transaction is
not complete within tSPTT.
(refer to Figure 26)
Transient Supply Current
IDDT
mA
Max supply current during a VDD ramp
from 0 to 5.0 V with > 500 us rise time.
Does not include charging currents for
bypass capacitors.
12
Typical
Max.
70
DC Electrical Specifications
Electrical Characteristics over recommended operating conditions. Typical values at 25°C, VDD=5.0 V.
Parameter
Symbol
Minimum Typical
Supply Current
(mouse moving)
IDD AVG
17.5
Supply Current
(mouse not moving)
IDD
13
Power-down Mode
Current
IDDPD
180
Maximum Units
Notes
20
Average sensor only current, at max
frame rate. No load on SDIO.
mA
mA
250
uA
0.8
V
SCLK pin
Input Low Voltage
VIL
Input High Voltage
VIH
Input Capacitance
CIN
Input Resistance
RIN
2.0
V
10
1
pF
MΩ
SDIO pin
VDD=4V, Load = 50pF, 80ns rise & fall
Input Low Voltage
VIL
0.8
Input High Voltage
VIH
Output Low Voltage
VOL
Output High Voltage
VOH
0.8*VDD
V
Drive Low Current
IL
2.0
mA
Drive High Current
IH
2.0
mA
Input Capacitance
CIN
Input Resistance
RIN
2.0
V
V
0.5
10
1
V
pF
MΩ
LED_CNTL pin
(Schematic A)
Output Low Voltage
VOL
0.1
V
Output High Voltage
VOH
0.8*VDD
V
Drive Low Current
IL
250
uA
Drive High Current
IH
250
μA
With 1kW connected to base of transistor
LED_CNTL pin
(Schematic B)
LED_CNTL Current
during run mode
(pin voltage range
should be greater
than 0.8V)
ILED_CNTL_run
45
LED_CNTL Peak Current
(pin voltage range
should be greater
than 0.8V)
IXY_PK
45
LED_CNTL Current
during mouse not
moving
ILED_CNTL_rest
25
mA
LED_CNTL Current
during power down
ILED_CNTL_pd
0.1
μA
13
50
mA
Average current at maximum frame rate
mA
Peak current at maximum frame rate
Power Down Deactivation Timing
Note: All timing circuits shown, from Figure 9 onwards, are based on the
24MHz resonator frequency.
Power Down deactivated
Power Down
Deactivation
IDD
75 frames
610 us
tpupd
tCOMPUTE (See Figure 12)
Figure 9. Power-up timing mode
Power Down deactivated
Power Down
Deactivation
Oscillator
Start
Reset
Count
250 us
360 us
Initialization
2410 us
New acquisition
LED
CURRENT
SCLK
610 us
Figure 10. Detail of wake-up timing after PD
14
Optional SPI transactions
with old image data
tcompute
SPI transactions
with new image data
At default frame rate
Power-down Mode (PD) and Timing
ADNS-5060 Power-down mode
ADNS-5060 can be placed in a power-down mode by
setting bit 6 in the configuration register via a serial I/O
port write operation. Note that while writing a “1” to bit 6
of the configuration register, all other bits must be written
with their original value in order to keep the current
configuration. After setting the configuration register,
wait at least 32 system clock cycles. To get the chip out
of the power-down mode, clear bit 6 in the configuration
register via a serial I/O port write operation. (CAUTION!
In power-down mode, the SPI timeout (tSPTT ) will not
function. Therefore, no partial SPI command should be
sent. Otherwise, the sensor may go into a hang-up state).
While the sensor is in power-down mode, only the bit 6
data will be written to the configuration register. Writing
the other configuration register values will not have any
effect. For an accurate report after power-up, wait for a
total period of 50ms before the microcontroller is able
to issue any write/read operation to the ADNS-5060. The
sensor register settings, prior to power-down mode, will
remain during power-down mode.
CLK
32 clock cycles min
SCLK
1
SDIO
A6
A5
A4
A3
D5
D4 D3
D2
D1
D0
IDD
tPD
Figure 11: Power-down timing
The address of the configuration register is 1000000 (retail
option). Assume that the original content of the configuration register is 0x00.
SCLK
Write
Operation
1
Con-guration Register Address
1
0
0
0
0
0
Con-guration Register Data (0x40)
0
0
1
SDIO
Figure 12: Power Down configuration register writing operation
Setting the power down bit simply sets the analog circuitry
into a no current state.
Note: LED_CNTL and SDIO will be tri-stated during power down mode.
15
0
0
0
0
0
0
Typical Performance Characteristics
The following graphs (Figures 13-15) are the typical performance of the ADNS-5060 sensor, assembled as shown in the
2D assembly drawing with the HDNS-2100 Lens, the HDNS-2200 clip, and the HLMP-ED80-xx000 (See Figure 4).
Resolution vs Z
1200
Manila
White Paper
Black Formica
Spruce Wood
Resolution (cpi)
1000
800
600
400
200
0
1.6
1.8
2
3
2.2
2.4
2.6
2.8
3.2
Distance from Lens Reference Plane to Tracking Surface, Z (mm)
3.4
Figure 13. Resolution (based on 1050cpi setting) vs. Z (mm)
Average Path Error vs Z
25
Manila
Black Formica
White Paper
Spruce Wood
Resolution (cpi)
20
15
10
5
0
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
Distance from Lens Reference Plane to Tracking Surface, Z (mm)
3.4
Normalized Response
Figure 14. Average error vs. distance (mm)
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
400
500
600
Figure 15. Relative wavelength responsivity
16
700
Wavelength (nm)
800
900
1000
LED Mode
Write Operation
For optimized tracking performance, the LED is in DC
mode when motion is detected, and ADNS-5060 will pulse
the LED when the mouse is in idle state.
Write operations, where data is going from the microcontroller to the ADNS-5060, is always initiated by the
microcontroller and consists of two bytes. The first byte
contains the address (seven bits) and has a “1” as its MSB
to indicate data direction. The second byte contains the
data. The transfer is synchronized by SCLK. The microcontroller changes SDIO on falling edges of SCLK. The ADNS5060 reads SDIO on rising edges of SCLK.
Synchronous Serial Port
The synchronous serial port is used to set and read
parameters in the ADNS-5060, and to read out the motion
information.
The port is a two wire, half duplex serial port. The host
micro-controller always initiates communication; the
ADNS-5060 never initiates data transfers.
The lines that comprise the SPI port:
SCLK: Clock input. It is always generated by the master
(the micro-controller).
SDIO: Input and Output data.
SCLK
Cycle #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
A6
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
SCLK
SDIO
SDIO Driven by Microcontroller
Figure 16. Write operation
1/(2 fSCLK) 1/(2 fSCLK)
SCLK
SDIO
250ns, min
tsetup = 60ns, min
Figure 17. SDIO setup and hold times SCLK pulse width
17
DON'T
CARE
Read Operation
A read operation, means data that is going from the ADNS5060 to the microcontroller, is always initiated by the microcontroller and consists of two bytes. The first byte that
contains the address is written by the microcontroller and
has a “0” as its MSB to indicate data direction. The second
byte contains the data and is driven by the ADNS-5060.
The transfer is synchronized by SCLK. SDIO is changed on
falling edges of SCLK and read on every rising edge of SCLK.
SCLK
Cycle #
1
2
3
4
5
6
7
8
0
A6
A5
A4
A3
A2
A1
The microcontroller must go to a high-Z state after the
last address data bit. The ADNS-5060 will go to the high-Z
state after the last data bit. Another thing to note during a
read operation is that SCLK needs to be delayed after the
last address data bit to ensure that the ADNS-5060 has at
least 100 us to prepare the requested data. This is shown
in the timing diagrams below (See Figures 18 to 20).
9
10
11
12
13
14
15
16
D7
D6
D5
D4
D3
D2
D1
D0
SCLK
SDIO
A0
SDIO Driven by Micro-Controller
SDIO Driven by ADNS-5060
Detail "A"
Detail "B"
Figure 18. Read operation
Detail “A”
250ns,max
tSRAD
SCLK
Microcontroller
to ADNS-5060
SDIO handoff
0ns, min
60ns, min
SDIO
A0
A1
250ns, min
250ns,max
Hi-Z
D7
D6
160ns, min
Figure 19. Microcontroller to ADNS-5060 SDIO handoff
Detail “B”
tHOLD
SCLK
ADNS-5060 to
Microcontroller
SDIO hando-
160ns, max
SDIO
D0
Released by ADNS-5060
Figure 20. ADNS-5060 to microcontroller SDIO handoff
18
R/W bit of next address
Driven by microcontroller
NOTE: The 250 ns high state of SCLK is the minimum data
hold time of the ADNS-5060. Since the falling edge of SCLK
is actually the start of the next read or write command, the
ADNS-5060 will hold the state of D0 on the SDIO line until
the falling edge of SCLK. In both write and read operations,
SCLK is driven by the microcontroller.
Forcing the SDIO line to the Hi-Z state
There are times when the SDIO line from the ADNS-5060
should be in the Hi-Z state. For example, if the microprocessor has completed a write to the ADNS-5060, the SDIO
line will go into a Hi-Z state because the SDIO pin was configured as an input. However, if the last operation from the
microprocessor was a read, the ADNS-5060 will hold the
D0 state on SDIO until a falling edge of SCLK.
PD
Timing
To place the SDIO pin into a Hi-Z state, activate the powerdown mode by writing to the configuration register. Then,
the power-down mode can stay activated, with the ADNS5060 in the shutdown state. Or the power down mode
can be deactivated, returning the ADNS-5060 to normal
operation. In both conditions, the SDIO line will go into
the Hi-Z state.
PD
Activated
32
clock
cycles
10ns, max
SDIO
Hi-Z
Figure 21. SDIO Hi-Z state and timing
Another method to put the SDIO line into the Hi-Z state,
while maintaining the ADNS-5060 at normal mode, is
to write any data to an invalid address such as 0x00 to
address 0x77. The SDIO line will go into the Hi-Z state after
the write operations.
Required Timing between Read and Write Commands (tsxx)
There are minimum timing requirements between read
and write commands on the serial port.
tSWW ≥100µs
SCLK
Address
Data
Address
Write Operation
Data
Write Operation
Figure 22. Timing between two write commands
If the rising edge of the SCLK for the last data bit of the
second write command occurs before the 100 us required
delay, then the first write command may not complete
correctly.
tSWR ≥100µs
SCLK
Address
Data
Write Operation
Figure 23. Timing between write and read commands
19
Address
Next Read Operation
If the rising edge of SCLK for the last address bit of the
read command occurs before the 100 us required delay,
then the write command may not complete correctly.
tSRW, tSRR ≥250ns
tSRAD
SCLK
Address
Data
Read Operation
Address
Next Read or
Write Operation
Figure 24. Timing between read and either write or subsequent read commands
The falling edge of SCLK for the first address bit of either
the read or write command must be at least 250 ns after
the last SCLK rising edge of the last data bit of the previous
read operation.
Error Detection and Recovery
1. The ADNS-5060 and the microcontroller might get out
of synchronization due to ESD events, power supply
droops or microcontroller firmware flaws.
2. The ADNS-5060 has a transaction timer for the serial
port. If the sixteenth SCLK rising edge is spaced more
than approximately 90 milliseconds from the first SCLK
edge of the current transaction, the serial port will
reset.
3. Invalid addresses:
– Writing to an invalid address will have no effect.
Reading from an invalid address will return all zeros.
4. Collision detection on SDIO
– The only time that the ADNS-5060 drives the SDIO
line is during a READ operation. To avoid data
collisions, the microcontroller should relinquish SDIO
before the falling edge of SCLK after the last address
bit. Then the ADNS-5060 begins to drive SDIO after
the next rising edge of SCLK. Next, the ADNS-5060
relinquishes SDIO within 160 ns of the falling SCLK
edge after the last data bit. The microcontroller
can begin driving SDIO any time after that. In order
to maintain low power consumption in normal
operation or when the PD pin is set high, the
microcontroller should not leave SDIO floating until
the next transmission (although that will not cause
any communication difficulties).
20
5. In case of synchronization failure, both the ADNS-5060
and the microcontroller may drive SDIO. The ADNS5060 can withstand 30 mA of short circuit current
and will withstand infinite duration short circuit
conditions.
6. The microcontroller can verify a successful write
operation by issuing a read command to the same
address and comparing the written data to the read
data.
7. The microcontroller can verify the synchronization of
the serial port by periodically reading the product ID
from status register (Address: 0x41).
Notes on Power-up and the Serial Port
The sequence in which VDD, SCLK and SDIO are set during
power-up can affect the operation of the serial port. The
diagram below shows what can happen shortly after
power-up when the microprocessor tries to read data
from the serial port.
VDD
SCLK
Address = 0x41
Data = 0x0b010XXXXX
SDIO
Problem Area
Figure 25. Power-up serial port sequence
This diagram shows the VDD rising to valid levels, at some
point the microcontroller starts it’s program, sets the SCLK
and SDIO lines to be outputs, and sets them high. Then,
the microcontroller waits to ensure the ADNS-5060 has
powered up and is ready to communicate. The microprocessor then tries to read from location 0x41, Status
register, and is expecting a value of 0x0b010XXXXX. If it
receives this value, then it knows the communication to
the ADNS-5060 is operational.
The problem occurs if the ADNS-5060 powers up before
the microprocessor sets the SCLK and SDIO lines to be
outputs and high. The ADNS-5060 sees the raising of the
SCLK as a valid rising edge, and clocks in the state of the
SDIO as the first bit of the address (sets either a read or a
write, depending upon the state).
In the case of a SDIO low, a read operation will start. When
the microprocessor actually begins to send the address,
the ADNS-5060 already has the first bit of an address.
When the seventh bit is sent by the microprocessor, the
ADNS-5060 has a valid address, and drives the SDIO line
high within 250 ns (see detail “A” in Figure 18 and Figure
19). This results in a bus fight for SDIO. Since the address
is wrong, the data sent back would be incorrect.
In the case of a SDIO high, a write operation will start. The
address and data will be out of synchronization, causing
the wrong data written to the wrong address.
Solution
One way to solve the problem is by waiting for the serial
port timer to time out.
1. Serial Port Timer Timeout
VDD
>tSPTT
SCLK
Address = 0x41
Data = 0x0b010XXXXX
SDIO
Don't Care State
Figure 26. Power up serial port timer sequence
21
Soft Reset
If the microprocessor waits at least tSPTT from VDD valid,
it will ensure that the ADNS-5060 has powered up and
the timer has timed out. This assumes that the microprocessor and the ADNS-5060 share the same power
supply. If not, then the microprocessor must wait for tSPTT
from ADNS-5060 VDD valid. Then when the SCLK toggles
for the address, the ADNS-5060 will be in-sync with the
microprocessor.
ADNS-5060 may also be given the reset command at any
time via the serial I/O port. The timing and transactions
are the same as those just specified for the power-up
mode in the previous section.
The proper way to perform soft reset on ADNS-5060 is:
1. The microcontroller starts the transaction by sending
a write operation containing the address of the
configuration register and the data value of 0x80. Since
the reset bit is set, ADNS-5060 will reset and any other
bits written into the configuration register at this time
is properly written into the Configuration Register.
After the chip has been reset, very quickly, ADNS5060 will clear the reset bit so there is no need for the
microcontroller to re-write the Configuration Register
to reset it.
Resync Note
If the microprocessor and the ADNS-5060 get out of sync,
then the data either written or read from the registers will
be incorrect. An easy way to solve this is to use watchdog
timer timeout sequence to resync the parts after an
incorrect read.
Power-up
ADNS-5060 has an on-chip internal power-up reset (POR)
circuit, which will reset the chip when VDD reaches the
valid value for the chip to function.
2. The digital section is now ready to go. It takes 3 frames
for the analog section to settle.
CLK
Reset Occurs
here
SCLK
1
SDIO
A6
A5
A4
A3
D5
D4
D3
D2
D1
D0
Figure 27. ADNS-5060 soft reset sequence timing
Soft reset will occur when writing 0x80 to the configuration register.
SCLK
Write
Operation
1 1
Con-guration Register Address
0
0
0
0
0
SDIO
Figure 28. Soft reset configuration register writing operation
22
Con-guration Register Data (0x80)
0
1
0
0
0
0
0
0
0
Registers
The ADNS-5060 registers are accessible via the serial port. The registers are used to read motion data and status as well
as to set the device configuration.
Address
Register
Read/Write
Default Value
0x00
Configuration1
R/W
0x00
0x01
Status1
R
0x01
0x02
Delta_Y1
R
0x00
0x03
Delta_X1
R
0x00
0x04
SQUAL1
R
0x00
0x05
Maximum_Pixel1
R
0x00
0x06
Minimum_Pixel1
R
0x3f
0x07
Pixel_Sum1
R
0x00
0x08
Pixel_Data1
R
0x00
0x09
Shutter_Upper1
R
0x01
0x0a
Shutter_Lower1
R
0x00
0x0b
Pixel_Grab
R/W
0x00
0x14
Product_ID2a
R
0x10
0x15
Product_ID2b
R
0x1N
0x16
Motion2
R
0x00
0x17
Delta_X2
R
0x00
0x18
Delta_Y2
R
0x00
0x19
SQUAL2
R
0x00
0x1a
Operation_Mode2
R/W
0x04
0x1b
Configuration2
R/W
0x00
0x33
Mouse_Control
R/W
0x07
0x40
Configuration3
R/W
0x00
0x41
Status3
R
0x41
0x42
Delta_Y3
R
0x00
0x43
Delta_X3
R
0x00
0x44
SQUAL3
R
0x00
0x45
Maximum_Pixel3
R
0x00
0x46
Minimum_Pixel3
R
0x3f
0x47
Pixel_Sum3
R
0x00
0x48
Pixel_Data3
R
0x00
0x49
Shutter_Upper3
R
0x01
0x4a
Shutter_Lower3
R
0x00
23
Configuration1
Access: Read/Write
Address: 0x00
Reset Value: 0x00
Bit
7
6
Field
Reset
PD
5
4
3
2
1
Reserved [1:5]
0
FWake
Data Type: Bit field
USAGE: The Configuration register allows the user to change the configuration of the sensor. Shown below are the bits,
their default values, and optional values.
Field Name
Description
Reset
Reset
0 = Normal operation
1 = Reset the part
PD
Power down
0 = Normal operation
1 = power down all analog circuitry
FWake
Forced Awake Mode
0 = Normal, fall asleep after one second of no movement
1 = Always awake
Status1
Access: Read
Address: 0x01
Reset Value: 0x01
Bit
7
6
5
Field
ID2
ID1
ID0
4
3
2
Reserved
Data Type: Bit field
USAGE: Status information and type of mouse sensor, current state of the mouse.
Field Name
Description
ID2 -ID0
Product ID (0b000)
Awake
Mouse State
0 = Asleep
1 = Awake
24
1
0
Awake
Delta_Y1
Access: Read
Address: 0x02
Reset Value: 0x00
Bit
7
6
5
4
3
2
1
0
Field
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
Data Type: Eight bit 2’s complement number.
USAGE: Y movement is counted since last report. Absolute value is determined by resolution. Reading clears the register.
Motion
-128
-127
-2
-1
0
+1
+2
+126
+127
Delta_Y
80
81
FE
FF
00
01
02
7E
7F
NOTES: Register 0x02 MUST be read prior to Register 0x03.
Delta_X1
Access: Read
Address: 0x03
Reset Value: 0x00
Bit
7
6
5
4
3
2
1
0
Field
X7
X6
X5
X4
X3
X2
X1
X0
Data Type: Eight bit 2’s complement number.
USAGE: X movement is counted since last report. Absolute value is determined by resolution. Reading clears the register.
Motion
Delta_X
-128
-127
-2
-1
0
+1
+2
+126
+127
80
81
FE
FF
00
01
02
7E
7F
NOTES: Register 0x02 MUST be read prior to Register 0x03.
25
SQUAL1
Access: Read
Address: 0x04
Reset Value: 0x00
Bit
7
6
5
4
3
2
1
0
Field
SQ7
SQ6
SQ5
SQ4
SQ3
SQ2
SQ1
SQ0
Data Type: Upper 8 bits of a 9-bit integer.
USAGE: SQUAL (Surface QUALity) is a measure of the number of features visible by the sensor in the current frame.
The maximum value is 128. Since small changes in the current frame can result in changes in SQUAL, variations
in SQUAL are expected, when looking at a surface. The graph below shows 250 sequentially acquired SQUAL
values, while a sensor was moved slowly over white paper. SQUAL is nearly equal to zero when there is no
surface below the sensor.
70
60
Squal value
50
40
30
20
10
0
1
50
99 148 197 246 295 344 393 442 491 540 589 638 687 736 785
Count
80
Avg-3sigma
Avg
Avg+3sigma
70
Squal count
60
50
40
30
20
10
0
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
Distance from Lens Reference Plane to Tracking Surface, Z (mm)
Figure 29. Typical mean SQUAL vs. z (white paper)
26
3.4
Maximum_Pixel1
Access: Read
Address: 0x05
Reset Value: 0x00
Bit
7
6
5
4
3
2
1
0
Field
O
MP6
MP5
MP4
MP3
MP2
MP1
MP0
Data Type: Six bit number.
USAGE: Maximum Pixel value in current frame. Minimum value = 0, maximum value = 127. The maximum pixel value
may vary from frame to frame. Shown below is a graph of 250 sequentially acquired maximum pixel values,
while the sensor was moved slowly over white paper.
Max Pixel on White Paper
120
110
100
Max Pixel
90
80
70
60
50
40
30
20
Count
Figure 30. Maximum Pixel on White Paper
27
800
750
700
650
600
550
500
450
400
350
300
250
200
150
100
50
0
10
0
Minimum_Pixel1
Access: Read
Address: 0x06
Reset Value: 0x3f
Bit
7
6
5
4
3
2
1
0
Field
O
MP6
MP5
MP4
MP3
MP2
MP1
MP0
Data Type: Six bit number.
USAGE: Minimum Pixel value in current frame. Minimum value = 0, maximum value = 127. The minimum pixel value may
vary from frame to frame.
Min Pixel on White Paper
80
70
60
Min Pixel
50
40
30
20
10
Count
Figure 31. Minimum Pixel on White Paper
28
800
750
700
650
600
550
500
450
400
350
300
250
200
150
100
50
0
0
Pixel_Sum1
Access: Read
Address: 0x07
Reset Value: 0x00
Bit
7
6
5
4
3
2
1
0
Field
PS7
PS6
PS5
PS4
PS3
PS2
PS1
PS0
Data Type: Upper 8 bits of a 15-bit unsigned integer.
USAGE: This register is used to find the average pixel value. It reports the upper 8 bits of a 15-bit unsigned integer, which
sums all 361 pixels in the current frame. It may be described as the full sum divided by 128. The formula to
calculate the average pixel value is as below:
Average Pixel = Register Value x 128/361
= Pixel_Sum x 0.355
The maximum register value is 178 (63 x 361 / 128 truncated to an integer). The minimum is 0. The pixel sum
value may vary from frame to frame.
Pixel Data1
Access: Read/Write
Address: 0x08
Reset Value: 0x00
Bit
7
6
5
4
3
2
1
0
Field
SOF
Data_Valid
PD5
PD4
PD3
PD2
PD1
PD0
Data Type: Two status bits, six bit pixel data.
USAGE: Digital Pixel data. Minimum value = 0, maximum value = 63. Any writes to this register resets the pixel hardware
so that the next read from the Pixel Data register will read pixel #1 and the StartOfFrame bit will be set. Subsequent reads will auto increment the pixel number.
To dump a complete image, set the LED to forced awake mode, write anything to this register, then read 361
times where the DataValid bit is set. On the 362th read, the StartOfFrame bit will be set indicating that we have
completed one frame of pixels and are starting back at pixel 1.
It takes at least 361 frames to complete an image as we can only read 1 pixel per frame.
The pixel hardware is armed with any read or write to the Pixel Data register and will output pixel data from
the next available frame. So, if you were to write the Pixel Data register, wait 5 seconds then read the Pixel Data
register; the reported pixel data was from 5 seconds ago.
Field Name
Description
SOF
Start of Frame
0 = Not start of frame
1 = Current pixel is number 1, start of frame
Data_Valid
There is valid data in the frame grabber
PD5– PD0
Six bit pixel data
29
Pixel Map (sensor is facing down, looking through the sensor and lens at the surface)
Last Pixel
18
37
56
75
94
113
132
151
170
189
208
227
246
265
284
303
322
341
360
17
36
55
74
93
112
131
150
169
188
207
226
245
264
283
302
321
340
359
16
35
54
73
92
111
130
149
168
187
206
225
244
263
282
301
320
339
358
15
34
53
72
91
110
129
148
167
186
205
224
243
262
281
300
319
338
357
14
33
52
71
90
109
128
147
166
185
204
223
242
261
280
299
318
337
356
13
32
51
70
89
108
127
146
165
184
203
222
241
260
279
298
317
336
355
12
31
50
69
88
107
126
145
164
183
202
221
240
259
278
297
316
335
354
11
30
49
68
87
106
125
144
163
182
201
220
239
258
277
296
315
334
353
10
29
48
67
86
105
124
143
162
181
200
219
238
257
276
295
314
333
352
9
28
47
66
85
104
123
142
161
180
199
218
237
256
275
294
313
332
351
8
27
46
65
84
103
122
141
160
179
198
217
236
255
274
293
312
331
350
7
26
45
64
83
102
121
140
159
178
197
216
235
254
273
292
311
330
349
6
25
44
63
82
101
120
139
158
177
196
215
234
253
272
291
310
329
348
5
24
43
62
81
100
119
138
157
176
195
214
233
252
271
290
309
328
347
4
23
42
61
80
99
118
137
156
175
194
213
232
251
270
289
308
327
346
3
22
41
60
79
98
117
136
155
174
193
212
231
250
269
288
307
326
345
2
21
40
59
78
97
116
135
154
173
192
211
230
249
268
287
306
325
344
1
20
39
58
77
96
115
134
153
172
191
210
229
248
267
286
305
324
343
0
19
38
57
76
95
114
133
152
171
190
209
228
247
266
285
304
323
342
First Pixel
Figure 32. Pixel Map
30
Shutter_Upper1
Access: Read
Address: 0x09
Reset Value: 0x01
Bit
7
6
5
4
3
2
1
0
Field
S15
S14
S13
S12
S11
S10
S9
S8
Shutter_Lower1
Access: Read
Address: 0x0A
Reset Value: 0x00
Bit
7
6
5
4
3
2
1
0
Field
S7
S6
S5
S4
S3
S2
S1
S0
Data Type: Sixteen bit word.
USAGE: Units are clock cycles; default value is 0x0100. Read Shutter_Upper first, then Shutter_Lower. They should be read
consecutively. The shutter is adjusted to keep the average and maximum pixel values within normal operating
ranges. The shutter value can be adjusted to a new value on every frame. When the shutter adjusts, it changes
by ± 1/16 of the current value. Shown below is a graph of 250 sequentially acquired shutter values, while the
sensor was moved slowly over white paper.
160
140
Shutter value
120
100
80
60
40
20
0
1 40 79 118 157 196 235 274 313 352 391 430 469 508 547 586 625 664 703 742 781
Count
300
Avg-3sigma
Avg
Avg+3sigma
Shutter value (Count)
250
200
150
100
50
0
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
Distance from Lens Reference Plane to Tracking Surface, Z (mm)
Figure 33. Typical mean shutter vs. z (white paper)
31
3.4
Pixel_Grab
Access: Read/Write
Address: 0x0b
Reset Value: 0x00
Bit
7
6
5
4
3
2
1
0
Field
Valid
PD6
PD5
PD4
PD3
PD2
PD1
PD0
Data Type: Eight-bit word.
USAGE: The pixel grabber captures 1 pixel per frame. If there is a valid pixel in the grabber when this register is read, the
MSB will be set, an internal counter will incremented to capture the next pixel and the grabber will be armed to
capture the next pixel. It will take 361 reads to upload the complete image. Any write to this register will reset
and arm the grabber to grab pixel 0 on the next image.
Product_ID2a
Access: Read
Address: 0x14
Reset Value: 0x10
Bit
7
6
5
4
3
2
1
0
Field
PID7
PID6
PID5
PID4
PID3
PID2
PID1
PID0
Data Type: 8-Bit unsigned integer.
USAGE: The value in this register does not change; it can be used to verify if the serial communications link is functional.
Product_ID2b
Access: Read
Address: 0x15
Reset Value: 0x1N
Bit
7
6
5
4
Field
PID3
PID2
PID1
PID0
3
2
1
0
Reserved
Data Type: 8-Bit unsigned integer.
USAGE: The value in this register does not change; upper nibble can be used to verify if the serial communications link
is functional.
32
Motion2
Access: Read
Address: 0x16
Reset Value: 0x00
Bit
7
Field
MOT
6
5
Reserved
4
3
OVFY
OVFX
2
1
Reserved
0
RES
Data Type: Bit field.
USAGE: Register 0x16 allows the user to determine if motion has occurred since the last time it was read. If the MOT bit is
set, then the user should read registers 0x17 and 0x18 to get the accumulated motion. Read this register before
reading the Delta_X and Delta_Y registers. It also tells if the motion buffers have overflowed and the current
resolution is also shown.
Field Name
Description
MOT
Motion since last report
0 = No motion
1 = Motion occurred, data ready for reading in Delta_X and Delta_Y registers
OVFY
Motion overflow Y, ∆Y buffer has overflowed since last report
0 = No overflow
1 = Overflow has occurred
OVFX
Motion overflow X, ∆X buffer has overflowed since last report
0 = No overflow
1 = Overflow has occurred
RES
Resolution in counts per inch
0 = 1050
1 = 600
33
Delta_X2
Access: Read
Address: 0x17
Reset Value: 0x00
Bit
7
6
5
4
3
2
1
0
Field
X7
X6
X5
X4
X3
X2
X1
X0
Data Type: Eight-bit word.
USAGE: X movement is counts since last report. Absolute value is determined by resolution. Reading clears the
register.
Motion
Delta_X
-128
-127
-2
-1
0
+1
+2
+126
+127
80
81
FE
FF
00
01
02
7E
7F
NOTES: Register 0x17 MUST be read prior to Register 0x18.
Delta_Y2
Access: Read
Address: 0x18
Reset Value: 0x00
Bit
7
6
5
4
3
2
1
0
Field
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
Data Type: Eight bit 2’s complement number.
USAGE: Y movement is counts since last report. Absolute value is determined by resolution. Reading clears the register.
Motion
-128
-127
-2
-1
0
+1
+2
+126
+127
Delta_Y
80
81
FE
FF
00
01
02
7E
7F
NOTES: Register 0x17 MUST be read prior to Register 0x18.
SQUAL2
Access: Read
Address: 0x19
Reset Value: 0x00
Bit
7
6
5
4
3
2
1
0
Field
SQ7
SQ6
SQ5
SQ4
SQ3
SQ2
SQ1
SQ0
Data Type: Upper 8 bits of a 9-bit integer.
USAGE: SQUAL (Surface QUALity) is a measure of the number of features visible by the sensor in the current frame.
The maximum value is 128. Since small changes in the current frame can result in changes in SQUAL, variations
in SQUAL are expected, when looking at a surface. Figure 29 shows 250 sequentially acquired SQUAL values,
while a sensor was moved slowly over white paper. SQUAL is nearly equal to zero when there is no surface below
the sensor.
34
Operation_Mode2
Access: Read/Write
Address: 0x1a
Reset Value: 0x04
Bit
7
6
Field
Reset
PD
5
4
Reserved
3
2
1
0
Sleep
FSleep
FWake
Data Type: Bit field.
USAGE: The Operation_Mode2 register allows the user to change the operation of the sensor. Shown below are the bits,
their default values, and optional values.
Operation_Mode2[2:0]
“0xx”=Disable sleep mode
“110”=Force enter sleep
“101”=Force wakeup from sleep mode
Notes:
1. After 1 sec not moving during normal mode, chip will enter sleep mode. The chip remains in sleep mode until motion is detected or wakeup is
asserted.
2. Only either one of these two bits FSleep and FWake can be set to 1 at the same time, others have to be set to 0. After a period of time, the bits which
were set to 1, will be reset to 0 by internal signal.
Field Name
Description
Reset
Full Chip Reset
0 = Normal operation
1 = Reset the chip
PD
Power down
0 = Normal operation
1 = Power down all analog circuitry
Sleep
Sleep Mode Enable
0 = Disable
1 = Enable
FSleep
Force Enter Sleep Mode Manually
0 = Normal, fall asleep after one second of no movement
1 = Enter sleep mode and this bit will be reset to “0”
FWake
Manual Wake Up From Sleep Mode Manually
0 = Normal, fall asleep after one second of no movement
1 = Enter wake up mode and this bit will be reset to “0”
35
Configuration2
Access: Read/Write
Bit
7
Field
RES
Address: 0x1b
Reset Value: 0x00
6
5
4
3
2
1
0
Reserved
Data Type: Bit field.
USAGE: The Configuration2 register allows the user to change the configuration of the sensor. Shown below are the bits,
their default values, and optional values.
Field Name
Description
RES
Resolution in count per inch
0 = 1050
1 = 600
Mouse_Control
Access: Read/Write
Address: 0x33
Reset Value: 0x07
Bit
7
6
5
4
3
2
1
0
Field
Reserved
Reserved
Reserved
RES_EN
RES3
RES2
RES1
RES0
Data Type: Eight bit number.
USAGE: Resolution information can be accessed or to be edited by this register.
Field Name
Description
RES_EN
= 0 Disable RES[3:0] setting.
= 1 Enable RES[3:0] setting.
RES[3:0]
= 0b0001: 150 CPI
= 0b0010: 300 CPI
= 0b0011: 450 CPI
= 0b0100: 600 CPI
= 0b0101: 750 CPI
= 0b0110: 900 CPI
= 0b0111: 1050 CPI
= 0b1000: 1200 CPI
= 0b1001: 1350 CPI
Note: Bit 4 MUST be set to ‘1’ before the resolution set in this register takes effect.
36
Configuration3
Access: Read/Write
Address: 0x40
Reset Value: 0x00
Bit
7
6
Field
Reset
PD
5
4
3
2
1
Reserved
0
FWake
Data Type: Bit field.
USAGE: The Configuration register allows the user to change the configuration of the sensor. Shown below are the bits,
their default values, and optional values.
Field Name
Description
Reset
Reset
0 = Normal operation
1 = Reset the part
PD
Power down
0 = Normal operation
1 = Power down all analog circuitry
Fwake
Forced Awake Mode
0 = Normal, fall asleep after one second of no movement
1 = Always awake
Status3
Access: Read
Address: 0x41
Reset Value: 0x41
Bit
7
6
5
Field
ID2
ID1
ID0
4
3
2
Reserved
Data Type: Bit field.
USAGE: Status information and mouse sensor type, current state of the mouse.
Field Name
Description
ID2 - ID0
Product ID (0b010)
Awake
Mouse State
0 = Asleep
1 = Awake
37
1
0
AWake
Delta_Y3
Access: Read
Address: 0x42
Reset Value: 0x00
Bit
7
6
5
4
3
2
1
0
Field
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
Data Type: Eight bit 2’s complement number.
USAGE: Y movement is counts since last report. Absolute value is determined by resolution. Reading clears the register.
Motion
-128
-127
-2
-1
0
+1
+2
+126
+127
Delta_Y
80
81
FE
FF
00
01
02
7E
7F
NOTES: Register 0x42 MUST be read prior to Register 0x43.
Delta_X3
Access: Read
Address: 0x43
Reset Value: 0x00
Bit
7
6
5
4
3
2
1
0
Field
X7
X6
X5
X4
X3
X2
X1
X0
Data Type: Eight bit 2’s complement number.
USAGE: X movement is counts since last report. Absolute value is determined by resolution. Reading clears the register.
Motion
Delta_X
-128
-127
-2
-1
0
+1
+2
+126
+127
80
81
FE
FF
00
01
02
7E
7F
NOTES: Register 0x42 MUST be read prior to Register 0x43.
SQUAL3
Access: Read
Address: 0x44
Reset Value: 0x00
Bit
7
6
5
4
3
2
1
0
Field
SQ7
SQ6
SQ5
SQ4
SQ3
SQ2
SQ1
SQ0
Data Type: Upper 8 bits of a 9-bit integer.
USAGE: SQUAL (Surface QUALity) is a measure of the number of features visible by the sensor in the current frame.
The maximum value is 128. Since small changes in the current frame can result in changes in SQUAL, variations
in SQUAL are expected, when looking at a surface. Figure 29 shows 250 sequentially acquired SQUAL values,
while a sensor was moved slowly over white paper. SQUAL is nearly equal to zero when there is no surface below
the sensor.
38
Maximum_Pixel3
Access: Read
Address: 0x45
Reset Value: 0x00
Bit
7
6
5
4
3
2
1
0
Field
O
MP6
MP5
MP4
MP3
MP2
MP1
MP0
Data Type: Six bit number.
USAGE: Maximum Pixel value in current frame. Minimum value = 0, maximum value = 127. The maximum pixel value
may vary from frame to frame. Shown in Figure 30 is a graph of 250 sequentially acquired maximum pixel
values, while the sensor was moved slowly over white paper.
Minimum_Pixel3
Access: Read
Address: 0x46
Reset Value: 0x3f
Bit
7
6
5
4
3
2
1
0
Field
O
MP6
MP5
MP4
MP3
MP2
MP1
MP0
Data Type: Six bit number.
USAGE: Minimum Pixel value in current frame. Minimum value = 0, maximum value = 127. The minimum pixel value
may vary from frame to frame. See Figure 31.
Pixel_Sum3
Access: Read
Address: 0x47
Reset Value: 0x00
Bit
7
6
5
4
3
2
1
0
Field
PS7
PS6
PS5
PS4
PS3
PS2
PS1
PS0
Data Type: Upper 8 bits of a 15-bit unsigned integer.
USAGE: This register is used to find the average pixel value. It reports the upper 8 bits of a 15-bit unsigned integer, which
sums all 361 pixels in the current frame. It may be described as the full sum divided by 128. The formula to
calculate the average pixel value is as below:
Average Pixel = Register Value x 128/361
= Pixel_Sum x 0.355
The maximum register value is 178 (63 x 361 / 128 truncated to an integer). The minimum is 0. The pixel sum
value may vary from frame to frame.
39
Pixel Data3
Access: Read/Write
Address: 0x48
Reset Value: 0x00
Bit
7
6
5
4
3
2
1
0
Field
SOF
Data_Valid
PD5
PD4
PD3
PD2
PD1
PD0
Data Type: Two status bits, six bit pixel data.
USAGE: Digital Pixel data. Minimum value = 0, maximum value = 63. Any writes to this register resets the pixel hardware
so that the next read from the Pixel Data register will read pixel #1 and the StartOfFrame bit will be set. Subsequent reads will auto increment the pixel number.
To dump a complete image, set the LED to forced awake mode, write anything to this register, then read 361
times where the DataValid bit is set. On the 362th read, the StartOfFrame bit will be set indicating that we have
completed one frame of pixels and are starting back at pixel 1.
It takes at least 361 frames to complete an image as we can only read 1 pixel per frame.
The pixel hardware is armed with any read or write to the Pixel Data register and will output pixel data from the
next available frame. So, if you were to write the Pixel Data register, wait 5 seconds then read the Pixel Data
register; the reported pixel data is from 5 seconds ago.
Field Name
Description
SOF
Start of Frame
0 = Not start of frame
1 = Current pixel is number 1, start of frame
Data_Valid
There is valid data in the frame grabber
PD5– PD0
Six bit pixel data
Shutter_Upper3
Access: Read
Address: 0x49
Reset Value: 0x01
Bit
7
6
5
4
3
2
1
0
Field
S15
S14
S13
S12
S11
S10
S9
S8
Shutter_Lower3
Access: Read
Address: 0x4A
Reset Value: 0x00
Bit
7
6
5
4
3
2
1
0
Field
S7
S6
S5
S4
S3
S2
S1
S0
Data Type: Sixteen bit word.
USAGE: Units are clock cycles; default value is 0x0100HEX. Read Shutter_Upper first, then Shutter_Lower. They should
be read consecutively. The shutter is adjusted to keep the average and maximum pixel values within normal
operating ranges. The shutter value can be adjusted to a new value on every frame. When the shutter adjusts,
it changes by ± 1/16 of the current value. Shown in Figure 32 is a graph of 250 sequentially acquired shutter
values, while the sensor was moved slowly over white paper.
40
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www.avagotech.com
Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries.
Data subject to change. Copyright © 2005-2009 Avago Technologies. All rights reserved.
AV02-1472N - May 14, 2009