Preliminary Spec. MITSUBISHI LSIs Some contents are subject to change without notice. MH8S64DBKG -6,-6L-7,-7L,-8,-8L 536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM DESCRIPTION The MH8S64DBKG is 8388608 - word by 64-bit Synchronous DRAM module. This consists of eight industry standard 4Mx16 Synchronous DRAMs in TSOP and one industory standard EEPROM in TSSOP. The mounting of TSOP on a card edge Dual Inline package provides any application where high densities and large quantities of memory are required. This is a socket type - memory modules, suitable for easy interchange or addition of modules. Utilizes industry standard 4M x 16 Sy nchronous DRAMs TSOP and industry standard EEPROM in TSSOP 144-pin (72-pin dual in-line package) single 3.3V±0.3V power supply Max. Clock frequency -6:133MHz,-7,8:100MHz Fully synchronous operation referenced to clock rising edge 4 bank operation controlled by BA0,1(Bank Address) /CAS latency- 2/3(programmable) FEATURES Burst length- 1/2/4/8/Full Page(programmable) Frequency CLK Access Time (Component SDRAM) 133MHz 5.4ns(CL=3) -7,-7L 100MHz 6.0ns(CL=2) -8,-8L 100MHz 6.0ns(CL=3) -6,-6L Burst type- sequential / interleave(programmable) Column access - random Auto precharge / All bank precharge controlled by A10 Auto refresh and Self refresh 4096 refresh cycle /64ms LVTTL Interface APPLICATION main memory or graphic memory in computer systems PCB Outline (Front) (Back) MIT-DS-0340-0.3 1 2 143 144 MITSUBISHI ELECTRIC ( 1 / 51 ) 27.Mar.2001 Preliminary Spec. MITSUBISHI LSIs Some contents are subject to change without notice. MH8S64DBKG -6,-6L-7,-7L,-8,-8L 536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM PIN CONFIGURATION PIN Number Front side Pin Name PIN Number Back side Pin Name PIN Number Front side Pin Name PIN Number Back side Pin Name 1 Vss 2 Vss 73 NC 74 CLK1 3 5 DQ0 DQ1 4 6 DQ32 DQ33 75 Vss 76 Vss 77 NC 78 NC 7 9 DQ2 DQ3 8 10 DQ34 DQ35 79 NC 80 NC 81 Vcc 82 Vcc 11 13 Vcc DQ4 12 14 Vcc DQ36 83 DQ16 84 DQ48 85 DQ17 86 DQ49 15 DQ5 16 DQ37 87 DQ18 88 DQ50 17 DQ6 18 DQ38 89 DQ19 90 DQ51 19 21 DQ7 Vss 20 DQ39 91 Vss 92 Vss 22 Vss 93 DQ20 94 DQ52 23 DQMB0 24 DQMB4 95 DQ21 96 DQ53 25 DQMB1 26 DQMB5 97 DQ22 98 DQ54 DQ23 27 Vcc 28 Vcc 99 100 DQ55 29 A0 30 A3 101 Vcc 102 Vcc 31 A1 32 A4 103 A6 104 A7 33 A2 34 A5 105 A8 106 BA0 35 Vss 36 Vss 107 Vss 108 Vss 37 DQ8 38 DQ40 109 A9 110 BA1 39 DQ9 40 DQ41 111 A10 112 A11 41 DQ10 42 DQ42 113 Vcc 114 43 DQ11 44 DQ43 115 DQMB2 116 DQMB6 45 Vcc 46 Vcc 117 DQMB3 118 DQMB7 47 DQ12 48 DQ44 119 Vss 120 Vss 49 DQ13 50 DQ45 121 DQ24 122 DQ56 51 DQ14 52 DQ46 123 DQ25 124 DQ57 53 DQ15 54 DQ47 125 DQ26 126 DQ58 55 Vss 56 Vss 127 DQ27 128 DQ59 57 NC 58 NC 129 Vcc 130 Vcc 59 NC 60 NC 131 DQ28 132 DQ60 61 CLK0 62 CKE0 133 DQ29 134 DQ61 63 Vcc 64 Vcc 135 DQ30 136 DQ62 65 /RAS 66 /CAS 137 DQ31 138 DQ63 67 /WE 68 CKE1 139 Vss 140 Vss 69 /S0 70 NC 141 SDA 142 SCL 71 /S1 72 NC 143 Vcc 144 Vcc Vcc NC = No Connection MIT-DS-0340-0.3 MITSUBISHI ELECTRIC ( 2 / 51 ) 27.Mar.2001 Preliminary Spec. MITSUBISHI LSIs Some contents are subject to change without notice. MH8S64DBKG -6,-6L-7,-7L,-8,-8L 536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM Block Diagram /S0 /S1 DQMB0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQML /CS DQMB1 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQML /CS I/O 0 I/O 1 D0 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 I/O I/O I/O I/O I/O I/O I/O I/O DQMU DQMU I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O 8 9 10 11 12 13 14 15 0 1 D4 2 3 4 5 6 7 8 9 10 11 12 13 14 15 DQMB2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQML /CS DQML /CS I/O 0 I/O 1 D1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 I/O I/O I/O I/O I/O I/O I/O I/O DQMB3 DQMU DQMU DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 10Ω CLK1 CLK0 CKE0 CKE1 /RAS /CAS /WE BA0,BA1,A<11:0> Vcc Vss MIT-DS-0340-0.3 I/O I/O I/O I/O I/O I/O I/O I/O 8 9 10 11 12 13 14 15 I/O I/O I/O I/O I/O I/O I/O I/O 0 1 D5 2 3 4 5 6 7 8 9 10 11 12 13 14 15 DQMB4 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQMB5 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQMB6 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQMB7 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DQML /CS DQML /CS I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O 0 1 D2 2 3 4 5 6 7 0 1 D6 2 3 4 5 6 7 DQMU DQMU I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O 8 9 10 11 12 13 14 15 8 9 10 11 12 13 14 15 DQML /CS DQML /CS I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O 0 1 D3 2 3 4 5 6 7 0 1 D7 2 3 4 5 6 7 DQMU DQMU I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O 8 9 10 11 12 13 14 15 8 9 10 11 12 13 14 15 4loads 4loads D0 - D3 D4 - D7 D0 - D7 D0 - D7 D0 - D7 D0 - D7 D0 - D7 SERIAL PD SCL A0 A1 A2 SDA D0 - D7 MITSUBISHI ELECTRIC ( 3 / 51 ) 27.Mar.2001 Preliminary Spec. MITSUBISHI LSIs Some contents are subject to change without notice. MH8S64DBKG -6,-6L-7,-7L,-8,-8L 536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM Serial Presence Detect Table I Byte SPD enrty data SPD DATA(hex) Defines # bytes written into serial memory at module mfgr 128 80 1 Total # bytes of SPD memory device 256 Bytes 08 2 Fundamental memory type SDRAM 04 0C 0 Function described 3 # Row Addresses on this assembly A0-A11 4 # Column Addresses on this assembly A0-A7 08 5 # Module Banks on this assembly 2BANK 02 6 Data Width of this assembly... x64 40 7 ... Data Width continuation 0 00 8 Voltage interface standard of this assembly LVTTL 7.5ns 01 75 9 SDRAM Cycletime at Max. Supported CAS Latency (CL). Cycle time for CL=3 10 -6,-6L -7,-7L,-8,-8L 10ns A0 SDRAM Access from Clock -6,-6L 5.4ns 54 tAC for CL=3 -7,-7L,-8,-8L 6ns 60 00 11 DIMM Configuration type (Non-parity,Parity,ECC) Non-PARITY 12 Refresh Rate/Type self refresh(15.625uS) 80 13 SDRAM width,Primary DRAM x16 10 Error Checking SDRAM data width N/A 00 01 8F 14 15 Minimum Clock Delay,Back to Back Random Column Addresses 16 Burst Lengths Supported 1 1/2/4/8/Full page 17 # Banks on Each SDRAM device 4bank 04 18 CAS# Latency 2/3 06 19 CS# Latency 0 01 20 Write Latency 0 01 SDRAM Module Attributes non-buffered,non-registered 00 22 SDRAM Device Attributes:General Precharge All,Auto precharge 0E 23 SDRAM Cycle time(2nd highest CAS latency) -6,-6L 10ns A0 -7,-7L 10ns A0 -8,-8L 13ns D0 60 21 Cycle time for CL=2 24 SDRAM Access form Clock(2nd highest CAS latency) tAC for CL=2 25 26 -6,-6L 6ns -7,-7L 6ns -8,-8L 7ns 60 70 N/A 00 N/A 00 20ns 14 -6,-6L 15ns 0F -7,-7L,-8,-8L 20ns 14 20ns 14 -6,-6L 45ns 2D -7,-7L,-8,-8L 50ns 32 SDRAM Cycle time(3rd highest CAS latency) SDRAM Access form Clock(3rd highest CAS latency) 27 Precharge to Active Minimum 28 Row Active to Row Active Min. 29 RAS to CAS Delay Min 30 Active to Precharge Min MIT-DS-0340-0.3 MITSUBISHI ELECTRIC ( 4 / 51 ) 27.Mar.2001 Preliminary Spec. MITSUBISHI LSIs Some contents are subject to change without notice. MH8S64DBKG -6,-6L-7,-7L,-8,-8L 536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM Serial Presence Detect Table II 31 32 33 Density of each bank on module Command and Address signal input setup time Command and Address signal input hold time 34 Data signal input setup time 35 Data signal input hold time 36-61 Superset Information (may be used in future) 62 SPD Revision 63 Checksum for bytes 0-62 32MByte 08 -6,-6L 1.5ns 15 -7,-7L,-8,-8L 2ns 20 -6,-6L 0.8ns 08 -7,-7L,-8,-8L 1ns 10 -6,-6L 1.5ns 15 -7,-7L,-8,-8L 2ns 20 -6,-6L 0.8ns 08 -7,-7L,-8,-8L 1ns 10 option 00 rev 1.2B 12 Check sum for -6,-6L 9E Check sum for -7,-7L 05 Check sum for -8,-8L 45 64-71 Manufactures Jedec ID code per JEP-108E MITSUBISHI 1CFFFFFFFFFFFFFF 72 Manufacturing location Miyoshi,Japan 01 Tajima,Japan 02 NC,USA 03 91-92 Revision Code Germany MH8S64DBKG-6 MH8S64DBKG-6L MH8S64DBKG-7 MH8S64DBKG-7L MH8S64DBKG-8 MH8S64DBKG-8L PCB revision 93-94 Manufacturing date year/week code yyww 73-90 Manufactures Part Number 04 4D483853363444424B472D36202020202020 4D483853363444424B472D364C2020202020 4D483853363444424B472D37202020202020 4D483853363444424B472D374C2020202020 4D483853363444424B472D38202020202020 4D483853363444424B472D384C2020202020 rrrr 95-98 Assembly Serial Number serial number ssssssss 99-125 Manufacture Specific Data option 00 126 Intetl specification frequency 100MHz 64 127 Intel specification CAS# Latency support CL=2/3,AP,CK0,1 CF CL=3,AP,CK0,1 CD open 00 -6,-6L,-7,-7L -8,-8L 128+ Unused storage locations MIT-DS-0340-0.3 MITSUBISHI ELECTRIC ( 5 / 51 ) 27.Mar.2001 Preliminary Spec. MITSUBISHI LSIs Some contents are subject to change without notice. MH8S64DBKG -6,-6L-7,-7L,-8,-8L 536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM PIN FUNCTION Input Master Clock:All other inputs are referenced to the rising edge of CK CKE0, CKE1 Input Clock Enable:CKE controls internal clock.When CKE is low,internal clock for the following cycle is ceased. CKE is also used to select auto / self refresh. After self refresh mode is started, CKE E becomes asynchronous input.Self refresh is maintained as long as CKE is low. /S0, /S1 Input Chip Select: When /S is high,any command means No Operation. /RAS,/CAS,/WE Input Combination of /RAS,/CAS,/WE defines basic commands. Input A0-11 specify the Row/Column Address in conjunction with BA0,1.The Row Address is specified by A0-11.The Column Address is specified by A0-7.A10 is also used to indicate precharge option.When A10 is high at a read / write command, an auto precharge is performed. When A10 is high at a precharge command, both banks are precharged. Input Bank Address:BA0,1 is not simply BA.BA specifies the bank to which a command is applied.BA0,1 must be set with ACT,PRE,READ,WRITE commands CLK (CLK0 ~ CLK1) A0-11 BA0,1 DQ0-63 DQMB0-7 Vdd,Vss Input/Output Data In and Data out are referenced to the rising edge of CK Input Din Mask/Output Disable:When DQMB is high in burst write.Din for the current cycle is masked.When DQMB is high in burst read,Dout is disabled at the next but one cycle. Power Supply Power Supply for the memory mounted module. SCL Input Serial clock for serial PD SDA Output Serial data for serial PD MIT-DS-0340-0.3 MITSUBISHI ELECTRIC ( 6 / 51 ) 27.Mar.2001 Preliminary Spec. MITSUBISHI LSIs Some contents are subject to change without notice. MH8S64DBKG -6,-6L-7,-7L,-8,-8L 536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM BASIC FUNCTIONS The MH8S64DBKG provides basic functions,bank(row)activate,burst read / write, bank(row)precharge,and auto / self refresh. Each command is defined by control signals of /RAS,/CAS and /WE at CK rising edge. In addition to 3 signals,/S,CKE and A10 are used as chip select,refresh option,and precharge option,respectively. To know the detailed definition of commands please see the command truth table. CK /S Chip Select : L=select, H=deselect /RAS Command /CAS Command /WE Command CKE Ref resh Option @ref resh command Precharge Option @precharge or read/write command A10 def ine basic commands Activate(ACT) [/RAS =L, /CAS = /WE =H] ACT command activates a row in an idle bank indicated by BA. Read(READ) [/RAS =H,/CAS =L, /WE =H] READ command starts burst read from the active bank indicated by BA.First output data appears after /CAS latency. When A10 =H at this command,the bank is deactivated after the burst read(auto-precharge,READA). Write(WRITE) [/RAS =H, /CAS = /WE =L] WRITE command starts burst write to the active bank indicated by BA. Total data length to be written is set by burst length. When A10 =H at this command, the bank is deactivated after the burst write(auto-precharge,WRITEA). Precharge(PRE) [/RAS =L, /CAS =H,/WE =L] PRE command deactivates the active bank indicated by BA. This command also terminates burst read / write operation. When A10 =H at this command, both banks are deactivated(precharge all, PREA). Auto-Refresh(REFA) [/RAS =/CAS =L, /WE =CKE =H] PEFA command starts auto-refresh cycle. Refresh address including bank address are generated internally. After this command, the banks are precharged automatically. MIT-DS-0340-0.3 MITSUBISHI ELECTRIC ( 7 / 51 ) 27.Mar.2001 Preliminary Spec. MITSUBISHI LSIs Some contents are subject to change without notice. MH8S64DBKG -6,-6L-7,-7L,-8,-8L 536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM COMMAND TRUTH TABLE CKE CKE n-1 n /RAS /CAS /WE BA0,1 A11 A10 A0-9 COMMAND MNEMONIC Deselect No Operation DESEL NOP H H X X H L X H X H X H X X X X X X X X ACT H X L L H H V V V V Single Bank Precharge Precharge All Bank PRE PREA H H X X L L L L H H L L V X X X L H X X Column Address Entry & Write WRITE H X L H L L V V L V Column Address Entry & Write with AutoPrecharge WRITEA H X L H L L V V H V Column Address Entry & Read READ H X L H L H V V L V Column Address Entry & Read with Auto Precharge READA H X L H L H V V H V Auto-Refresh Self-Refresh Entry Self-Refresh Exit REFA REFS REFSX Burst Terminate Mode Register Set TERM MRS H H L L H H H L H H X X L L H L L L L L X H H L L L X H H L H H X H L L X X X X X L X X X X X L X X X X X L X X X X X V*1 Row Adress Entry & Bank Activate /S H =High Level, L = Low Level, V = Valid, X = Don't Care, n = CK cycle number NOTE: 1.A7-9 = 0, A0-6 = Mode Address MIT-DS-0340-0.3 MITSUBISHI ELECTRIC ( 8 / 51 ) 27.Mar.2001 Preliminary Spec. MITSUBISHI LSIs Some contents are subject to change without notice. MH8S64DBKG -6,-6L-7,-7L,-8,-8L 536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM FUNCTION TRUTH TABLE /S IDLE H X X X X DESEL NOP L H H H X NOP NOP L H H L X TBST ILLEGAL*2 L H L X BA,CA,A10 L L H H BA,RA ACT L L H L L L L H BA,A10 X PRE/PREA REFA L ROW ACTIVE READ /RAS /CAS L L /WE L Address Command Current State Op-Code, Mode-Add Action READ/WRITE ILLEGAL*2 MRS Bank Active,Latch RA NOP*4 Auto-Refresh*5 Mode Register Set*5 H X X X X DESEL NOP L H H H X NOP NOP L H H L X TBST NOP L H L H BA,CA,A10 L H L L BA,CA,A10 L L H H BA,RA ACT Bank Active/ILLEGAL*2 L L H L BA,A10 PRE/PREA Precharge/Precharge All L L L H X L L L L H X X X X DESEL NOP(Continue Burst to END) L H H H X NOP NOP(Continue Burst to END) L H H L X TBST Terminate Burst L H L H BA,CA,A10 Op-Code, Mode-Add READ/READA Begin Read,Latch CA, Determine Auto-Precharge WRITE/ Begin Write,Latch CA, WRITEA Determine Auto-Precharge REFA ILLEGAL MRS ILLEGAL Terminate Burst,Latch CA, READ/READA Begin New Read,Determine Auto-Precharge*3 Terminate Burst,Latch CA, L H L L BA,CA,A10 WRITE/WRITEA Begin Write,Determine AutoPrecharge*3 MIT-DS-0340-0.3 L L H H BA,RA ACT L L H L BA,A10 PRE/PREA L L L H X L L L L Op-Code, Mode-Add Bank Active/ILLEGAL*2 Terminate Burst,Precharge REFA ILLEGAL MRS ILLEGAL MITSUBISHI ELECTRIC ( 9 / 51 ) 27.Mar.2001 Preliminary Spec. MITSUBISHI LSIs Some contents are subject to change without notice. MH8S64DBKG -6,-6L-7,-7L,-8,-8L 536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM FUNCTION TRUTH TABLE(continued) Current State WRITE /S /RAS /CAS /WE Address Command Action H X X X X DESEL NOP(Continue Burst to END) L H H H X NOP NOP(Continue Burst to END) L H H L X TBST Terminate Burst L H L H BA,CA,A10 Terminate Burst,Latch CA, READ/READA Begin Read,Determine AutoPrecharge*3 L H L L BA,CA,A10 WRITE/ WRITEA Terminate Burst,Latch CA, Begin Write,Determine AutoPrecharge*3 L L H H BA,RA ACT Bank Active/ILLEGAL*2 L L H L BA,A10 PRE/PREA L L L H X REFA ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL READ with H X X X X AUTO L H H H PRECHARGE L H H L L H L H BA,CA,A10 L H L L BA,CA,A10 L L H H BA,RA ACT L L H L BA,A10 PRE/PREA L L L H X Terminate Burst,Precharge DESEL NOP(Continue Burst to END) X NOP NOP(Continue Burst to END) X TBST ILLEGAL READ/READA ILLEGAL WRITE/ WRITEA Op-Code, ILLEGAL Bank Active/ILLEGAL*2 ILLEGAL*2 REFA ILLEGAL MRS ILLEGAL L L L L WRITE with H X X X X DESEL NOP(Continue Burst to END) AUTO L H H H X NOP NOP(Continue Burst to END) PRECHARGE L H H L ILLEGAL H L H X BA,CA,A10 TBST L L H L L BA,CA,A10 L L H H BA,RA ACT L L H L BA,A10 PRE/PREA L L L H X REFA ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL MIT-DS-0340-0.3 Mode-Add READ/READA ILLEGAL WRITE/ WRITEA MITSUBISHI ELECTRIC ( 10 / 51 ) ILLEGAL Bank Active/ILLEGAL*2 ILLEGAL*2 27.Mar.2001 Preliminary Spec. MITSUBISHI LSIs Some contents are subject to change without notice. MH8S64DBKG -6,-6L-7,-7L,-8,-8L 536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM FUNCTION TRUTH TABLE(continued) /S PRE - H X X X X DESEL NOP(Idle after tRP) CHARGING L H H H X NOP NOP(Idle after tRP) L H H L X TBST ILLEGAL*2 L H L X BA,CA,A10 L L H H BA,RA ACT L L H L BA,A10 PRE/PREA L L L H X L L L L ROW H X X X X DESEL NOP(Row Active after tRCD ACTIVATING L H H H X NOP NOP(Row Active after tRCD L H H L X TBST ILLEGAL*2 L H L X BA,CA,A10 L L H H BA,RA ACT ILLEGAL*2 L L H L BA,A10 PRE/PREA ILLEGAL*2 L L L H X L L L L WRITE RE- H X X X X DESEL NOP COVERING L H H H X NOP NOP L H H L X TBST ILLEGAL*2 L H L X BA,CA,A10 L L H H BA,RA ACT ILLEGAL*2 L L H L BA,A10 PRE/PREA ILLEGAL*2 L L L H X L L L L MIT-DS-0340-0.3 /RAS /CAS /WE Address Command Current State Action READ/WRITE ILLEGAL*2 Op-Code, Mode-Add ILLEGAL*2 NOP*4(Idle after tRP) REFA ILLEGAL MRS ILLEGAL READ/WRITE ILLEGAL*2 Op-Code, Mode-Add REFA ILLEGAL MRS ILLEGAL READ/WRITE ILLEGAL*2 Op-Code, Mode-Add MITSUBISHI ELECTRIC ( 11 / 51 ) REFA ILLEGAL MRS ILLEGAL 27.Mar.2001 Preliminary Spec. MITSUBISHI LSIs Some contents are subject to change without notice. MH8S64DBKG -6,-6L-7,-7L,-8,-8L 536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM FUNCTION TRUTH TABLE(continued) Current State /S /RAS /CAS /WE Address Command Action RE- H X X X X DESEL NOP(Idle after tRC) FRESHING L H H H X NOP NOP(Idle after tRC) L H H L X TBST ILLEGAL L H L X BA,CA,A10 L L H H BA,RA ACT ILLEGAL L L H L BA,A10 PRE/PREA ILLEGAL L L L H X REFA ILLEGAL L L L L MRS ILLEGAL MODE H X X X X DESEL NOP(Idle after tRSC) REGISTER L H H H X NOP NOP(Idle after tRSC) SETTING L H H L X TBST ILLEGAL L H L X BA,CA,A10 L L H H BA,RA ACT ILLEGAL L L H L BA,A10 PRE/PREA ILLEGAL L L L H X REFA ILLEGAL L L L L MRS ILLEGAL READ/WRITE ILLEGAL Op-Code, Mode-Add READ/WRITE ILLEGAL Op-Code, Mode-Add ABBREVIATIONS: H = Hige Level, L = Low Level, X = Don't Care BA = Bank Address, RA = Row Address, CA = Column Address, NOP = No Operation NOTES: 1. All entries assume that CKE was High during the preceding clock cycle and the current clock cycle. 2. ILLEGAL to bank in specified state; function may be legal in the bank indicated by BA, depending on the state of that bank. 3. Must satisfy bus contention, bus turn around, write recovery requirements. 4. NOP to bank precharging or in idle state.May precharge bank indicated by BA. 5. ILLEGAL if any bank is not idle. ILLEGAL = Device operation and / or date-integrity are not guaranteed. MIT-DS-0340-0.3 MITSUBISHI ELECTRIC ( 12 / 51 ) 27.Mar.2001 Preliminary Spec. MITSUBISHI LSIs Some contents are subject to change without notice. MH8S64DBKG -6,-6L-7,-7L,-8,-8L 536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM FUNCTION TRUTH TABLE FOR CKE Current State CK n-1 CK n /S SELF - H X X X REFRESH*1 L H H L H L /RAS /CAS /WE Add Action X X X INVALID X X X X Exit Self-Refresh(Idle after tRC) L H H H X Exit Self-Refresh(Idle after tRC) H L H H L X ILLEGAL L H L H L X X ILLEGAL L H L L X X X ILLEGAL L L X X X X X NOP(Maintain Self-Refresh) POWER H X X X X X X INVALID DOWN L H X X X X X Exit Power Down to Idle L L X X X X X NOP(Maintain Self-Refresh) ALL BANKS H H X X X X X Refer to Function Truth Table IDLE*2 H L L L L H X Enter Self-Refresh H L H X X X X Enter Power Down H L L H H H X Enter Power Down H L L H H L X ILLEGAL H L L H L X X ILLEGAL H L L L X X X ILLEGAL L X X X X X X Refer to Current State = Power Down ANY STATE H H X X X X X Refer to Function Truth Table other than H L X X X X X Begin CK0 Suspend at Next Cycle*3 listed above L H X X X X X Exit CK0 Suspend at Next Cycle*3 L L X X X X X Maintain CK0 Suspend ABBREVIATIONS: H = High Level, L = Low Level, X = Don't Care NOTES: 1. CKE Low to High transition will re-enable CK and other inputs asynchronously. A m inimum setup time must be satisfied before any command other than EXIT. 2. Power-Down and Self-Refresh can be entered only form the All banks idle State. 3. Must be legal command. MIT-DS-0340-0.3 MITSUBISHI ELECTRIC ( 13 / 51 ) 27.Mar.2001 Preliminary Spec. MITSUBISHI LSIs Some contents are subject to change without notice. MH8S64DBKG -6,-6L-7,-7L,-8,-8L 536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM SIMPLIFIED STATE DIAGRAM SELF REFRESH REFS REFSX MRS MODE REGISTER SET REFA AUTO REFRESH IDLE CKEL CKEH CLK SUSPEND ACT POWER DOWN CKEL CKEH ROW ACTIVE TERM TERM WRITE READA WRITEA CKEL WRITE SUSPEND READ READ WRITE WRITE CKEL READ CKEH CKEH WRITEA READA WRITEA READA CKEL WRITEA SUSPEND POWER APPLIED READ SUSPEND CKEL PRE WRITEA CKEH POWER ON PRE PRE READA PRE CKEH READA SUSPEND PRE CHARGE Automatic Sequence Command Sequence MIT-DS-0340-0.3 MITSUBISHI ELECTRIC ( 14 / 51 ) 27.Mar.2001 Preliminary Spec. MITSUBISHI LSIs Some contents are subject to change without notice. MH8S64DBKG -6,-6L-7,-7L,-8,-8L 536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM POWER ON SEQUENCE Before starting normal operation, the following power on sequence is necessary to prevent a SDRAM from damaged or malfunctioning. 1. Apply power and start clock.Attempt to maintain CKE high,DQM0-7 high and NOP condition at the inputs. 2. Maintain stable power, stable cock, and NOP input conditions for a minimum of 200us. 3. Issue precharge commands for all banks. (PRE or PREA) 4. After all banks become idle state (after tRP), issue 8 or more auto-refresh commands. 5. Issue a mode register set command to initialize the mode register. After these sequence, the SDRAM is idle state and ready for normal operation. MODE REGISTER Burst Length, Burst Type and /CAS Latency can be programmed by setting the mode register(MRS). The mode register stores these date until the next MRS command, which may be issued when both banks are in idle state. After tRSC from a MRS command, the SDRAM is ready for new command. CK /S BA0 BA1 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 /RAS /CAS 0 0 0 0 WM 0 0 LTMODE BT BL /WE BA0,1 A11-0 CL 000 001 LATENCY MODE 0 0 1 1 1 1 WRITE MODE MIT-DS-0340-0.3 1 1 0 0 1 1 0 1 0 1 0 1 0 1 /CAS LATENCY R R 2 3 R R R R BURST SINGLE BIT BURST LENGTH BURST TYPE V BL BT= 0 BT= 1 0 0 1 1 0 0 1 0 1 0 1 2 4 8 R 1 2 4 8 R 101 110 111 R R FP R R R 0 0 0 0 1 0 1 SEQUENTIAL INTERLEAVED R:Reserved for Future Use FP: Full Page MITSUBISHI ELECTRIC ( 15 / 51 ) 27.Mar.2001 Preliminary Spec. MITSUBISHI LSIs Some contents are subject to change without notice. MH8S64DBKG -6,-6L-7,-7L,-8,-8L 536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM CK Command Read Write Y Y Address Q0 DQ CL= 3 BL= 4 /CAS Latency Q1 Q2 Q3 D0 Burst Length D1 D2 D3 Burst Length Burst Type Initial Address BL Column Addressing A2 A1 A0 0 0 0 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 0 1 1 2 3 4 5 6 7 0 1 0 3 2 5 4 7 6 0 1 0 2 3 4 5 6 7 0 1 2 3 0 1 6 7 4 5 0 1 1 3 4 5 6 7 0 1 2 3 2 1 0 7 6 5 4 Sequential Interleaved 8 1 0 0 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 1 0 1 5 6 7 0 1 2 3 4 5 4 7 6 1 0 3 2 1 1 0 6 7 0 1 2 3 4 5 6 7 4 5 2 3 0 1 1 1 1 7 0 1 2 3 4 5 6 7 6 5 4 3 2 1 0 - 0 0 0 1 2 3 0 1 2 3 - 0 1 1 2 3 0 1 0 3 2 4 - 1 0 2 3 0 1 2 3 0 1 - 1 1 3 0 1 2 3 2 1 0 - - 0 0 1 0 1 1 0 1 0 2 - - 1 MIT-DS-0340-0.3 MITSUBISHI ELECTRIC ( 16 / 51 ) 27.Mar.2001 Preliminary Spec. MITSUBISHI LSIs Some contents are subject to change without notice. MH8S64DBKG -6,-6L-7,-7L,-8,-8L 536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM OPERATION DESCRIPTION BANK ACTIVATE One of four banks is activated by an ACT command. An bank is selected by BA0-1. A row is selected by A0-11. Multiple banks can be active state concurrently by issuing multiple ACT commands. Minimum activation interval between one bank and another bank is tRRD. PRECHARGE An open bank is deactivated by a PRE command. A bank to be deactivated is designated by BA0-1. When multiple banks are active, a precharge all command (PREA, PRE + A10=H) deactivates all of open banks at the same time. BA0-1 are "Don't Care" in this case. Minimum delay time of an ACT command after a PRE command to the same bank is tRP. Bank Activation and Precharge All (BL=4, CL=2) CK Command ACT ACT ACT tRP Xa Xb Yb A10 Xa Xb 0 BA0,1 00 01 01 DQ PRE tRCD tRRD A0-9,11 READ Xa 1 Xa 00 Qb0 Qb1 Qb2 Qb3 Precharge all READ A READ command can be issued to any active bank. The start address is specified by A07(x16) . 1st output data is available after the /CAS Latency from the READ. The consecutive data length is defined by the Burst Length. The address sequence of the burst data is defined by the Burst Type. Minimum delay time of a READ command after an ACT command to the same bank is tRCD. When A10 is high at a READ command, auto-precharge (READA) is performed. Any command (READ, WRITE, PRE, ACT, TBST) to the same bank is inhibited till the internal precharge is complete. The internal precharge starts at the BL after READA. The next ACT command can be issued after (BL + tRP) from the previous READA. In any case, tRCD+BL > tRASmin must be met. MIT-DS-0340-0.3 MITSUBISHI ELECTRIC ( 17 / 51 ) 27.Mar.2001 Preliminary Spec. MITSUBISHI LSIs Some contents are subject to change without notice. MH8S64DBKG -6,-6L-7,-7L,-8,-8L 536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM Multi Bank Interleaving READ (BL=4, CL=2) CK Command ACT READ ACT tRCD READ PRE tRCD ACT tRP A0-9, 11 Xa Ya Xb Yb A10 Xa 0 Xb 0 0 Xa BA0,1 00 00 01 01 00 00 Qa2 Qa3 DQ Qa0 Qa1 Xa Qb0 Qb1 Qb2 Qb3 READ with Auto-Precharge (BL=4, CL=2) CK Command ACT READ tRCD ACT tRP BL A0-9, 11 Xa Ya Xa A10 Xa 1 Xa 00 00 BA0,1 00 DQ Qa0 Qa1 Qa2 Qa3 Internal precharge starts Auto-Precharge Timing (READ BL=4) CK Command ACT READ tRCD CL=3 DQ CL=2 DQ ACT BL Qa0 Qa0 Qa1 Qa2 Qa1 Qa2 Qa3 Qa3 Internal precharge starts MIT-DS-0340-0.3 MITSUBISHI ELECTRIC ( 18 / 51 ) 27.Mar.2001 Preliminary Spec. MITSUBISHI LSIs Some contents are subject to change without notice. MH8S64DBKG -6,-6L-7,-7L,-8,-8L 536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM WRITE A WRITE command can be issued to any active bank. The start address is specified by A0-7 (x16). 1st input data is set at the same cycle as the WRITE. The consecutive data length to be written is defined by the Burst Length. The address sequence of burst data is defined by the Burst Type. Minimum delay time of a WRITE command after an ACT command to the same bank is tRCD. From the last input data to the PRE command, the write recovery time (tWR) is required. When A10 is high at a WRITE command, auto-precharge (WRITEA) is performed. Any command (READ, WRITE, PRE, ACT, TBST) to the same bank is inhibited till the internal precharge is complete. The internal precharge starts at tWR after the last input data cycle. The next ACT command can be issued after (BL + tWR -1 + tRP) from the previous WRITEA. In any case, tRCD + BL + tWR -1 > tRASmin must be met. WRITE (BL=4) CK Command ACT Write PRE tRCD BL A0-9, 11 Xa Ya A10 Xa 0 BA0,1 00 00 ACT tRP Xa 0 Xa 00 tWR DQ Da0 Da1 Da2 Da3 WRITE with Auto-Precharge (BL=4) CK Command ACT Write ACT tRCD tRP BL A0-9, 11 Xa Ya Xa A10 Xa 1 Xa 00 00 BA0,1 00 tWR DQ Da0 Da1 Da2 Da3 Internal precharge begins MIT-DS-0340-0.3 MITSUBISHI ELECTRIC ( 19 / 51 ) 27.Mar.2001 Preliminary Spec. MITSUBISHI LSIs Some contents are subject to change without notice. MH8S64DBKG -6,-6L-7,-7L,-8,-8L 536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM BURST INTERRUPTION [ Read Interrupted by Read ] Burst read oparation can be interrupted by new read of the same or the other bank. Random column access is allowed READ to READ interval is minimum 1 CK Read Interrupted by Read (BL=4, CL=2) CK Command READ A0-9,11 Ya Yb Yc A10 0 0 0 BA0,1 00 00 10 READ READ DQ Qa0 Qa1 Qa2 Qb0 Qc0 Qc1 Qc2 Qc3 [ Read Interrupted by Write ] Burst read operation can be interrupted by write of any active bank. Random column access is allowed. In this case, the DQ should be controlled adequately by using the DQMB0-7 to prevent the bus contention. The output is disabled automatically 2 cycle after WRITE assertion. Read Interrupted by Write (BL=4, CL=2) CK Command ACT READ Write A0-9,11 Xa Ya Ya A10 Xa 0 0 00 00 BA0,1 00 DQMB0-7 DQ Qa0 Da0 Da1 Output disable by DQM MIT-DS-0340-0.3 Da2 Da3 by WRITE MITSUBISHI ELECTRIC ( 20 / 51 ) 27.Mar.2001 Preliminary Spec. MITSUBISHI LSIs Some contents are subject to change without notice. MH8S64DBKG -6,-6L-7,-7L,-8,-8L 536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM [ Read Interrupted by Precharge ] A burst read operation can be interrupted by precharge of the same bank . READ to PRE interval is minimum 1 CK. A PRE command output disable latency is equivalent to the /CAS Latency. Read Interrupted by Precharge (BL=4) CK Command READ PRE DQ Q0 Q1 Q0 Q1 Q2 CL=3 Command READ PRE DQ Command READ PRE DQ Command Q0 PRE READ DQ Q0 Q1 Q2 CL=2 Command READ DQ Command DQ MIT-DS-0340-0.3 PRE Q0 Q1 READ PRE Q0 MITSUBISHI ELECTRIC ( 21 / 51 ) 27.Mar.2001 Preliminary Spec. MITSUBISHI LSIs Some contents are subject to change without notice. MH8S64DBKG -6,-6L-7,-7L,-8,-8L 536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM [ Read Interrupted by Burst Terminate ] Sim ilarly to the precharge, burst terminate command can interrupt burst read operation and disable the data output. The terminated bank remains active,READ to TBST interval is minimum of 1 CK. A TBSTcommand to output disable latency is equivalent to the /CAS Latency. Read Interrupted by Terminate (BL=4) CK Command READ TBST DQ Command READ Q0 Q1 Q0 Q1 Q2 TBST CL=3 DQ Command READ TBST DQ Command Q0 TBST READ DQ Command Q0 Q1 Q2 TBST READ CL=2 DQ Command DQ MIT-DS-0340-0.3 Q0 Q1 READ TBST Q0 MITSUBISHI ELECTRIC ( 22 / 51 ) 27.Mar.2001 Preliminary Spec. MITSUBISHI LSIs Some contents are subject to change without notice. MH8S64DBKG -6,-6L-7,-7L,-8,-8L 536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM [ Write Interrupted by Write ] Burst write operation can be interrupted by new write of any active bank. Random column access is allowed. WRITE to WRITE interval is minimum 1 CK. Write Interrupted by Write (BL=4) CK Command Write A0-9, 11 Write Write Ya Yb Yc A10 0 0 0 BA0,1 00 00 10 DQ Da0 Db0 Dc0 Da1 Da2 Dc1 Dc2 Dc3 [ Write Interrupted by Read ] Burst write operation can be interrupted by read of any active bank. Random column access is allowed. WRITE to READ interval is minimum 1 CK. The input data on DQ at the interrupting READ cycle is "don't care". Write Interrupted by Read (BL=4, CL=2) CK Command ACT Write READ A0-9,11 Xa Ya Yb A10 Xa 0 0 BA0,1 00 00 00 DQ Da0 Da1 Qb0 Qb1 Qb2 Qb3 don't care MIT-DS-0340-0.3 MITSUBISHI ELECTRIC ( 23 / 51 ) 27.Mar.2001 Preliminary Spec. MITSUBISHI LSIs Some contents are subject to change without notice. MH8S64DBKG -6,-6L-7,-7L,-8,-8L 536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM [ Write Interrupted by Precharge ] Burst write operation can be interrupted by precharge of the same bank . Write recovery time(tWR) is required from the last data to PRE command. During write recovery, data inputs must be masked by DQM. Write Interrupted by Precharge (BL=4) CK Command ACT Write PRE ACT tRP A0-9,11 Xa Ya Xa A10 0 0 0 0 BA0,1 00 00 00 00 DQMB0-7 tWR DQ Da0 Da1 [ Write Interrupted by Burst Terminate ] Burst terminate command can terminate burst write operation. In this case, the write recovery time is not required and the bank remains active.The WRITE to TBST minimum interval is 1CK. Write Interrupted by Burst Terminate (BL=4) CK Command ACT Write A0-9,11 Xa Ya Yb A10 0 0 0 BA0,1 00 00 00 DQ MIT-DS-0340-0.3 Da0 TBST Da1 Write Db0 Db1 MITSUBISHI ELECTRIC ( 24 / 51 ) Db2 Db3 27.Mar.2001 Preliminary Spec. MITSUBISHI LSIs Some contents are subject to change without notice. MH8S64DBKG -6,-6L-7,-7L,-8,-8L 536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM [ Write with Auto-Precharge interrupted by Write or Read to anotehr Bank ] Burst write with auto-precharge can be interrupted by write or read toanother bank . Next ACT command can be issued after (BL+tWR-1+tRP) from the WRITEA. Autoprecharge interrrupted by a command to the same bank is inhibited. WRITEA Interrupted by WRITE to another bank (BL=4) CK Command Write A0-9,11 Write BL Ya ACT tRP Ya Xa tWR A10 1 0 Xa BA0,1 00 10 00 DQ Da0 Da1 Db0 Db1 Db2 Db3 activate auto-precharge interrupted WRITEA interrupted by READ to another bank (CL=2,BL=4) CK Command Write Read ACT BL Ya A0-9,11 tRP Yb Xa tWR A10 1 0 Xa BA0,1 00 10 00 DQ Da0 Da1 auto-precharge interrupted MIT-DS-0340-0.3 Db0 Db1 Db2 Db3 activate MITSUBISHI ELECTRIC ( 25 / 51 ) 27.Mar.2001 Preliminary Spec. MITSUBISHI LSIs Some contents are subject to change without notice. MH8S64DBKG -6,-6L-7,-7L,-8,-8L 536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM [ Read with Auto-Precharge interrupted by Read to anotehr Bank ] Burst read with auto-precharge can be interrupted by read toanother bank . Next ACT command can be issued after (BL+tRP) from the READA. Auto-precharge interrrupted by a command to the same bank is inhibited. READA Interrupted by READ to another bank (CL=2,BL=4) CK Command Read A0-9,11 Read BL ACT tRP Ya Ya Xa A10 1 0 Xa BA0,1 00 10 00 DQ Qa0 Qa1 auto-precharge interrupted Qb0 Qb1 Qb2 Qb3 activate Full Page Burst Full page burst length is available for only the sequential burst type. Full page burst read or write is repeated untill aPrecharge or a Burst Terminate command is issued. In case of the full page burst , a read or write with auto-precharge command is illegal. Single Write When single write mode is set, burst length for write is always one, independently of Burst Length defined by (A2-0). MIT-DS-0340-0.3 MITSUBISHI ELECTRIC ( 26 / 51 ) 27.Mar.2001 Preliminary Spec. MITSUBISHI LSIs Some contents are subject to change without notice. MH8S64DBKG -6,-6L-7,-7L,-8,-8L 536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM AUTO REFRESH Single cycle of auto-refresh is initiated with a REFA(/CS=/RAS=/CAS=L, /WE=/CKE=H) command. The refresh address is generated internally.4096 REFA cycle within 64ms refresh 64Mbit memory cells. The auto-refresh is performed on 4banks concurrently. Before performing an auto-refresh, all banks must be in the idle state. Auto-refresh to auto-refresh interval is minimum tRFC. Any command must not be issued before tRFC from the REFA command. Auto-Refresh CK /S NOP or DESLECT /RAS /CAS /WE CKE minimum tRFC A0-11 BA0,1 Auto Refresh on All Banks MIT-DS-0340-0.3 Auto Refresh on All Banks MITSUBISHI ELECTRIC ( 27 / 51 ) 27.Mar.2001 Preliminary Spec. MITSUBISHI LSIs Some contents are subject to change without notice. MH8S64DBKG -6,-6L-7,-7L,-8,-8L 536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM SELF REFRESH Self-refresh mode is entered by issuing a REFS command (/CS=/RAS=/CAS=L, /WE=H, CKE=L). Once the self-refresh is initiated, it is maintained as log as CKE is kept low.During the self-refresh mode, CKE is asynchronous and the only enabled input , all other inputs including CK are disabled and ignored, so that power consumption due to synchronous inputs is saved. To exit the self-refresh, supplying stable CK inputs, asserting DESEL or NOP command and then asserting CKE=H. After tRFC from the 1st CK edge follwing CKE=H, all banks are in the idle state and a new command can be issued after, but DESEL or NOP commands must be asserted till then. Self-Refresh CK Stable CK /S NOP /RAS /CAS /WE CKE new command A0-11 X BA0,1 00 Self Refresh Entry MIT-DS-0340-0.3 Self Refresh Exit MITSUBISHI ELECTRIC ( 28 / 51 ) minimum tRFC for recovery 27.Mar.2001 Preliminary Spec. MITSUBISHI LSIs Some contents are subject to change without notice. MH8S64DBKG -6,-6L-7,-7L,-8,-8L 536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM CLK SUSPEND and POWER DOWN CKE controls the internal CLK at the following cycle. Figure below shows how CKE works. By negating CKE, the next internal CLK is suspended. The purpose of CLK suspend is power down, output suspend or input suspend. CKE is a synchronous input except during the self-refresh mode. CLK suspend can be performed either when the banks are active or idle. A command at the suspended cycle is ignored. CK (ext.CLK) tIH tIS tIH tIS CKE int.CLK Power Down by CKE CK Standby Power Down CKE Command PRE NOP NOP NOP Activ e Power Down CKE Command ACT NOP NOP NOP DQ Suspend by CKE CK CKE Command DQ MIT-DS-0340-0.3 Write D0 READ D1 D2 D3 MITSUBISHI ELECTRIC ( 29 / 51 ) Q0 Q1 Q2 Q3 27.Mar.2001 Preliminary Spec. MITSUBISHI LSIs Some contents are subject to change without notice. MH8S64DBKG -6,-6L-7,-7L,-8,-8L 536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM DQM CONTROL DQMB0-7 is a dual function signal defined as the data mask for writes and the output disable for reads. During writes, DQMB0-7 masks input data word by word. DQMB0-7 to Data In latency is 0. During reads, DQMB0-7 forces output to Hi-Z word by word. DQMB0-7 to output Hi-Z latency is 2. DQM Function CK Command READ Write DQMB0-7 DQ D0 D2 D3 Q0 masked by DQMB=H MIT-DS-0340-0.3 Q1 Q3 disabled by DQMB=H MITSUBISHI ELECTRIC ( 30 / 51 ) 27.Mar.2001 Preliminary Spec. MITSUBISHI LSIs Some contents are subject to change without notice. MH8S64DBKG -6,-6L-7,-7L,-8,-8L 536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM ABSOLUTE M AXIMUM RATINGS Symbol Parameter Condition Ratings Unit Vdd Supply Voltage with respect to Vss -0.5 ~ 4.6 V VI Input Voltage with respect to Vss -0.5 ~ Vdd+0.5 V VO Output Voltage with respect to Vss -0.5 ~ Vdd+0.5 V IO Output Current 50 mA Pd Power Dissipation 8 W Topr Operating Temperature 0 ~ 70 °C Tstg Storage Temperature -40 ~ 100 °C Ta=25°C RECOM M ENDED OPERATING CONDITION (Ta=0 ~ 70°C, unless otherwise noted) Limits Parameter Symbol Min. Typ. Max. Unit Vdd Supply Voltage 3.0 3.3 3.6 V Vss Supply Voltage 0 0 0 V VIH High-Level Input Voltage all inputs 2.0 Vdd+0.3 V VIL Low-Level Input Voltage all inputs -0.3 0.8 V Note) 1:VIH(max)=5.5V f or pulse width less than 10ns. 2.VIL(min)=-1.0 f or pulse width less than 10ns. CAPACITANCE (Ta=0 ~ 70°C, Vdd = 3.3 ± 0.3V, Vss = 0V, unless otherwise noted) Symbol Parameter Test Condition CI(A) Input Capacitance, address pin CI(C) Input Capacitance, control pin CI(K) Input Capacitance, CK pin CI/O Input Capacitance, I/O pin MIT-DS-0340-0.3 VI = 1.4V f=1MHz Vi=200mVrms MITSUBISHI ELECTRIC ( 31 / 51 ) Limits(max.) Unit 45 pF 45 pF 35 pF 22 pF 27.Mar.2001 Preliminary Spec. MITSUBISHI LSIs Some contents are subject to change without notice. MH8S64DBKG -6,-6L-7,-7L,-8,-8L 536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM AVERAGE SUPPLY CURRENT from Vdd (Ta=0 ~70°C, Vdd = 3.3 ± 0.3V, Vss = 0V, unless otherwise noted) Symbol Parameter Limits (max) -7,-7L, -6,-6L -8,-8L Test Condition operating current one bank activ e (discrete) Unit tRC=min.tCLK=min, BL=1,CL=3 Icc1 precharge stanby Icc2P CKE=L,tCLK=15ns, /CS>Vcc-0.2V current in power-down mode Icc2PS CKE=CLK=L, /CS>Vcc-0.2V precharge stanby current Icc2N CKE=H,tCLK=15ns,VIH>Vcc-0.2V,VIL<0.2V in non power-down mode Icc2NS CKE=H,CLK=L,VIH>Vcc-0.2V,VIL<0.2V(f ixed) 460 440 mA 16 16 mA 8 160 120 8 160 120 mA mA mA active stanby current in non power-down mode 240 240 mA 200 200 mA 520 1040 440 880 mA -6,-7,-8 8 8 mA mA -6L,-7L,-8L 4 4 mA one bank activ e (discrete) burst current auto-refresh current self-refresh current Icc3N CKE=H,tCLK=15ns Icc3NS CKE=H,CLK=L tCLK=min, BL=4, CL=3,all banks activ e(discerte) Icc4 tRC=min, tCLK=min Icc5 Icc6 CKE <0.2V Note) 1:Icc(max) is specif ied at the output open condition. 2.Input signals are changed one time during 30ns. AC OPERATING CONDITIONS AND CHARACTERISTICS (Ta=0 ~ 70°C, Vdd = 3.3 ± 0.3V, Vss = 0V, unless otherwise noted) Symbol VOH(DC) VOL(DC) IOZ VOH(AC) Ii VOL(AC) Limits Min. Max. Unit High-Level Output Voltage(DC) IOH=-2mA 2.4 V Low-Level Output Voltage(DC) IOL=2mA 0.4 V floating VO=0 10 uA Off-stare Output Current High-Level Output Voltage(AC) Q CL=50pF, IOH=- ~ Vdd -10 2 V 40 -40 Input Current 2mA VIH=0 ~ Vdd+0.3V Low-Level Output Voltage(AC) CL=50pF, IOL=2mA 0.8 uA V MIT-DS-0340-0.3 Parameter Test Condition MITSUBISHI ELECTRIC ( 32 / 51 ) 27.Mar.2001 Preliminary Spec. MITSUBISHI LSIs Some contents are subject to change without notice. MH8S64DBKG -6,-6L-7,-7L,-8,-8L 536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM AC TIMING REQUIREMENTS (SDRAM Component) (Ta=0 ~ 70°C, Vdd = 3.3 ± 0.3V, Vss = 0V, unless otherwise noted) Input Pulse Levels: 0.8V to 2.0V Input Timing Measurement Level: 1.4V Symbol Parameter tCLK tCH tCL tT tIS tIH tRC tRFC tRCD tRAS tRP tWR tRRD tRSC tREF Limits -7,-7L Min. Max. -6,-6L Min. Max. CL=2 -8,-8L Unit Min. Max. 10 10 13 ns 7.5 2.5 CK High pulse width 2.5 CK Low pilse width 1 Transition time of CK 1.5 Input Setup time(all inputs) 0.8 Input Hold time(all inputs) 67.5 Row cycle time 75 Refresh Cycle time 20 Row to Column Delay 45 Row Active time 20 Row Precharge time 12 Write Recovery time 15 Act to Act Deley time Mode Register Set Cycle time 10 Refresh Interval time 10 3 3 1 2 1 70 80 20 50 20 12 20 10 10 3 3 1 2 1 70 80 20 50 20 12 20 10 ns ns ns 10 ns ns ns ns ns ns 100K ns ns ns ns ns 64 ms CK cycle tim e CL=3 10 100K 64 10 100K 64 Note:1 The timing requirements are assumed tT=1ns.If tT is longer than 1ns,(tT-1)ns should be added to the parameter. CK 1.4V Any AC timing is referenced to the input Signal 1.4V signal crossing through 1.4V. MIT-DS-0340-0.3 MITSUBISHI ELECTRIC ( 33 / 51 ) 27.Mar.2001 Preliminary Spec. MITSUBISHI LSIs Some contents are subject to change without notice. MH8S64DBKG -6,-6L-7,-7L,-8,-8L 536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM SWITCHING CHARACTERISTICS (SDRAM Component) (Ta=0 ~ 70°C, Vdd = 3.3 ± 0.3V, Vss = 0V, unless otherwise note3) Limits -6,-6L -8,-8L -7,-7L Min. Max. Min. Max. Min. Max. Symbol Parameter tAC tOH tOLZ tOHZ Access time from CK Output Hold tim e from CK Unit CL=2 6 6 7 ns CL=3 5.4 6 6 ns CL=2 3 3 3 ns CL=3 2.7 3 3 ns 0 0 0 ns Delay time, output low impedance from CK Delay time, output high impedance from CK 5.4 2.7 3 6 3 6 ns Note) 1 If clock rising time is longer than 1ns,(tT/2-0.5)ns should be added to parameter. Output Load Condition CK 1.4V V OUT DQ 1.4V 50pF Output Timing Measurement Reference Point 1.4V CK tOLZ DQ 1.4V tAC MIT-DS-0340-0.3 tOH tOHZ MITSUBISHI ELECTRIC ( 34 / 51 ) 27.Mar.2001 Preliminary Spec. MITSUBISHI LSIs Some contents are subject to change without notice. MH8S64DBKG -6,-6L-7,-7L,-8,-8L 536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM Burst Write (single bank) @BL=4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 CLK tRC /CS tRAS tRP /RAS tRCD tRCD /CAS /WE tWR tWR CKE DQM A0-7 X A10 X X A8-9,11 X X BA0,1 0 Y 0 D0 DQ ACT#0 X 0 D0 WRITE#0 D0 Y 0 D0 D0 PRE#0 0 0 ACT#0 D0 WRITE#0 D0 D0 PRE#0 Italic parameter indicates minimum case MIT-DS-0340-0.3 MITSUBISHI ELECTRIC ( 35 / 51 ) 27.Mar.2001 Preliminary Spec. MITSUBISHI LSIs Some contents are subject to change without notice. MH8S64DBKG -6,-6L-7,-7L,-8,-8L 536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM Burst Write (multi bank) @BL=4 0 1 2 3 4 5 6 CLK 7 8 9 10 11 12 13 14 15 16 17 tRC tRC /CS tRRD tRAS tRP /RAS tRCD tRCD tRCD /CAS tWR tWR /WE CKE DQM A0-7 X A10 X X X X A8-9,11 X X X X BA0,1 0 DQ ACT#0 Y X 0 1 D0 D0 Y 1 D0 WRITE#0 ACT#1 D0 D1 X 0 D1 D1 Y 0 0 D1 D0 PRE#0 ACT#0 WRITEA#1 (Auto-Precharge) X 1 D0 D0 0 D0 WRITE#0 ACT#1 PRE#0 Italic parameter indicates minimum case MIT-DS-0340-0.3 MITSUBISHI ELECTRIC ( 36 / 51 ) 27.Mar.2001 Preliminary Spec. MITSUBISHI LSIs Some contents are subject to change without notice. MH8S64DBKG -6,-6L-7,-7L,-8,-8L 536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM Burst Read (single bank) @BL=4 CL=2 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 CLK tRC /CS tRAS tRP tRAS /RAS tRCD tRCD /CAS /WE CKE DQM A0-7 X A10 X X A8-9,11 X X BA0,1 0 Y X 0 0 Q0 DQ ACT#0 READ#0 Q0 Q0 Y 0 0 0 Q0 Q0 PRE#0 ACT#0 READ#0 Q0 Q0 Q0 PRE#0 Italic parameter indicates minimum case MIT-DS-0340-0.3 MITSUBISHI ELECTRIC ( 37 / 51 ) 27.Mar.2001 Preliminary Spec. MITSUBISHI LSIs Some contents are subject to change without notice. MH8S64DBKG -6,-6L-7,-7L,-8,-8L 536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM Burst Read (multiple bank) @BL=4 CL=2 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 CLK tRC tRC /CS tRAS tRRD /RAS tRCD tRCD tRCD /CAS /WE CKE DQM A0-7 X A10 X X X X A8-9,11 X X X X BA0,1 0 Y 0 X Y 1 1 Q0 DQ ACT#0 READA#0 ACT#1 X Q0 Q0 Y 0 0 Q1 Q0 X Q1 ACT#0 READA#1 Q1 0 1 Q1 Q0 Q0 READ#0 Q0 Q0 PRE#0 ACT#1 Italic parameter indicates minimum case MIT-DS-0340-0.3 MITSUBISHI ELECTRIC ( 38 / 51 ) 27.Mar.2001 Preliminary Spec. MITSUBISHI LSIs Some contents are subject to change without notice. MH8S64DBKG -6,-6L-7,-7L,-8,-8L 536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM Write Interrupted by Write @BL=4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 CLK /CS tRRD /RAS tRCD /CAS tWR /WE CKE DQM A0-7 X A10 X X X A8-9,11 X X X BA0,1 0 DQ Y X 0 1 D0 D0 Y Y 0 D0 D0 Y 1 D1 D1 X 0 D1 WRITE#0 ACT#0 WRITE#0 WRITEA#1 ACT#1 interrupt same bank interrupt other bank D1 D0 0 D0 WRITE#0 interrupt other bank D0 1 D0 PRE#0 ACT#1 Italic parameter indicates minimum case MIT-DS-0340-0.3 MITSUBISHI ELECTRIC ( 39 / 51 ) 27.Mar.2001 Preliminary Spec. MITSUBISHI LSIs Some contents are subject to change without notice. MH8S64DBKG -6,-6L-7,-7L,-8,-8L 536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM Read Interrupted by Read @BL=4 CL=2 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 CLK /CS tRRD /RAS tRCD tRCD /CAS /WE CKE DQM A0-7 X A10 X X X A8-9,11 X X X BA0,1 0 Y 0 X Y 1 1 Q0 DQ ACT#0 READ#0 ACT#1 Y Q0 Y 1 Q0 Q0 X 0 Q1 Q1 READ#1 READA#1 interrupt interurrpt other bank same bank Q1 1 Q1 Q0 READ#0 interurrpt other bank Q0 Q0 Q0 ACT#1 Italic parameter indicates minimum case MIT-DS-0340-0.3 MITSUBISHI ELECTRIC ( 40 / 51 ) 27.Mar.2001 Preliminary Spec. MITSUBISHI LSIs Some contents are subject to change without notice. MH8S64DBKG -6,-6L-7,-7L,-8,-8L 536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM Write Interrupted by Read, Read Interrupted by Write @BL=4,CL=2 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 CLK /CS tRRD /RAS tRCD tRCD /CAS tWR /WE CKE DQM A0-7 X X A10 X X A8-9,11 X X BA0,1 0 1 Y Y Y 0 1 1 D0 DQ ACT#0 D0 WRITE#0 READ#1 ACT#1 Q1 Q1 1 D1 D1 D1 D1 PRE#1 WRITE#1 Italic parameter indicates minimum case MIT-DS-0340-0.3 MITSUBISHI ELECTRIC ( 41 / 51 ) 27.Mar.2001 Preliminary Spec. MITSUBISHI LSIs Some contents are subject to change without notice. MH8S64DBKG -6,-6L-7,-7L,-8,-8L 536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM Write/Read Terminated by Precharge @BL=4 CL=2 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 CLK tRC /CS tRRD tRP tRAS tRP /RAS tRCD tRCD /CAS tWR /WE CKE DQM A0-7 X Y A10 X X X A8-9,11 X X X BA0,1 0 0 D0 DQ ACT#0 X 0 Y 0 0 D0 X 0 Q0 PRE#0 ACT#0 Termination WRITE#0 READ#0 0 Q0 PRE#0 ACT #0 Termination Italic parameter indicates minimum case MIT-DS-0340-0.3 MITSUBISHI ELECTRIC ( 42 / 51 ) 27.Mar.2001 Preliminary Spec. MITSUBISHI LSIs Some contents are subject to change without notice. MH8S64DBKG -6,-6L-7,-7L,-8,-8L 536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM Write/Read Terminated by Burst Terminate @BL=4,CL=2 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 CLK /CS /RAS tRCD /CAS tWR /WE CKE DQM A0-7 X A10 X A8-9,11 X BA0,1 0 Y Y Y 0 0 0 D0 DQ ACT#0 D0 D0 Q0 Q0 WRITE#0 TBST READ#0 0 D0 D0 WRITE#0 D0 D0 PRE#0 TBST Italic parameter indicates minimum case MIT-DS-0340-0.3 MITSUBISHI ELECTRIC ( 43 / 51 ) 27.Mar.2001 Preliminary Spec. MITSUBISHI LSIs Some contents are subject to change without notice. MH8S64DBKG -6,-6L-7,-7L,-8,-8L 536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM Single Write Burst Read @BL=4 CL=2 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 CLK /CS /RAS tRCD /CAS /WE CKE DQM A0-7 X A10 X A8-9,11 X BA0,1 0 Y Y 0 0 D0 DQ ACT#0 Q0 Q0 Q0 Q0 READ#0 WRITE#0 Italic parameter indicates minimum case MIT-DS-0340-0.3 MITSUBISHI ELECTRIC ( 44 / 51 ) 27.Mar.2001 Preliminary Spec. MITSUBISHI LSIs Some contents are subject to change without notice. MH8S64DBKG -6,-6L-7,-7L,-8,-8L 536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM Power-Up Sequence and Intialize CLK 200us /CS tRFC tRP tRFC tRSC /RAS /CAS /WE CKE DQM A0-7 MA X A10 0 X A8-9,11 0 X BA0,1 0 0 DQ NOP Power On PRE ALL REFA REFA REFA MRS ACT#0 Minimum 8 REFA cy c les MIT-DS-0340-0.3 MITSUBISHI ELECTRIC ( 45 / 51 ) 27.Mar.2001 Preliminary Spec. MITSUBISHI LSIs Some contents are subject to change without notice. MH8S64DBKG -6,-6L-7,-7L,-8,-8L 536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM Auto Refresh 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 CLK tRFC /CS /RAS tRP tRCD /CAS /WE CKE DQM A0-7 X A10 X A8-9,11 X BA0,1 0 Y 0 D0 DQ PRE ALL REFA ACT #0 D0 D0 D0 WRITE#0 Italic parameter indicates minimum case MIT-DS-0340-0.3 MITSUBISHI ELECTRIC ( 46 / 51 ) 27.Mar.2001 Preliminary Spec. MITSUBISHI LSIs Some contents are subject to change without notice. MH8S64DBKG -6,-6L-7,-7L,-8,-8L 536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM Self Refresh 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 CLK tRFC /CS tRP /RAS /CAS /WE CKE DQM A0-7 X A10 X A8-9,11 X 0 BA0,1 DQ PRE ALL Self Refresh Entry Self RefreshExit ACT#0 All banks must be idle bef ore REFS is issued. MIT-DS-0340-0.3 MITSUBISHI ELECTRIC ( 47 / 51 ) 27.Mar.2001 Preliminary Spec. MITSUBISHI LSIs Some contents are subject to change without notice. MH8S64DBKG -6,-6L-7,-7L,-8,-8L 536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM CLK Suspension @BL=4 CL=2 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 CLK /CS /RAS tRCD /CAS /WE CKE DQM A0-7 X A10 X A8-9,11 X BA0,1 0 Y Y 0 0 D0 DQ ACT#0 D0 D0 D0 Q0 D0 WRITE#0 Q0 Q0 Q0 READ#0 Internal CLK suspended Internal CLK suspended Italic parameter indicates minimum case MIT-DS-0340-0.3 MITSUBISHI ELECTRIC ( 48 / 51 ) 27.Mar.2001 Preliminary Spec. MITSUBISHI LSIs Some contents are subject to change without notice. MH8S64DBKG -6,-6L-7,-7L,-8,-8L 536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM Power Down 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 CLK /CS /RAS /CAS /WE Active Power Down Stanby Power Down CKE DQM A0-7 X A10 X A8-9,11 X BA0,1 0 DQ PRE ALL ACT#0 Italic parameter indicates minimum case MIT-DS-0340-0.3 MITSUBISHI ELECTRIC ( 49 / 51 ) 27.Mar.2001 Preliminary Spec. MITSUBISHI LSIs Some contents are subject to change without notice. MH8S64DBKG -6,-6L-7,-7L,-8,-8L 536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM OUTLINE 31.75 20.00 4.00 MIT-DS-0340-0.3 6.00 MITSUBISHI ELECTRIC ( 50 / 51 ) 27.Mar.2001 Preliminary Spec. MITSUBISHI LSIs Some contents are subject to change without notice. MH8S64DBKG -6,-6L-7,-7L,-8,-8L 536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM Keep safety first in your circuit designs! Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. 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It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Mitsubishi Electric Corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Mitsubishi Electric Corporation by various means, including the Mitsubishi Semiconductor home page (http://www.mitsubishichips.com). 4.When using any or all of the information contained in these materials, including product data, diagrams, charts, programs and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. 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Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6.The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials. 7.If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8.Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein. MIT-DS-0340-0.3 MITSUBISHI ELECTRIC ( 51 / 51 ) 27.Mar.2001