Anpec APA0714XAI-TRG 3w mono fully differential audio power amplifier Datasheet

APA0714
3W Mono Fully Differential Audio Power Amplifier
Features
General Description
•
•
•
Operating Voltage: 2.4V~5.5V
Fully Differential Class-AB Amplifier
The APA0714 is a Mono, fully differential Class-AB audio
amplifier which can operate with supply voltage from 2.4V
High PSRR and Excellent RF Rectification
Immunity
to 5V and is available in MSOP8, MSOP8P, or TDFN3x3-8
package.
Low Crosstalk
3W Output Power into 3Ω Load at VDD=5V
The built-in feedback resistors can minimize the external
component count and save the PCB space. High PSRR
Thermal and Over-Current Protections
Built-in Feedback Resistors Eliminate
and fully differential architecture increase immunity to
noise and RF rectification. In addition to these features, a
External Components Counts
Space Saving Package
short startup time and small package size make the
APA0714 an ideal choice for Mobil Phones and Portable
- MSOP-8
- MSOP-8P
Devices.
The APA0714 also integrates the de-pop circuitry that re-
- TDFN3x3-8
Lead Free and Green Devices Available
duces the pops and click noises during power on/off and
shutdown mode operation. Both Thermal and over-cur-
(RoHS Compliant)
rent protections are integrated to avoid the IC to be destroyed by over temperature and short-circuit.
•
•
•
•
•
•
Applications
The APA0714 is capable of driving 3W at 5V into 3Ω
speaker.
•
•
Pin Configuration
Mobil Phones
Portable Devices
SD 1
BYPASS 2
Simplified Application Circuit
INP 3
8 OUTN
MSOP-8
Top View
INN 4
LINN
LOUTP
APA0714
Input
LINP
INP 3
6 VDD
5 OUTP
SD 1
BYPASS 2
7 GND
8 OUTN
MSOP-8P
Top View
INN 4
7 GND
6 VDD
5 OUTP
Speaker
LOUTN
8 OUTN
SD 1
7 GND
BYPASS 2
INP 3
INN 4
TDFN3x3-8
TOP View
6 VDD
5 OUTP
=Thermal Pad (connected the Thermal Pad to
GND plane for better heat dissipation)
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and
advise customers to obtain the latest version of relevant information to verify before placing orders.
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Apr., 2010
1
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APA0714
Ordering and Marking Information
Package Code
X : MSOP-8 XA : MSOP-8P QB : TDFN3x3-8
Operating Ambient Temperature Range
I : -40 to 85 oC
Handling Code
TR : Tape & Reel
Assembly Material
G : Halogen and Lead Free Device
APA0714
Assembly Material
Handling Code
Temperature Range
Package Code
APA0714 X :
A0714
XXX
XX
XXXXX - Date Code
APA0714 XA :
A0714
XXX
XX
XXXXX - Date Code
APA0714 QB :
APA
0714
XXXXX
XXXXX - Date Code
Note : ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which
are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for
MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen
free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by
weight).
Absolute Maximum Ratings
Symbol
VDD
VIN
TJ
TSTG
TSDR
PD
(Note 1)
Parameter
Rating
Unit
V
Supply Voltage
-0.3 to 6
Input Voltage (INN, INP, SD to GND)
-0.3 to 6
Input Voltage (OUTN, OUTP to GND)
-0.3 to VDD +0.3
Maximum Junction Temperature
Storage Temperature Range
Maximum Soldering Temperature Range, 10 Seconds
Power Dissipation
V
150
ο
-65 to +150
ο
260
ο
C
C
C
Internally Limited
W
Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Thermal Characteristics
Symbol
Parameter
Thermal Resistance -Junction to Ambient
Typical Value
θJA
θJC
Unit
(Note 2)
MSOP-8
MSOP-8P
TDFN3x3-8
200
50
52
ο
MSOP-8P
TDFN3x3-8
10
11
ο
Thermal Resistance -Junction to Case (Note 3)
C/W
C/W
Note 2: Please refer to “ Layout Recommendation”, the Thermal Pad on the bottom of the IC should soldered directly to the PCB’s
ThermalPad area that with several thermal vias connect to the ground plan, and the PCB is a 2-layer, 5-inch square area with 2oz
copper thickness.
Note 3: The case temperature is measured at the center of the Thermal Pad on the underside of the MSOP-8P and TDFN3x3-8
package.
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Apr., 2010
2
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APA0714
Recommended Operating Conditions
Symbol
VDD
Parameter
Supply Voltage
VIH
High Level Threshold Voltage
VIL
Low Level Threshold Voltage
VIC
Rating
Unit
2.4
~ 5.5
V
SD
1.8
~ VDD
V
SD
0
~ 0.35
V
Common Mode Input Voltage
0.5
~ VDD-0.5
Operating Ambient Temperature Range
-40
~ 85
ο
Operating Junction Temperature Range
-40
~ 125
ο
~
Ω
Speaker Resistance
3
V
C
C
Electrical Characteristics
o
VDD=5V, GND=0V, TA= 25 C (unless otherwise noted)
Symbol
Parameter
IDD
Supply Current
ISD
Shutdown Current
LSD=RSD=0V
Input Current
LSD, RSD
II
Gain
TSTART-UP
RSD
Unit
Min.
Typ.
Max.
-
3
6
mA
-
-
5
µA
-
0.1
-
µA
36kΩ
Ri
40kΩ
Ri
44kΩ
Ri
V/V
-
65
-
ms
90
100
110
kΩ
RL=3Ω
-
2.4
-
RL=4Ω
-
2.1
-
RL=8Ω
1
1.3
-
RL=3Ω
-
3
-
RL=4Ω
-
2.6
-
RL=8Ω
-
1.6
-
RL=4Ω
PO=1.5W
-
0.05
-
RL=8Ω
PO=0.9W
-
0.035
-
RL=4Ω
Start-Up Time from End of
Shutdown
APA0714
Test Conditions
Cb=0.22µF
Resistance from Shutdown to GND
VDD=5V, TA=25°
C
THD+N=1%
PO
Output Power
THD+N=10%
fin=1kHz
W
Total Harmonic Distortion Pulse
Noise
fin=1kHz
PSRR
Power Supply Rejection Ratio
Cb=0.22µF, RL=8Ω, VRR=0.2VPP,
fin=217Hz
-
80
-
dB
CMRR
Common-Mode Rejection Ratio
Cb=0.22µF, RL=8Ω, VIC=0.2VPP,
fin=217Hz
-
60
-
dB
S/N
Signal to Noise Ratio
With A-weighted Filter,
PO=1.3W, RL=8Ω
-
105
-
dB
VOS
Output Offset Voltage
RL=8Ω
-
5
20
mV
Vn
Noise Output Voltage
Cb=0.22µF, With A-weighting Filter
-
15
-
µV
(rms)
THD+N
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Apr., 2010
3
%
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APA0714
Electrical Characteristics (Cont.)
o
VDD=5V, GND=0V, TA= 25 C (unless otherwise noted)
Symbol
Parameter
APA0714
Test Conditions
Unit
Min.
Typ.
Max.
RL=3Ω
-
1.2
-
RL=4Ω
-
1
-
RL=8Ω
-
0.65
-
RL=3Ω
-
1.5
-
RL=4Ω
-
1.3
-
RL=8Ω
-
0.8
-
RL=4Ω
PO=0.7W
-
0.07
-
RL=8Ω
PO=0.45W
-
0.05
-
VDD=3.6V, TA=25°
C
THD+N=1%
PO
Output Power
THD+N=10%
fin=1kHz
W
Total Harmonic Distortion
Pulse Noise
fin=1kHz
PSRR
Power Supply Rejection Ratio
Cb=0.22µF, RL=8Ω, VRR=0.2VPP,
fin=217Hz
-
78
-
CMRR
Common-Mode Rejection
Ratio
Cb=0.22µF, RL=8Ω, VIC=0.2VPP,
fin=217Hz
-
60
-
S/N
Signal to Noise Ratio
With A-weighting Filter,
PO=0.65W, RL=8Ω
-
103
-
VOS
Output Offset Voltage
RL=8Ω
-
5
20
mV
Vn
Noise Output Voltage
Cb=0.22µF, With A-weighting Filter
-
15
-
µV
(rms)
THD+N
%
dB
VDD=2.4V, TA=25°
C
THD+N=1%
PO
Output Power
THD+N=10%
fin=1kHz
RL=3Ω
-
0. 5
-
RL=4Ω
-
0.45
-
RL=8Ω
-
0.3
-
RL=3Ω
-
0.7
-
RL=4Ω
-
0.6
-
RL=8Ω
-
0.35
-
PO=0.3W,
RL=4Ω
-
0.1
-
PO=0.2W,
RL=8Ω
-
0.08
-
W
Total Harmonic Distortion
Pulse Noise
fin = 1kHz
PSRR
Power Supply Rejection Ratio
Cb=0.22µF, RL=8Ω, VRR=0.2VPP,
fin=217Hz
-
75
-
CMRR
Common-Mode Rejection
Ratio
Cb=0.22µF, RL=8Ω, VIC=0.2VPP,
fin=217Hz
-
60
-
S/N
Signal to Noise Ratio
With A-weighting Filter,
PO=0.3W, RL=8Ω
-
100
-
VOS
Output Offset Voltage
RL=8Ω
-
5
20
mV
Vn
Noise Output Voltage
Cb=0.22µF, With A-weighting Filter
-
15
-
µV
(rms)
THD+N
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Apr., 2010
4
%
dB
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APA0714
Typical Operating Characteristics
THD+N vs. Output Power
10
THD+N vs. Output Power
10
RL=3Ω
fin=1kHz
Ci=0.22µF
AV=12dB
BW<80kHz
1
THD+N (%)
THD+N (%)
1
RL=4Ω
fin=1kHz
Ci=0.22µF
AV=12dB
BW<80kHz
VDD=2.4V
0.1
VDD=2.4V
0.1
VDD=3.6V
VDD=3.6V
VDD=5.0V
0.01
10m
100m
1
0.01
10m
5
Output Power (W)
5
THD+N vs. Frequency
1
VDD=2.4V
0.1
VDD=3.6V
0.01
10m
VDD=5.0V
RL=3Ω
Ci=0.22µF
AV=12dB
BW<80kHz
1
PO=1W
0.1
PO=1.7W
VDD=5.0V
100m
1
0.01
3
20
100
Output Power (W)
THD+N vs. Frequency
THD+N vs. Frequency
THD+N (%)
PO=1W
0.1
VDD=5.0V
RL=8Ω
Ci=0.22µF
AV=12dB
BW<80kHz
1
PO=0.5W
0.1
PO=1.5W
20
100
10k 20k
10
VDD=5.0V
RL=4Ω
Ci=0.22µF
AV=12dB
BW<80kHz
1
1k
Frequency (Hz)
10
THD+N (%)
1
10
RL=8Ω
fin=1kHz
Ci=0.22µF
AV=12dB
BW<80kHz
THD+N (%)
THD+N (%)
100m
Output Power (W)
THD+N vs. Output Power
10
0.01
VDD=5.0V
1k
PO=0.9W
0.01
10k 20k
20
Frequency (Hz)
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Apr., 2010
100
1k
10k 20k
Frequency (Hz)
5
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APA0714
Typical Operating Characteristics (Cont.)
THD+N vs. Frequency
THD+N vs. Frequency
10
VDD=3.6V
RL=4Ω
Ci=0.22µF
AV=12dB
BW<80kHz
1
PO=0.1W
PO=0.5W
0.1
PO=0.7W
VDD=3.6V
RL=8Ω
Ci=0.22µF
AV=12dB
BW<80kHz
1
THD+N (%)
THD+N (%)
10
PO=0.1W
PO=0.25W
0.1
PO=0.45W
0.01
20
100
1k
0.01
10k 20k
20
100
10
1
PO=0.1W
0.1
20
PO=0.3W
100
1k
VDD=2.4V
RL=8Ω
Ci=0.22µF
AV=12dB
BW<80kHz
1
THD+N (%)
THD+N (%)
VDD=2.4V
RL=4Ω
Ci=0.22µF
AV=12dB
BW<80kHz
PO=0.1W
0.1
0.01
10k 20k
20
100
Frequency (Hz)
Output Power vs. Supply Voltage
2.5
2.0
10k 20k
Output Power vs. Load Resistance
fin=1kHz
AV=12dB
VDD=5V,THD+N=10%
RL=3Ω,THD+N=10%
VDD=5V,THD+N=1%
RL=4Ω,THD+N=10%
RL=3Ω,THD+N=1%
1.5
1.0
0.5
3.5
4.0
4.5
VDD=3.6V,THD+N=10%
VDD=3.6V,THD+N=1%
2.0
VDD=2.4V,THD+N=10%
1.5
VDD=2.4V,THD+N=1%
1.0
0.0
3
5.0
8
13
18
23
28
32
Load Resistance (Ω)
Supply Volume (V)
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Apr., 2010
2.5
0.5
RL=8Ω,THD+N=10%
RL=8Ω,THD+N=1%
3.0
fin=1kHz
AV=12dB
3.0
RL=4Ω,THD+N=1%
0.0
2.4
1k
3.5
Output Power (W)
3.0
PO=0.2W
Frequency (Hz)
3.5
Output Power (W)
10k 20k
THD+N vs. Frequency
THD+N vs. Frequency
10
0.01
1k
Frequency (Hz)
Frequency (Hz)
6
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APA0714
Typical Operating Characteristics (Cont.)
Power Dissipation vs. Output Power
Power Dissipation vs. Output Power
1.0
1.5
RL=3Ω
RL=4Ω
1.0
0.5
RL=8Ω
0.0
0.0
0.5
1.0
1.5
0.8
Power Dissipation (W)
Power Dissipation (W)
2.0
RL=3Ω
0.6
RL=4Ω
0.4
2.0
2.5
VDD=3.6V
fin=1kHz
AV=12dB
0.2
VDD=5V
fin=1kHz
AV=12dB
RL=8Ω
0.0
3.0
0.0
0.3
0.6
0.9
1.2
0.8
RL=3Ω
RL=3Ω
0.8
0.6
Supply Current (A)
Supply Current (A)
1.8
Supply Current vs. Output Power
Supply Current vs. Output Power
1.0
0.6
RL=4Ω
0.4
RL=8Ω
VDD=5V
fin=1kHz
AV=12dB
0.2
0.0
0.0
0.5
1.0
1.5
2.0
2.5
RL=4Ω
0.4
RL=8Ω
0.2
VDD=3.6V
fin=1kHz
AV=12dB
0.0
0.0
3.0
0.3
0.6
0.9
1.2
1.5
1.8
Output Power (W)
Output Power (W)
Output Noise Voltage vs. Frequency
Output Noise Voltage vs. Frequency
50u
40u
50u
40u
30u
Output Noise Voltage (Vrms)
Output Noise Voltage (Vrms)
1.5
Output Power (W)
Output Power (W)
20u
10u
7u
5u
4u
VDD=5.0V
RL=8Ω
AV=12dB
Ci=0.22µF
A-Weighting
3u
2u
50
20u
10u
7u
5u
4u
VDD=3.6V
RL=8Ω
AV=12dB
Ci=0.22µF
A-Weighting
3u
2u
1u
1u
20
30u
100 200
500 1k
2k
20
5k 10k 20k
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Apr., 2010
50 100 200
500 1k
2k
5k 10k 20k
Frequency (Hz)
Frequency (Hz)
7
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APA0714
Typical Operating Characteristics (Cont.)
Output Noise Voltage vs. Frequency
PSRR vs. Frequency
+0
Power Supply Rejection Ratio (dB)
Output Noise Voltage (Vrms)
50u
40u
30u
20u
10u
7u
5u
4u
VDD=2.4V
RL=8Ω
AV=12dB
Ci=0.22µF
A-Weighting
3u
2u
1u
20
100
1k
RL=8Ω
AV=12dB
Cb=0.22µF
Ci=0.22µF
Vrr=0.2Vrms
-10
-20
-30
-40
-50
-60
-70
VDD=2.4V
-80
VDD=3.6V
-90
-100
10k 20k
20
100
Frequency (Hz)
Common Mode Rejection Ratio (dB)
VDD=3.6V
RL=8Ω
AV=12dB
Ci=0.22µF
Vrr=0.2Vrms
-20
-30
-40
Cb=0.01µF
-50
Cb=0.1µF
-60
-70 Cb=0.47µF
-80
Cb=1µF
-90
-20
-30
-40
-50
100
1k
VDD=2.4V
-60
VDD=3.6V
-70
-80
20
RL=8Ω
AV=12dB
Vin=0.2VPP
Ci=0.22µF
-10
10k 20k
VDD=5.0V
20
100
CMRR vs. Common Mode Input Voltage
10k 20k
Frequency Response
+0
+260
+14
RL=8Ω
AV=12dB
fin=1kHz
Ci=0.22µF
Gain
+12
+220
-30
-40
-50
Gain (dB)
Common Mode Rejection Ratio (dB)
1k
Frequency (Hz)
Frequency (Hz)
VDD=2.4V
VDD=3.6V
-60
VDD=5.0V
+10
+180
Phase
+8
+140
Phase (deg)
Power Supply Rejection Ratio (dB)
+0
-10
-20
10k 20k
CMRR vs. Frequency
PSRR vs. Frequency
-10
1k
Frequency (Hz)
+0
-100
VDD=5.0V
-70
-80
VDD=5.0V
AV=12dB
RL=8Ω
Ci=0.22µF
+6
-90
-100
+4
1
2
3
4
5
10
Common Mode Input Voltage (Vrms)
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Apr., 2010
100
1k
10k
200k
+100
+60
Frequency (Hz)
8
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APA0714
Typical Operating Characteristics (Cont.)
Frequency Response
Frequency Response
+14
+260
+14
+220
+12
Gain
+8
+140
VDD=3.6V
AV=12dB
RL=8Ω
Ci=0.22µF
+6
10
100
1k
+100
+10
+180
Phase
+8
+140
VDD=2.4V
AV=12dB
RL=8Ω
Ci=0.22µF
+6
+4
+60
200k
10k
+220
10
100
Frequency (Hz)
200k
+60
Start-up Time vs. Bypass Capacitor
Supply Current vs. Supply Voltage
200
Av=12dB
No Load
Start-up Time (ms)
4
Supply Current (mA)
10k
+100
Frequency (Hz)
5
3
2
1
0
2.4
3.0
3.5
4.0
4.5
5.0
150
VDD=5.0V
Av=12dB
No Load
100
50
0
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
5.5
Supply Voltage (V)
+0
-40
-80
-120
-160
+0
Supply Voltage (dBV)
Bypass Capacitor (µF)
GSM Power Supply Rejection vs.
Frequency
Output Voltage (dBV)
1k
Phase (deg)
+180
Phase
Gain (dB)
Gain (dB)
+10
Phase (deg)
Gain
+12
+4
+260
-40
-80
-120
-160
0
400
800
1.2k
1.6k
2k
Frequency (Hz)
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Apr., 2010
9
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APA0714
Operating Waveforms
GSM Power Supply Rejection vs. Time
Power On
VDD
1
VDD
1
2
VOUT
VOUT
2
CH1: VDD, 2V/Div, DC
CH1: VDD, 100mV/Div, DC
Vottage Offset = 5.0V
CH2: VOUT, 20mV/Div, DC
CH2: VOUT, 50mV/Div, DC
TIME: 20ms/Div
TIME: 2ms/Div
Power Off
Shutdown Release
VDD
VSD
1
1
2
VOUT
VOUTN
2
CH2: VOUT, 50mV/Div, DC
CH1: VSD, 2V/Div, DC
CH2: VOUTN, 2V/Div, DC
TIME: 50ms/Div
TIME: 20ms/Div
CH1: VDD, 2V/Div, DC
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Apr., 2010
10
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APA0714
Operating Waveforms (Cont.)
Shutdown
VSD
1
VOUTN
2
CH1: VSD, 2V/Div, DC
CH2: VOUTN, 2V/Div, DC
TIME: 20ms/Div
Pin Description
PIN
I/O/P
FUNCTION
SD
I
Shutdown mode control signal input, place left channel speaker amplifier in shutdown mode
when held low.
2
BYPASS
P
Bypass voltage input pin
3
INP
I
The non-inverting input of amplifier. INP is via a capacitor to Gnd for single-end (SE) input
signal.
4
INN
I
The inverting input of amplifier. INN is used as audio input terminal, typically.
5
ROUTP
O
The positive output terminal of speaker amplifier.
6
VDD
P
Supply voltage input pin
NO.
NAME
1
7
GND
P
Ground connection for circuitry.
8
LOUTN
O
The negative output terminal of speaker amplifier.
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Apr., 2010
11
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APA0714
Block Diagram
LINN
OUTP
OUTN
LINP
BYPASS
SD
Bias and Control Circuitrys
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APA0714
Typical Application Circuits
Single-ended input mode
VDD
Cs2
0.1µF
Cs1
10µF
6 VDD
40kΩ Rf1
Ci1
Ri1
Input
0.22µF
Ci2
0.22µF
INN 4
5 OUTP
10kΩ
Ri2
8 OUTN
INP 3
4Ω
10kΩ
40kΩ Rf2
SHUTDOWN
Control
SD 1
Bias and Control
Circuitrys
2 BYPASS
Cb
0.22µF
RSD
100kΩ
7 GND
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APA0714
Typical Application Circuits (Cont.)
Differential input mode
VDD
Cs2
0.1µF
Cs1
10µF
6 VDD
40kΩ Rf1
Ci1
0.22µF
Ri1
INN 4
5 OUTP
10kΩ
Input
Ci2
0.22µF
Ri2
8 OUTN
INP 3
4Ω
10kΩ
40kΩ Rf2
SHUTDOWN
Control
SD 1
Bias and Control
Circuitrys
2 BYPASS
Cb
0.22µF
RSD
100kΩ
7 GND
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APA0714
Function Description
Fully Differential Amplifier
The power amplifiers are fully differential amplifiers with
maximum device performance. By switching the SD pin
to low level, the amplifier enters a low-consumption-cur-
differential inputs and outputs. The fully differential amplifier has some advantages versus traditional amplifiers.
rent state, IDD for APA0714 is in shutdown mode. Under
normal operating, APA0714’s SD pin should pull to high
First, don’t need the input coupling capacitors because
the common-mode feedback compensates the input bias.
level to keep the IC out of the shutdown mode. The SD
pin should be tied to a definite voltage to avoid unwanted
The inputs can be biased from 0.5V~VDD-0.5V, and the
outputs are still biased at mid-supply of the power
state change.
amplifier. If the inputs are biased at out of the input range,
the coupling capacitors are required. Second, the fully
differential amplifier has outstanding immunity against
supply voltage ripple (217Hz) cuased by the GSM RF transmitters signal which is better than the typical audio
amplifier.
Thermal Protection
The over-temperature circuit limits the junction temperature of the APA0714. When the junction temperature exceeds T J =+150 o C, a thermal sensor turns off the
amplifiers, allowing the device to cool. The thermal sensor allows the amplifiers to start-up after the junction temperature cools down to about 125 oC. The thermal protection is designed with a 25 oC hysteresis to lower the average TJ during continuous thermal overload conditions,
increasing lifetime of the IC.
Over-Current Protection
The APA0714 monitors the output buffers current. When
the over current occurs, the output buffers current will be
reduced and limited to a fold-back current level.
The power amplifier will go back to normal operation until
the over-current current situation has been removed. In
addition, if the over-current period is long enough and the
IC’s junction temperature reaches the thermal protection
threshold, the IC enters thermal protection mode.
Shutdown Function
In order to reduce power consumption while not in use,
the APA0714 contains a shutdown function to externally
turn off the amplifier bias circuitry. This shutdown feature
turns the amplifier off when logic low is placed on the SD
pin for APA0714. The trigger point between a logic high
and logic low level is typically 1.8V. It is best to switch
between ground and the supply voltage VDD to provide
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APA0714
Application Information
amplifiers’ inputs are held at VDD/2. Please note that it is
important to confirm the capacitor polarity in the application.
Input Resistance (Ri)
The gain for the APA0714 is set by the external input resistors (Ri) and internal feedback resistors (Rf).
R
AV = f
Ri
Effective Bypass Capacitor (CBYPASS)
The BYPASS pin sets the VDD/2 for internal reference by
voltage divider. Adding capacitors at this pin to filter the
(1)
The internal feedback resistors are 40kΩ typical. For the
performance of a fully differential amplifier, it’s better to
noise and regulator the mid-supply rail will increase the
PSRR and noise performance.
select matching input resistors Ri1 and Ri2. Therefore,
1% tolerance resistors are recommended. If the input
The capacitors should be as close to the device as
possible. The effect of a larger bypass capacitor will im-
resistors are not matched, the CMRR and PSRR performance are worse than using matching devices.
prove PSRR due to increased supply stability.
The bypass capacitance also affects to the start time. The
large capacitors will increase the start time when device
in shutdown.
Input Capacitor (Ci)
When the APA0714 is driven by a differential input source,
the input capacitor may not be required.
Optimizing Depop Circuitry
In the single-ended input application, an input capacitor,
Ci, is required to allow the amplifier to bias the input sig-
Circuitry has been included in the APA0714 to minimize
the amount of popping noise at power-up and when coming out of shutdown mode. Popping occurs whenever a
nal to the proper DC level for optimum operation. In this
case, Ci and the input resistance Ri form a high-pass filter
voltage step is applied to the speaker. In order to eliminate clicks and pops, all capacitors must be fully dis-
with the corner frequency determined in the following
equation:
1
FC(highpass) =
(2)
2πR iCi
The value of Ci must be considered carefully because it
directly affects the low frequency performance of the circuit.
charged before turn-on. Rapid on/off switching of the device or the shutdown function will cause the click and pop
circuitry.
The value of Ci will also affect turn-on pops. The bypass
voltage ramp up should be slower than input bias voltage.
Consider the example where Ri is 10kΩ and the specification that calls for a flat bass response down to 100Hz.
Although the BYPASS pin current source cannot be
modified, the size of CBYPASS can be changed to alter the
device turn-on time and the amount of clicks and pops.
The equation is reconfigured below:
Ci =
1
2πRiFc
By increasing the value of CBYPASS, turn-on pop can be
reduced. However, the tradeoff for using a larger bypass
(3)
When the input resistance variation is considered, the Ci
capacitor is to increase the turn-on time for this device.
There is a linear relationship between the size of CBYPASS
is 0.16µF. So a value in the range of 0.22µF to 0.47µF
would be chosen. A further consideration for this capaci-
and the turn-on time.
A high gain amplifier intensifies the problem as the small
tor is the leakage path from the input source through the
input network (Ri + Rf, Ci) to the load.
delta in voltage is multiplied by the gain. Hence, it is advantageous to use low-gain configurations.
This leakage current creates a DC offset voltage at the
input of the amplifier. The offset reduces useful
Power Supply Decoupling Capacitor (Cs)
headroom, especially in high gain applications. For this
reason, a low-leakage tantalum or ceramic capacitor is
The APA0714 is a high-performance CMOS audio amplifier that requires adequate power supply decoupling to
the best choice. When polarized capacitors are used, the
positive side of the capacitor should face the amplifier
ensure the output total harmonic distortion (THD+N) is
as low as possible. Power supply decoupling also pre-
input in most applications because the DC level of the
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APA0714
Application Information (Cont.)
less than the dissipation in the half power range. Calcu-
Power Supply Decoupling Capacitor (Cs) (Cont.)
lating the efficiency for a specific system is the key to
proper power supply design. For a Mono 1W audio system with 8Ω loads and a 5V supply, the maximum draw
on the power supply is almost 1.63W.
vents the oscillations caused by long lead length between
the amplifier and the speaker.
The optimum decoupling is achieved by using two different types of capacitors that target on different types of
noises on the power supply leads. For higher frequency
Table 1: Efficiency vs. Output Power in 5-V Differential
Amplifier Syetems
transients, spikes, or digital hash on the line, a good low
equivalent-series- resistance (ESR) ceramic capacitor,
RL (Ω)
typically 0.1µF, is placed as close as possible to the device VDD lead works best. For filtering lower frequency
8
noise signals, a large aluminum electrolytic capacitor of
10µF or greater placed near the audio power amplifier is
recommended.
4
Fully Differential Amplifier Efficiency
The traditional class AB power amplifier efficiency can be
calculated starts out as being equal to the ratio of power
3
from the power supply to the power delivered to the load.
The following equations are the basis for calculating the
amplifier efficiency.
Efficiency (η) =
2
PO
PSUP
0.25
0.50
1
1.6
0.4
1.2
2
2.6
0.5
1
2
3
30.1
43.1
61.5
77.7
27.5
48.1
62.4
74.1
27.5
38.7
55.1
66.8
0.17
0.23
0.33
0.43
0.29
0.51
0.66
0.70
0.37
0.52
0.74
0.92
PD (W) PSUP (W)
0.58
0.66
0.63
0.46
1.06
1.30
1.21
0.91
1.32
1.58
1.63
1.49
0.83
1.16
1.63
2.06
1.46
2.50
3.21
3.51
1.82
2.58
3.63
4.49
efficiency equation to an utmost advantage when possible.
Note that in equation, VDD is in the denominator. This indicates that as VDD goes down, efficiency goes up. In other
words, use the efficiency analysis to choose the correct
2
supply voltage and speaker impedance for the application.
VP
2
2V V
PSUP = VDD XIDD（AVG）＝ DD PP
πRL
IDD（AVG)
IDD(A)
SE or Differential) is how to manipulate the terms in the
(4)
VOrms
V
= P
RL
2RL
VOrms =
Efficiency
(%)
A final point to remember about linear amplifiers (either
where:
PO =
PO (W)
Layout Recommendation
1. All components should be placed close to the APA0714.
(5)
For example, the input capacitor (Ci) should be close to
APA0714’s input pins to avoid causing noise coupling to
2VP
=
πRL
APA0714’s high impedance inputs; the decoupling capacitor (Cs) should be placed by the APA0714’s power pin
So the Efficiency (η) is:
πVP π 2PORL
Efficiency (η) =
＝
4VDD
4VDD
to decouple the power rail noise.
2. The output traces should be short, wide ( >50mil), and
(6)
symmetric.
3. The input trace should be short and symmetric.
Table 1 calculates efficiencies for four different output
power levels. Note that the efficiency of the amplifier is
4. The power trace width should greater than 50mil.
5. The MSOP-8P and DFN3x3-8 Thermal PAD should be
quite low for lower power levels and rises sharply as
power to the load is increased resulting in nearly flat in-
soldered on PCB, and the ground plane needs soldered
mask (to avoid short circuit) except the Thermal PAD area.
ternal power dissipation over the normal operating range.
Note that the internal dissipation at full output power is
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APA0714
Application Information (Cont.)
Layout Recommendation (Cont.)
1.85mm
1.95mm
3.3mm
1.4mm
0.38mm
0.65mm
0.7mm
ThermalVia
diameter
0.3mm X 5
Ground plane
for Thermal
PAD
Solder Mask
to Prevent
Short Circuit
Figure 1: TDFN3X3-8 Land Pattern Recommendation
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APA0714
Package Information
MSOP-8
D
b
0.25
A
A1
A2
c
L
GAUGE PLANE
SEATING PLANE
0
e
E
E1
SEE VIEW A
VIEW A
S
Y
M
B
O
L
MSOP-8
MILLIMETERS
MIN.
INCHES
MIN.
MAX.
A
MAX.
0.043
1.10
A1
0.00
0.15
0.000
0.006
A2
0.75
0.95
0.030
0.037
b
0.22
0.38
0.009
0.015
c
0.08
0.23
0.003
0.009
D
2.90
3.10
0.114
0.122
0.201
0.122
E
4.70
5.10
0.185
E1
2.90
3.10
0.114
e
0.65 BSC
0.026 BSC
L
0.40
0.80
0.016
0.031
0
0°
8°
0°
8°
Note: 1. Follow JEDEC MO-187 AA.
2. Dimension “D”does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion or gate burrs shall not exceed 6 mil
per side.
3. Dimension “E1”does not include inter-lead flash or protrusions.
Inter-lead flash and protrusions shall not exceed 5 mil per side.
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APA0714
Package Information (Cont.)
MSOP-8P
D
SEE VIEW A
E
c
A
0.25
b
GAUGE PLANE
SEATING PLANE
A1
L
0
A2
e
E1
EXPOSED
PAD
E2
D1
VIEW A
S
Y
M
B
O
L
A
MSOP-8P
INCHES
MILLIMETERS
MIN.
MAX.
MIN.
MAX.
0.000
0.006
1.10
0.043
A1
0.00
0.15
A2
0.75
0.95
0.030
0.037
0.015
0.009
b
0.22
0.38
0.009
c
0.08
0.23
0.003
D
2.90
3.10
0.114
0.122
D1
1.50
2.50
0.059
0.098
E
4.70
5.10
0.185
0.201
E1
2.90
3.10
0.114
0.122
E2
1.50
2.50
0.059
0.098
e
0.65 BSC
0.026 BSC
L
0.40
0.80
0.016
0.031
0
0°
8°
0°
8°
Note: 1. Follow JEDEC MO-187 AA-T
2. Dimension “D”does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion or gate burrs shall not flash or protrusions.
3. Dimension “E1” does not include inter-lead flash or protrusions.
Inter-lead flash and protrusions shall not exceed 6 mil per side.
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APA0714
Package Information (Cont.)
TDFN3x3-8
A
b
E
D
Pin 1
A1
D2
A3
L K
E2
Pin 1 Corner
e
S
Y
M
B
O
L
TDFN3x3-8
MILLIMETERS
INCHES
MIN.
MAX.
MIN.
MAX.
A
0.70
0.80
0.028
0.031
A1
0.00
0.05
0.000
0.002
A3
0.20 REF
0.008 REF
0.35
0.010
0.014
2.90
3.10
0.114
0.122
D2
1.90
2.40
0.075
0.094
E
2.90
3.10
0.114
0.122
E2
1.40
1.75
0.055
0.069
b
D
0.25
e
0.65 BSC
L
0.30
K
0.20
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Rev. A.2 - Apr., 2010
0.026 BSC
0.012
0.50
0.020
0.008
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APA0714
Carrier Tape & Reel Dimensions
P0
P2
P1
A
B0
W
F
E1
OD0
K0
A0
A
OD1 B
B
T
SECTION A-A
SECTION B-B
H
A
d
T1
Application
A
H
330.0±2.00 50 MIN.
MSOP-8
P0
T1
C
d
12.4+2.00 13.0+0.50 1.5 MIN.
-0.00
-0.20
P1
P2
4.00±0.10 8.00±0.10 2.00±0.05
Application
A
H
330.0±2.00 50 M IN.
MSOP-8P
P0
P1
A
H
178.0±2.00 50 MIN.
TDFN3x3-8
D1
1.5 MIN.
T1
C
d
12.4+2.00 13.0+0.50
-0.00
-0.20 1.5 MIN.
P2
D0
1.5+0.10
-0.00
1.5 MIN.
T1
C
12.4+2.00 13.0+0.50
-0.00
-0.20
1.5 MIN.
4.00±0.10 8.00±0.10 2.00±0.05
Application
D0
1.5+0.10
-0.00
P0
P1
P2
4.0±0.10
8.0±0.10
2.0±0.05
D0
1.5+0.10
-0.00
D1
d
D1
1.5 MIN.
D
W
E1
20.2 MIN. 12.0±0.30 1.75±0.10
T
0.6+0.00
-0.40
D
A0
B0
D
W
E1
A0
B0
K0
F
5.5±0.05
K0
5.30±0.20 3.30±0.20 1.40±0.20
W
E1
20.2 MIN. 12.0±0.30 1.75±0.10
T
0.6+0.00
-0.40
5.5±0.05
5.30±0.20 3.30±0.20 1.40±0.20
20.2 MIN. 12.0±0.30 1.75±0.10
T
0.6+0.00
-0.40
F
A0
B0
F
5.5±0.05
K0
3.30±0.20 3.30±0.20 1.30±0.20
(mm)
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APA0714
Devices Per Unit
Package Type
MOSP-8
Unit
Tape & Reel
Quantity
3000
MOSP-8P
Tape & Reel
3000
TDFN3x3-8
Tape & Reel
3000
Taping Dircetion Information
MSOP-8(P)
USER DIRECTION OF FEED
TDFN3x3-8
USER DIRECTION OF FEED
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APA0714
Classification Profile
Classification Reflow Profiles
Profile Feature
Sn-Pb Eutectic Assembly
Pb-Free Assembly
100 °C
150 °C
60-120 seconds
150 °C
200 °C
60-120 seconds
3 °C/second max.
3°C/second max.
183 °C
60-150 seconds
217 °C
60-150 seconds
See Classification Temp in table 1
See Classification Temp in table 2
Time (tP)** within 5°C of the specified
classification temperature (Tc)
20** seconds
30** seconds
Average ramp-down rate (Tp to Tsmax)
6 °C/second max.
6 °C/second max.
6 minutes max.
8 minutes max.
Preheat & Soak
Temperature min (Tsmin)
Temperature max (Tsmax)
Time (Tsmin to Tsmax) (ts)
Average ramp-up rate
(Tsmax to TP)
Liquidous temperature (TL)
Time at liquidous (tL)
Peak package body Temperature
(Tp)*
Time 25°C to peak temperature
* Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum.
** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum.
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APA0714
Classification Reflow Profiles (Cont.)
Table 1. SnPb Eutectic Process – Classification Temperatures (Tc)
3
Package
Thickness
<2.5 mm
Volume mm
<350
235 °C
Volume mm
≥350
220 °C
≥2.5 mm
220 °C
220 °C
3
Table 2. Pb-free Process – Classification Temperatures (Tc)
Package
Thickness
<1.6 mm
1.6 mm – 2.5 mm
≥2.5 mm
Volume mm
<350
260 °C
260 °C
250 °C
3
Volume mm
350-2000
260 °C
250 °C
245 °C
3
Volume mm
>2000
260 °C
245 °C
245 °C
3
Reliability Test Program
Test item
SOLDERABILITY
HOLT
PCT
TCT
HBM
MM
Latch-Up
Method
JESD-22, B102
JESD-22, A108
JESD-22, A102
JESD-22, A104
MIL-STD-883-3015.7
JESD-22, A115
JESD 78
Description
5 Sec, 245°C
1000 Hrs, Bias @ Tj=125°C
168 Hrs, 100%RH, 2atm, 121°C
500 Cycles, -65°C~150°C
VHBM≧2KV
VMM≧200V
10ms, 1tr≧100mA
Customer Service
Anpec Electronics Corp.
Head Office :
No.6, Dusing 1st Road, SBIP,
Hsin-Chu, Taiwan
Tel : 886-3-5642000
Fax : 886-3-5642050
Taipei Branch :
2F, No. 11, Lane 218, Sec 2 Jhongsing Rd.,
Sindian City, Taipei County 23146, Taiwan
Tel : 886-2-2910-3838
Fax : 886-2-2917-3838
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