TI CDCS502PW Crystal oscillator / clock generator with optional ssc Datasheet

CDCS502
www.ti.com........................................................................................................................................................................................... SCAS868 – DECEMBER 2008
Crystal Oscillator / Clock Generator with optional SSC
FEATURES
APPLICATIONS
•
•
1
•
•
•
•
•
•
Part of a Family of Easy to use Clock
Generator Devices With Optional SSC
Crystal Oscillator With Integrated Crystal
Capacitors, Selectable Output Frequency and
Selectable SSC
SSC Controllable via 2 External Pins
– ±0%, ±0.5%, ±1%, ±2% Center Spread
Frequency Multiplication Selectable Between
x1 or x4 With one External Control Pin
Single 3.3V Device Power Supply
Wide Temperature Range –40°C to 85°C
Low space Consumption by 8 pin TSSOP
Package
Consumer and Industrial Applications
requiring Crystal Oscillator with the possibility
of EMI reduction through Spread Spectrum
Clocking
PACKAGE
XIN
SSC_SEL 0
SSC_SEL 1
GND
1
2
3
4
CDCS502
8
7
6
5
XOUT
VDD
OUT
FS
BLOCK DIAGRAM
V DD
GND
XIN
XO
x1 or x4
/SSC
LV
CMOS
OUT
Xout
SSC_SEL 0
SSC_SEL 1
FS
Control
Logic
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2008, Texas Instruments Incorporated
CDCS502
SCAS868 – DECEMBER 2008........................................................................................................................................................................................... www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
DESCRIPTION
The CDCS502 is a spread spectrum capable, fundamental mode crystal oscillator with selectable frequency
multiplication.
It features an advanced gain controlled fundamental mode crystal oscillator stage with a built-in load capacitance
of 10pF. This oscillator stage accepts crystals from 8MHz to 32MHz with an ESR of up to 180Ω. The stage can
be used with crystals with power dissipation of 50µW and up.
The input signal is processed by a PLL, whose output frequency is either equal to the input frequency or
multiplied by the factor of 4.
The PLL is also able to spread the clock signal by ±0%, ±0.5%, ±1% or ±2% centered around the output clock
frequency with an triangular modulation.
By this, the device can generate output frequencies between 8MHz and 108MHz with or without SSC from a
fundamental mode crystal.
In x1 Mode with an SSC amount of 0%, the device works as a standard crystal oscillator and does not make use
of the built in PLL.
The CDCS502 operates in 3.3V environment.
It is characterized for operation from –40°C to 85°C. It is offered in an 8 Pin TSSOP package.
FUNCTION TABLE
FS
SSC_SEL 0
SSC_SEL 1
SSC Amount
fOUT/fIN
fOUT at fin = 27 MHz
0
0
0
±0.00%
1
27 MHz (1)
0
0
1
±0.50%
1
27 MHz
0
1
0
±1.00%
1
27 MHz
0
1
1
±2.00%
1
27 MHz
1
0
0
±0.00%
4
108 MHz
1
0
1
±0.50%
4
108 MHz
1
1
0
±1.00%
4
108 MHz
1
1
1
±2.00%
4
108 MHz
(1)
In this mode the signal from the crystal bypasses the internal PLL for maximum performance.
PACKAGE
XIN
SSC_SEL 0
SSC_SEL 1
GND
1
2
3
4
CDCS502
8
7
6
5
XOUT
VDD
OUT
FS
PIN FUNCTIONS
SIGNAL
PIN
TYPE
DESCRIPTION
XIN
1
I
Crystal Input
XOUT
8
O
Crystal Output
OUT
6
O
LVCMOS Clock Output
SSC_SEL 0, 1
2, 3
I
Spread Selection Pins, internal pull-up
FS
5
I
Frequency Multiplication Selection, internal pull-up
VDD
7
Power
3.3V Power Supply
GND
4
Ground
Ground
2
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CDCS502
www.ti.com........................................................................................................................................................................................... SCAS868 – DECEMBER 2008
PACKAGE THERMAL RESISTANCE FOR TSSOP (PW) PACKAGE (1)
THERMAL AIR FLOW (CFM)
CDCV304PW 8-PIN TSSOP
0
150
250
500
UNIT
RθJA
High K
149
142
138
132
°C/W
RθJA
Low K
230
185
170
150
°C/W
RθJC
High K
65
°C/W
RθJC
High K
69
°C/W
(1)
The package thermal impedance is calculated in accordance with JESD 51 and JEDEC2S2P (high-k board).
ABSOLUTE MAXIMUM RATINGS (1)
over operating free-air temperature range (unless otherwise noted)
VALUE
UNIT
VDD
Supply voltage range
–0.5 to 4.6
V
VIN
Input voltage range
–0.5 to 4.6
V
Vout
Output voltage range
–0.5 to 4.6
V
IIN
Input current (VI < 0, VI > VDD)
±20
mA
Iout
Continuous output current
±50
mA
TST
Storage temperature range
–65 to 150
°C
TJ
Maximum junction temperature
125
°C
(1)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
MIN
VDD
Supply voltage
fIN
Input Frequency
VIL
Low level input voltage LVCMOS
VIH
High level input voltage LVCMOS
VI
Input Voltage threshold LVCMOS
CL
Output Test Load LVCMOS
IOH/IOL
Output Current
TA
Operating free-air temperature
NOM
MAX
UNIT
3.0
3.6
V
8
32
MHz
0.3 VDD
0.7 VDD
V
V
0.5 VDD
V
–40
10
pF
12
mA
85
°C
RECOMMENDED CRYSTAL SPECIFICATIONS (1)
PARAMETER
CONDITIONS
fX-tal
Crystal input frequency range
ESR
Effective series resistance (2)
CL
On-chip load capacitance at Xin and Xout
TX-tal
Crystal power dissipation
(1)
(2)
MIN
NOM
MAX
FS = 0
8
32
FS = 1
8
27
180
10
50
UNIT
MHz
Ω
pF
µW
For further details on the crystal, see the crystal part in the Applications section
With 5 pF crystal package parallel capacitance
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3
CDCS502
SCAS868 – DECEMBER 2008........................................................................................................................................................................................... www.ti.com
DEVICE CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
PARAMET
ER
CONDITIONS
MIN
fout = 20 MHz; FS = 0, no SSC
IDD
Device supply current
18
fout = 70 MHz; FS = 1, SSC = 2%
22
32
MHz
FS = 1
32
108
MHz
10
µA
–10
µA
LVCMOS input current
VI = VDD; VDD = 3.6 V
IIL
LVCMOS input current
VI = 0 V; VDD = 3.6 V
VOL
mA
8
IIH
LVCMOS low-level output
voltage
UNIT
FS = 0
Output frequency
LVCMOS high-level output
voltage
MAX
8
fout = 20 MHz; FS = 0, SSC = 2%
fOUT
VOH
TYP
IOH = –0.1 mA
2.9
IOH = - 8 mA
2.4
IOH = –12 mA
2.2
V
IOL = 0.1 mA
0.1
IOL = 8 mA
0.5
IOL = 12 mA
0.8
tjit(CC)
Cycle to cycle jitter
fout = 108 MHz; FS = 1, SSC = 1%,
10000 Cycles
tr/tf
Rise and fall time
20%–80%
Odc
Output duty cycle
PLL active
fMOD
Modulation frequency
100
ps
0.75
45%
V
ns
55%
30
kHz
40
IDD - Input Current - mA
30
x4 Mode
20
x1 Mode
10
0
5
10
15
20
25
fi - Input Frequency - MHz
30
35
Figure 1. IDD vs Input Frequency, VCC = 3.3V, SSC = 2%
4
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CDCS502
www.ti.com........................................................................................................................................................................................... SCAS868 – DECEMBER 2008
Figure 2. Phase Noise Plot, x1 Mode, 0% SSC, 27 MHz Crystal
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5
CDCS502
SCAS868 – DECEMBER 2008........................................................................................................................................................................................... www.ti.com
APPLICATION INFORMATION
SELECTION OF A CRYSTAL
The CDCS502 requires a crystal with a frequency between 8 and 32 MHz (27MHz in x4 Mode). The crystal stage
is designed with an internal load capacitance of 10pF for crystals with this shunt load capacitance. If a slightly
bigger capacity then 10pF is needed, small external capacitors can be used to get to this value. This solution
however might influence the power-up behavior of the crystal stage, so using a 10pF load capacitance crystal is
highly recommended.
For further details on capacitive load calculation, see application report (SCAA085).
NOTE:
Even though the CDCS502 is characterized down to –40°C, a standard crystal is
usually not rated for operation at this low temperature.
SSC MODULATION
The exact implementation of the SSC modulation plays a vital role for the EMI reduction. The CDCS502 uses a
triangular modulation scheme implemented in a way that the modulation frequency depends on the VCO
frequency of the internal PLL and the spread amount is independent from the VCO frequency.
The modulation frequency can be calculated by using one of the below formulas chosen by frequency
multiplication mode.
FS =0: fmod = fIN / 708
FS =1: fmod = fIN / 620
PARAMETER MEASUREMENT INFORMATION
VDD
1 kW
CDCS502
LVCMOS
1 kW
10 pF
Figure 3. Test Load
CDCS502
LVCMOS
Typical Driver
Impedance
~ 32 Ω
LVCMOS
ZL = 50 W
Series Termination
~18Ω
Figure 4. Test Load for 50-Ω Board Environment
6
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PACKAGE OPTION ADDENDUM
www.ti.com
2-Jan-2009
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
CDCS502PW
ACTIVE
TSSOP
PW
8
150
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CDCS502PWR
ACTIVE
TSSOP
PW
8
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
31-Dec-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
CDCS502PWR
Package Package Pins
Type Drawing
TSSOP
PW
8
SPQ
Reel
Reel
Diameter Width
(mm) W1 (mm)
2000
330.0
12.4
Pack Materials-Page 1
A0 (mm)
B0 (mm)
K0 (mm)
P1
(mm)
7.0
3.6
1.6
8.0
W
Pin1
(mm) Quadrant
12.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
31-Dec-2008
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
CDCS502PWR
TSSOP
PW
8
2000
346.0
346.0
29.0
Pack Materials-Page 2
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
0,65
14
0,10 M
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
8
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064/F 01/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-153
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