ASAHI KASEI [AKD4710-A] AKD4710-A AK4710 Evaluation Board Rev.1 GENERAL DESCRIPTION AKD4710 is an evaluation board for quickly evaluating the AK4710, Single SCART Driver. Evaluation requires audio/video analog analyzers/generators and a power supply. Ordering guide AKD4710-A --- AK4710 Evaluation Board (Control software and USB cable are packed with this.) FUNCTION • RCA connectors for analog audio output • XLR connectors for analog audio input • RCA connectors for SD video input/output • USB connector for serial control interface VP +12V → +3.3V Regulator +12V → +3.3V Regulator VD1 AGND VSS2 VVD VD2 AINL- VD1 VP AINL+ VVD VD2 AINR+ AINR- AK4710 ENCB ENCC TVOUTL CINCHOUTL TVOUTR CINCHOUTR TVVOUT TVRC TVG TVB ENCG RCAVOUT ENCV TVFB ENCY TVSB ENCRC USB PORT 5.0V PIC4550 Regulator 3.3V Figure 1. AKD4710 Block Diagram ※Circuit diagram and PCB layout are attached at the end of this manual. <KM105902> 2011/06 -1- ASAHI KASEI [AKD4710-A] EVALUATION BOARD MANUAL Operation sequence 1) Set up the power supply lines. Name of Jack VP Color of Jack Yellow Voltage Used for Comment and attention +10.8∼+13.2V VP of AK4710 VD1 Red +3.13∼+3.47 VD1 of AK4710 VD2 Red +3.13∼+3.47V VD2 of AK4710 VVD Red +3.13∼+3.47V VVD of AK4710 D3.3V Red +3.13 ∼ 3.47V Power supply of logic AGND VSS2 Black Black 0V 0V Analog Ground Analog Ground DGND Black 0V Digital Ground Should be always connected Should be connected when jp5 (VD1_SEL) is set to REG side. Should be open when JP5 (VD1_SEL) is set to VD1 side. Should be connected when R 51(VD2_SEL) is set to REG side. Should be open when R51 (VD2_SEL) is set to VD2 side. Should be connected when JP6 (VVD_SEL) is set to REG side. Should be open when JP6(VVD_SEL) is set to VVD side. Should be connected when JP7 (VCC_SEL) is set to REG side. Should be open when JP7 (VCC_SEL) is set to D3.3V side. Should be always connected Should be always connected Should be connected when JP4 (GND_SEL) is set to AGND side. Should be open when JP4 (GND_SEL) is set to DGND side. Default of Jack +12V open open open open 0V open open Table 1. Power supply lines Each supply line should be distributed from the power supply unit. 2) Set-up jumper pins. (See the followings.) 3) Power on. The AK4710 should be reset once bringing SW1 “L” upon power-up. Jumper pins set up [JP1] (GND): AINL- pin input select OPEN: J5 (AINL): 3pin <Default> SHORT: GND (Not to use) [JP2] (GND): AINR- pin input select OPEN: J13 (AINR): 3pin <Default> SHORT: GND (Not to use) [JP3] Not to use [JP4] (GND): Analog ground and Digital ground OPEN: Separated SHORT: Common. (The connector “DGND” can be open.) <Default> [JP5] (VD1): Regulator (+3.3V) or VD1 connector OPEN: VD1 pin is supplied from VD1 connector. SHORT: VD1 pin is supplied to regulator (+3.3V). (The connector “VD1” can be open.) <Default> <KM105902> 2011/06 -2- ASAHI KASEI [AKD4710-A] [JP6] (VVD): Regulator (+3.3V) or VVD connector OPEN: VVD pin are supplied from VVD connector. SHORT: VVD pin are supplied from regulator (+3.3V) (The connector “VVD” can be open.) <Default> [JP7] (D3.3V): Regulator (+3.3V) or D3.3V connector OPEN: Logic voltage is supplied from D3.3V connector. SHORT: Logic voltage is supplied form regulator (+3.3V). (The connector “VCC” can be open.) <Default> The regulator can be supplied 3.3V to all circuits by shorting JP5, JP6 and JP7 and supplying 12V to VP connector. The function of the toggle SW [S1] (PDN): Resets the AK4710. Keep “H” during normal operation. Bord Control The AK4710 can be controlled USB PORT of PC. Connect PORT1 with PC by USB cable packed with the AKD4710-A. The control software packed with this evaluation board Analog Input/Output List Audio Video Input Output Input Output Fast Blanking SlowBlanking Output Output Signal Name J5(AINL+, AINL-), J13(AINR+, AINR-) J4 (TVOUTL), J9 (TVOUTR), J6 (CHINOUTL), J14 (CHINOUTR) J2 (ENCV), J7 (ENCY), J10 (ENCRC), J15 (ENCC),J17 (ENCG), J19(ENCB) J3 (TVVOUT), J8 (TVRC), J11(TVG), J16(TVB), J18 (RCAVOUT) J22 (TVFB), J24 (TVSB) Note Max. 2Vrms Max. 2.15Vrms Max. 1.25Vpp Max. 2.5Vpp Max. VVD Max. VP Table 2. Analog Input/Output List <KM105902> 2011/06 -3- ASAHI KASEI [AKD4710-A] Control Soft Manual ■ Evaluation Board and Control Soft Settings 1. Set an evaluation board properly. 2. Connect Evaluation board to PC with USB cable. USB control is recognized as HID (Human Interface Device) on the PC. When it can not be recognized correctly please reconnect Evaluation board to PC with USB cable. 3. Proceed evaluation by following the process below. [Support OS] Windows 2000 / XP 64bit OS’s are not supported. Windows 95 / 98 / Me / NT are not supported. ■ Operation Screen 1. Start up the control program following the process above. 2. After the evaluation board’s power is supplied, the AK4710 must be reset once bring S1 (AK4710-PDN) “L” to “H”. 3. The operation screen is shown below <KM105902> 2011/06 -4- ASAHI KASEI [AKD4710-A] ■ Operation Overview Function, register map and testing tool can be controlled by this control soft. These controls are selected by upper tabs. Buttons which are frequently used such as register initializing button “Write Default”, are located outside of the switching tab window. Refer to the “■ Dialog Boxes” for details of each dialog box setting. 1. [Port Reset]: For when connecting to PC with USB cable Click this button after the control soft starts up when connecting to PC with USB cable. 2. [Write Default]: Register Initializing When the device is reset by a hardware reset, use this button to initialize the registers. 3. [All Write]: Executing write commands for all registers displayed. 4. [All Read]: Executing read commands for all registers displayed. 5. [Save]: Saving current register settings to a file. 6. [Load]: Executing data write from a saved file. 7. [All Reg Write]: [All Reg Write] dialog box is popped up. 8. [Data R/W]: [Data R/W] dialog box is popped up. 9. [Read]: Reading current register settings and display on to the Register area (on the right of the main window). This is different from [All Read] button, it does not reflect to a register map, only displaying hexadecimal. <KM105902> 2011/06 -5- ASAHI KASEI [AKD4710-A] ■ Tab Functions 1. [REG]: Register Map This tab is for a register writing and reading. Each bit on the register map is a push-button switch. Button Down indicates “H” or “1” and the bit name is in red (when read only it is in deep red). Button Up indicates “L” or “0” and the bit name is in blue (when read only it is in gray) Grayout registers are Read Only registers. They can not be controlled. The registers which is not defined in the datasheet are indicated as “---”. Figure 2. Window of [ REG] <KM105902> 2011/06 -6- ASAHI KASEI [AKD4710-A] 1-1. [Write]: Data Writing Dialog It is for when changing two or more bits on the same address at the same time. Click [Write] button located on the right of the each corresponded address for a pop-up dialog box. When the checkbox is checked, the data will be “H” or “1”. When the checkbox is not checked, the data will be “L” or “0”. Click [OK] to write setting values to the registers, or click [Cancel] to cancel this setting. Figure 3. Window of [ Register Set ] 1-2. [Read]: Data Read Click [Read] button located on the right of the each corresponded address to execute a register read. After register reading, the display will be updated regarding to the register status. Button Down indicates “H” or “1” and the bit name is in red (when read only it is in deep red). Button Up indicates “L” or “0” and the bit name is in blue (when read only it is in gray) Please be aware that button statuses will be changed by a Read command. <KM105902> 2011/06 -7- ASAHI KASEI [AKD4710-A] 2. [Tool]: Testing Tools Evaluation testing tools are available in this tab. Click buttons for each testing tool. Figure 4. Window of [ Tool ] <KM105902> 2011/06 -8- ASAHI KASEI [AKD4710-A] 2-1. [Repeat Test]: Repeat Test Dialog Click [Repeat Test] button in the Test tab to open a repeat test dialog shown below. Repeat writing test can be executed by this dialog. Figure 5. Window of [ Repeat Test ] [Start] Button : Starts the repeat test. A dialog for saving a file of the test result will open when clicking this button. Name the file. Test will start after specifying a saving file. [Close] Button : Closes this dialog and finishes the process. [Address] Box : Data writing address in hexadecimal numbers. [Start Data] Box : Start data in hexadecimal numbers. [End Data] Box : End data in hexadecimal numbers. [Step] Box : Data write step interval. [Repeat Count] Box : Repeat count of the test writing. [Up and Down] Box : Data write flow is changed as below. • Checked: Writes in step interval from the start data to the end data and turn back from the end data to the start data. [Example] Start Data = 00, End Data = 05, Step = 1, [ ]…for 1 count. Data flow: [00→01→02→03→04→05→05→04→03→02→01→00] x Repeat Count Number • Not checked: Writes in step interval from the start data to the end data and finishes writing. [Example] Start Data = 00, End Data = 05, Step = 1, [ ]…for 1 count. Data flow: [00→01→02→03→04→05] x Repeat Count Number [Sampling Frequency] Box: Selects sampling frequency 44.1kHz/48kHz [Count] Box : Indicates the count number during a repeat test. [Lch Level] Box : Indicates the Lch Level during a repeat test. <KM105902> 2011/06 -9- ASAHI KASEI [AKD4710-A] 2-2. [Loop Setting]: Loop Dialog Click [Loop Setting] button in the Tool tab to open loop setting dialog as shown below. Writing test can be executed. Figure 6. Window of [ Loop ] [ OK ] Button [ Cancel ] Button [ Address ] Box [ Start Data ] Box [ End Data ] Box [ Interval ] Box [ Step ] Box [ Mode Select ] Box : Starts the test. : Closes the dialog and finishes the process. : Data writing address in hexadecimal numbers. : Start data in hexadecimal numbers. : End data in hexadecimal numbers. : Data write interval time. : Data write step interval. : Mode select check box. • Checked: Writes in step interval from the start data to the end data and turn back from the end data to the start data. [Example] Start Data = 00, End Data = 05, Step = 1 Data flow: 00→01→02→03→04→05→05→04→03→02→01→00 • Not Checked: Writes in step interval from the start data to the end data and finishes writing. [Example] Start Data = 00, End Data = 05, Step = 1 Data flow: 00→01→02→03→04→05 <KM105902> 2011/06 - 10 - ASAHI KASEI [AKD4710-A] ■ Dialog Boxes 1. [All Req Write]: All Reg Write dialog box Click [All Reg Write] button in the main window to open register setting files. Register setting files saved by [SAVE] button can be applied. Figure 7. Window of [ All Reg Write ] [Open (left)]: Selects a register setting file (*.akr). [Write]: Executes register writing by the setting of selected file. [Write All]: Executes all register writings. Selected files are executed in descending order. [Help]: Opens a help window. [Save]: Saves a register setting file assignment. The file name is “*.mar”. [Open (right)]: Opens a saved register setting file assignment “*. mar”. [Close]: Closes the dialog box and finish the process. ~ Operating Suggestions ~ 1. 2. Those files saved by [Save] button and opened by [Open] button on the right of the dialog “*.mar” should be stored in the same folder. When register settings are changed by [Save] button in the main window, re-read the file to reflect new register settings. <KM105902> 2011/06 - 11 - ASAHI KASEI [AKD4710-A] 2. [Data R/W]: Data R/W Dialog Box Click the [Data R/W] button in the main window for data read/write dialog box. Data write is available to specified address. Figure 8. Window of [ Data R/W ] [Address] Box: Input data address in hexadecimal numbers for data writing. [Data] Box : Input data in hexadecimal numbers. [Mask] Box : Input mask data in hexadecimal numbers. This is “AND” processed input data. [Write]: Writs the data generated from Data and Mask values to the address specified by “Address” box. [Read]: Reads data from the address specified by “Address” box. The result will be shown in the Read Data Box in hexadecimal numbers. [Close]: Closes the dialog box and finishes the process. Data writing can be cancelled by this button instead of executing a write command. *The register map will be updated after executing [Write] or [Read] commands. <KM105902> 2011/06 - 12 - ASAHI KASEI [AKD4710-A] MEASUREMENT RESULTS Audio [Measurement condition] • Measurement unit : Audio Precision SYS-2722 • BW : 20Hz∼20kHz • Power Supply : VP=12V, VD1=3.3V, VD2=3.3V, VVD=3.3V • Interface : Input: Cannon, Output: BNC • Temperature : Room • Volume Gain : 0dB • Measurement signal line path: AINL/AINR → Volume→ TVOUTL/TVOUTR Parameter Input signal Measurement filter 20kLPF Results Lch [dB] 97.0 Results Rch [dB] 95.6 S/(N+D) (At 2Vrms Output) DR S/N 1kHz, 0dBFS 1kHz, -60dBFS “no-input 22kLPF, A-weighted 22kLPF, A-weighted 101.0 101.0 101.0 101.0 Plots Figure 1-1. FFT (1kHz, 0dBFS input) at 2Vrms output Figure 1-2. FFT (1kHz, -60dBFS input) Figure 1-3. FFT (Noise floor) Figure 1-4. THD+N vs. Input Level (fin=1kHz) Figure 1-5. THD+N vs. fin (Input Level=0dBFS) Figure 1-6. Linearity (fin=1kHz) Figure 1-7. Frequency Response (Input Level=0dBFS) Figure 1-8. Crosstalk (Input Level=0dBFS) <KM105902> 2011/06 - 13 - ASAHI KASEI [AKD4710-A] Video [Measurement condition] • Signal Generator : Tektronix TG2000 : Tektronix TG700 (for S/N measurement) • Measurement unit : Tektronix VM700T • Power Supply : VP=12V, VD1=3.3V, VD2=3.3V, VDD1=3.3V, VDD2=3.3V • Interface : Input: BNC, Output: BNC • Temperature : Room • Measurement signal line path: S/N: ENCV → TVVOUT Y/C Crosstalk: ENCV → TVVOUT, ENCRC → TVRC DG, DP: ENCV → TVVOUT Parameter S/N Input Signal 0% Flat Field Y/C Crosstalk (Measured at TVVOUT) DG 100% Red Field (YÆENCV, CÆENCRC) Modulated 5 step DP Modulated 5 step Measurement Filter BW=15kHz to 5MHz Filter=Uni-Weighted BW=15kHz to Full Results 76.1 -59.5 (Note1) Min: -0.31 Max: 0.00 Min: -0.93 Max: 0.11 Unit dB dB % deg. Plots Figure 2-1. Noise spectrum (Input=0% Flat Field, BW=15kHz to 5MHz, Filter=Uni-Weighted) Figure 2-2. Y/C Crosstalk (Measured at TVVOUT, Input= 100% Red, ENCV=Y, ENCRC=C), BW=15kHz to Full) Figure 2-3. DG, DP (Input= Modulated 5 step) (Note1) Y/C Crosstalk: Reference Measurement: Results: 1.7dB (p-p) Composite signalÆENCV, no inputÆENCRC, TVRC is terminated by 75Ohm. Y/C Crosstalk: Measurement: Results: -57.8dB (p-p) YÆENCV, CÆENCRC, TVRC is terminated by 75Ohm. Y/C Crosstalk calculation: -57.8dB (p-p) – 1.7dB (p-p) = -59.5dB (p-p) <KM105902> 2011/06 - 14 - ASAHI KASEI [AKD4710-A] Plots (Audio) AK4710 AINL/AINR Æ TVOUTL/TVOUTR: FFT: fin=1KHz, Input Level=0dB +0 -10 -20 -30 -40 -50 -60 -70 d B r -80 A -100 -90 -110 -120 -130 -140 -150 -160 -170 -180 20 50 100 200 500 1k 2k 5k 10k 20k 10k 20k Hz Figure1-1. FFT (fin=1kHz, Input Level=0dB) AK4710 AINL/AINR Æ TVOUTL/TVOUTR: FFT: fin=1KHz, Input Level=-60dB +0 -10 -20 -30 -40 -50 -60 -70 d B r -80 A -100 -90 -110 -120 -130 -140 -150 -160 -170 -180 20 50 100 200 500 1k 2k 5k Hz Figure-1-2. FFT (fin=1kHz Input Level=-60dB) <KM105902> 2011/06 - 15 - ASAHI KASEI [AKD4710-A] AK4710 AINL/AINR Æ TVOUTL/TVOUTR: FFT: No-Input +0 -10 -20 -30 -40 -50 -60 -70 d B r -80 A -100 -90 -110 -120 -130 -140 -150 -160 -170 -180 20 50 100 200 500 1k 2k 5k 10k 20k Hz Figure1-3. FFT (Noise Floor) AK4710 AINL/AINR Æ TVOUTL/TVOUTR: THD+N Amplitude vs Input Amplitude: fin=1KHz -80 -82 -84 -86 -88 -90 -92 d B r -94 -96 A -98 -100 -102 -104 -106 -108 -110 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 +0 dBr Figure1-4. THD+N vs. Input level (fin=1kHz) <KM105902> 2011/06 - 16 - ASAHI KASEI [AKD4710-A] AK4710 AINL/AINR Æ TVOUTL/TVOUTR: THD+N Amplitude vs Input Frequency: Input Level=0dB -80 -82 -84 -86 -88 -90 -92 d B r -94 -96 A -98 -100 -102 -104 -106 -108 -110 20 50 100 200 500 1k 2k 5k 10k 20k Hz Figure1-5. THD+N vs. Input Frequency (Input level=0dB) AK4710 AINL/AINR Æ TVOUTL/TVOUTR: Linearity: fin=1KHz +0 -10 -20 -30 -40 -50 d B r A -60 -70 -80 -90 -100 -110 -120 -130 -140 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 +0 dBr Figure1-6.Linearity (fin=1kHz) <KM105902> 2011/06 - 17 - ASAHI KASEI [AKD4710-A] AK4710 AINL/AINR Æ TVOUTL/TVOUTR: Frequency Response: Input Level=0dBr +1 +0.8 +0.6 +0.4 +0.2 +0 -0.2 -0.4 -0.6 d B r A -0.8 -1 -1.2 -1.4 -1.6 -1.8 -2 -2.2 -2.4 -2.6 -2.8 -3 20 50 100 200 500 1k 2k 5k 10k 20k Hz Figure1-7. Frequency Response (Input level=0dB) AK4710 AINL/AINR Æ TVOUTL/TVOUTR: Crosstalk: fin=1KHz, Input Level=0dBr / No-input -70 -75 -80 -85 -90 -95 -100 d B -105 -110 -115 -120 -125 -130 -135 -140 20 50 100 200 500 1k 2k 5k 10k 20k Hz Figure1-8. Crosstalk (Input level=0dB) <KM105902> 2011/06 - 18 - ASAHI KASEI [AKD4710-A] Plots(Video) AK4710 ENCV Æ TVVOUT: S/N: Input Signal=0% Flat Field, BW=15kHz to 5MHz, Filter=Uni-Weighted Figure 2-1. Noise spectrum (Input=0% Flat Field, BW=15kHz to 5MHz, Filter=Uni-Weighted) <KM105902> 2011/06 - 19 - ASAHI KASEI [AKD4710-A] AK4710 ENCV Æ TVVOUT / ENCRCÆTVRC: Y/C Crosstalk: Input Signal=100% Red Field, YÆENCV, CÆENCRC, BW=15kHz to Full Figure 2-2 Crosstalk (Measured at TVVOUT, Input= 100% Red Field, YÆENCV, CÆENCRC, BW=15kHz to Full) <KM105902> 2011/06 - 20 - ASAHI KASEI [AKD4710-A] AK4710 ENCV Æ TVVOUT: DG, DP: Input Signal=Modulated 5 step Figure 2-3 DG, DP (Input Signal= Modulated 5 step) <KM105902> 2011/06 - 21 - ASAHI KASEI [AKD4710-A] Revision History Date (YY/MM/DD) 11/01/14 Manual Revision KM105900 11/02/03 KM105901 11/06/21 KM105902 Board Reason Revision First Edition 0 Modification 0 1 Modification Contents Update of measurement results and Plots Update of measurement results and Plots IMPORTANT NOTICE z These products and their specifications are subject to change without notice. When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei Microdevices Corporation (AKM) or authorized distributors as to current status of the products. z Descriptions of external circuits, application circuits, software and other related information contained in this document are provided only to illustrate the operation and application examples of the semiconductor products. You are fully responsible for the incorporation of these external circuits, application circuits, software and other related information in the design of your equipments. AKM assumes no responsibility for any losses incurred by you or third parties arising from the use of these information herein. AKM assumes no liability for infringement of any patent, intellectual property, or other rights in the application or use of such information contained herein. z Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. z AKM products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or other hazard related device or systemNote2), and AKM assumes no responsibility for such use, except for the use approved with the express written consent by Representative Director of AKM. As used here: Note1) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. z It is the responsibility of the buyer or distributor of AKM products, who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification. z The PCB layout diagram above is an example only. Asahi Kasei Microdevices Corporation (AKM) assumes no responsibility for any losses incurred by you or third parties arising from the use of the information herein. You are fully responsible for your PCB layout design. Please double check the mounting capability when designing PCB layout. <KM105902> 2011/06 - 22 - SDA PDN 2 1 VD2 3 SCL 4 HDVDD 5 CN1 VSS2 C3 R1 open R2 open 1 2 28 CN3 9 9 TVG TVFB TVOUTL 21 TVOUTR 20 6 TVRC VD1 19 7 TVG VSS1 18 8 TVB TVSB 17 U2 open 9 AINL- AINRP 25 7 AINR+ AINRN 24 6 AINR- TVOUTL 23 5 TVOUTL TVOUTR 22 4 TVOUTR 3 VD1 AINLP TVVOUT 5 AINL+ 8 25 26 27 CN VEE 28 29 CP VSS2 30 31 VD2 SCL 4 9 26 VD1 21 VP 8 TVRC 22 27 AINLN VSS1 20 16 8 23 AINRN ENCY TVRC AINRP VSS3 ENCV 7 TVFB RCAVOUT 15 7 3 VVD TVFB 2 14 6 TVVOUT 6 24 ENCC AGND AINLN ENCRC 5 VSS3 5 PDN 13 4 RCAVOUT 1 open U1 VEE CN CP 29 30 31 VSS2 SCL 32 33 34 SDA 35 3 HDPB 4 TVVOUT open open 12 RCAVOUT open ENCG R3 ENCB 3 11 HDPB 2 HDPR 10 2 C4 AINLP 32 HDPR open 1 HDY 1 SDA HDY PDN 36 HDVDD CN2 C 3 + C6 open VD2 C5 C1 open open + C2 4 5 6 7 8 D 9 D C7 open C8 + C open 2 B B AGND 18 VP 17 ENCY 16 ENCV 15 ENCC 14 ENCRC 13 ENCG 12 ENCB 1 TVSB open C10 open + C9 11 VVD TVSB 19 10 TVB TVG + C11 open C12 open 9 8 7 6 5 4 3 2 1 R4 open A A CN4 5 4 VP ENCY ENCV ENCC ENCRC ENCG ENCB VVD TVB Title AKD4710-A_MAIN Size A3 - 23 3 Date: 2 Document Number Rev 0 AK4710/AK4711 Friday, January 14, 2011 Sheet 1 1 of 4 4 C14 0.1u R5 75 1 ENCV J3 TVVOUT 1 TVVOUT R8 75 2 3 4 5 Audio Intput J1 AINL+ 2 3 4 5 C13 0.47u Audio Output R6 300 1 C15 (short) AINL+ 1 D AGND 3 C17 0.1u R11 75 ENCY J8 TVRC 1 TVRC R12 75 R10 300 1 2 3 4 5 JP1 AGND C18 (short) AGND R13 300 ENCRC 1 TVG R16 75 AGND 2 3 4 5 AGND C20 0.47u 1 ENCC 1 J16 TVB 1 TVB R19 75 AGND J13 AINR J14 CINCHOUTR 1 2 3 4 5 1 C 3 R18 75 AGND 2 3 4 5 AGND AGND C22 0.47u R20 300 AINR- + 2 3 4 5 C21 0.1u AGND AINR+ 3 AGND R17 300 1 AGND C J15 ENCC + J12 AINR+ 2 3 4 5 2 3 4 5 R14 10k 2 1 AGND J11 TVG 2 R15 75 + 2 3 4 5 C19 0.1u J9 TVOUTR 1 TVOUTR AGND J10 ENCRC 2 3 4 5 AINL- GND AGND J6 CINCHOUTL AGND C16 0.47u + 1 2 3 4 5 1 AGND 3 AGND J4 TVOUTL R9 10k AGND J7 ENCY 2 3 4 5 R7 300 TVOUTL J5 AINL 1 AGND AGND 1 + D 2 3 4 5 Video Output (SD) 2 J2 ENCV 2 2 Video Intput 3 + 5 AGND JP2 GND AGND J17 ENCG 2 3 4 5 C23 0.1u R21 75 1 ENCG J18 RCAVOUT 1 RCAVOUT R22 75 AGND AGND AGND B J19 ENCB 2 3 4 5 AGND 2 3 4 5 Video Output (HD) C24 0.1u B 1 ENCB R23 75 J20 HDY AGND 1 HDY AGND 2 3 4 5 AGND Blanking Output J21 HDPB 1 HDPB R24 75 J22 TVFB 1 TVFB A 2 3 4 5 AGND R25 470 1 TVSB 1 HDPR 2 3 4 5 2 3 4 5 Title AGND AGND 5 A J23 HDPR AGND J24 TVSB 2 3 4 5 AKD4710-A-MAIN Size A3 - 24 4 3 Date: 2 Document Number Rev 0 Audio Video Input / Output Friday, January 14, 2011 Sheet 1 2 of 4 5 4 3 R26 C25 4.7k 10 8 6 4 2 2.2u 2 1 PORT2 A1-10PA-2.54DSA(open) 9 7 SCL 5 SDA 3 SDA(ACK) 1 10pin-CTRL 1 2 3 4 R44 R45 0 0 R30 R31 R32 NC/ICCK/ICPGC NC/ICDT/ICPGD NC/ICRST_N/ICVpp NC/ICPORTS 12 13 33 34 OSC1/CLKI OSC2/CLKO/RA6 30 31 RE0/AN5/CK1SPP RE1/AN6/CK2SPP RE2/AN7/OESPP 25 26 27 VUSB 37 RA0/AN0 RA1/AN1 RA2/AN2/Vref-/CVref RA3/AN3/Vref+ RA4/T0CKI/C1OUT/RCV RA5/AN4/SS_N/HLVDIN/C2OUT 19 20 21 22 23 24 38 39 40 41 2 3 4 5 RD0/SPP0 RD1/SPP1 RD2/SPP2 RD3/SPP3 RD4/SPP4 RD5/SPP5/P1B RD6/SPP6/P1C RD7/SPP7/P1D 42 43 44 1 7 6 28 MCLR_N/Vpp/RE3 RB7/KBI3/PGD RB6/KBI2/PGC RB5/KBI1/PGM RB4/AN11/KBI0/CSSPP RB3/AN9/CPP2/VPO RB2/AN8/INT2/VMO RB1/AN10/INT1/SCK/SCL RB0/AN12/INT0/FLT0/SDI/SDA PIC18F4550 TQFP 44-PIN U3 RC0/T1OSO/T13CKI RC1/T1OSI/CCP2/UOE_N RC2/CCP1/P1A RC4/D-/VM RC5/D+/VP RC6/TX/CK RC7/RX/DT/SDO D3.3V R35 470 R39 470 R38 18 17 16 15 14 11 10 9 8 32 35 36 PORT1 VSS0 1 2 3 4 5 0.1u VDD1 JP3 DGND USB(B type) C29 0.1u C VUSB DD+ GND DGND C28 VSS1 SILK-SCREEN 1:VDD 2:MCLR 3:PGD 4:PGC 5:GND C27 10u VDD0 1u 29 C30 DGND 10k 10k 10k 51(open) 51(open) 51(open) + + C26 10u D D3.3V R27 R28 R29 NC NC Vin Vout Vcont PCL NC GND T1 5V => 3.3V DGND 8 7 6 5 TK73633AME 1 2 3 4 DGND D 0 14 C32 0.1u 7 D3.3V R40 0.1u 100k R34 10k 10k U4 1 3 5 9 11 13 USB-RST C31 R33 1A 2A 3A 4A 5A 6A 1Y 2Y 3Y 4Y 5Y 6Y 2 4 6 8 10 12 R36 51 R37 51 SCL SDA Vcc GND 74HC07 C DGND XTI XTO C33 22p X1 20MHz C34 22p C35 470n R41 R42 R43 51 51 51 DGND DGND SCL SDA SDA(ACK) PIC18F4550 B B A K D3.3V R46 D1 HSU119 10k 1 L 3 PDN PDN 2 ATE1D-2M3 H S1 A DGND U6 C36 0.1u 1 2 3 4 5 6 7 1A 1Y 2A 2Y 3A 3Y GND VCC 6A 6Y 5A 5Y 4A 4Y 14 13 12 11 10 9 8 D3.3V A C37 0.1u 74HC14 Title AKD4710-A-MAIN DGND 5 4 Size A3 - 25 3 Date: 2 Document Number Rev 0 uP-I/F Friday, January 14, 2011 Sheet 1 3 of 4 5 4 3 2 1 VP L1 (short) 1 2 VP D D C38 + 47u AGND VD1 JP4 GND DGND T3 LM1117 1 JP5 VD1 OUT L2 (short) 3 1 2 VD1 2 VD2 2 D3.3V 2 1 DGND IN GND AGND VP C44 10u 1 C45 0.1u C46 0.1u C47 0.1u + C43 47u + 2 + VP AGND TJ563_Y VD2 VD1 C VD1 1 L3 (short) R51 TJ563-R 1 AGND 1 0 VD2 VD2 + C48 47u 1 2 TJ563-R VVD VVD C VSS2 1 TJ563-R D3.3V D3.3V D3.3V L6 (short) 1 1 TEST1 TEST2 TEST3 TEST4 (open) (open) (open) (open) TJ563-R TJ563-BK AGND B DGND + C50 47u 1 2 AGND JP7 D3.3V 1 TEST5 (open) DGND B 1 TJ563-BK DGND TEST6 (open) T4 LM1117 VVD JP6 VVD 1 1 TJ563-BK OUT L4 (short) 3 1 1 C54 C52 0.1u C53 10u + 2 HDVDD + C49 47u 2 10u C51 0.1u VVD 1 + 2 L5 (short) 2 VSS2 IN GND VSS2 AGND AGND A A Title AKD4710-A-MAIN Size A3 - 26 5 4 3 Date: 2 Document Number Rev 0 Power Supplly Friday, January 14, 2011 Sheet 1 4 of 4 - 27 - - 28 - - 29 - - 30 -