AOSMD AOZ8900 Ultra-low capacitance tvs diode array Datasheet

AOZ8900
Ultra-Low Capacitance TVS Diode Array
General Description
Features
The AOZ8900 is a transient voltage suppressor array
designed to protect high speed data lines from Electro
Static Discharge (ESD) and lightning.
●
This device incorporates eight surge rated, low
capacitance steering diodes and a Transient Voltage
Suppressor (TVS) in a single package. During transient
conditions, the steering diodes direct the transient to
either the positive side of the power supply line or to
ground. They may be used to meet the ESD immunity
requirements of IEC 61000-4-2, Level 4 (±15kV air,
±8kV contact discharge).
The AOZ8900 comes in RoHS compliant SOT-23
package. It is rated over a -40°C to +85°C ambient
temperature range.
ESD protection for high-speed data lines:
– Exceeds: IEC 61000-4-2 (ESD) ±15kV (air),
±8kV (contact)
– IEC 61000-4-5 (Lightning) 5A (8/20µs)
– Human Body Model (HBM) ±15kV
●
Small package saves board space
●
Low insertion loss
●
Protects four I/O lines
●
Low clamping voltage
●
Low operating voltage: 5.0V
Applications
●
USB 2.0 Power and Data Line Protection
●
Video Graphics Cards
●
Monitors and Flat Panel Displays
●
Digital Video Interface (DVI)
Typical Application
USB Host
Controller
+5V
Downstream
Ports
VBUS
RT
D+
RT
DVBUS
GND
AOZ8900
+5V
VBUS
RT
D+
RT
DGND
Figure 1. 2 USB High Speed Ports
Rev. 1.7 October 2008
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Page 1 of 9
AOZ8900
Ordering Information
Part Number
Ambient Temperature Range
Package
Environmental
AOZ8900CI
-40°C to +85°C
SOT23-6
RoHS Compliant
All AOS products are offered in packages with Pb-free plating and compliant to RoHS standards.
Please visit www.aosmd.com/web/quality/rohs_compliant.jsp for additional information.
Pin Configuration
CH1
1
6
CH4
VN
2
5
VP
CH2
3
4
CH3
SOT23-6
(Top View)
Absolute Maximum Ratings
Exceeding the Absolute Maximum ratings may damage the device.
Parameter
Rating
VP – VN
6V
Peak Pulse Current (IPP), tP = 8/20µs
5A
Peak Power Dissipation (8 x 20µs@ 25°C)
50W
Storage Temperature (TS)
-65°C to +150°C
ESD Rating per IEC61000-4-2,
contact(1)
±8kV
ESD Rating per IEC61000-4-2,
air(2)
±15kV
Model(2)
±15kV
ESD Rating per Human Body
Junction Temperature (TJ)
-40°C to +125°C
Notes:
1. IEC 61000-4-2 discharge with CDischarge = 150pF, RDischarge = 330Ω.
2. Human Body Discharge per MIL-STD-883, Method 3015 CDischarge = 100pF, RDischarge = 1.5kΩ.
Rev. 1.7 October 2008
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Page 2 of 9
AOZ8900
Electrical Characteristics
TA = 25°C unless otherwise specified
Symbol
VRWM
VBR
Parameter
Reverse Working Voltage
Conditions
Between pin 5 and 2
Min.
(5)
Reverse Breakdown Voltage
IT = 1mA, between pins 5 and 2
IR
Reverse Leakage Current
VRWM = 5V, between pins 5 and 2
VF
Diode Forward Voltage
If = 15mA
VCL
Channel Clamp Voltage
Positive Transients
Negative Transient
IPP = 1A, tp = 100ns, any I/O pin to
Ground(3)(6)(8)
Channel Clamp Voltage
Positive Transients
Negative Transient
IPP = 5A, tp = 100ns, any I/O pin to
Ground(3)(6)(8)
Channel Clamp Voltage
Positive Transients
Negative Transient
IPP = 12A, tp = 100ns, any I/O pin to
Ground(3)(6)(8)
Junction Capacitance
VR = 0V, f = 1Mhz, any I/O pin to Ground(3)(7)
Cj
ΔCj
Channel Input Capacitance
Matching
Typ.
(4)
VR = 0V, f = 1Mhz, between I/O
Units
5.5
V
6.6
0.7
pins(3)(7)
Max.
V
0.85
1.25
1
µA
0.95
V
10.50
-2.00
V
V
12.50
-3.50
V
V
15.50
-5.00
V
V
1.3
pF
0.03
pF
Notes:
3. These specifications are guaranteed by design.
4. The working peak reverse voltage, VRWM, should be equal to or greater than the DC or continuous peak operating voltage level.
5. VBR is measured at the pulse test current IT.
6. Measurements performed with no external capacitor on VP (Pin 5 floating).
7. Measurements performed with VP biased to 3.3 Volts (Pin 5 @ 3.3V).
8. Measurements performed using a 100 nSec Transmission Line Pulse (TLP) system.
Rev. 1.7 October 2008
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AOZ8900
Typical Performance Characteristics
I/O – Gnd Insertion Loss (S21) vs. Frequency
Clamping Voltage vs. Peak Pulse Current
(Vp = 3.3V)
(tperiod = 100ns, tr = 1ns)
16
Insertion Loss (dB)
Clamping Voltage, VCL (V)
17
15
14
13
12
11
10
9
0
2
4
6
8
10
1
0
-1
-2
-3
-4
-5
-6
-7
-8
-9
-10
1
12
10
100
1000
Frequency (MHz)
Peak Pulse Current, IPP (A)
Forward Voltage vs. Forward Current
Analog Crosstalk (I/O–I/O) vs. Frequency
(tperiod = 100nS, tr = 1ns)
7
20
Insertion Loss (dB)
Forward Voltage (V)
6
5
4
3
2
1
0
-20
-40
-60
-80
0
0
2
4
6
8
10
10
12
100
1000
Frequency (MHz)
Forward Current, IPP (A)
I/O – I/O Insertion Loss (S21) vs. Frequency
Insertion Loss (dB)
(Vp = Float)
1
0
-1
-2
-3
-4
-5
-6
-7
-8
-9
-10
1
10
100
1000
Frequency (MHz)
Rev. 1.7 October 2008
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Page 4 of 9
AOZ8900
Application Information
The AOZ8900 TVS is design to protect four data lines
from fast damaging transient over-voltage by clamping it
to a reference. When the transient on a protected data
line exceed the reference voltage the steering diode is
forward bias thus, conducting the harmful ESD transient
away from the sensitive circuitry under protection.
PCB Layout Guidelines
Printed circuit board layout is the key to achieving the
highest level of surge immunity on power and data lines.
The location of the protection devices on the PCB is the
simplest and most important design rule to follow. The
AOZ8900 devices should be located as close as possible
to the noise source. The placement of the AOZ8900
devices should be used on all data and power lines that
enter or exit the PCB at the I/O connector. In most
systems, surge pulses occur on data and power lines
that enter the PCB through the I/O connector. Placing
the AOZ8900 devices as close as possible to the noise
source ensures that a surge voltage will be clamped
before the pulse can be coupled into adjacent PCB
traces. In addition, the PCB should use the shortest
possible traces. A short trace length equates to low
impedance, which ensures that the surge energy will be
dissipated by the AOZ8900 device. Long signal traces
will act as antennas to receive energy from fields that are
produced by the ESD pulse. By keeping line lengths as
short as possible, the efficiency of the line to act as an
antenna for ESD related fields is reduced. Minimize
interconnecting line lengths by placing devices with the
most interconnect as close together as possible. The
protection circuits should shunt the surge voltage to
either the reference or chassis ground. Shunting the
surge voltage directly to the IC’s signal ground can cause
ground bounce. The clamping performance of TVS
diodes on a single ground PCB can be improved by
minimizing the impedance with relatively short and wide
ground traces. The PCB layout and IC package parasitic
inductances can cause significant overshoot to the TVS’s
clamping voltage. The inductance of the PCB can be
Rev. 1.7 October 2008
reduced by using short trace lengths and multiple layers
with separate ground and power planes. One effective
method to minimize loop problems is to incorporate a
ground plane in the PCB design. The AOZ8900 ultra-low
capacitance TVS is designed to protect four high speed
data transmission lines from transient over-voltages by
clamping them to a fixed reference. The low inductance
and construction minimizes voltage overshoot during
high current surges. When the voltage on the protected
line exceeds the reference voltage the internal steering
diodes are forward biased, conducting the transient
current away from the sensitive circuitry.
Good circuit board layout is critical for the suppression
of ESD induced transients. The following guidelines are
recommended:
1. Place the TVS near the IO terminals or connectors to
restrict transient coupling.
2. Fill unused portions of the PCB with ground plane.
3. Minimize the path length between the TVS and the
protected line.
4. Minimize all conductive loops including power and
ground loops.
5. The ESD transient return path to ground should be
kept as short as possible.
6. Never run critical signals near board edges.
7. Use ground planes whenever possible.
8. Avoid running critical signal traces (clocks, resets,
etc.) near PCB edges.
9. Separate chassis ground traces from components
and signal traces by at least 4mm.
10. Keep the chassis ground trace length-to-width ratio
<5:1 to minimize inductance.
11. Protect all external connections with TVS diodes.
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Page 5 of 9
AOZ8900
TPBIASx
1μ
56Ω
56Ω
IEEE 1394
Connector
TPAx+
IEEE 1394
PHY
TPAxTPBx+
TPBxGND
56Ω
5.1kΩ
56Ω
270p
AOZ8900
IEEE1394 Port Connection
Rev. 1.7 October 2008
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Page 6 of 9
AOZ8900
Package Dimensions, SOT23-6L
Gauge Plane
D
e1
Seating Plane
0.25mm
c
L
E E1
θ1
e
b
A2
A
.010mm
A1
Dimensions in millimeters
RECOMMENDED LAND PATTERN
2.40
0.80
0.95
0.63
UNIT: mm
Dimensions in inches
Symbols
A
A1
A2
Min.
0.90
0.00
0.80
Nom.
—
—
1.10
Max.
1.25
0.15
1.20
Symbols
A
A1
A2
Min.
0.035
0.00
0.031
Nom.
—
—
0.043
Max.
0.049
0.006
0.047
b
c
D
E
E1
0.30
0.08
2.70
2.50
1.50
0.40
0.13
2.90
2.80
1.60
0.50
0.20
3.10
3.10
1.70
b
c
D
E
E1
0.012
0.003
0.106
0.098
0.059
0.016
0.005
0.114
0.110
0.063
0.020
0.008
0.122
0.122
0.067
e
e1
L
θ1
0.95 BSC
1.90 BSC
0.30
—
0.60
0°
—
8°
e
e1
L
θ1
0.037 BSC
0.075 BSC
0.012
—
0.024
0°
—
8°
Notes:
1. Package body sizes exclude mold flash and gate burrs. Mold flash at the non-lead sides should be less than 5 mils each.
2. Dimension “L” is measured in gauge plane.
3. Tolerance ±0.100mm (4 mil) unless otherwise specified.
4. Followed from JEDEC MO-178C & MO-193C.
6. Controlling dimension is millimeter. Converted inch dimensions are not necessarily exact.
Rev. 1.7 October 2008
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Page 7 of 9
AOZ8900
Tape and Reel Dimensions, SOT23-6L
Tape
P1
D1
T
P2
E1
E2
E
B0
K0
A0
D0
P0
Feeding Direction
Unit: mm
Package
SOT-23
(8mm)
A0
3.15
±0.10
B0
3.20
±0.10
K0
D0
D1
E
E1
E2
P0
P1
P2
T
1.40
±0.10
1.00
Min.
1.50
±0.10
8.00
±0.30
1.75
±0.10
3.50
±0.05
4.00
±0.10
4.00
±0.10
2.00
±0.05
0.25
±0.05
Reel
W1
S
G
N
M
K
V
R
H
Unit: mm
W
Tape Size
Reel Size
M
N
W
W1
H
K
S
G
R
V
8mm
ø180
ø180.00
±0.50
ø60.50
9.00
±0.30
11.40
±1.00
ø13.00
10.60
2.00
±0.50
ø9.00
5.00
18.00
+0.50 / -0.20
Leader/Trailer and Orientation
Trailer Tape
(300mm min., 75 Empty Pockets)
Rev. 1.7 October 2008
Components Tape
Orientation in Pocket
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Leader Tape
(500mm min., 125 Empty Pockets)
Page 8 of 9
AOZ8900
Part Marking
AOZ8900CI
ADOW
Part Number Code
Underscore Denotes Green Product
LT
(SOT-23)
Assembly Lot Code
Week & Year Code
Otption & Assembly Location Code
This datasheet contains preliminary data; supplementary data may be published at a later date.
Alpha & Omega Semiconductor reserves the right to make changes at any time without notice.
LIFE SUPPORT POLICY
ALPHA & OMEGA SEMICONDUCTOR PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL
COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS.
As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant into
the body or (b) support or sustain life, and (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
reasonably expected to result in a significant injury of
the user.
Rev. 1.7 October 2008
2. A critical component in any component of a life
support, device, or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
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