Renesas ISL8216MIRZ Complete high voltage 80v, 4a dc/dc power module Datasheet

DATASHEET
ISL8216M
FN8607
Rev 2.00
May 9, 2014
Complete High Voltage 80V, 4A DC/DC Power Module
The ISL8216M is a simple and easy to use, high voltage DC/DC
module and is ideal for a wide variety of applications. It
eliminates design and manufacturing risks while dramatically
improving time to market.
The simplicity is in the "Off-The-Shelf" unassisted
implementation. All you need is the ISL8216M, input and
output capacitors, and one resistor to program the output
voltage and you have a complete high voltage power design
ready for the market.
Features
• Complete switch mode power supply in one package
• Wide input voltage range: 10V to 80V
• Output current 4A
• Programmable soft-start
• Compliant with EN 55022 Class B (see AN1907)
The ISL8216M is packaged in a thermally enhanced, compact
(15mm×15mm×3.6mm) over-molded High-Density Array
(HDA) Package, which permits full load operation without heat
sink or fans. The package is suitable for automated assembly
by standard surface mount equipment. The small amount of
external components reduce the PCB to a component layer
and a simple ground layer.
Related Literature
• AN1907 “ISL8216MEVAL1Z Evaluation Board User’s Guide”
• SYNC and adjustable frequency 200kHz to 600kHz
• Single resistor sets VOUT +2.5V up to +30V
• Setpoint accuracy ±1.5%
• Programmable overcurrent protection
• RoHS compliant with exemption
• Small footprint, low profile (15mm×15mm×3.6mm)
Applications
• Servers
• 48V telecom and datacom applications
• 12V and 42V automotive and industrial equipment
• Distributed power converters and point-of-load (POL)
regulation
• General purpose step-down DC/DC
16V TO 80V
VIN
VIN
VOUT
12V @ 4A
2.2µF×4
VOUT
22µF×6
PCOMPX
VDD
CSS
ENSS
ISL8216M
0.1µF
FB
PVCC
10µF
SYNC
SGND
PGND
RFB
1.24k
3.6mm
15m
m
m
15m
NOTE: ALL PINS NOT SHOWN ARE FLOATING
FIGURE 1. TYPICAL APPLICATION CIRCUIT
FN8607 Rev 2.00
May 9, 2014
FIGURE 2. SMALL FOOTPRINT PACKAGE WITH LOW PROFILE (3.6mm)
Page 1 of 29
ISL8216M
Table of Contents
Internal Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Recommended Operating Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Typical Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Efficiency Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Typical Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Transient Response Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Start-Up Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Short Circuit Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Programming the Output Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Enable/Soft-Start. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Oscillator and Frequency Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Overcurrent Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Resistor Between BOOT and VIN for Charging The Bootstrap Capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power-Good . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Capacitor Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Capacitor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Thermal Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Thermal Considerations and Current Derating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11
11
11
12
13
14
14
14
15
15
15
Typical Application Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Power Loss Curves. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Derating Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Layout Guide. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Package Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
PCB Layout Pattern Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Thermal Vias. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stencil Pattern Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reflow Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
22
22
22
23
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
About Intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
FN8607 Rev 2.00
May 9, 2014
Page 2 of 29
ISL8216M
Internal Block Diagram
SYNC
PGOOD
VDD
PVCC
PGND
OCSET
RT/CT
OSCILLATOR
INTERNAL
REGULATOR
VIN
SOFT- START
AND FAULT
LOGIC
ENSS
UGATE
SGND
-
+
BOOT
PWM
ZCOMP
COMP
-
+
GATE CONTROL
LOGIC
GM
PHASE
FB
VOUT
INTERNAL
REFERENCE
PCOMX
ZCOMP
D1
5.6µH
D1
CONTROLLER
PGND
VOUT
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
PART
MARKING
ISL8216MIRZ
ISL8216M
ISL8216MEVAL1Z
Evaluation Board
TEMP RANGE
(°C)
-40 to +85
PACKAGE
(RoHS Compliant)
22 Ld HDA
PKG.
DWG. #
Y22.15x15
NOTES:
1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu plate e4 termination finish, which is RoHS compliant by EU exemption 7C-I and compatible with both SnPb and Pb-free soldering operations. Intersil Pbfree products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020
3. For Moisture Sensitivity Level (MSL), please see product information page for ISL8216M. For more information on MSL, please see tech brief TB363
FN8607 Rev 2.00
May 9, 2014
Page 3 of 29
ISL8216M
Pin Configuration
SGND
A
FB
B
FB
C
COMP
D
PGOOD
E
PCOMPX
F
2
3
4
5
6
9
UGATE
8
PVCC
7
PGND
OCSET
1
VDD
RTCT
SYNC
ISL8216M
(22 LD HDA)
TOP VIEW
10 11 12 13 14
RTCT
BOOT
PAD1
SGND
ENSS
PGND
PAD2
VIN
PAD3
VOUT
FN8607 Rev 2.00
May 9, 2014
PAD4
PHASE
PAD5
PGND
Page 4 of 29
ISL8216M
Pin Descriptions
PIN
NUMBER
PIN
NAME
TYPE
A1
SGND
PWR Control signal ground. All voltage levels are measured with respect to this pin.
A3, B3
RTCT
I
Frequency setting pin. This pin sets the frequency of the sawtooth oscillator. The module has a resistor and a capacitor
internally, which set the default frequency to 300kHz. Connect an external resistor to VIN and an external capacitor to SGND
to change the frequency of the sawtooth oscillator. See “Oscillator and Frequency Synchronization” on page 12. Range: 0V to
VIN.
A5
SYNC
I
Signal synchronization. The switching frequency can be synchronized to an external clock through this pin. When the sync
function is not used, this pin must be tied to ground. If the sync function is used, the RTCT natural frequency must be set to a
frequency lower than the sync input frequency. See “Oscillator and Frequency Synchronization” on page 12. Range: 0V to 5V.
A7
VDD
A8
OCSET
A11, F8
PGND
PWR Power ground. These pins provides the power ground to the internal controller IC. Tie these pins to the power ground plane
through the lowest impedance connection. These pins are not internally connected to PAD5.
A12
PVCC
PWR Internal linear regulator output. Typical: 11V.
PIN DESCRIPTION
PWR Power connection for the internal controller. Tie to VIN directly. A decoupling ceramic capacitor between this pin and
signal ground (SGND) is optional.
I
Current limit sensing pin. The current limit can be reduced by placing a resistor, ROCSET_EX, between this pin and VIN. See
“Overcurrent Protection” on page 13. Range: 0V to VIN.
A14
UGATE
-
Test pin. This pin must be floating. Avoid routing any trace close to this pin, as voltage on this pin can be as high as 100V.
B1, C1
FB
I
Feedback pin. Output voltage is set by an external resistor between FB to SGND. Refer to Equation 1 and Table 1 on page 10.
Typical: 1.2V
C11
BOOT
D1
COMP
E1
PGOOD
E14
ENSS
F1
PCOMPX
PAD1
SGND
PAD2
VIN
PWR Power input pin. Apply input voltage between VIN and PGND (PAD5). It is recommended to place an input decoupling capacitor
directly between VIN pin and PGND. The input capacitor should be placed as closely as possible to the module. Range: 10V to 80V.
PAD3
VOUT
PWR Power output pin. Apply output load between VOUT and PGND (PAD5). Place a high frequency output decoupling capacitor
directly between VOUT and PGND (PAD5). The output capacitor should be placed as closely to the module as possible. Range:
1.2V to 30V.
PAD4
PHASE
PWR Phase node. The PHASE pin should be floating. To achieve better thermal performance, the phase planes can also be used
for heat removal with thermal vias connected to large inner layers.
PAD5
PGND
PWR Power Ground. Power ground pins for both input and output returns. Connect to power ground plane immediately below the
module to maximize heat dissipation and to minimize the effect of switching noise and power loss due to the impedance of
the copper traces.
PWR Floating bootstrap supply pin for the MOSFET gate driver. The module has a bootstrap diode and a bootstrap capacitor
internally. This pin can be used to provide an additional current path for charging the internal bootstrap capacitor; the charging
current is derived from VIN through a resistor. See Figure 23, on page 14. Range: 0V to 92V.
I/O Error amplifier output. This pin is connected to the output of the transconductance error amplifier and may be used to
compensate the feedback loop. Range: 0V to 12V.
O
Power good. Provides a power good status. An open drain output is asserted when the voltage at the FB pins is within ±14%
of the reference voltage. See “Power-Good” on page 14. Range: 0V to 12V.
I/O Enable and soft-start pin. This pin provides enable/disable functionality and soft-start timing functionality for the PWM
output. Connect a capacitor to SGND to set the soft-start time. See “Enable/Soft-Start” on page 11. The module is disabled
when this pin is held below 0.5V. To use this pin as an enable control pin, connect to a device with open drain output, or
alternatively to an external enable control circuit, as shown in Figure 18. Range: 0V to 5V.
I
Compensation adjustment pin. Short this pin to VOUT if the output capacitors are all ceramic capacitors. Connect a lower
than 1kΩ resistor to VOUT if the output capacitors are tantalum capacitors, polymer capacitors, or aluminum electrolytic
capacitors. Range: 1.2V to 30V.
PWR Signal ground of the internal controller. All voltage levels are measured with respect to this pad. This pad is electrically
isolated. Connect this pad to the signal ground plane using multiple vias for a robust thermal conduction path.
FN8607 Rev 2.00
May 9, 2014
Page 5 of 29
ISL8216M
Absolute Maximum Ratings
Thermal Information
Input Voltage (VIN,VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100V
BOOT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105V
ENSS pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6V
FB, COMP, SYNC pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8V
PHASE (Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100V
ESD Rating
Human Body Model (Tested per JESD22-A114E) . . . . . . . . . . . . . . . . 2kV
Machine Model (Tested per JESD22-A115-A) . . . . . . . . . . . . . . . . . 200V
Charge Device Model (Tested per JESD22-C101C). . . . . . . . . . . . . . 750V
Latch Up (Tested per JESD-78B; Class 2, Level A) . . . . . . . . . . . . . . 100mA
Thermal Resistance (Typical)
JA (°C/W)
JC (°C/W)
13
2.6
22 Ld HDA (Notes 5, 6) . . . . . . . . . . . . . . . .
Storage Temperature Range, (TSTG) . . . . . . . . . . . . . . . . -55°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
Recommended Operating Ratings
Input Supply Voltage (VIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . +10V to +80V
VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +10V or +80V
Output Voltage (VOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +2.5V to +30V
Ambient Temperature Range (TA) . . . . . . . . . . . . . . . . . . . -40°C to +85°C
Junction Temperature Range, (TJ) . . . . . . . . . . . . . . . . . . .-40°C to +125°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact
product reliability and result in failures not covered by warranty.
NOTES:
4. VAC (Anode to Cathode) specification for internal power diode.
5. JA is tested in free air with device mounted on a four-layer FR-4 test board (76.2x76.2x1.6mm) with 80% coverage, 2oz Cu on top and bottom layers,
plus two, buried, 1oz Cu layers with coverage across the entire test board area. Multiple vias were used, with via diameter = 0.3mm on 1.2mm pitch.
6. For JC, the “case” temperature is measured at the center of the package underside.
Electrical Specifications
TA = +25°C. VIN = 24V, VOUT = 12V, fSW = 300kHz, CIN = 1x100µF ALUM and 2x2.2µF Ceramic,
COUT = 6x22µF Ceremic, unless otherwise noted.
PARAMETER
SYMBOL
CONDITIONS
MIN
(Note 7)
TYP
MAX
(Note 7)
UNITS
VDD SUPPLY
Bias Voltage Range
Bias Supply Current
VDD Shutdown Current
IVIN
IVIN_SD
10
-
80
V
VIN = VDD = 24V, VOUT = 12V, IOUT = 0A
-
14
-
mA
VIN = VDD = 24V, ENSS = 0V
-
20
-
µA
INTERNAL LINEAR REGULATOR (PVCC) (Note 9)
-
10
-
V
Maximum Output Current
20
-
-
mA
Short Current Protection
-
60
-
mA
Rising VDD Threshold
6.8
7.8
8.5
V
Falling VDD Threshold
-
220
-
mV
-
+10
-
%
Output Voltage
PVCC
VDD = 15V to 80V, Load = 3mA to 20mA
POWER-ON RESET (Note 9)
OSCILLATOR (Note 9)
Total Variation on Set
Frequency
fSW = 300kHz
Frequency Range
Set by RT and CT. RT range = 20k to 100k,
CT range = 470pF to 1200pF
200
-
600
kHz
SYNC Frequency Range
above RT and CT natural frequency
200
-
600
kHz
-
0.11*VIN
-
VP-P
-
190
300
ns
0
-
4
A
Ramp Amplitude
ΔVOSC
VDD varied from 9.0V to 75V
Min OFF Time
OUTPUT CHARACTERISTICS
Output Continuous Current
Range
IOUT(DC)
Line Regulation Accuracy
ΔVOUT/ΔVIN
Load Regulation Accuracy
FN8607 Rev 2.00
May 9, 2014
VOUT = 12V, IOUT = 0A, VIN = 15V - 75V
-
0.005
-
%
VOUT = 12V, IOUT = 4A, VIN = 15V - 75V
-
0.005
-
%
-
-
0.15
%
ΔVOUT/ΔIOUT VIN = 80V, CIN = 2x100µF ALUM,
3x4.7µF ceramic capacitor, VOUT = 12V,
COUT = 2x100µF ALUM, 2x10µF ceramic
capacitor, IOUT = 0A to 4A, fSW = 300kHz".
Page 6 of 29
ISL8216M
Electrical Specifications
TA = +25°C. VIN = 24V, VOUT = 12V, fSW = 300kHz, CIN = 1x100µF ALUM and 2x2.2µF Ceramic,
COUT = 6x22µF Ceremic, unless otherwise noted. (Continued)
PARAMETER
Output Ripple Voltage
CONDITIONS
MIN
(Note 7)
TYP
IOUT = 4A, VOUT = 12V, VIN = 24V, fSW = 400kHz
-
IOUT = 0A, VOUT = 12V, VIN = 24V, fSW = 400kHz
-
IOUT = 4A, VOUT = 12V, VIN = 80V, fSW = 400kHz
IOUT = 0A, VOUT = 12V, VIN = 80V, fSW = 400kHz
SYMBOL
ΔVOUT
MAX
(Note 7)
UNITS
40
-
mVP-P
10
-
mVP-P
-
60
-
mVP-P
-
20
-
mVP-P
DYNAMIC CHARACTERISTICS
Voltage Change For Positive
Load Step
ΔVOUT-DP
IOUT = 1A to 4A. Current slew rate = 2.5A/µs,
VIN = 24V, VOUT = 12V
-
220
-
mVP-P
Voltage Change For Negative
Load Step
ΔVOUT-DN
IOUT = 4A to 1A. Current slew rate = 2.5A/µs,
VIN = 24V, VOUT = 12V
-
180
-
mVP-P
REFERENCE VOLTAGE (Note 9)
Feedback Voltage
VFB
Accuracy
-
1.192
-
V
-1.0
-
+1.0
%
-
2
-
µA
ENABLE/SS (Note 9)
Soft-Start Current
ISS
Enable Threshold
VEN
Maximum Disable Voltage
VENSS = 0V
VENSS = 1.3V
22
33
43
µA
Voltage level where soft-start current changes
from low-to-high
0.5
0.77
1.0
V
-
-
0.5
V
4.2
5.7
7.2
mS
GBW
-
15
-
MHz
SR
-
6
-
V/µs
ICOMP
-
±300
-
µA
%
VDISEN
ERROR AMPLIFIER (Note 9)
Transconductance
Gain-Bandwidth Product
(Note 10)
Slew Rate (Note 10)
COMP Pin Drive (Note 10)
POWER GOOD (OPEN DRAIN) (Note 9)
Power-Good Lower Threshold
Power-Good Higher Threshold
PGOOD Leakage Current
VPG-
Percentage of Nominal VFB; ~ 3µs noise filter
84
-
88
VPG+
Percentage of Nominal VFB; ~ 3µs noise filter
IPGLKG
PGOOD Voltage Low
112
-
116
%
VPULLUP = 5.5V
-
-
1
µA
IPGOOD = 4mA
-
-
0.5
V
OVERCURRENT PROTECTION (Note 9)
Dynamic Current Limit
OFF-time
tOCOFF
-
4
-
SS cycle
OCP (OCSET) Current Source
IOCSET
89
104
119
µA
NOTES:
7. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
8. Parameters with TYP limits are not production tested unless otherwise specified.
9. Parameters with MIN and/or MAX limits are 100% tested for internal IC prior to module assembly, unless otherwise specified. Temperature limits
established by characterization and are not production tested.
10. Limits should be considered typical and are not production tested.
FN8607 Rev 2.00
May 9, 2014
Page 7 of 29
ISL8216M
Typical Performance Characteristics
Efficiency Performance
TA = +25°C. The efficiency equation is as follows:
 V OUT xI OUT 
P OUT
Output Power
Efficiency = ----------------------------------------- = ---------------- = -------------------------------------P IN
 V IN xI IN 
Input Power
100
100
95
24VIN TO 5VOUT 300kHz
95
90
85
EFFICIENCY (%)
EFFICIENCY (%)
90
80
75
48VIN TO 5VOUT 300kHz
70
36VIN TO 5VOUT 300kHz
65
60
75
48VIN TO 12VOUT 400kHz
70
64VINTO 12VOUT 350kHz
65
50
60
1
2
3
4
36VIN TO 12VOUT 400kHz
80
55
0
24VIN TO 12VOUT 400kHz
85
80VIN TO 12VOUT 350kHz
0
1
LOAD CURRENT (A)
FIGURE 3. EFFICIENCY vs LOAD CURRENT (5VOUT AT 300kHz)
2
LOAD CURRENT (A)
3
FIGURE 4. EFFICIENCY vs LOAD CURRENT (12VOUT)
100
64VIN TO 24VOUT 400kHz
95
EFFICIENCY (%)
90
48VIN TO 24VOUT 450kHz
85
80
80 VIN TO 24VOUT 350kHz
75
70
65
60
0
1
2
LOAD CURRENT (A)
3
4
FIGURE 5. EFFICIENCY vs LOAD CURRENT (24VOUT)
FN8607 Rev 2.00
May 9, 2014
Page 8 of 29
4
ISL8216M
Typical Performance Characteristics
Transient Response Performance
COUT = 6x22µF ceramic capacitors, IOUT = 1A to 4A, current slew rate = 2.5A/µs. TA = +25°C.
50mV/DIV
VOUT
VOUT
50mV/DIV
VIN = 36V
VOUT = 5V
FSW = 300kHz
VIN = 24V
VOUT = 5V
FSW = 300kHz
1A/DIV
IOUT
IOUT
1A/DIV
100µs/DIV
100µs/DIV
FIGURE 7. 5VOUT TRANSIENT RESPONSE
FIGURE 6. 5VOUT TRANSIENT RESPONSE
50mV/DIV
100mV/DIV
VOUT
VOUT
VIN = 24V
VIN = 48V
VOUT = 12V
FSW = 350kHz
VOUT = 12V
FSW = 400kHz
IOUT
1A/DIV
IOUT
1A/DIV
100µs/DIV
100µs/DIV
FIGURE 8. 12VOUT TRANSIENT RESPONSE
FIGURE 9. 12VOUT TRANSIENT RESPONSE
200mV/DIV
VOUT
200mV/DIV
VOUT
VIN = 80V
VOUT = 24V
FSW = 400kHz
VIN = 64V
VOUT = 24V
FSW = 400kHz
IOUT
1A/DIV
1A/DIV
IOUT
100µs/DIV
100µs/DIV
FIGURE 10. 24VOUT TRANSIENT RESPONSE
FIGURE 11. 24VOUT TRANSIENT RESPONSE
FN8607 Rev 2.00
May 9, 2014
Page 9 of 29
ISL8216M
Start-Up Performance TA = +25°C, VIN = 36V, VOUT = 12V, CIN = 100µF ALUM, 4x2.2µF ceramic capacitors, COUT = 6x22µF ceramic
capacitors, CSS = 0.047µF, IOUT = 0A, 4A
5V/DIV
VOUT
200mA/DIV
IIN
VIN = 36V
VOUT = 12V
IOUT = 0A
5V/DIV
VOUT
500mA/DIV
IIN
VIN = 36V
VOUT =12V
IOUT = 4A
2ms/DIV
2ms/DIV
FIGURE 12. START-UP AT 0A
FIGURE 13. START-UP AT 4A
Short Circuit Performance
capacitors, IOUT = 0A, 4A
TA = +25°C, VIN = 36V, VOUT = 12V, CIN = 100µF ALUM, 4x2.2µF ceramic capacitors, COUT = 6x22µF ceramic
VOUT
5V/DIV
IIN
1A/DIV
VIN = 36V
VOUT = 12V
IOUT = 0A
5V/DIV
VIN = 36V
VOUT = 12V
VOUT
IOUT = 4A
1A/DIV
IIN
50µs/DIV
100µs/DIV
FIGURE 14. SHORT CIRCUIT AT 0A
FIGURE 15. SHORT CIRCUIT AT 4A
FN8607 Rev 2.00
May 9, 2014
Page 10 of 29
ISL8216M
Application Information
the IC starts switching (t2) can be approximated by using
Equation 2:
Programming the Output Voltage
t delay switching = 3.712  10  C SS
5
The ISL8216M has an internal 1.192V ±1% reference voltage.
Programming the output voltage requires a resistor, RFB,
between FB and SGND. Please note that the output voltage
accuracy is also dependent on the resistance accuracy. The
customer should select a high accuracy resistor (i.e. 0.5%) in
order to achieve the overall output accuracy. The output voltage
can be calculated as shown in Equation 1.
11.3k
V OUT =  1 + --------------------  1.192V


R
(EQ. 1)
FB
The value of RFB for selecting different typical output voltages is
shown in Table 1.
(EQ. 2)
The output voltage soft-start time is determined by the rise time
of ENSS voltage from 1.4V to 2.6V (t3 - t2). The output voltage
ramp time can be calculated from:
1.2
t SS = ----------------------  C SS
–6
33 10
(EQ. 3)
The soft-start capacitor CSS is continuously charged up linearly
and clamped at 5V. Note that any leakage current on the ENSS
node will extend the start-up period. Figure 17 shows the typical
soft-start waveforms.
TABLE 1. VALUE OF RFB FOR DIFFERENT OUTPUT VOLTAGES
RFB
(Ω)
TYPICAL VOUT
(V)
3.48k
5
1.24k
12
715
20
590
24
464
30
R
RTCT
T/CT
ENSS
ENSS
V
VOUT
OUT
PHASE
PHASE
FIGURE 17. TYPICAL SOFT-START WAVEFORM
Enable/Soft-Start
VOUT
5V
ENSS
4V
3V
2.6V
2V
1.4V
1V
POR
The module can be enabled by an external signal by using an
open-drain output device, or by adding an external circuit, as
shown in Figure 18. For such circuit, a bias voltage of
approximately 5.1V is recommended, which can be generated
from VIN simply through a resistor in series with a zener diode
that has a nominal working voltage of 5.1V. When the external
control signal is low, ENSS is pulled to ground. When the external
control signal is high, ENSS is released to allow the soft-start
function.
VIN
0.7V
RZ
T0
T1 T2
FIGURE 16. TYPICAL SOFT-START DIAGRAM
Figure 16 illustrates the start-up scheme of the ISL8216M. The
Power-On Reset (POR) function continually monitors the bias
voltage at VDD and VIN. When the voltage at VDD and VIN exceed
their rising POR thresholds (T0), the ISL8216M initially provides
2µA to charge the soft-start capacitor, CSS, connected to the
ENSS pin. If the voltage at this pin is allowed to rise, it will
ramp-up with at a slope determined by the 2µA current and the
value of the soft-start capacitor. When the voltage at ENSS
reaches 0.77V (Typ) at T1, the oscillator circuit is active, causing
the voltage at the RTCT pin to drop from VIN and generate a
sawtooth waveform. At the same time, the soft-start current is
increased to 33µA; as a result, the ENSS voltage then ramps up
at a faster rate. The UGATE starts switching when the ENSS
voltage reaches 1.4V (Typ). The delay from POR (t0) to the time
FN8607 Rev 2.00
May 9, 2014
BIAS VOLTAGE
T3
ENSS
ZENER
DIODE
100k
2N7002
2N7002
ON/OFF
FIGURE 18. EXTERNAL ENABLE CIRCUIT
Page 11 of 29
ISL8216M
The selection of the resistor in series with the zener diode can be
calculated as:
V IN – V Z
R Z = ----------------------IZ
(EQ. 4)
Where:
TABLE 2. SWITCHING FREQUENCY FOR OPTIMUM EFFICIENCY FOR
DIFFERENT INPUT AND OUTPUT VOLTAGES (Continued)
VIN
(V)
VOUT
(V)
SWITCHING
FREQUENCY
(kHz)
RT
CT
48
12
400
143kΩ
open
54.9kΩ
220pF
143kΩ
open
54.9kΩ
220pF
267kΩ
open
73.2kΩ
220pF
95.3kΩ
open
43.2kΩ
220pF
143kΩ
open
54.9kΩ
220pF
267kΩ
open
73.2kΩ
220pF
• VZ is the zener diode’s working voltage, nominal 5.1V.
• IZ is the zener diode’s working reverse current, typically about
5mA.
Power dissipation rating should be taken into consideration when
selecting RZ.
Oscillator and Frequency Synchronization
500
SWITCHING FREQUENCY (kHz)
80
48
The ISL8216M has an internally set fixed frequency of 300kHz.
By adding an external resistor (RT) between VIN and RTCT pin and
a capacitor (CT) between RTCT pin and SGND, the ISL8216M can
provide adjustable frequency from 200kHz to 600kHz. The time
constant of RT/CT determines the oscillator frequency. The
frequency setting curve is shown in Figure 20. Note that any
parasitic capacitance present on the RTCT pin adds to the
equivalent CT value and thus decreases the switching frequency.
450
64
CT OPEN
64
80
12
400
12
350
24
450
24
400
24
350
Note that when the controller is disabled, the voltage at RTCT pin
rises up to the input voltage. Hence, the voltage rating of the CT
capacitor must be sufficient to support the maximum input
voltage.
The SYNC pin provides the function to synchronize the
ISL8216M’s switching frequency to an external source. When
frequency synchronization is used, the time constant of RT/CT
must be set longer than the period of the sync signal. When the
external sync feature is not used, the customer should tie the
SYNC pin to SGND.
400
350
CT = 220pF
300
250
10
1k
100
R5 VALUE (kΩ)
FIGURE 19. RT AND CT vs SWITCHING FREQUENCY
Table 2 provides frequency selection for optimum efficiency at
typical VIN and VOUT conditions and corresponding RT and CT
values.
TABLE 2. SWITCHING FREQUENCY FOR OPTIMUM EFFICIENCY FOR
DIFFERENT INPUT AND OUTPUT VOLTAGES
VIN
(V)
VOUT
(V)
SWITCHING
FREQUENCY
(kHz)
RT
CT
24
5
300
open
open
36
5
300
open
open
48
5
300
open
open
24
12
400
143kΩ
open
54.9kΩ
220pF
143kΩ
open
54.9kΩ
220pF
36
12
FN8607 Rev 2.00
May 9, 2014
400
PHASE
SYNC
RT/CT
FIGURE 20. SYNCHRONIZATION OPERATION
Page 12 of 29
ISL8216M
MINIMUM ON-TIME
The ISL8216M requires the internal MOSFET to be turned on to a
minimum of 200ns (Typ). This minimum gate pulse width is
required to ensure proper samplings of the overcurrent
protection circuit.
For low duty cycle applications, the switching frequency must be
selected to satisfy the condition shown in Equation 5:
V OUT
1
F OSC  ------------------  ---------------------  V IN t on  min 
(EQ. 5)
(EQ. 7)
 V IN - V OUT V OUT
I L =  --------------------------------  ----------------
V IN 
 f SW  L
Where:
• ROCSET_EX is the external resistor between OCSET and VIN
• fSW is the switching frequency
Where  is converter efficiency.
• Internal inductor L = 5.6µH nominal
MINIMUM OFF-TIME
At the termination of the oscillator’s ramp, there is a 190ns time
interval before the next ramp starts. This time interval creates
the minimum-off time of the PWM. This period ensures that the
boot capacitor charge is refreshed. Equation 6 can be used to
calculate the switching frequency to meet the condition:
V OUT 

1
F OSC   1 – ------------------  ---------------------
 V IN t off  min 

I L
I
+ --------  r DS  ON 
R OCSET – EX  2k
 OC
2 
R OCSET = ------------------------------------------------------- = ---------------------------------------------------------I OCSET
R OCSET – EX + 2k
If overcurrent is detected, the output immediately shuts off, it
cycles the soft-start function in a hiccup mode (4 dummy
soft-start time-outs, then up to one real one) to provide fault
protection. If the shorted condition is not removed, this cycle will
continue indefinitely. Figures 21 and 22 illustrate typical
waveforms during overcurrent protection.
(EQ. 6)
Overcurrent Protection
The overcurrent protection function protects the module from
overcurrent conditions by monitoring the current flowing through
the MOSFET. OCP (Overcurrent protection) is implemented via a
resistor (ROCSET) and a capacitor (COCSET) connected between
the OCSET pin and the drain of the MOSFET. An internal 104µA
current source develops a voltage across ROCSET, which is then
compared with the drain-to-source voltage developed across the
MOSFET measured with regard to the PHASE node. When the
drain-to-source voltage across the MOSFET exceeds the voltage
drop across the resistor ROCSET, an OCP event occurs. COCSET is
placed in parallel with ROCSET to smooth the voltage across
ROCSET in the presence of switching noise on the input bus. The
module has an internal resistor of 2kΩ; an external ROCSET_EX
can be added in between OCSET and VIN, and thus in parallel
with the internal 2kΩ, to further reduce the overcurrent limit.
V
VOUT
OUT
ENSS
ENSS
LIL
FIGURE 21. TYPICAL OVERCURRENT PROTECTION
VOUT
VOUT
A 200ns blanking period is used to reduce the current sampling
error due to leading-edge switching noise.
The OCP trip point varies mainly due to MOSFET rDS(ON)
variations and layout noise concerns. To avoid overcurrent
tripping in the normal operating load range, find the ROCSET_EX
resistor from the Equation 7 with:
ENSS
IL
IL
1. The maximum rDS(ON) at the highest junction temperature.
2. The minimum IOCSET, 89µA.
Determine the overcurrent limit greater than the inductor peak
current at the maximum output continuous current.
FIGURE 22. TYPICAL HICCUP RECOVER
FN8607 Rev 2.00
May 9, 2014
Page 13 of 29
ISL8216M
Resistor Between BOOT and VIN for Charging
The Bootstrap Capacitor
PGOOD circuit has a typical 3µs delay. The PGOOD is de-asserted
under disable, overcurrent event, or over-temperature event.
The internal bootstrap diode connected to the PVCC pin provides
charge for the internal bootstrap capacitor. For above 12VOUT
applications, a resistor connecting between BOOT pin and VIN pin
is recommended for certain conditions. Refer to Table 3. This
resistor provides additional bootstrap charge introduced from
VIN, which can ensure the gate drive circuit functions properly at
very light load. See Figure 23 for the recommended external
resistor values at 20VOUT, 24VOUT, 27VOUT, and 30VOUT
conditions. A minimum 0.25W power rating is recommended for
this resistor.
For >12VOUT applications where VIN power-up/down (module
self enable/disable) is required and PGOOD signal is utilized, a
PGOOD delay circuit and a 1kΩ, 1W rating dummy load resistor
are recommended. The PGOOD delay circuit is shown in
Figure 25. Note when the dummy load resistor is used, the
resistor between VIN and BOOT (Figure 23) is no longer required.
During VIN power-up (module self enable) for >12VOUT
applications at very light load current, without such a delay
circuit, VOUT may have a drop after initially reaching the target
due to the lack of bootstrap charge. With such a delay circuit, the
PGOOD signal can be delayed for 250ms. For applications of
≤12VOUT, the PGOOD delay circuit is not required.
RECOMMENDED RESISTOR (kΩ)
20
18
20VOUT
16
PG O O D
14
12
27VOUT
10
1µF
8
PVCC
24VOUT
6
2N7002
150k
4
30VOUT
2
0
20
30
40
50
60
70
80
VIN (V)
FIGURE 25. PGOOD DELAY CIRCUIT
FIGURE 23. RECOMMENDED EXTERNAL RESISTOR VALUE FROM
BOOT TO PVIN
If such a resistor is used while an external control signal is used
to enable the module, an external circuit is required to pull ENSS
and VOUT to ground when the external control signal is low, as
shown in Figure 24. The bias voltage in this circuit can be the
same bias voltage as shown in Figure 18. Without such a circuit,
a residual voltage can be generated on VOUT through the path of
VIN, resistor, bootstrap diode, bootstrap capacitor, inductor and
VOUT.
BIAS VOLTAGE
ENSS
V OUT
100k
2N7002
2N7002
2N7002
ON/OFF
FIGURE 24. EXTERNAL ENABLE CIRCUIT WHILE VIN-BOOT
RESISTOR IS USED
Power-Good
The PGOOD comparator monitors the voltage on the FB pin.
PGOOD is asserted (open drain) when the FB pin voltage is within
14% of the reference voltage. The turn-on response of the
FN8607 Rev 2.00
May 9, 2014
Output Capacitor Selection
An output capacitor is required to filter the output and supply the
load transient current. The output capacitor can be a low ESR
tantalum capacitor, a low ESR polymer capacitor, a low ESR
aluminum electrolytic capacitor, or all ceramic capacitors.
Internally optimized loop compensation provides sufficient
stability margins for applications using different types of
capacitors. A minimum total output capacitance of 120µF with
low ESR is recommended to meet the output voltage ripple and
load transient requirements.
Use only specialized low-ESR capacitors intended for switching
regulator applications for the bulk capacitors. The bulk
capacitor’s ESR will determine the output ripple voltage and the
initial voltage drop after a high slew-rate transient. An
aluminum electrolytic capacitor's ESR value is related to the
case size with lower ESR available in larger case sizes. However,
the equivalent series inductance (ESL) of these capacitors
increases with case size and can reduce the usefulness of the
capacitor to high slew-rate transient loading. In most cases,
multiple electrolytic capacitors of small case size perform
better than a single large case capacitor.
A high frequency ceramic decoupling capacitor can be placed
between module’s VOUT and PGND, as close to the module as
possible, in order to decouple high frequency switching noise.
High frequency ceramic decoupling capacitors should also be
placed as close to the power pins of the load as possible. Be
careful not to add inductance in the circuit board wiring that
could cancel the usefulness of these low inductance
components. Consult with the manufacturer of the load on
specific decoupling requirements.
Page 14 of 29
ISL8216M
Input Capacitor Selection
A combination of bulk capacitors and low Equivalent Series
Resistance (ESR) ceramic capacitors are recommended as input
capacitors. A bulk input capacitor(s) is needed to supply the
current during output load transient conditions. The minimum
required input bulk capacitance can be calculated as shown in
Equation 8.
2
1.21  I IN  L TRACE
C MIN  BULK  = --------------------------------------------------------V DROP
(EQ. 8)
V OUT
I IN = -------------------  I O
  V IN
Where:
• ΔVDROP is the maximum allowable drop on the input voltage
during output peak load transient.
• CMIN(BULK) is the minimum required bulk capacitance (µF).
• ΔIIN is the input transient current reflected from the output
load transient current (A).
• LTRACE is the parasitic inductance of the trace connected to
input supply due to PCB layout. Typically 50nH.
• ΔIO is the output load transient current (A).
• is the efficiency of the converter (%).
Other important parameters for the bulk input capacitor are the
voltage rating and the RMS current rating. The capacitor voltage
rating should be at least 1.25x greater than the maximum input
voltage. A voltage rating of 1.5x greater is a conservative
guideline. The RMS current rating requirement for the total input
capacitance is calculated approximately as shown in Equation 9.
I CIN  RMS  = I O D  1 – D 
VO
D = --------V IN
increasing the ceramic capacitance, the RMS current
requirement for the bulk input capacitors can be reduced. A
typical 4x2.2µF ceramic capacitance is recommended.
For a through-hole design, several electrolytic capacitors in
parallel may be needed. For surface mount designs, solid
tantalum capacitors can be used, but caution must be exercised
with regard to the capacitor surge current rating. These
capacitors must be capable of handling the surge-current at
power-up.
Thermal Protection
If the ISL8216M’s junction temperature reaches a nominal
temperature of +150°C, the controller will be disabled. The
ISL8216M will not be re-enabled until the junction temperature
drops below +110°C.
Thermal Considerations and Current Derating
Experimental power loss curves (Figures 30 through 32), along
with JA from thermal modeling analysis, can be used as a guide
for thermal consideration for the module. The derating curves
(Figures 33 through 42) are derived from the maximum power
allowed while maintaining temperature below the maximum
junction temperature of +115°C. The maximum +115°C
junction temperature is considered for the module to load the
current consistently and it provides 10°C margin of safety from
the rated junction temperature of +125°C. If necessary,
customers can adjust the margin of safety according to the real
applications. In the actual application, other heat sources and
design margins should be considered.
(EQ. 9)
In addition to the bulk capacitance, low ESR ceramic capacitance
is recommended in order to reduce input voltage ripple and
decouple between the VIN and GND of the module. This
capacitance reduces voltage ringing created by the switching
current across parasitic circuit elements. The ceramic capacitors
should be placed as closely as possible to the module pins. The
minimum required input ceramic capacitors can be calculated as
shown in Equation 10.
IO  D  1 – D 
C MIN  CER  = ------------------------------------------f SW  V
(EQ. 10)
IN  P – P 
Where:
• CMIN(CER) is the minimum required ceramic capacitance (µF)
• IO is the output current (A)
• D is the duty cycle, D = VOUT/VIN
• fSW is the switching frequency (kHz)
• VIN(P-P) is the allowable peak-to-peak input voltage ripple (V)
The higher the ceramic capacitance, the less RMS current the
bulk capacitance is subject to, since the bulk capacitance
typically has much higher ESR than the ceramic capacitance. By
FN8607 Rev 2.00
May 9, 2014
Page 15 of 29
ISL8216M
Typical Application Circuits
TABLE 3. EXTERNAL CIRCUITS REQUIREMENT BASED ON APPLICATION CONDITIONS
CONDITIONS
VOUT
Use PGOOD Signal
EXTERNAL CIRCUITS REQUIREMENTS
Enable Method
PGOOD Delay Circuit 1kΩ Dummy Load
Resistor
FIGURES
VIN-BOOT Resistor
-
≤12V
No
Self or External Enable
Control
No
No
No
Figures 26 and 27
≤12V
Yes
Self or External Enable
Control
No
No
No
Figures 26 and 27
>12V
No
Self or External Enable
Control
No
No
Yes
Figure 28
>12V
Yes
External Enable Control
No
No
Yes
Figure 28
>12V
Yes
Self Enable
Yes
Yes
No
Figure 29
24V TO 48V
VIN
VIN
CIN1
CIN2
68µF
4x2.2µF
UGATE
VDD
PVCC
BOOT
PGOOD
RTCT
VOUT
10µF
5V at 4A
ISL8216M
SYNC
EXTERNAL SYNC
EXTERNAL ENABLE CIRCUIT
(OPTIONAL)
OCSET
VOUT
6x22µF
PCOMPX
COMP
5V BIAS VOLTAGE
100k
2N7002
ON/OFF
ENSS
FB
SGND
PGND
3.48k
0.047µF
2N7002
SHORT AT SINGLE LOCATION
NOTE:
• If module is to be enabled by an external signal, an open drain device or an external enable circuit is required. Refer to
“Enable/Soft-Start” on page 11.
FIGURE 26. 24VIN TO 48VIN 5VOUT, 4A, 300kHz
FN8607 Rev 2.00
May 9, 2014
Page 16 of 29
ISL8216M
24V TO 80V
VIN
VIN
CIN1
CIN2
68µF
4×2.2µF
UGATE
VDD
RT
PVCC
BOOT
PGOOD
RTCT
VOUT
10µF
12V at 4A
ISL8216M
SYNC
EXTERNAL ENABLE CIRCUIT
(OPTIONAL)
VOUT
6x22µF
PCOMPX
OCSET
COMP
5V BIAS VOLTAGE
100k
ENSS
FB
SGND
PGND
1.24k
0.047µF
2N7002
2N7002
SHORT AT SINGLE LOCATION
ON/OFF
NOTES:
• If module is to be enabled by an external signal, an open drain device or an external enable circuit is required. Refer to
“Enable/Soft-Start” on page 11.
• Refer to Figure 19 and Table 2 for optimum switching frequency and RT and/or CT values.
FIGURE 27. 24VIN TO 80VIN, 12VOUT, 4A
36V TO 64V
VIN
VIN
CIN1
CIN2
68µF
4×2.2µF
UGATE
VDD
PVCC
RBOOT
RT
BOOT
PGOOD
RTCT
VOUT
10µF
24V at 4A
ISL8216M
SYNC
EXTERNAL ENABLE CIRCUIT
(OPTIONAL)
OCSET
VOUT
6x22µF
PCOMPX
COMP
5V BIAS VOLTAGE
100k
ENSS
FB
SGND
PGND
2N7002
590
0.1µF
2N7002
SHORT AT SINGLE LOCATION
ON/OFF
2N7002
NOTES:
• If module is to be enabled by an external signal, an open drain device or an external enable circuit is required. Refer to
“Enable/Soft-Start” on page 11.
• Refer to Figure 19 and Table 2 for optimum switching frequency and RT and/or CT values.
• Refer to Figure 23 for VIN-BOOT resistor (RBOOT) value.
FIGURE 28. 36VIN TO 64VIN, 24VOUT, 4A, 400kHz
FN8607 Rev 2.00
May 9, 2014
Page 17 of 29
ISL8216M
48V TO 80V
VIN
VIN
CIN1
CIN2
68µF
4×2.2µF
RT
ROCSET_EX
UGATE
PVCC
VDD
BOOT
PGOOD
RTCT
VOUT
ISL8216M
SYNC
PGOOD DELAY CIRCUIT
(OPTIONAL)
OCSET
PGOOD
PVCC
2N7002
1µF
PCOMPX
10µF
24V at 3A
RDUMMY
1k
VOUT
6x22µF
COMP
ENSS
FB
SGND
PGND
0.1µF
590
150k
SHORT AT SINGLE LOCATION
NOTES:
• For this condition (module self-enable, >12VOUT, using PGOOD), a PGOOD delay circuit, a 1kΩ, 1W rating dummy load
resistor, as well as a soft-start capacitor of at least 0.1µF are required. Refer to “Power-Good” on page 14. The VIN-BOOT
resistor (RBOOT) is not required when 1kΩ dummy load resistor is present.
• Refer to “Overcurrent Protection” on page 13 for the external OCSET resistor selection.
• Refer to Figure 19 and Table 2 for optimum switching frequency and RT and/or CT values.
FIGURE 29. 80VIN 24VOUT, 3A, 350kHz, SELF ENABLE, USING PGOOD SIGNAL
FN8607 Rev 2.00
May 9, 2014
Page 18 of 29
ISL8216M
Power Loss Curves
4.5
8
4.0
7
80VIN 12VOUT 350kHz
6
POWER LOSS (W)
POWER LOSS (W)
3.5
3.0
2.5
36VIN 5VOUT 300kHz
2.0
24VIN 5VOUT 300kHz
1.5
48VIN 12VOUT 400kHz
4
3
2
1.0
36VIN 12VOUT 400kHz
1
0.5
0
64VIN 12VOUT 350kHz
5
0
1
2
3
0
4
24VIN 12VOUT 400kHz
0
0.5
1.0
LOAD CURRENT (A)
1.5
2.0
2.5
3.0
3.5
4.0
LOAD CURRENT (A)
FIGURE 30. POWER LOSS vs LOAD CURRENT (5VOUT) FOR VARIOUS
INPUT VOLTAGES
FIGURE 31. POWER LOSS vs LOAD CURRENT (12VOUT) FOR VARIOUS
INPUT VOLTAGE
10
9
POWER LOSS (W)
8
7
6
80VIN 24VOUT 350kHz
5
4
64VIN 24VOUT 400kHz
3
2
48VIN 24VOUT 450kHz
1
0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
LOAD CURRENT (A)
FIGURE 32. POWER LOSS vs LOAD CURRENT (24VOUT) FOR VARIOUS INPUT VOLTAGE
FN8607 Rev 2.00
May 9, 2014
Page 19 of 29
ISL8216M
Derating Curves
4.0
4.0
3.5
3.5
400LFM
200LFM
2.5
2.0
0LFM
1.5
1.0
0.5
0
400LFM
3.0
LOAD CURRENT (A)
LOAD CURRENT (A)
3.0
200LFM
2.5
2.0
0LFM
1.5
1.0
0.5
65
75
85
95
105
0
115
65
75
FIGURE 33. DERATING CURVE 24VIN TO 5VOUT
115
3.5
400LFM
LOAD CURRENT (A)
3.0
LOAD CURRENT (A)
105
4.0
3.5
200LFM
2.5
2.0
0LFM
1.5
1.0
3.0
0LFM
400LFM
2.5
2.0
200LFM
1.5
1.0
0.5
0.5
65
75
85
95
105
0
115
55
FIGURE 35. DERATING CURVE 24VIN TO 12VOUT
115
FIGURE 36. DERATING CURVE 36VIN TO 12VOUT
4.0
4.0
3.5
3.5
400LFM
LOAD CURRENT (A)
3.0
2.5
95
75
AMBIENT TEMPERATURE(°C)
AMBIENT TEMPERATURE(°C)
LOAD CURRENT (A)
95
FIGURE 34. DERATING CURVE 36VIN TO 5VOUT
4.0
0
85
AMBIENT TEMPERATURE(°C)
AMBIENT TEMPERATURE(°C)
0LFM
2.0
200LFM
1.5
1.0
3.0
0LFM
2.5
400LFM
2.0
1.5
200LFM
1.0
0.5
0.5
0
55
75
95
AMBIENT TEMPERATURE(°C)
FIGURE 37. DERATING CURVE 48VIN TO 12VOUT
FN8607 Rev 2.00
May 9, 2014
115
0
35
55
75
95
115
AMBIENT TEMPERATURE(°C)
FIGURE 38. DERATING CURVE 64VIN TO 12VOUT
Page 20 of 29
ISL8216M
4.0
4.0
3.5
3.5
400LFM
3.0
LOAD CURRENT (A)
LOAD CURRENT (A)
Derating Curves (Continued)
2.5
0LFM
2.0
1.5
1.0
200LFM
0LFM
3.0
2.5
2.0
1.5
200LFM
1.0
0.5
0.5
0
400LFM
35
55
75
95
0
115
25
45
105
FIGURE 40. DERATING CURVE 48VIN TO 24VOUT
4.0
4.0
3.5
3.5
400LFM
3.0
400LFM
LOAD CURRENT (A)
LOAD CURRENT (A)
85
AMBIENT TEMPERATURE(°C)
AMBIENT TEMPERATURE(°C)
FIGURE 39. DERATING CURVE 80VIN TO 12VOUT
0LFM
2.5
2.0
1.5
1.0
3.0
2.5
2.0
0LFM
1.5
1.0
200LFM
200LFM
0.5
0
65
0.5
25
45
65
85
AMBIENT TEMPERATURE(°C)
FIGURE 41. DERATING CURVE 64VIN TO 24VOUT
FN8607 Rev 2.00
May 9, 2014
105
0
25
45
65
85
105
AMBIENT TEMPERATURE(°C)
FIGURE 42. DERATING CURVE 80VIN TO 24VOUT
Page 21 of 29
ISL8216M
Layout Guide
To achieve stable operation, low losses and good thermal
performance, some layout considerations are necessary.
• VOUT, VIN, PHASE, and GND should have large copper areas for
power path to minimize conduction loss and thermal stress.
Place enough thermal vias to connect the power planes in
different layers under or around the module.
• Establish a separate ground plane for SGND (pin A1 and
PAD 1) and PGND (pin F8, A11, and PAD 5) and connect them
at a single point as shown in Figure 43. This will help block the
high frequency noise from entering the controller via SGND.
• Place at least one high frequency ceramic capacitor between
(1) VIN and PGND, (2) VOUT and PGND, and (3) PVCC and GND,
as closely to the module as possible in order to minimize
high-frequency noise.
• Avoid routing any sensitive signal traces, such as VOUT and FB
near the PHASE pad.
• PHASE pad is a switching node that generates switching noise.
Keep the pad under the module. For noise-sensitive
applications, it is recommended to keep phase pad only on the
top and inner layers of the PCB. Also, do not place phase pads
exposed to the outside on the bottom layer of the PCB.
TO
VIN
SGND SHORT TO PGND
PAD1
SGND
PAD2
VIN
<PAD4>
PHASE
CIN
<PAD5>
GND
COUT
FIGURE 43. RECOMMENDED LAYOUT
Package Description
The structure of ISL8216M belongs to the High Density Array
(HDA) package. This kind of package has advantages, such as
good thermal and electrical conductivity, low weight and small
size. The HDA package is applicable for surface mounting
technology. The ISL8216M contains several types of devices,
including resistors, capacitors, inductors and control ICs. The
ISL8216M is a copper lead-frame based package with exposed
copper thermal pads, which have good electrical and thermal
conductivity. The copper lead frame and multi-component
assembly is over-molded with polymer mold compound to
protect these devices.
FN8607 Rev 2.00
May 9, 2014
PCB Layout Pattern Design
The bottom of the ISL8216M is a lead-frame footprint, which is
attached to the PCB by surface mounting process. The PCB
layout pattern is shown in the Package Outline Drawing on
page 29. The PCB layout pattern is essentially 1:1 with the HDA
exposed pad and I/O termination dimensions. The thermal lands
on the PCB layout should match 1:1 with the package exposed
die pads.
Thermal Vias
A grid of 1.0mm to 1.2mm pitch thermal vias, which drops down
and connects to buried copper plane(s), should be placed under
the thermal land. The vias should be about 0.3mm to 0.33mm in
diameter with the barrel plated to about 1.0 ounce copper.
Although adding more vias (by decreasing via pitch) will improve
the thermal performance, diminishing returns will be seen as
more and more vias are added. Simply use as many vias as
practical for the thermal land size and your board design rules
allow.
Stencil Pattern Design
RFB
<PAD3>
VOUT
The package outline, typical PCB layout pattern design, and
typical stencil pattern design are shown in the “Package Outline
Drawing” on page 25. The module has a small size of
15mmx15mmx3.6mm. Figure 44 shows typical reflow profile
parameters. These guidelines are general design rules. Users can
modify parameters according to their application.
Reflowed solder joints on the perimeter I/O lands should have
about a 50µm to 75µm (2mils to 3mils) standoff height. The
solder paste stencil design is the first step in developing
optimized, reliable solder joints. Stencil aperture size to land size
ratio should typically be 1:1. The aperture width may be reduced
slightly to help prevent solder bridging between adjacent I/O
lands. To reduce solder paste volume on the larger thermal
lands, it is recommended that an array of smaller apertures be
used instead of one large aperture. It is recommended that the
stencil printing area cover 50% to 80% of the PCB layout pattern.
A typical solder stencil pattern is shown in the Package Outline
Drawing on page 28. The gap width between pad to pad is
0.6mm. The user should consider the symmetry of the whole
stencil pattern when designing its pads. A laser cut, stainless
steel stencil with electropolished trapezoidal walls is
recommended. Electropolishing “smooths” the aperture walls
resulting in reduced surface friction and better paste release
which reduces voids. Using a trapezoidal section aperture (TSA)
also promotes paste release and forms a "brick like" paste
deposit that assists in firm component placement. A 0.1mm to
0.15mm stencil thickness is recommended for this large pitch
(1.3mm) HDA.
Page 22 of 29
ISL8216M
Reflow Parameters
Due to the low mount height of the HDA, "No Clean" Type 3 solder
paste per ANSI/J-STD-005 is recommended. Nitrogen purge is
also recommended during reflow. A system board reflow profile
depends on the thermal mass of the entire populated board, so it
is not practical to define a specific soldering profile just for the
HDA. The profile given in Figure 44 is provided as a guideline, to
be customized for varying manufacturing practices and
applications.
300
PEAK TEMPERATURE +230°C~+245°C;
KEEP ABOUT 30s ABOVE +220°C
TEMPERATURE (°C)
250
SLOW RAMP AND
SOAK FROM +100°C TO
+180°C FOR 90s~120s
200
150
100
RAMP RATE ≤1.5°C FROM +70°C TO +90°C
50
0
0
100
150
200
250
300
350
DURATION (s)
FIGURE 44. TYPICAL REFLOW PROFILE
FN8607 Rev 2.00
May 9, 2014
Page 23 of 29
ISL8216M
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you
have the latest revision.
DATE
REVISION
CHANGE
May 9, 2014
FN8607.2
Page 1: Added “Compliant with “EN55022 Class B (see AN1907)” bullet to Features section.
Page 3: Removed redundant line that was on the “Internal Block Diagram”.
March 14, 2014
FN8607.1
Updated the following in the “Electrical Specifications” on page 6, OSCILLATOR section:
Frequency Range, MIN from 100 to 200
SYNC Frequency Range, MIN from 100 to 200
February 10, 2014
FN8607.0
Initial Release
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
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For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
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For information regarding Intersil Corporation and its products, see www.intersil.com
FN8607 Rev 2.00
May 9, 2014
Page 24 of 29
Y22.15x15
ISL8216M
FN8607 Rev 2.00
May 9, 2014
Package Outline Drawing
Y22.15x15
22 I/O 15mmx15mmx3.6mm CUSTOM HDA MODULE
Rev 2, 9/13
PIN 1 INDICATOR
C = 0.35
DATUM A
15.00
A
13.00
B
A
B
C
D
E
F
13.60 ±0.15
fff
CAB
15.00
SEE DETAIL A
14 13 12 11 10 9 8 7 6 5 4 3 2 1
SEE DETAIL B
TERMINAL #A1
INDEX AREA
(7.5x7.5)
5.00
7.30
0.10 C 2X
0.10 C 2X
13.60 ±0.15
fff
CAB
TOP VIEW
DATUM B
0.50
BOTTOM VIEW
1.50
3.7 MAX
0.10 C
0.10
0.10
0.08 C
MAX 0.025
4 17x (0.60±0.05)
SEATING PLANE
SIDE VIEW
C
DETAIL B
C A B
C
3
1.00
NOTES:
1.
All dimensions are in millimeters.
2.
All tolerances ± 0.10mm, unless otherwise noted.
Page 25 of 29
3.
Represents the basic land grid pitch.
4.
The total number of smaller I/O pads is 17. All 17
I/O’s are centered in a fixed row and column matrix
at 1.0mm pitch BSC.
5.
Dimensioning and tolerancing per ASME Y14.5M-1994.
6.
Tolerance for exposed DAP edge location dimension.
1.00
1.00
4 17x (0.60±0.05)
1.00
DETAIL A
TERMINAL TIP
3
Details for the 5 expose Pads
ISL8216M
FN8607 Rev 2.00
May 9, 2014
3.00
4.30
A1
A1
3.30
3.65
4.65
2.30
7.30
3.00
3.60
2.00
2.30
6.15
4.35
3.30
3.15
0.35
4.00
3.00
5.15
3.00
3.70
4.65
6.50
4.30
3.60
0.60
4.30
CENTERLINE POSITION DETAILS FOR THE 5 EXPOSED DAPS
DIMENSIONAL DETAILS FOR THE 5 EXPOSED PADS
BOTTOM VIEW
BOTTOM VIEW
Page 26 of 29
Terminal and Pad Edge Details
6.80
7.50
6.20
4.80
4.20
2.80
1.50
2.20
0.20
0.80
0.20
0.00
1.50
0.80
3.20
3.80
4.80
4.20
6.20
7.50
6.80
ISL8216M
FN8607 Rev 2.00
May 9, 2014
7.50
7.50
6.20
6.20
6.80
6.80
5.50
4.20
2.50
1.50
5.20
4.80
4.20
2.80
3.20
2.20
2.20
5.80
4.80
3.80
2.80
1.80
1.20
0.50
0.00
0.00
0.80
1.80
3.20
4.80
5.50
6.80
6.80
TERMINAL AND PAD EDGE DETAILS
BOTTOM VIEW
7.50
6.80
1.80
2.50
0.00
2.50
1.80
3.50
5.50
6.80
6.20
7.50
7.50
7.50
Page 27 of 29
5.50
4.70
5.22
4.50
4.50
4.22
3.30
3.22
2.50
2.22
2.50
1.50
0.88
1.22
6.22
6.79
7.50
4.22
4.79
3.79
1.30
3.22
0.22
0.79
0.10
0.00
0.10
0.79
2.79
2.22
1.30
4.79
7.50
6.79
6.22
5.79
4.79
4.79
3.79
4.10
2.79
2.79
1.79
2.70
0.45
0.00
0.18
0.00
0.83
4.22
6.79
6.22
3.50
6.22
7.50
6.19
5.15
4.11
4.50
3.50
0.70
0.50
0.00
0.70
0.50
2.50
4.50
6.50
7.50
6.50
7.50
7.50
7.50
6.50
ISL8216M
2.15
3.88
3.98
4.48
4.30
4.15
4.55
5.40
SUGGESTED STENCIL OPENING CENTER POSITION
SUGGESTED STENCIL OPENING EDGE POSITION
TOP VIEW
TOP VIEW
6.55
6.75
7.50
5.20
6.25
5.55
4.15
5.15
4.00
3.68
3.75
2.48
2.75
1.45
2.15
0.15
0.55
1.45
7.50
2.85
7.50
4.85
7.50
6.05
4.60
4.65
3.25
3.08
1.00
1.35
0.65
3.65
5.65
7.50
7.50
6.45
7.50
5.65
6.48
7.50
6.15
4.22
3.90
2.22
1.30
0.25
2.10
3.15
4.98
5.48
5.30
1.83
2.63
3.15
6.79
0.60
0.17
4.45
FN8607 Rev 2.00
May 9, 2014
7.50
0.22
Stencils
3.45
4.50
6.65
Page 28 of 29
PCB Land Pattern
6.80
7.50
6.20
4.80
3.80
3.20
4.20
1.50
0.20
0.80
0.00
0.20
1.50
0.80
2.80
2.20
4.80
4.20
6.20
7.50
6.80
ISL8216M
FN8607 Rev 2.00
May 9, 2014
7.50
7.50
6.80
5.80
4.80
3.80
2.80
1.80
6.80
6.20
6.20
5.50
5.20
4.20
4.20
3.20
2.80
2.20
2.20
4.80
2.50
1.50
1.20
0.50
0.00
0.00
0.80
1.80
3.20
4.80
5.50
6.80
6.80
7.50
PCB LAND PATTERN
7.50
6.20
6.80
5.50
3.50
2.50
1.80
0.00
1.80
2.50
6.80
7.50
7.50
Page 29 of 29