SPANSION AM29F004BT-90JF 4 megabit (512 k x 8-bit) cmos 5.0 volt-only boot sector flash memory Datasheet

Am29F004B
Data Sheet
This product has been retired and is not recommended for designs. Please contact your Spansion
representative for alternates. Availability of this document is retained for reference and historical
purposes only.
The following document contains information on Spansion memory products.
Continuity of Specifications
There is no change to this data sheet as a result of offering the device as a Spansion product. Any
changes that have been made are the result of normal data sheet improvement and are noted in the
document revision summary.
For More Information
Please contact your local sales office for additional information about Spansion memory solutions.
Publication Number Am29F004B_00
Revision E
Amendment 4
Issue Date May 9, 2006
THIS PAGE LEFT INTENTIONALLY BLANK.
DATA SHEET
Am29F004B
4 Megabit (512 K x 8-Bit)
CMOS 5.0 Volt-only Boot Sector Flash Memory
This product has been retired and is not recommended for designs. Please contact your Spansion representative for alternates. Availability of this document is retained for reference
and historical purposes only.
DISTINCTIVE CHARACTERISTICS
„ 5.0 Volt single power supply operation
— Minimizes system-level power requirements
„ High performance
— Access times as fast as 70 ns
„ Manufactured on 0.32 µm process technology
„ Ultra low power consumption (typical values at
5 MHz)
— 20 mA typical active read current
— 30 mA typical program/erase current
— 1 µA typical standby mode current
„ Flexible sector architecture
— One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and
seven 64 Kbyte sectors
— Supports full chip erase
— Sector Protection features:
A hardware method of locking a sector to
prevent any program or erase operations within
that sector
Sectors can be locked in-system or via
programming equipment
Temporary Sector Unprotect feature allows code
changes in previously locked sectors
„ Top or bottom boot block configurations available
„ Minimum 1,000,000 write cycle guarantee per
sector
„ Package option
— 32-pin PLCC
„ Compatible with JEDEC standards
— Pinout and software compatible with singlepower supply Flash
— Superior inadvertent write protection
„ Embedded Algorithms
— Embedded Erase algorithm automatically
preprograms and erases the entire chip or any
combination of designated sectors
— Embedded Program algorithm automatically
writes and verifies data at specified addresses
„ Erase Suspend/Erase Resume
— Suspends an erase operation to read data from,
or program data to, a sector that is not being
erased, then resumes the erase operation
„ Data# Polling and toggle bits
— Provides a software method of detecting
program or erase operation completion
„ 20-year data retention at 125°C
This Data Sheet states AMD’s current technical specifications regarding the Products described herein. This Data
Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
Publication# Am29F004B_00 Revision: E
Amendment: 4 Issue Date: May 9, 2006
D A T A
S H E E T
GENERAL DESCRIPTION
The Am29F004B is a 4 Mbit, 5.0 volt-only Flash memory
device organized as 524,288 bytes. The data appears on
DQ0–DQ7. The device is offered in a 32-pin PLCC package.
This device is designed to be programmed in-system with the
standard system 5.0 volt VCC supply. A 12.0 volt VPP is not
required for program or erase operations. The device can also
be programmed in standard EPROM programmers.
The device offers access times of up to 70 ns, allowing high
speed microprocessors to operate without wait states. To
eliminate bus contention each device has separate chip
enable (CE#), write enable (WE#) and output enable (OE#)
controls.
Each device requires only a single 5.0 volt power supply for
both read and write functions. Internally generated and regulated voltages are provided for the program and erase
operations.
The Am29F004B is entirely command set compatible with the
JEDEC single-power-supply Flash standard. Commands
are written to the command register using standard microprocessor write timing. Register contents serve as inputs to an
internal state-machine that controls the erase and programming circuitry. Write cycles also internally latch addresses
and data needed for the programming and erase operations.
Reading data out of the device is similar to reading from other
Flash or EPROM devices.
Device programming occurs by executing the program
command sequence. This initiates the Embedded Program
algorithm-an internal algorithm that automatically times the
program pulse widths and verifies proper cell margin.
Device erasure occurs by executing the erase command
sequence. This initiates the Embedded Erase algorithm–an
internal algorithm that automatically preprograms the array (if it
2
is not already programmed) before executing the erase operation. During erase, the device automatically times the erase
pulse widths and verifies proper cell margin.
The host system can detect whether a program or erase
operation is complete by reading the DQ7 (Data# Polling), or
DQ6 (toggle) status bits. After a program or erase cycle is
completed, the device is ready to read array data or accept
another command.
The sector erase architecture allows memory sectors to be
erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when
shipped from the factory.
Hardware data protection measures include a low VCC
detector that automatically inhibits write operations during
power transitions. The hardware sector protection feature disables both program and erase operations in any combination
of sectors of memory. This can be achieved in-system or via
programming equipment.
The Erase Suspend feature enables the user to put erase on
hold for any period of time to read data from, or program data
to, any sector that is not selected for erasure. True background erase can thus be achieved.
The device offers a standby mode as a power-saving feature. Once the system places the device into the standby
mode power consumption is greatly reduced.
AMD’s Flash technology combines years of Flash memory
manufacturing experience to produce the highest levels of
quality, reliability and cost effectiveness. The device electrically erases all bits within a sector simultaneously via FowlerNordheim tunnelling. The data is programmed using hot electron injection.
Am29F004B
Am29F004B_00_E4 May 9, 2006
D A T A
S H E E T
TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 4
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . 5
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 7
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . 8
DQ6: Toggle Bit I .................................................................... 18
DQ2: Toggle Bit II ................................................................... 18
Reading Toggle Bits DQ6/DQ2 ............................................... 18
DQ5: Exceeded Timing Limits ................................................ 18
DQ3: Sector Erase Timer ....................................................... 18
Am29F004B Device Bus Operations ................................................8
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 20
Requirements for Reading Array Data ..................................... 8
Writing Commands/Command Sequences .............................. 8
Program and Erase Operation Status ...................................... 8
Standby Mode .......................................................................... 8
Output Disable Mode ................................................................ 9
Maximum Negative Overshoot Waveform ..................................... 20
Maximum Positive Overshoot Waveform ....................................... 20
Am29F004B Top Boot Block Sector Addresses ...............................9
Am29F004B Bottom Boot Block Sector Addresses ..........................9
Autoselect Mode ..................................................................... 10
Am29F004B Autoselect Codes (High Voltage Method) ..................10
Sector Protection/Unprotection ............................................... 10
In-System Sector Protect/Sector Unprotect Algorithms ..................11
Temporary Sector Unprotect .................................................. 12
Toggle Bit Algorithm ....................................................................... 19
Write Operation Status ................................................................... 19
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . 20
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 21
TTL/NMOS Compatible .......................................................... 21
CMOS Compatible .................................................................. 22
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Test Setup ...................................................................................... 23
Test Specifications ......................................................................... 23
Key to Switching Waveforms . . . . . . . . . . . . . . . 23
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 24
Read Operations .................................................................... 24
Temporary Sector Unprotect Operation ..........................................12
Read Operations Timings .............................................................. 24
Hardware Data Protection ...................................................... 13
Erase/Program Operations ..................................................... 25
Low VCC Write Inhibit ......................................................................13
Write Pulse Glitch Protection ..........................................................13
Logical Inhibit ..................................................................................13
Power-Up Write Inhibit ....................................................................13
Program Operation Timings ........................................................... 26
Chip/Sector Erase Operation Timings ............................................ 26
Data# Polling Timings (During Embedded Algorithms) .................. 27
Toggle Bit Timings (During Embedded Algorithms) ....................... 27
DQ2 vs. DQ6.................................................................................. 27
Sector Unlock Sequence Timing Diagram ..................................... 28
Sector Relock Timing Diagram ...................................................... 28
Sector Protect/Unprotect Timing Diagram ..................................... 29
Command Definitions . . . . . . . . . . . . . . . . . . . . . . 13
Reading Array Data ................................................................ 13
Reset Command ..................................................................... 13
Autoselect Command Sequence ............................................ 13
Byte Program Command Sequence ....................................... 13
Program Operation ..........................................................................14
Chip Erase Command Sequence ........................................... 14
Sector Erase Command Sequence ........................................ 14
Erase Operation ..............................................................................15
Erase Suspend/Erase Resume Commands ........................... 15
Am29F004B Command Definitions .................................................16
Write Operation Status . . . . . . . . . . . . . . . . . . . . . 17
DQ7: Data# Polling ................................................................. 17
Alternate CE# Controlled Erase/Program Operations ............ 30
Alternate CE# Controlled Write Operation Timings ........................ 31
Erase and Programming Performance . . . . . . . 32
Latchup Characteristics . . . . . . . . . . . . . . . . . . . 32
PLCC Pin Capacitance . . . . . . . . . . . . . . . . . . . . 32
Data Retention . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 33
PL 032—32-Pin Plastic Leaded Chip Carrier ......................... 33
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 34
Data# Polling Algorithm ...................................................................17
May 9, 2006 Am29F004B_00_E4
Am29F004B
3
D A T A
S H E E T
PRODUCT SELECTOR GUIDE
Family Part Number
Am29F004B
Speed Option
VCC = 5.0 V ± 10%
-70
-90
Max access time, ns (tACC)
70
90
Max CE# access time, ns (tCE)
70
90
Max OE# access time, ns (tOE)
30
35
Note: See “AC Characteristics” for full specifications.
BLOCK DIAGRAM
DQ0–DQ7
VCC
Sector Switches
VSS
Erase Voltage
Generator
WE#
Input/Output
Buffers
State
Control
Command
Register
PGM Voltage
Generator
Chip Enable
Output Enable
Logic
CE#
OE#
VCC Detector
Address Latch
STB
Timer
A0–A18
4
Am29F004B
STB
Data
Latch
Y-Decoder
Y-Gating
X-Decoder
Cell Matrix
Am29F004B_00_E4 May 9, 2006
D A T A
S H E E T
4 3 2
WE#
A17
VCC
A18
A16
A12
A15
CONNECTION DIAGRAMS
1 32 31 30
A7
5
29
A14
A6
6
28
A13
A5
A4
7
8
27
26
A8
A9
A3
9
25
A11
A2
10
24
OE#
A1
11
23
A10
A0
12
22
DQ0
13
CE#
DQ7
PLCC
21
DQ5
DQ6
DQ4
VSS
DQ3
DQ1
DQ2
14 15 16 17 18 19 20
Standard 48-Pin TSOP
May 9, 2006 Am29F004B_00_E4
Am29F004B
5
D A T A
PIN CONFIGURATION
A0–A18
S H E E T
LOGIC SYMBOL
= 19 addresses
19
DQ0–DQ7 = 8 data inputs/outputs
A0–A18
CE#
= Chip enable
OE#
= Output enable
WE#
= Write enable
CE#
VCC
= +5.0 V single power supply
(see Product Selector Guide for
device speed ratings and voltage
supply tolerances)
OE#
VSS
= Device ground
NC
= Pin not connected internally
6
8
DQ0–DQ7
WE#
Am29F004B
Am29F004B_00_E4 May 9, 2006
D A T A
S H E E T
ORDERING INFORMATION
Standard Product
AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed
by a combination of the elements below.
Am29F004B
T
-70
J
I
TEMPERATURE RANGE
I
= Industrial (–40°C to +85°C)
F
= Industrial (–40°C to +85°C) for Pb-free package
E
= Extended (–55°C to +125°C)
K
= Extended (–55°C to +125°C) for Pb-free package
PACKAGE TYPE
J
= 32-Pin Rectangular Plastic Leaded Chip Carrier (PL 032)
SPEED OPTION
See Product Selector Guide and Valid Combinations
BOOT CODE SECTOR ARCHITECTURE
T
=
Top sector
B
=
Bottom sector
DEVICE NUMBER/DESCRIPTION
Am29F004B
4 Megabit (512 K x 8-Bit) CMOS Flash Memory
5.0 Volt-only Program and Erase
Valid Combinations
VCC Voltage
AM29F004BT-70
AM29F004BB-70
JI, JF
Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales
office to confirm availability of specific valid combinations and
to check on newly released combinations.
5.0 V ± 10%
AM29F004BT-90
AM29F004BB-90
JI, JE,
JF, JK
Valid Combinations
May 9, 2006 Am29F004B_00_E4
Am29F004B
7
D A T A
S H E E T
DEVICE BUS OPERATIONS
This section describes the requirements and use of the
device bus operations, which are initiated through the internal
command register. The command register itself does not
occupy any addressable memory location. The register is
composed of latches that store the commands, along with the
address and data information needed to execute the com-
mand. The contents of the register serve as inputs to the
internal state machine. The state machine outputs dictate the
function of the device. The appropriate device bus operations
table lists the inputs and control levels required, and the
resulting output. The following subsections describe each of
these operations in further detail.
Table 1. Am29F004B Device Bus Operations
Operation
CE#
OE#
WE#
A0–A18
DQ0–DQ7
DOUT
Read
L
L
H
AIN
Write
L
H
L
AIN
DIN
VCC ± 0.5 V
X
X
X
High-Z
H
X
X
X
High-Z
Output Disable
L
H
H
X
High-Z
Temporary Sector Unprotect (See Note)
X
X
X
X
X
CMOS Standby
TTL Standby
Legend:
L = Logic Low = VIL, H = Logic High = VIH, VID = 12.0 ± 0.5 V, X = Don’t Care, DIN = Data In, DOUT = Data Out, AIN = Address In
Note: See the sections on Sector Protection and Temporary Sector
Unprotect for more information.
Requirements for Reading Array Data
To read array data from the outputs, the system must drive
the CE# and OE# pins to VIL. CE# is the power control and
selects the device. OE# is the output control and gates array
data to the output pins. WE# should remain at VIH.
The internal state machine is set for reading array data upon
device power-up. This ensures that no spurious alteration of
the memory content occurs during the power transition. No
command is necessary in this mode to obtain array data.
Standard microprocessor read cycles that assert valid
addresses on the device address inputs produce valid data
on the device data outputs. The device remains enabled for
read access until the command register contents are altered.
See Reading Array Data on page 13 for more information.
Refer to the AC Read Operations table for timing specifications and to the Read Operations Timings diagram for the
timing waveforms. ICC1 in the DC Characteristics table represents the active current specification for reading array data.
Writing Commands/Command Sequences
To write a command or command sequence (which includes
programming data to the device and erasing sectors of
memory), the system must drive WE# and CE# to VIL, and
OE# to VIH.
An erase operation can erase one sector, multiple sectors, or
the entire device. The Sector Address Tables indicate the
address space that each sector occupies. A “sector address”
consists of the address bits required to uniquely select a
sector. See the Command Definitions on page 13 section for
details on erasing a sector or the entire chip, or suspending/resuming the erase operation.
After the system writes the autoselect command sequence,
the device enters the autoselect mode. The system can then
read autoselect codes from the internal register (which is
8
separate from the memory array) on DQ7–DQ0. Standard
read cycle timings apply in this mode. Refer to the Autoselect
Mode on page 10 and Autoselect Command Sequence sections for more information.
ICC2 in the DC Characteristics table represents the active
curren t speci fi ca t ion fo r th e wri te mode . The AC
Characteristics on page 24 section contains timing specification tables and timing diagrams for write operations.
Program and Erase Operation Status
During an erase or program operation, the system may check
the status of the operation by reading the status bits on DQ7–
DQ0. Standard read cycle timings and ICC read specifications
apply. Refer to Write Operation Status on page 17 for more
information, and to each AC Characteristics section for timing
diagrams.
Standby Mode
When the system is not reading or writing to the device, it can
place the device in the standby mode. In this mode, current
consumption is greatly reduced, and the outputs are placed
in the high impedance state, independent of the OE# input.
The device enters the CMOS standby mode when CE# pin is
held at VCC ± 0.5 V. (Note that this is a more restricted voltage
range than VIH.) The device enters the TTL standby mode
when CE# pin is held at VIH. The device requires standard
access time (tCE) for read access when the device is in either
of these standby modes, before it is ready to read data.
If the device is deselected during erasure or programming,
the device draws active current until the operation is
completed.
In the DC Characteristics tables, ICC3 represents the standby
current specification.
Am29F004B
Am29F004B_00_E4 May 9, 2006
D A T A
S H E E T
Output Disable Mode
When the OE# input is at VIH, output from the device is disabled. The output pins are placed in the high impedance
state.
Table 2. Am29F004B Top Boot Block Sector Addresses
Sector
A18
A17
A16
A15
A14
A13
Sector Size
(Kbytes)
Address Range
(in hexadecimal)
SA0
0
0
0
X
X
X
64
00000h–0FFFFh
SA1
0
0
1
X
X
X
64
10000h–1FFFFh
SA2
0
1
0
X
X
X
64
20000h–2FFFFh
SA3
0
1
1
X
X
X
64
30000h–3FFFFh
SA4
1
0
0
X
X
X
64
40000h–4FFFFh
SA5
1
0
1
X
X
X
64
50000h–5FFFFh
SA6
1
1
0
X
X
X
64
60000h–6FFFFh
SA7
1
1
1
0
X
X
32
70000h–77FFFh
SA8
1
1
1
1
0
0
8
78000h–79FFFh
SA9
1
1
1
1
0
1
8
7A000h–7BFFFh
SA10
1
1
1
1
1
X
16
7C000h–7FFFFh
Table 3.
Am29F004B Bottom Boot Block Sector Addresses
Sector
A18
A17
A16
A15
A14
A13
Sector Size
(Kbytes)
Address Range
(in hexadecimal)
SA0
0
0
0
0
0
X
16
00000h–03FFFh
SA1
0
0
0
0
1
0
8
04000h–05FFFh
SA2
0
0
0
0
1
1
8
06000h–07FFFh
SA3
0
0
0
1
X
X
32
08000h–0FFFFh
SA4
0
0
1
X
X
X
64
10000h–1FFFFh
SA5
0
1
0
X
X
X
64
20000h–2FFFFh
SA6
0
1
1
X
X
X
64
30000h–3FFFFh
SA7
1
0
0
X
X
X
64
40000h–4FFFFh
SA8
1
0
1
X
X
0
64
50000h–5FFFFh
SA9
1
1
0
X
X
1
64
60000h–6FFFFh
SA10
1
1
1
X
X
X
64
70000h–7FFFFh
May 9, 2006 Am29F004B_00_E4
Am29F004B
9
D A T A
Autoselect Mode
The autoselect mode provides manufacturer and device identification, and sector protection verification, through identifier
codes output on DQ7–DQ0. This mode is primarily intended
for programming equipment to automatically match a device
to be programmed with its corresponding programming algorithm. However, the autoselect codes can also be accessed
in-system through the command register.
When using programming equipment, the autoselect mode
requires VID on address pin A9. Address pins A6, A1, and A0
must be as shown in Autoselect Codes (High Voltage
Method) table. In addition, when verifying sector protection,
S H E E T
the sector address must appear on the appropriate highest
order address bits. Refer to the corresponding Sector
Address Tables. The Command Definitions table shows the
remaining address bits that are don’t care. When all necessary bits are set as required, the programming equipment
may then read the corresponding identifier code on DQ7–
DQ0.
To access the autoselect codes in-system, the host system
can issue the autoselect command via the command register,
as shown in the Command Definitions table. This method
does not require VID. See Command Definitions on page 13
for details on using the autoselect mode.
Table 4. Am29F004B Autoselect Codes (High Voltage Method)
CE#
OE#
WE#
A18
to
A13
Manufacturer ID: AMD
L
L
H
X
X
VID
X
L
X
L
L
01h
Device ID:
Am29F004B (Top Boot Block)
L
L
H
X
X
L
X
L
H
77h
L
H
VID
X
L
Device ID:
Am29F004B (Bottom Boot Block)
L
L
H
X
X
L
X
L
H
7Bh
L
H
VID
X
L
Sector Protection Verification
L
L
H
SA
X
VID
X
L
X
H
L
Description
A12
to
A10
A9
A8
to
A7
A6
A5
to
A2
A1
A0
DQ7
to
DQ0
01h (protected)
00h
(unprotected)
L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care.
Sector Protection/Unprotection
The hardware sector protection feature disables both
program and erase operations in any sector. The hardware
sector unprotection feature re-enables both program and
erase operations in previously protected sectors.
The primary method requires VID on the OE# pin only, and
can be implemented either in-system or via programming
equipment. Figure 1, on page 11 and 2 show the algorithms
and Figure 16, on page 28, Figure 17, on page 28, and Figure
18, on page 29 show the timing diagrams. This method uses
standard microprocessor bus cycle timing in addition to the
sector unlock and sector relock sequences. For sector unprotect, all unprotected sectors must first be protected prior to
the first sector unprotect write cycle.
10
The alternate method intended only for programming equipment required VID on address pin A9 and OE#. This method
is compatible with programmer routines written for earlier 5.0
volt-only AMD Flash devices. Publication number 22289 contains further details; contact an AMD representative to
request a copy.
The device is shipped with all sectors unprotected. AMD
offers the option of programming and protecting sectors at its
factory prior to shipping the device through AMD’s ExpressFlash™ Service. Contact an AMD representative for details.
It is possible to determine whether a sector is protected or
unprotected. See Autoselect Mode on page 10 for details.
Am29F004B
Am29F004B_00_E4 May 9, 2006
D A T A
S H E E T
START
START
PLSCNT = 1
PLSCNT = 1
Set OE# = VID.
Write Sector
Unlock sequence
with command 24h
Set OE# = VID.
Write Sector
Unlock sequence
with command 24h
Protect all sectors:
The indicated portion
of the sector protect
algorithm must be
performed for all
unprotected sectors
prior to issuing the
first sector
unprotect address
Wait 1 μs
Write 60h to any
address with
A6 = 0, A5 = 1,
A1 = 1, A0 = 0
Set up sector
address
Wait 1 μs
Write 60h to
any address with
A6 = 1, A5 = 1,
A1 = 1, A0 = 0
No
All sectors
protected?
Sector Protect:
Write 60h to sector
address with
A6 = 0, A5 = 1,
A1 = 1, A0 = 0
Yes
Set up first sector
address
Wait 150 ± 15 µs
Sector Unprotect:
Write 60h to sector
address with
A6 = 1, A5 = 1,
A1 = 1, A0 = 0
Set OE# = VIH
Increment
PLSCNT
Verify Sector
Protect: Write 40h
to sector address
with A6 = 0,
A1 = 1, A0 = 0
Wait 15 ± 1.5 ms
Read from
sector address
with A6 = 0,
A1 = 1, A0 = 0
(requires 1 µs
access time)
Verify Sector
Unprotect: Write
40h to sector
address with
A6 = 1, A1 = 1,
A0 = 0
Increment
PLSCNT
Set OE# = VIL
Read from
sector address
with A6 = 1,
A1 = 1, A0 = 0
(requires 1 µs
access time)
No
Data = 01h?
Yes
Yes
Device failed
Reset
PLSCNT = 1
Set OE# = VIL
No
PLSCNT
= 25?
Set OE# = VIH
Protect another
sector?
No
Yes
PLSCNT
= 1000?
No
Yes
Set OE# = VID.
Write Sector
Relock sequence.
Set OE# = VIH.
Device failed
Set up
next sector
address
No
Data = 00h?
Yes
Last sector
verified?
No
Yes
Sector Protect
Algorithm
Sector Protect
complete
Sector Unprotect
Algorithm
Set OE# = VID.
Write Sector
Relock sequence.
Set OE# = VIH.
Sector Unprotect
complete
Figure 1.
May 9, 2006 Am29F004B_00_E4
In-System Sector Protect/Sector Unprotect Algorithms
Am29F004B
11
D A T A
S H E E T
Temporary Sector Unprotect
This feature allows temporary unprotection of previously protected sectors to change data in-system. The Sector
Unprotect mode is activated by setting the OE# pin to 12.0
Volts (VID). Figure 2 shows the algorithm, and Figure 16, on
page 28 and Figure 17, on page 28 show the timing diagrams, for this feature. While OE# is at VID, the sector unlock
sequence is written to the device. After the sector unlock
sequence is written, the OE# pin is taken back to VIH. The
device is now in the temporary sector unprotect mode.
START
OE# = VID
Write the three-cycle
Unlock sequence with command 20h (Figure 16)
While in this mode, formerly protected sectors can be programmed or erased by selecting the appropriate sector
address during programming or erase operations. Either
sector erase or chip erase operations can be performed in
this mode. Byte program operations require only two cycles,
while sector and chip erase operations only require four
cycles. Refer to the Command Definitions table.
OE# = VIH (Note 1)
Perform Erase or
Program Operations
Exiting the temporary sector unprotect mode is accomplished
by either removing VCC from the device or by taking OE#
back to VID and writing the sector relock sequence.
OE# = VID
After writing the sector relock sequence, the OE# pin is taken
back to VIH and all previously protected sectors are protected
again.
Write the two-cycle
Sector Relock sequence (Figure 17)
OE# = VIH
Temporary Sector
Unprotect
Completed (Note 2)
Notes:
1. All protected sectors unprotected.
2. All previously protected sectors are protected once again.
Figure 2. Temporary Sector Unprotect Operation
12
Am29F004B
Am29F004B_00_E4 May 9, 2006
D A T A
Hardware Data Protection
The command sequence requirement of unlock cycles for
programming or erasing provides data protection against
inadvertent writes (refer to the Command Definitions table).
In addition, the following hardware data protection measures
prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during
VCC power-up and power-down transitions, or from system
noise.
Low VCC Write Inhibit
When VCC is less than VLKO, the device does not accept any
write cycles. This protects data during VCC power-up and
power-down. The command register and all internal program/erase circuits are disabled, and the device resets.
Subsequent writes are ignored until VCC is greater than VLKO.
The system must provide the proper signals to the control
pins to prevent unintentional writes when VCC is greater than
VLKO.
Write Pulse Glitch Protection
Noise pulses of less than 5 ns (typical) on OE#, CE# or WE#
do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE# = VIL,
CE# = VIH or WE# = VIH. To initiate a write cycle, CE# and
WE# must be a logical zero while OE# is a logical one.
Power-Up Write Inhibit
If WE# = CE# = VIL and OE# = VIH during power up, the
device does not accept commands on the rising edge of
WE#. The internal state machine is automatically reset to
reading array data on power-up.
S H E E T
The system must issue the reset command to re-enable the
device for reading array data if DQ5 goes high, or while in the
autoselect mode. See the Reset Command section, next.
See also “Requirements for Reading Array Data” in the
Device Bus Operations on page 8 section for more information. The Read Operations table provides the read
parameters, and Read Operation Timings diagram shows the
timing diagram.
Reset Command
Writing the reset command to the device resets the device to
reading array data. Address bits are don’t care for this
command.
The reset command may be written between the sequence
cycles in an erase command sequence before erasing
begins. This resets the device to reading array data. Once
erasure begins, however, the device ignores reset commands
until the operation is complete.
The reset command may be written between the sequence
cycles in a program command sequence before programming
begins. This resets the device to reading array data (also
applies to programming in Erase Suspend mode). Once programming begins, however, the device ignores reset
commands until the operation is complete.
The reset command may be written between the sequence
cycles in an autoselect command sequence. Once in the
autoselect mode, the reset command must be written to
return to reading array data (also applies to autoselect during
Erase Suspend).
If DQ5 goes high during a program or erase operation, writing
the reset command returns the device to reading array data
(also applies during Erase Suspend).
COMMAND DEFINITIONS
Autoselect Command Sequence
Writing specific address and data commands or sequences
into the command register initiates device operations. The
Command Definitions table defines the valid register
command sequences. Writing incorrect address and data
values or writing them in the improper sequence resets the
device to reading array data.
The autoselect command sequence allows the host system
to access the manufacturer and devices codes, and determine whether or not a sector is protected. The Command
Definitions table shows the address and data requirements.
This method is an alternative to that shown in the Autoselect
Codes (High Voltage Method) table, which is intended for
PROM programmers and requires VID on address bit A9.
All addresses are latched on the falling edge of WE# or CE#,
whichever happens later. All data is latched on the rising edge
of WE# or CE#, whichever happens first. Refer to the appropriate timing diagrams in AC Characteristics on page 24.
Reading Array Data
The device is automatically set to reading array data after
device power-up. No commands are required to retrieve data.
The device is also ready to read array data after completing
an Embedded Program or Embedded Erase algorithm.
After the device accepts an Erase Suspend command, the
device enters the Erase Suspend mode. The system can
read array data using the standard read timings, except that
if it reads at an address within erase-suspended sectors, the
device outputs status data. After completing a programming
operation in the Erase Suspend mode, the system may once
again read array data with the same exception. See Reset
Command for more information on this mode.
May 9, 2006 Am29F004B_00_E4
The autoselect command sequence is initiated by writing two
unlock cycles, followed by the autoselect command. The
device then enters the autoselect mode, and the system may
read at any address any number of times, without initiating
another command sequence.
A read cycle at address XX00h or retrieves the manufacturer
code. A read cycle at address XX01h returns the device code.
A read cycle containing a sector address (SA) and the
address 02h in returns 01h if that sector is protected, or 00h
if it is unprotected. Refer to the Sector Address tables for valid
sector addresses.
The system must write the reset command to exit the autoselect mode and return to reading array data.
Byte Program Command Sequence
Programming is a four-bus-cycle operation. The program
command sequence is initiated by writing two unlock write
Am29F004B
13
D A T A
cycles, followed by the program set-up command. The
program address and data are written next, which in turn initiate the Embedded Program algorithm. The system is not
required to provide further controls or timings. The device
automatically provides internally generated program pulses
and verify the programmed cell margin. (Note that if the
device is in the temporary sector unprotect mode, the byte
program command sequence only requires two cycles.) The
Command Definitions table shows the address and data
requirements for the byte program command sequence.
When the Embedded Program algorithm is complete, the
device then returns to reading array data and addresses are
no longer latched. The system can determine the status of
the program operation by using DQ7 or DQ6. See Write
Operation Status on page 17 for information on these status
bits.
Any commands written to the device during the Embedded
Program Algorithm are ignored. The Sector Erase command
sequence should be reinitiated once the device returns to
reading array data, to ensure data integrity.
Programming is allowed in any sequence and across sector
boundaries. A bit cannot be programmed from a 0 back to
a 1. Attempting to do so may halt the operation and set DQ5
to 1, or cause the Data# Polling algorithm to indicate the operation was successful. However, a succeeding read shows
that the data is still 0. Only erase operations can convert a 0
to a 1”.
Data Poll
from System
Increment Address
No
Last Address?
Yes
Programming
Completed
Note: See the appropriate Command Definitions table for program
command sequence.
Figure 3.
14
Any commands written to the chip during the Embedded
Erase algorithm are ignored. The Sector Erase command
sequence should be reinitiated once the device returns to
reading array data, to ensure data integrity.
The system can determine the status of the erase operation
by using DQ7, DQ6, or DQ2. See Write Operation Status on
page 17 for information on these status bits. When the
Embedded Erase algorithm is complete, the device returns to
reading array data and addresses are no longer latched.
Figure 4, on page 15 illustrates the algorithm for the erase
operation. See the Erase/Program Operations on page 25
for parameters, and to Figure 12, on page 26 for timing
waveforms.
The device does not require the system to preprogram the
memory prior to erase. The Embedded Erase algorithm automatically programs and verifies the sector for an all zero data
pattern prior to electrical erase. The system is not required to
provide any controls or timings during these operations.
Yes
No
Chip erase is a six-bus-cycle operation. The chip erase
command sequence is initiated by writing two unlock cycles,
followed by a set-up command. Two additional unlock write
cycles are then followed by the chip erase command, which
in turn invokes the Embedded Erase algorithm. The device
does not require the system to preprogram prior to erase. The
Embedded Erase algorithm automatically preprograms and
verifies the entire memory for an all zero data pattern prior to
electrical erase. The system is not required to provide any
controls or timings during these operations. (Note that if the
device is in the temporary sector unprotect mode, the chip
erase command sequence only requires four cycles.) The
Command Definitions table shows the address and data
requirements for the chip erase command sequence.
Sector erase is a six-bus-cycle operation. The sector erase
command sequence is initiated by writing two unlock cycles,
followed by a set-up command. Two additional unlock write
cycles are then followed by the address of the sector to be
erased, and the sector erase command. (Note that if the
device is in the temporary sector unprotect mode, the sector
erase command sequence only requires four cycles.) The
Command Definitions table shows the address and data
requirements for the sector erase command sequence.
Write Program
Command Sequence
Verify Data?
Chip Erase Command Sequence
Sector Erase Command Sequence
START
Embedded
Program
algorithm
in progress
S H E E T
Program Operation
After the command sequence is written, a sector erase timeout of 50 µs begins. During the time-out period, additional
sector addresses and sector erase commands may be
written. Loading the sector erase buffer may be done in any
sequence, and the number of sectors may be from one sector
to all sectors. The time between these additional cycles must
be less than 50 µs, otherwise the last address and command
might not be accepted, and erasure may begin. It is recommended that processor interrupts be disabled during this time
to ensure all commands are accepted. The interrupts can be
re-enabled after the last Sector Erase command is written. If
the time between additional sector erase commands can be
assumed to be less than 50 µs, the system need not monitor
DQ3. Any command other than Sector Erase or Erase
Suspend during the time-out period resets the device to
reading array data. The system must rewrite the command
Am29F004B
Am29F004B_00_E4 May 9, 2006
D A T A
sequence and any additional sector addresses and
commands.
The system can monitor DQ3 to determine if the sector erase
timer timed out. (See DQ3: Sector Erase Timer on page 18.)
The time-out begins from the rising edge of the final WE#
pulse in the command sequence.
Once the sector erase operation begins, only the Erase
Suspend command is valid. All other commands are ignored.
The Sector Erase command sequence should be reinitiated
once the device returns to reading array data, to ensure data
integrity.
When the Embedded Erase algorithm is complete, the device
returns to reading array data and addresses are no longer
latched. The system can determine the status of the erase
operation by using DQ7, DQ6, or DQ2. Refer to Write Operation Status on page 17 for information on these status bits.
Figure 4 illustrates the algorithm for the erase operation.
Refer to the Erase/Program Operations on page 25 for
parameters, and to the Sector Erase Operations Timing
diagram for timing waveforms.
START
Write Erase
Command Sequence
Data Poll
from System
No
S H E E T
Erase Suspend/Erase Resume Commands
The Erase Suspend command allows the system to interrupt
a sector erase operation and then read data from, or program
data to, any sector not selected for erasure. This command is
valid only during the sector erase operation, including the 50
µs time-out period during the sector erase command
sequence. The Erase Suspend command is ignored if written
during the chip erase operation or Embedded Program algorithm. Writing the Erase Suspend command during the
Sector Erase time-out immediately terminates the time-out
period and suspends the erase operation. Addresses are
don’t-cares when writing the Erase Suspend command.
When the Erase Suspend command is written during a sector
erase operation, the device requires a maximum of 20 µs to
suspend the erase operation. However, when the Erase
Suspend command is written during the sector erase timeout, the device immediately terminates the time-out period
and suspends the erase operation.
After the erase operation is suspended, the system can read
array data from or program data to any sector not selected for
erasure. (The device “erase suspends” all sectors selected
for erasure.) Normal read and write timings and command
definitions apply. Reading at any address within erase-suspended sectors produces status data on DQ7–DQ0. The
system can use DQ7, or DQ6 and DQ2 together, to determine if a sector is actively erasing or is erase-suspended.
See Write Operation Status on page 17 for information on
these status bits.
After an erase-suspended program operation is complete,
the system can once again read array data within non-suspended sectors. The system can determine the status of the
program operation using the DQ7 or DQ6 status bits, just as
in the standard program operation. See Write Operation
Status on page 17 for more information.
Embedded
Erase
algorithm
in progress
The system may also write the autoselect command
sequence when the device is in the Erase Suspend mode.
The device allows reading autoselect codes even at
addresses within erasing sectors, since the codes are not
stored in the memory array. When the device exits the
autoselect mode, the device reverts to the Erase Suspend
mode, and is ready for another valid operation. See
Autoselect Command Sequence on page 13 for more
information.
Data = FFh?
Yes
The system must write the Erase Resume command
(address bits are don’t care) to exit the erase suspend mode
and continue the sector erase operation. Further writes of the
Resume command are ignored. Another Erase Suspend
command can be written after the device resumes erasing.
Erasure Completed
Note:
1. See the appropriate Command Definitions table for erase
command sequence.
2. See DQ3: Sector Erase Timer on page 18 for more information.
Figure 4. Erase Operation
May 9, 2006 Am29F004B_00_E4
Am29F004B
15
D A T A
Command
Sequence
(Note 1)
Cycles
Table 5.
S H E E T
Am29F004B Command Definitions
Bus Cycles (Notes 2–4)
First
Second
Addr
Data
RD
Third
Fourth
Addr
Data
Addr
Data
Addr
Data
Fifth
Sixth
Addr
Data
Addr
Data
Read (Note 5)
1
RA
Reset (Note 6)
1
XXX
F0
Manufacturer ID
4
555
AA
2AA
55
555
90
X00
01
Device ID,
Top Boot Block
4
555
AA
2AA
55
555
90
X01
77
Device ID,
Bottom Boot Block
4
555
AA
2AA
55
555
90
X01
7B
Sector Protect Verify
(Note 8)
4
555
AA
2AA
55
555
90
(SA)
X02
00
Program
4
555
AA
2AA
55
555
A0
PA
PD
Chip Erase
6
555
AA
2AA
55
555
80
555
AA
2AA
55
555
10
Sector Erase
6
555
AA
2AA
55
555
80
555
AA
2AA
55
SA
30
Erase Suspend (Note 11)
1
XXX
B0
Erase Resume (Note 12)
1
XXX
30
Temporary
Sector
Unprotect
Mode (Note
9)
Enter TSU Mode
3
555
AA
2AA
55
555
20
Program
2
XXX
A0
PA
PD
Sector Erase
4
XXX
80
XXX
AA
XXX
55
SA
30
Chip Erase
4
XXX
80
XXX
AA
XXX
55
555
10
555
24
SA+
60
SA+
60
SA+
40
Autoselect
(Note 7)
Sector Unlock (Note 9)
3
555
AA
2AA
55
Sector Relock (Notes 9, 10)
2
XXX
90
XXX
00
Legend:
01
PD = Data to be programmed at location PA. Data latches on the
rising edge of WE# or CE# pulse, whichever happens first.
X = Don’t care
SA = Address of the sector to be verified (in autoselect mode) or
erased. Address bits A18–A13 uniquely select any sector.
RA = Address of the memory location to be read.
RD = Data read from location RA during read operation.
PA = Address of the memory location to be programmed. Addresses
latch on the falling edge of the WE# or CE# pulse, whichever
happens later.
Notes:
1. See Table 1 for description of bus operations.
2. All values are in hexadecimal.
3. Except when reading array or autoselect data, all bus cycles are
write operations.
SA+ = The sector address must be asserted in combination with A0
= 0, A1 = 1, A5 = 1, and A6 = 0 (for protect) or 1 (for unprotect).
8. The data is 00h for an unprotected sector and 01h for a protected
sector. See Autoselect Command Sequence on page 13 for
more information.
9. To activate the sequence, OE# must be at VID.
4. Address bits A18–A11 are don’t cares for unlock and command
cycles, except when PA or SA is required.
10. The sector relock command in the second cycle may be written
as either 00h or F0h.
5. No unlock or command cycles required when reading array data.
11. The system may read and program in non-erasing sectors, or
enter the autoselect mode, when in the Erase Suspend mode.
The Erase Suspend command is valid only during a sector erase
operation.
6. The Reset command is required to return to reading array data
when device is in the autoselect mode, or if DQ5 goes high (while
the device is providing status data).
7. The fourth cycle of the autoselect command sequence is a read
cycle.
16
12. The Erase Resume command is valid only during the Erase Suspend mode.
Am29F004B
Am29F004B_00_E4 May 9, 2006
D A T A
S H E E T
WRITE OPERATION STATUS
The device provides several bits to determine the status of a
write operation: DQ2, DQ3, DQ5, DQ6, and DQ7. Table 6 on
page 19 and the following subsections describe the functions
of these bits. DQ7 and DQ6 each offer a method for determining whether a program or erase operation is complete or
in progress. These three bits are discussed first.
START
Read DQ7–DQ0
Addr = VA
DQ7: Data# Polling
The Data# Polling bit, DQ7, indicates to the host system
whether an Embedded Algorithm is in progress or completed,
or whether the device is in Erase Suspend. Data# Polling is
valid after the rising edge of the final WE# pulse in the
program or erase command sequence.
DQ7 = Data?
During the Embedded Program algorithm, the device outputs
on DQ7 the complement of the datum programmed to DQ7.
This DQ7 status also applies to programming during Erase
Suspend. When the Embedded Program algorithm is complete, the device outputs the datum programmed to DQ7. The
system must provide the program address to read valid status
information on DQ7. If a program address falls within a prot e c t ed s e c t o r, Da t a # Po ll i n g o n DQ 7 i s a c t i ve fo r
approximately 2 µs, then the device returns to reading array
data.
No
No
When the system detects DQ7 changes from the complement to true data, it can read valid data at DQ7–DQ0 on the
following read cycles. This is because DQ7 may change
asynchronously with DQ0–DQ6 while Output Enable (OE#) is
asserted low. The Data# Polling Timings (During Embedded
Algorithms) figure in the AC Characteristics on page 24
section illustrates this.
DQ5 = 1?
Yes
Read DQ7–DQ0
Addr = VA
During the Embedded Erase algorithm, Data# Polling produces a “0” on DQ7. When the Embedded Erase algorithm is
complete, or if the device enters the Erase Suspend mode,
Data# Polling produces a “1” on DQ7. This is analogous to
the complement/true datum output described for the
Embedded Program algorithm: the erase function changes
all the bits in a sector to “1”; prior to this, the device outputs
the “complement,” or “0.” The system must provide an
address within any of the sectors selected for erasure to read
valid status information on DQ7.
After an erase command sequence is written, if all sectors
selected for erasing are protected, Data# Polling on DQ7 is
active for approximately 100 µs, then the device returns to
reading array data. If not all selected sectors are protected,
the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected.
Yes
DQ7 = Data?
Yes
No
FAIL
PASS
Notes:
1. VA = Valid address for programming. During a sector erase
operation, a valid address is an address within any sector
selected for erasure. During chip erase, a valid address is any
non-protected sector address.
2. DQ7 should be rechecked even if DQ5 = “1” because DQ7 may
change simultaneously with DQ5.
Figure 5. Data# Polling Algorithm
Table 6 on page 19 shows the outputs for Data# Polling on
DQ7. Figure 5, on page 17 shows the Data# Polling
algorithm.
May 9, 2006 Am29F004B_00_E4
Am29F004B
17
D A T A
DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded
Program or Erase algorithm is in progress or complete, or
whether the device entered the Erase Suspend mode. Toggle
Bit I may be read at any address, and is valid after the rising
edge of the final WE# pulse in the command sequence (prior
to the program or erase operation), and during the sector
erase time-out.
During an Embedded Program or Erase algorithm operation,
successive read cycles to any address cause DQ6 to toggle.
(The system may use either OE# or CE# to control the read
cycles.) When the operation is complete, DQ6 stops toggling.
After an erase command sequence is written, if all sectors
selected for erasing are protected, DQ6 toggles for approximately 100 μs, then returns to reading array data. If not all
selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the
selected sectors that are protected.
The system can use DQ6 and DQ2 together to determine
whether a sector is actively erasing or is erase-suspended.
When the device is actively erasing (that is, the Embedded
Erase algorithm is in progress), DQ6 toggles. When the
device enters the Erase Suspend mode, DQ6 stops toggling.
However, the system must also use DQ2 to determine which
sectors are erasing or erase-suspended. Alternatively, the
system can use DQ7 (see the subsection on DQ7: Data#
Polling).
If a program address falls within a protected sector, DQ6
toggles for approximately 2 µs after the program command
sequence is written, then returns to reading array data.
DQ6 also toggles during the erase-suspend-program mode,
and stops toggling once the Embedded Program algorithm is
complete.
The Write Operation Status table shows the outputs for
Toggle Bit I on DQ6. Refer to Figure 6 for the toggle bit algorithm, and to the Toggle Bit Timings figure in the “AC
Characteristics” section for the timing diagram. The DQ2 vs.
DQ6 figure shows the differences between DQ2 and DQ6 in
graphical form. See also the subsection on DQ2: Toggle Bit II.
DQ2: Toggle Bit II
The Toggle Bit II on DQ2, when used with DQ6, indicates
whether a particular sector is actively erasing (that is, the
Embedded Erase algorithm is in progress), or whether that
sector is erase-suspended. Toggle Bit II is valid after the
rising edge of the final WE# pulse in the command sequence.
DQ2 toggles when the system reads at addresses within
those sectors that were selected for erasure. (The system
may use either OE# or CE# to control the read cycles.) But
DQ2 cannot distinguish whether the sector is actively erasing
or is erase-suspended. DQ6, by comparison, indicates
whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for
erasure. Thus, both status bits are required for sector and
mode information. Refer to Table 6 on page 19 to compare
outputs for DQ2 and DQ6.
Figure 6, on page 19 shows the toggle bit algorithm in flowchart form, and the section DQ2: Toggle Bit II on page 18
18
S H E E T
explains the algorithm. See also the DQ6: Toggle Bit I on
page 18 subsection. Refer to the Toggle Bit Timings figure for
the toggle bit timing diagram. The DQ2 vs. DQ6 figure shows
the differences between DQ2 and DQ6 in graphical form.
Reading Toggle Bits DQ6/DQ2
Refer to Figure 6, on page 19 for the following discussion.
Whenever the system initially begins reading toggle bit
status, it must read DQ7–DQ0 at least twice in a row to determine whether a toggle bit is toggling. Typically, a system
would note and store the value of the toggle bit after the first
read. After the second read, the system would compare the
new value of the toggle bit with the first. If the toggle bit is not
toggling, the device completed the program or erase operation. The system can read array data on DQ7–DQ0 on the
following read cycle.
However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also
should note whether the value of DQ5 is high (see the section
on DQ5). If it is, the system should then determine again
whether the toggle bit is toggling, since the toggle bit may
have stopped toggling just as DQ5 went high. If the toggle bit
is no longer toggling, the device successfully completed the
program or erase operation. If it is still toggling, the device did
not complete the operation successfully, and the system must
write the reset command to return to reading array data.
The remaining scenario is that the system initially determines
that the toggle bit is toggling and DQ5 has not gone high. The
system may continue to monitor the toggle bit and DQ5
through successive read cycles, determining the status as
described in the previous paragraph. Alternatively, it may
choose to perform other system tasks. In this case, the
system must start at the beginning of the algorithm when it
returns to determine the status of the operation (top of Figure
6, on page 19).
DQ5: Exceeded Timing Limits
DQ5 indicates whether the program or erase time exceeded
a specified internal pulse count limit. Under these conditions
DQ5 produces a 1. This is a failure condition that indicates
the program or erase cycle was not successfully completed.
The DQ5 failure condition may appear if the system tries to
program a 1 to a location that is previously programmed to 0.
Only an erase operation can change a “0” back to a 1.
Under this condition, the device halts the operation, and
when the operation exceeds the timing limits, DQ5 produces
a 1.
Under both these conditions, the system must issue the reset
command to return the device to reading array data.
DQ3: Sector Erase Timer
After writing a sector erase command sequence, the system
may read DQ3 to determine whether or not an erase operation started. (The sector erase timer does not apply to the
chip erase command.) If additional sectors are selected for
erasure, the entire time-out also applies after each additional
sector erase command. When the time-out is complete, DQ3
switches from 0 to 1. The system may ignore DQ3 if the
system can guarantee that the time between additional sector
Am29F004B
Am29F004B_00_E4 May 9, 2006
D A T A
S H E E T
erase commands is always less than 50 μs. See also the
Sector Erase Command Sequence on page 14 section.
START
After the sector erase command sequence is written, the
system should read the status on DQ7 (Data# Polling) or DQ6
(Toggle Bit I) to ensure the device accepts the command
sequence, and then read DQ3. If DQ3 is 1, the internally controlled erase cycle started; all further commands (other than
Erase Suspend) are ignored until the erase operation is complete. If DQ3 is 0, the device accepts additional sector erase
commands. To ensure the command was accepted, the
system software should check the status of DQ3 prior to and
following each subsequent sector erase command. If DQ3 is
high on the second status check, the last command might not
have been accepted. Table 6 on page 19 shows the outputs
for DQ3.
Read DQ7–DQ0
(Note
1)
Read DQ7–DQ0
Toggle Bit
= Toggle?
No
Yes
No
DQ5 = 1?
Yes
Read DQ7–DQ0
Twice
Toggle Bit
= Toggle?
(Notes
1, 2)
No
Yes
Program/Erase
Operation Not
Complete, Write
Reset Command
Program/Erase
Operation Complete
Notes:
1. Read toggle bit twice to determine whether or not it is toggling.
See text.
2. Recheck toggle bit because it may stop toggling as DQ5
changes to 1. See text.
Figure 6. Toggle Bit Algorithm
Table 6.
DQ7
(Note 1)
DQ6
DQ5
(Note 2)
DQ3
DQ2
(Note 1)
DQ7#
Toggle
0
N/A
No toggle
0
Toggle
0
1
Toggle
1
No toggle
0
N/A
Toggle
Reading within Non-Erase Suspended
Sector
Data
Data
Data
Data
Data
Erase-Suspend-Program
DQ7#
Toggle
0
N/A
N/A
Operation
Standard
Mode
Erase
Suspend
Mode
Write Operation Status
Embedded Program Algorithm
Embedded Erase Algorithm
Reading within Erase
Suspended Sector
Notes:
1. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.
2. DQ5 switches to 1 when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits. See DQ5:
Exceeded Timing Limits on page 18 for more information.
May 9, 2006 Am29F004B_00_E4
Am29F004B
19
D A T A
S H E E T
ABSOLUTE MAXIMUM RATINGS
Storage Temperature
Plastic Packages . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Ambient Temperature
with Power Applied. . . . . . . . . . . . . . . . . . . –55°C to +125°C
Voltage with Respect to Ground
VCC (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . –2.0 V to +7.0 V
20 ns
20 ns
+0.8 V
–0.5 V
–2.0 V
A9, OE# (Note 2) . . . . . . . . . . . . . . . . . . . . –2.0 V to +12.5 V
20 ns
All other pins (Note 1) . . . . . . . . . . . . . . . . . –0.5 V to +7.0 V
Output Short Circuit Current (Note 3) . . . . . . . . . . . 200 mA
Figure 7. Maximum Negative Overshoot Waveform
Notes:
1. Minimum DC voltage on input or I/O pins is –0.5 V. During voltage
transitions, input or I/O pins may overshoot VSS to –2.0 V for
periods of up to 20 ns. See Figure 7, on page 20. Maximum DC
voltage on input or I/O pins is VCC +0.5 V. During voltage
transitions, input or I/O pins may overshoot to VCC +2.0 V for
periods up to 20 ns. See Figure 8, on page 20.
2. Minimum DC input voltage on pins A9 and OE# is –0.5 V. During
voltage transitions, A9 and OE# may overshoot VSS to –2.0 V for
periods of up to 20 ns. See Figure 7, on page 20. Maximum DC
input voltage on pin A9 is +12.5 V which may overshoot to +13.5
V for periods up to 20 ns.
3. No more than one output may be shorted to ground at a time.
Duration of the short circuit should not be greater than one
second.
Stresses above those listed under Absolute Maximum Ratings may
cause permanent damage to the device. This is a stress rating only;
functional operation of the device at these or any other conditions
above those indicated in the operational sections of this data sheet is
not implied. Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability.
20 ns
VCC
+2.0 V
VCC
+0.5 V
2.0 V
20 ns
20 ns
Figure 8. Maximum Positive Overshoot Waveform
OPERATING RANGES
Industrial (I) Devices
Ambient Temperature (TA) . . . . . . . . . . . . . . –40°C to +85°C
Extended (E) Devices
Ambient Temperature (TA) . . . . . . . . . . . . . –55°C to +125°C
VCC Supply Voltages
VCC for ± 5% devices . . . . . . . . . . . . . . . .+4.75 V to +5.25 V
VCC for ± 10% devices . . . . . . . . . . . . . . . . .+4.5 V to +5.5 V
Operating ranges define those limits between which the functionality of the device is guaranteed.
20
Am29F004B
Am29F004B_00_E4 May 9, 2006
D A T A
S H E E T
DC CHARACTERISTICS
TTL/NMOS Compatible
Parameter
Description
Test Conditions
Min
Typ
Max
Unit
±1.0
µA
50
µA
±1.0
µA
ILI
Input Load Current
VIN = VSS to VCC, VCC = VCC max
ILIT
A9, OE# Input Load Current
(Note 4)
VCC = VCC max;
A9, OE# = 12.5 V
ILO
Output Leakage Current
VOUT = VSS to VCC, VCC = VCC max
ICC1
VCC Active Read Current (Notes 1, 2)
CE# = VIL, OE# = VIH
20
30
mA
ICC2
VCC Active Write Current (Notes 1, 3, 4)
CE# = VIL, OE# = VIH
30
40
mA
ICC3
VCC Standby Current (Note 1)
CE#, OE# = VIH
0.4
1
mA
VIL
Input Low Voltage
–0.5
0.8
V
VIH
Input High Voltage
2.0
VCC
+ 0.5
V
VID
Voltage for Autoselect and Temporary Sector
VCC = 5.0 V
Unprotect
11.5
12.5
V
VOL
Output Low Voltage
IOL = 12 mA, VCC = VCC min
0.45
V
VOH
Output High Voltage
IOH = –2.5 mA, VCC = VCC min
VLKO
Low VCC Lock-Out Voltage
3.2
Notes:
1. Maximum ICC specifications are tested with VCC = VCCmax.
2. The ICC current listed is typically less than 2 mA/MHz, with OE#
at VIH.
May 9, 2006 Am29F004B_00_E4
2.4
V
4.2
V
3. ICC active while Embedded Erase or Embedded Program is in
progress.
4. Not 100% tested.
Am29F004B
21
D A T A
S H E E T
DC CHARACTERISTICS
CMOS Compatible
Parameter
Description
Test Conditions
Min
Typ
Max
Unit
ILI
Input Load Current
VIN = VSS to VCC,
VCC = VCC max
±1.0
µA
ILIT
A9, OE#, Input Load Current (Note
4)
VCC = VCC max;
A9, OE# = 12.5 V
50
µA
ILO
Output Leakage Current
VOUT = VSS to VCC,
VCC = VCC max
±1.0
µA
ICC1
VCC Active Read Current
(Notes 1, 2)
CE# = VIL, OE# = VIH
20
30
mA
ICC2
VCC Active Write Current
(Notes 1, 3, 4)
CE# = VIL, OE# = VIH
30
40
mA
ICC3
VCC Standby Current
(Notes 1, 5)
CE# = VCC ± 0.5 V
0.3
5
µA
VIL
Input Low Voltage
–0.5
0.8
V
VIH
Input High Voltage
0.7 x VCC
VCC + 0.3
V
VID
Voltage for Autoselect and
Temporary Sector Unprotect
VCC = 5.0 V
11.5
12.5
V
VOL
Output Low Voltage
IOL = 12 mA, VCC = VCC min
0.45
V
VOH1
Output High Voltage
VOH2
VLKO
IOH = –2.5 mA, VCC = VCC min
0.85 VCC
IOH = –100 µA, VCC = VCC min
VCC–0.4
Low VCC Lock-Out Voltage
3.2
Notes:
1. Maximum ICC specifications are tested with VCC = VCCmax.
2. The ICC current listed is typically less than 2 mA/MHz, with OE#
at VIH.
V
4.2
V
3. ICC active while Embedded Erase or Embedded Program is in
progress.
4. Not 100% tested.
5. ICC3 = 20 µA max at extended temperature (>+85° C).
22
Am29F004B
Am29F004B_00_E4 May 9, 2006
D A T A
S H E E T
TEST CONDITIONS
Table 7. Test Specifications
5.0 V
Test Condition
2.7 kΩ
Device
Under
Test
CL
6.2 kΩ
Note: Diodes are IN3064 or equivalent
Figure 9.
70, 90
Output Load
Unit
1 TTL gate
Output Load Capacitance, CL
(including jig capacitance)
100
pF
Input Rise and Fall Times
20
ns
Input Pulse Levels
0.45–2.4
V
Input timing measurement
reference levels
0.8, 2.0
V
Output timing measurement
reference levels
0.8, 2.0
V
Test Setup
KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
OUTPUTS
Steady
Changing from H to L
Changing from L to H
May 9, 2006 Am29F004B_00_E4
Don’t Care, Any Change Permitted
Changing, State Unknown
Does Not Apply
Center Line is High Impedance State (High Z)
Am29F004B
23
D A T A
S H E E T
AC CHARACTERISTICS
Read Operations
Parameter
Speed Options
JEDEC
Std
Description
tAVAV
tRC
Read Cycle Time (Note 1)
tAVQV
tACC
Address to Output Delay
tELQV
tCE
Chip Enable to Output Delay
tGLQV
tOE
tEHQZ
tGHQZ
tAXQX
Test Setup
-70
-90
Unit
Min
70
90
ns
CE# = VIL
OE# = VIL
Max
70
90
ns
OE# = VIL
Max
70
90
ns
Output Enable to Output Delay
Max
30
35
ns
tDF
Chip Enable to Output High Z (Note 1)
Max
20
20
ns
tDF
Output Enable to Output High Z
(Note 1)
Max
20
20
ns
Read
Min
0
ns
Toggle and
Data# Polling
Min
10
ns
Min
0
ns
tOEH
Output Enable
Hold Time
(Note 1)
tOH
Output Hold Time From Addresses, CE# or OE#,
Whichever Occurs First (Note 1)
Notes:
1. Not 100% tested.
2. See Table 7 and Figure 9, on page 23 for test specifications.
tRC
Addresses Stable
Addresses
tACC
CE#
tDF
tOE
OE#
tOEH
WE#
tCE
tOH
HIGH Z
HIGH Z
Output Valid
Outputs
Figure 10. Read Operations Timings
24
Am29F004B
Am29F004B_00_E4 May 9, 2006
D A T A
S H E E T
AC CHARACTERISTICS
Erase/Program Operations
Parameter
Speed Options
JEDEC
Std
Description
-70
-90
Unit
tAVAV
tWC
Write Cycle Time (Note 1)
Min
70
90
ns
tAVWL
tAS
Address Setup Time
Min
tWLAX
tAH
Address Hold Time
Min
45
45
ns
tDVWH
tDS
Data Setup Time
Min
30
45
ns
tWHDX
tDH
Data Hold Time
Min
0
ns
tOES
Output Enable Setup Time
Min
0
ns
Read Recovery Time Before Write
(OE# High to WE# Low)
Min
0
ns
0
ns
tGHWL
tGHWL
tELWL
tCS
CE# Setup Time
Min
0
ns
tWHEH
tCH
CE# Hold Time
Min
0
ns
tWLWH
tWP
Write Pulse Width
Min
tWHWL
tWPH
Write Pulse Width High
Min
20
ns
tWHWH1
tWHWH1
Programming Operation (Note 2)
Typ
7
µs
tWHWH2
tWHWH2
Sector Erase Operation (Note 2)
Typ
1
sec
VCC Setup Time (Note 1)
Min
50
µs
tVCS
35
45
ns
Notes:
1. Not 100% tested.
2. See Erase and Programming Performance on page 32 for more
information.
May 9, 2006 Am29F004B_00_E4
Am29F004B
25
D A T A
S H E E T
AC CHARACTERISTICS
Program Command Sequence (last two cycles)
tAS
tWC
Addresses
Read Status Data (last two cycles)
555h
PA
PA
PA
tAH
CE#
tCH
OE#
tWHWH1
tWP
WE#
tWPH
tCS
tDS
tDH
PD
A0h
Data
Status
DOUT
VCC
tVCS
Notes:
1. PA = program address, PD = program data, DOUT is the true data
at the program address.
Figure 11. Program Operation Timings
Erase Command Sequence (last two cycles)
tAS
tWC
2AAh
Addresses
Read Status Data
VA
SA
VA
555h for chip erase
tAH
CE#
tCH
OE#
tWP
WE#
tWPH
tCS
tWHWH2
tDS
tDH
Data
55h
30h
In
Progress
Complete
10 for Chip Erase
tVCS
VCC
Notes:
1. SA = sector address (for Sector Erase), VA = Valid Address for
reading status data (”see Write Operation Status on page 17).
Figure 12. Chip/Sector Erase Operation Timings
26
Am29F004B
Am29F004B_00_E4 May 9, 2006
D A T A
S H E E T
AC CHARACTERISTICS
tRC
Addresses
VA
VA
VA
tACC
tCE
CE#
tCH
tOE
OE#
tOEH
tDF
WE#
tOH
High Z
DQ7
Complement
Complement
DQ0–DQ6
Status Data
Status Data
Valid Data
True
High Z
Valid Data
True
Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle.
Figure 13. Data# Polling Timings (During Embedded Algorithms)
tRC
Addresses
VA
VA
VA
VA
tACC
tCE
CE#
tCH
tOE
OE#
tOEH
tDF
WE#
tOH
DQ6/DQ2
High Z
Valid Status
Valid Status
(first read)
(second read)
Valid Status
Valid Data
(stops toggling)
Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read cycle, and
array data read cycle.
Figure 14. Toggle Bit Timings (During Embedded Algorithms)
Enter
Embedded
Erasing
WE#
Erase
Suspend
Erase
Enter Erase
Suspend Program
Erase Suspend
Read
Erase
Suspend
Program
Erase
Resume
Erase Suspend
Read
Erase
Erase
Complete
DQ6
DQ2
Note: The system may use CE# or OE# to toggle DQ2 and DQ6. DQ2 toggles only when read at an address within an erase-suspended sector.
Figure 15. DQ2 vs. DQ6
May 9, 2006 Am29F004B_00_E4
Am29F004B
27
D A T A
S H E E T
AC CHARACTERISTICS
Parameter
JEDEC
Std.
Description
tVIDR
VID Rise and Fall Time (Not 100% tested)
All Speed Options
Unit
500
ns
Min
VID
OE#
VSS, VIL
or VIH
tVIDR
A18 – A0
D7 – D0
555h
2AAh
555h
AAh
55h
20h/24h
CE#
WE#
Device is ready to read from array.
Figure 16.
If 20h is written, Sector Unprotect mode
is enabled. If 24h is written, command mode
Sector Protect/Unprotect is enabled.
Sector Unlock Sequence Timing Diagram
VID
OE# VSS, VIL
or VIH
0 V or 5 V
tVIDR
A18 – A0
D7 – D0
tVIDR
XXXh
XXXh
90h
F0h or 00h
CE#
WE#
Device is in either Temporary Sector Unprotect
mode or command mode Sector Protect/Unprotect.
Figure 17.
28
Device exits Temporary Sector Unprotect mode
or command mode Sector Protect/Unprotect.
Returns to reading array data.
Sector Relock Timing Diagram
Am29F004B
Am29F004B_00_E4 May 9, 2006
D A T A
S H E E T
AC CHARACTERISTICS
VID
VIH
OE#
VSS
A18 – A0
D7 – D0
XXXh
Valid (Note 2)
Valid (Note 2)
60h
60h
40h
Array Data
CE#
WE#
Sector Unlock sequence (three cycles)
Sector Relock sequence (two cycles)
Notes:
1. To enable the command mode sector protection/unprotection
algorithm, the system must issue the command 24h in the sector
unlock sequence.
unprotection, a valid address consists of the sector address with
A6 = 1, A5 = 1, A1 = 1, A0 = 0.
2. For sector protection, a valid address consists of the sector
address with A6 = 0, A5 = 1, A1 = 1, A0 = 0. For sector
Figure 18. Sector Protect/Unprotect Timing Diagram
May 9, 2006 Am29F004B_00_E4
Am29F004B
29
D A T A
S H E E T
AC CHARACTERISTICS
Alternate CE# Controlled Erase/Program Operations
Parameter
Speed Options
JEDEC
Std.
Description
-70
-90
Unit
tAVAV
tWC
Write Cycle Time (Note 1)
Min
70
90
ns
tAVEL
tAS
Address Setup Time
Min
tELAX
tAH
Address Hold Time
Min
45
45
ns
tDVEH
tDS
Data Setup Time
Min
30
45
ns
tEHDX
tDH
Data Hold Time
Min
0
ns
tOES
Output Enable Setup Time
Min
0
ns
tGHEL
tGHEL
Read Recovery Time Before Write
(OE# High to WE# Low)
Min
0
ns
tWLEL
tWS
WE# Setup Time
Min
0
ns
tEHWH
tWH
WE# Hold Time
Min
0
ns
tELEH
tCP
CE# Pulse Width
Min
tEHEL
tCPH
CE# Pulse Width High
Min
20
ns
tWHWH1
tWHWH1
Programming Operation (Note 2)
Typ
7
µs
tWHWH2
tWHWH2
Sector Erase Operation (Note 2)
Typ
1
sec
0
35
ns
45
ns
1. Not 100% tested.
2. See Erase and Programming Performance on page 32 for more
information.
30
Am29F004B
Am29F004B_00_E4 May 9, 2006
D A T A
S H E E T
AC CHARACTERISTICS
555 for program
2AA for erase
PA for program
SA for sector erase
555 for chip erase
Data# Polling
Addresses
PA
tWC
tAS
tAH
tWH
WE#
tGHEL
OE#
tWHWH1 or 2
tCP
CE#
tWS
tCPH
tDS
tDH
DQ7#
Data
A0 for program
55 for erase
DOUT
PD for program
30 for sector erase
10 for chip erase
Notes:
1. PA = Program Address, PD = Program Data, DQ7# = complement of data written to device, DOUT = data written to device.
2. Figure indicates the last two bus cycles of the command sequence.
Figure 19. Alternate CE# Controlled Write Operation Timings
May 9, 2006 Am29F004B_00_E4
Am29F004B
31
D A T A
S H E E T
ERASE AND PROGRAMMING PERFORMANCE
Parameter
Typ (Note 1)
Max (Note 2)
Unit
Comments
Sector Erase Time
1
8
s
Chip Erase Time
8
Excludes 00h programming prior to
erasure (Note 4)
Byte Programming Time
7
300
µs
3.6
10.8
s
Chip Programming Time (Note 3)
s
Excludes system level overhead
(Note 5)
Notes:
1. Typical program and erase times assume the following conditions: 25°C, 5.0 V VCC, 1,000,000 cycles. Additionally, programming typicals
assume checkerboard pattern.
2. Under worst case conditions of 90°C, VCC = 4.5 V (4.75 V for ±5% devices), 1,000,000 cycles.
3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes program faster
than the maximum program times listed.
4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the four-bus-cycle sequence for the program command. See Table for further
information on command definitions.
6. The device has a minimum guaranteed erase and program cycle endurance of 1,000,000 cycles.
LATCHUP CHARACTERISTICS
Description
Min
Max
Input voltage with respect to VSS on all pins except I/O pins
(including A9 and OE#)
–1.0 V
12.5 V
Input voltage with respect to VSS on all I/O pins
–1.0 V
VCC + 1.0 V
–100 mA
+100 mA
VCC Current
Note: Includes all pins except VCC. Test conditions: VCC = 5.0 V, one pin at a time.
PLCC PIN CAPACITANCE
Parameter
Symbol
CIN
Parameter Description
Test Conditions
Typ
Max
Unit
Input Capacitance
VIN = 0
4
6
pF
COUT
Output Capacitance
VOUT = 0
8
12
pF
CIN2
Control Pin Capacitance
VPP = 0
8
12
pF
Notes:
1. Sampled, not 100% tested.
2. Test conditions TA = 25°C, f = 1.0 MHz.
DATA RETENTION
Parameter
Test Conditions
Min
Unit
150°C
10
Years
125°C
20
Years
Minimum Pattern Data Retention Time
32
Am29F004B
Am29F004B_00_E4 May 9, 2006
D A T A
S H E E T
PHYSICAL DIMENSIONS
PL 032—32-Pin Plastic Leaded Chip Carrier
Dwg rev AH; 10/99
May 9, 2006 Am29F004B_00_E4
Am29F004B
33
D A T A
REVISION SUMMARY
S H E E T
sector protect or unprotect algorithm requires an access time
of 1 µs.
Revision A (January 1999)
Revision C (November 12, 1999)
Initial release.
AC Characteristics—Figure 11, Program
Operations Timing and Figure 12, Chip/Sector
Erase Operations
Revision B (March 10, 1999)
Global
Deleted tGHWL and changed OE# waveform to start at high.
Revised document into full data sheet.
Physical Dimensions
Revision B+1 (March 18, 1999)
Replaced figures with more detailed illustrations.
In-System Sector Protect/Sector Unprotect
Algorithms figure
Revision D (February 22, 2000)
Added requirements for asserting address A5 and setting
OE# to VIH during both algorithms.
Command Definitions table
Added A5 requirement to definition for SA+ in the legend. In
the fourth cycle of the Sector Relock sequence, changed
address from XXX to SA+.
Global
The “preliminary” designation was removed from the document. Parameters are now stable, and only speed, package,
and temperature range combinations are expected to change
in future data sheet revisions.
Revision E (November 29, 2000)
Sector Protect/Unprotect Timing Diagram
Added table of contents.
Modified drawing to indicate that OE# should be dropped to
VIH during the third cycle.
Ordering Information
Revision B+2 (May 14, 1999)
Table , Command Definitions
Ordering Information
Changed the temperature range in the example to I.
In Note 4, corrected lower address bit of don’t care range to
A11.
Device Bus Operation table
Revision E+1 (March 28, 2005)
Corrected the highest bit in the address range column header
to A18.
Global
Deleted burn-in option.
Added Colophon
Command Definitions table
In Note 4, changed the address range for bits that are don’t
care to A18–A12.
Updated Trademark
Ordering Information
Added Pb-free temperature ranges for Industrial and
Extended packaging
DC Characteristics table
In Note 5, deleted reference to ICC4.
Added Valid Combination Codes
Read Operations Timings and Alternate CE#
Controlled Write Operations figures
Revision E+2 (July 26, 2005)
Deleted RESET# waveform.
Global
Revision B+3 (July 12, 1999)
Removed all 55 ns information from the Datasheet.
Global
Revision E+3 (December 23, 2005)
Deleted all references to the PDIP package. Changed data
sheet status to Preliminary.
Global
In-System Sector Protect/Unprotect Algorithms
figure
Added tolerance specifications to the 150 µs and 15 ms waits.
Clarified that reading from the sector address during either
34
Eliminated 120 speed option from entire document.
Revision E4 (May 9, 2006)
Added “Not recommended for new designs” note.
Am29F004B
Am29F004B_00_E4 May 9, 2006
D A T A
S H E E T
Colophon
The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the
public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility,
aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for
any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion LLC will not be liable
to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor
devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design
measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating
conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign
Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior authorization by the respective government entity will be required for export of those products.
Trademarks
Copyright © 2000-2006 Advanced Micro Devices, Inc. All rights reserved.
AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc.
ExpressFlash is a trademark of Advanced Micro Devices, Inc.
Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
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