CXL1517N/1518N CMOS-CCD Signal Processor Description The CXL1517N/1518N are CMOS-CCD signal processors developed for CCD camera complementary color filter array processing system. CXL1517N 452.5-bit × 2, 453.5-bit 1H CCD delay line CXL1518N 300.5-bit × 2, 301.5-bit 1H CCD delay line Features • Single 5V power supply • Low power consumption (Typ.) CXL1517N 120mW CXL1518N 75mW • Built-in peripheral circuits • Built-in CDS (Correlated Double Sampling) circuit 24 pin SSOP (Plastic) Structure CMOS-CCD Functions • Clock driver • Autobias circuit (Center and black) • Pedestal clamp circuit • CDS circuit • Overflow prevention circuit Absolute Maximum Ratings (Ta = 25°C) • Supply voltage VDD 6 • Operating temperature Topr –10 to +65 • Storage temperature Tstg –55 to +150 • Allowable power dissipation PD 350 V °C °C mW (SSOP package) Recommended Operating Voltage Range (Ta = 25°C) Supply voltage VDD 4.6 to 5.25 Item Symbol Min. V Typ. Max. Unit Clock voltage Low VL VSS 0.3 × VDD V Clock voltage High VH 0.7 × VDD VDD V Clock frequency Remarks CXL1517N fCL 7.16 MHz NTSC: 455fH CCIR: 454fH CXL1518N fCL 4.77 MHz NTSC: 910fH/3 CCIR: 908fH/3 Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E91778A78-PS CXL1517N/1518N XDL1 XDL2 VDD VDD VDD VSS VSS VSS VSS Block Diagram and Pin Configuration (Top View) 19 18 5 8 20 1 2 16 17 TIMING GENERATOR ABBL 4 A.B. BLACK ABCN 21 A.B. CENTER DRIVER PRECHARGE DRAIN PG. GEN. IN-A 23 (n bit) CLP DL A CDS OUTPUT CIRCUIT 14 OUT-A CDS OUTPUT CIRCUIT 11 OUT-B CDS OUTPUT CIRCUIT 9 OUT-C PG. GEN. IN-B 3 (n bit) CLP DL B PG. GEN. C OVERFLOW PREVENTION CIRCUIT 7 22 POTENTIAL CONTROL ABOVF CLP PULSE GEN. VSS 1 24 NC VSS 2 23 IN-A IN-B 3 22 ABOVF ABBL 4 21 ABCN VDD 5 20 VDD IN-C 6 19 XDL1 CLP 7 18 XDL2 VDD 8 17 VSS OUT-C 9 16 VSS 15 CDS VGG 10 14 OUT-A OUT-B 11 13 NC NC 12 –2– CDS 10 15 CDS DL VGG CLP CLP IN-C 6 (n + 1 bit) CXL1517N/1518N Pin Description Pin No. Symbol I/O Description Comment 1 VSS — 2 VSS — 3 IN-B I Signal input B channel (Y) 4 ABBL O Autobias DC output for Y signal Black level bias 5 VDD — Power supply Analog 6 IN-C I Signal input C channel (Y) Black level bias at no clamp > 100k 7 CLP I Clamp pulse input > 100k 8 VDD — Power supply Output circuit 9 OUT-C O Signal output C channel 10 VGG O Output circuit bias DC output 11 OUT-B O Signal output B channel 12 NC — — 13 NC — — 14 OUT-A O Signal output A channel 15 CDS O DC output for CDS 16 VSS — GND Output circuit 17 VSS — GND Timing 18 XDL2 I Clock pulse input 2 > 100k 19 XDL1 I Clock pulse input 1 > 100k 20 VDD — Power supply Timing 21 ABCN O Autobias DC output for C signal 22 ABOVF O Autobias DC output for overflow prevention circuit 23 IN-A I Signal input A channel (C) 24 NC — GND Analog — –3– Center level bias at no clamp > 100k ABBL ABOVF CDS VGG IDD Autobias black level Overflow prevention circuit Autobias level CDS source level Output circuit bias level Current ∗ supply –4– b b a to c a ↑ ↓ b a ∗ Standard values are different between CXL1517N and CXL1518N. Cross-talk between channels CRT Bch ∆LBC → Cch V6 b a a A → V1 B, C → V2 + 0.25V ↓ A → V1 B, C → V2 + 0.25V 20 log Output amplitude (mVp-p) Input amplitude (SIN 100kHz, 100mVp-p) 15 –4.5 –3.5 — 24 0.8 2.3 3.0 4.3 Note 4) 0 0 0 0 1 1 5 5 Output amplitude (SIN 1MHz, 100mVp-p) –1.5 –0.4 Output amplitude (SIN 100kHz, 100mVp-p) –1.8 –0.8 Note 1) 20 log 0.3 a — 1.2 a a 2.6 a 3.9 a 4.6 3 5 12 12 — — — 25 35 3.0 3.5 3.3 4.5 4.8 Min. Typ. Max. 4.2 V1 Conditions Ratings % % % % dB dB mA V V V V V Unit fCL = 7.16MHz (CXL1517N) fCL = 4.77MHz (CXL1518N) a Note 3) b b b ↑ ↓ c a to c a to c a to c a a a a a a Linearity difference between channels V6 b a a a b b b b b a a a a a E1 Bias conditions Note 2) Lin. V6 V6 A1 V5 V4 V3 V2 V1 SW4 SW1 SW2 SW3 to 6 SW conditions Ta = 25°C, VDD = 5.0V, VSS = 0V The insertion gain difference ∆G between channels Linearity fG Frequency ∗ response CXL1518N IG Insertion gain CXL1517N CXL1518N CXL1517N ABCN Test Symbol point Autobias center level Item Electrical Characteristics CXL1517N/1518N CXL1517N/1518N Notes) 1) Linearity testing For A channel, set input bias to ABCN – 0.2V first, and then set it to ABCN and ABCN + 0.2V. Then input a sine wave of 100kHz and 100mVp-p, and compare the three output amplitudes. For B channel and C channel, set input bias to ABBL + 0.45V first, and then set it to ABBL + 0.25V and ABBL + 0.05V. Then input a sine wave of 100kHz and 100mVp-p, and compare the three output amplitudes. The maximum output amplitude for the respective A, B and C channels is taken as Sout max and the minimum output amplitude as Sout min. The linearity of the respective channels is defined as: Lin. = Sout max – Sout min × 200 [%] Sout max + Sout min 2) Calculation of insertion gain difference As the maximum insertion gain among A, B and C channels is taken as Gmax and the minimum as Gmin, the insertion gain difference between channels ∆G as: ∆G = | 1 – 10 ( Gmax20– Gmin ) | × 100 [%] 3) Calculation of linearity difference Define B channel linearity as LB and C channel linearily as LC we obtain the difference ∆LBC as: ∆LBC = | LB – LC | [%] 4) Cross-talk calculation CRTa : The cross-talk value of A channel when B and C channels are input : The output value of A channel when A channel is input OUTA-a SW3-a, SW4-a, SW5, 6-b OUTA-bc : The output value of A channel when B and C channels are input (Cross-talk component) SW3-a, SW4-b, SW5, 6-a CRTa = OUTA-bc OUTA-a × 100 [%] Clock Waveform Timing (140) ∗ 210ns (52.5) ∗ 87.5ns 10ns XDL1 10ns 90% 90% 50% 50% 10% 10% 17.5ns (52.5) ∗ 87.5ns 10ns XDL2 10ns 90% 90% 50% 50% 10% 10% –5– ∗ The value in brackets is for CXL1517N. CXL1517N/1518N Electrical Characteristics Test Circuit a b a 100kHz, 100mVp-p sine wave c SW1 a No signal (GND) b 1MHz, 100mVp-p sine wave a b b SW6 SW5 SW4 V3 V1 V4 1µ 1µ 16V 16V VDD 1µ 16V XDL XDL 1 2 3.3k (NC) (NC) 23 24 21 22 19 20 18 17 13 14 15 16 a b 4 3 2 5 6 9 8 7 10 1µ 16V 1µ 16V L.P.F 3.3k 12 11 ×1 c VDD 1 SW3 (NC) ×1 V5 V6 VDD 3.3k V2 10k 10k 10k SW2 A1 VDD E1 a b Application Circuit XDL XDL VDD 1 2 4.7µ 16V Input A 0.1µ 16V 1µ 1µ 16V 16V (NC) 24 23 22 VDD 20 Output A (NC) 100p 21 3.3k 1µ 16V 19 18 17 16 15 14 13 VDD 1 4 3 2 1µ 16V 0.1µ 16V Input B 5 100p 6 7 8 9 10 11 100p 3.3k 12 Output B (NC) 1µ 16V 0.1µ 4.7µ 16V 4.7µ 16V 16V VDD Input CLP VDD C input VDD 3.3k Output C Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. –6– CXL1517N/1518N Package Outline Unit: mm 24PIN SSOP(PLASTIC) + 0.2 1.25 – 0.1 ∗7.8 ± 0.1 24 0.1 13 ∗5.6 ± 0.1 7.6 ± 0.2 A 1 + 0.1 0.22 – 0.05 12 + 0.05 0.15 – 0.02 0.13 M 0.65 0.5 ± 0.2 0.1 ± 0.1 0° to 10° NOTE: Dimensions “∗” does not include mold protrusion. DETAIL A PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN SONY CODE SSOP-24P-L01 LEAD TREATMENT SOLDER/PALLADIUM PLATING EIAJ CODE SSOP024-P-0056 LEAD MATERIAL 42/COPPER ALLOY PACKAGE MASS 0.1g JEDEC CODE –7–