19-2530; Rev 2; 8/03 µP Reset Circuits with Capacitor-Adjustable Reset/Watchdog Timeout Delay Features ♦ Factory-Set Reset Threshold Options from 1.575V to 5V in ~100mV Increments The MAX6746–MAX6753 are available with a push-pull or open-drain active-low RESET output. The MAX6746– MAX6753 are available in an 8-pin SOT23 package and are fully specified over the automotive temperature range (-40°C to +125°C). Intelligent Instruments Portable Equipment ♦ Min/Max (Windowed) Watchdog Option ♦ Manual Reset Input Option ♦ Guaranteed RESET Valid for VCC ≥ 1V ♦ 3.7µA Supply Current ♦ Push-Pull or Open-Drain RESET Output Options ♦ Power-Supply Transient Immunity ♦ Small 8-Pin SOT23 Packages Ordering Information PART TEMP RANGE PIN-PACKAGE MAX6747KA_ _-T -40°C to +125°C 8 SOT23-8 MAX6748KA-T -40°C to +125°C 8 SOT23-8 MAX6749KA-T -40°C to +125°C 8 SOT23-8 Embedded Controllers MAX6750KA_ _-T -40°C to +125°C 8 SOT23-8 Critical µP Monitoring Set-Top Boxes Computers MAX6751KA_ _-T -40°C to +125°C 8 SOT23-8 MAX6752KA_ _-T -40°C to +125°C 8 SOT23-8 MAX6753KA_ _-T -40°C to +125°C 8 SOT23-8 TOP VIEW RESET IN (MR) 1 2 3 ♦ Capacitor-Adjustable Watchdog Timeout 8 SOT23-8 Pin Configurations SRT ♦ Capacitor-Adjustable Reset Timeout -40°C to +125°C Battery-Powered Computers/Controllers SWT ♦ Single/Dual Voltage Monitoring MAX6746KA_ _-T Applications Medical Equipment Automotive ♦ Adjustable Reset Threshold Options MAX6746– MAX6751 GND 4 8 VCC 7 RESET 6 WDI 5 WDS SOT23-8 Note: “_ _” represents the two number suffix needed when ordering the reset threshold voltage value for the MAX6746/MAX6747 and MAX6750–MAX6753. The reset threshold voltages are available in approximately 100mV increments. Table 2 contains the suffix and reset factory-trimmed voltages. All devices are available in tape-and-reel only. There is a 2500-piece minimum order increment for standard versions (see Table 3). Sample stock is typically held on standard versions only. Nonstandard versions require a minimum order increment of 10,000 pieces. Contact factory for availability. Selector Guide appears at end of data sheet. Typical Operating Circuit appears at end of data sheet. ( ) ARE FOR MAX6746 AND MAX6747 ONLY. Pin Configurations continued at end of data sheet. ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX6746–MAX6753 General Description The MAX6746–MAX6753 low-power microprocessor (µP) supervisory circuits monitor single/dual system supply voltages from 1.575V to 5V and provide maximum adjustability for reset and watchdog functions. These devices assert a reset signal whenever the VCC supply voltage or RESET IN falls below its reset threshold or when manual reset is pulled low. The reset output remains asserted for the reset timeout period after VCC and RESET IN rise above the reset threshold. The reset function features immunity to power-supply transients. The MAX6746–MAX6753 have ±2% factory-trimmed reset threshold voltages in approximately 100mV increments from 1.575V to 5.0V and/or adjustable reset threshold voltages using external resistors. The reset and watchdog delays are adjustable with external capacitors. The MAX6746–MAX6751 contain a watchdog select input that extends the watchdog timeout period by 128x. The MAX6752/MAX6753 contain a window watchdog timer that looks for activity outside an expected window of operation. MAX6746–MAX6753 µP Reset Circuits with Capacitor-Adjustable Reset/Watchdog Timeout Delay ABSOLUTE MAXIMUM RATINGS VCC to GND ...........................................................-0.3V to +6.0V SRT, SWT, SET0, SET1, RESET IN, WDS, MR, WDI, to GND .......................................…-0.3V to (VCC + 0.3V) RESET (Push-Pull) to GND......................…-0.3V to (VCC + 0.3V) RESET (Open Drain) to GND .............................…-0.3V to +6.0V Input Current (All Pins) .....................................................±20mA Output Current (RESET) ...................................................±20mA Continuous Power Dissipation (TA = +70°C) 8-Pin SOT23 (derate 8.9mW/°C above +70°C)............714mW Operating Temperature Range .........................-40°C to +125°C Storage Temperature Range ............................-65°C to +150°C Junction Temperature ......................................................+150°C Lead Temperature (soldering, 10s) .................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VCC = +1.2V to +5.5V, TA = TMIN to TMAX, unless otherwise specified. Typical values are at VCC = +5V and TA = +25°C.) (Note 1) PARAMETER SYMBOL Supply Voltage VCC Supply Current ICC VCC Reset Threshold Hysteresis VTH tRP IRAMP SRT Ramp Threshold VRAMP Normal Watchdog Timeout Period (MAX6746–MAX6751) tWD Extended Watchdog Timeout (MAX6746–MAX6751) tWD Slow Watchdog Period (MAX6752/MAX6753) tWD2 Fast Watchdog Timeout Period, SET Ratio = 8, (MAX6752/MAX6753) tWD1 Fast Watchdog Timeout Period, SET Ratio = 16, (MAX6752/MAX6753) tWD1 TYP MAX TA = 0°C to +125°C 1.0 5.5 TA = -40°C to 0°C 1.2 5.5 VCC ≤ 5.5V 5 10 VCC ≤ 3.3V 4.2 9 VCC ≤ 2.0V 3.7 8 See VTH selection table TA = -40°C to+125°C VTH 2% VCC falling from VTH + 100mV to VTH 100mV at 1mV/µs SRT Ramp Current 2 MIN VHYST VCC to Reset Delay Reset Timeout Period CONDITIONS CSRT = 1500pF 5.692 CSRT = 100pF VSRT = 0 to 1.23V; VCC = 1.6V to 5V VTH + 2% µs 7.590 9.487 250 nA V 1.173 1.235 1.297 7.590 9.487 0.506 728.6 CSWT = 1500pF 1214.4 64.77 728.6 CSWT = 100pF CSWT = 1500pF 971.5 971.5 1214.4 64.77 91.08 121.43 ms 300 5.692 CSWT = 100pF V 20 VCC = 1.6V to 5V (VRAMP rising) CSWT = 1500pF µA % CSWT = 1500pF CSWT = 100pF V 0.8 0.506 200 UNITS ms ms ms 151.80 ms CSWT = 100pF CSWT = 1500pF 8.09 45.53 60.71 75.89 ms CSWT = 100pF 4.05 _______________________________________________________________________________________ µP Reset Circuits with Capacitor-Adjustable Reset/Watchdog Timeout Delay MAX6746–MAX6753 ELECTRICAL CHARACTERISTICS (continued) (VCC = +1.2V to +5.5V, TA = TMIN to TMAX, unless otherwise specified. Typical values are at VCC = +5V and TA = +25°C.) (Note 1) PARAMETER Fast Watchdog Timeout Period, SET Ratio = 64, (MAX6752/MAX6753) SYMBOL CONDITIONS CSWT = 1500pF TYP MAX 11.38 15.18 18.98 tWD1 1.01 2000 SWT Ramp Current IRAMP VSWT = 0 to 1.23V, VCC = 1.6V to 5V SWT Ramp Threshold VRAMP VCC = 1.6V to 5V (VRAMP rising) RESET Output Voltage LOW Open-Drain, Push-Pull (Asserted) VOL RESET Output Voltage HIGH, Push-Pull (Not Asserted) VOH ILKG UNITS ms CSWT = 100pF Fast Watchdog Minimum Period (MAX6752/MAX6753) RESET Output Leakage Current, Open Drain MIN ns 200 250 300 nA 1.173 1.235 1.297 V VCC ≥ 1.0V, ISINK = 50µA 0.3 VCC ≥ 2.7V, ISINK = 1.2mA 0.3 VCC ≥ 4.5V, ISINK = 3.2mA 0.4 VCC ≥ 1.8V, ISOURCE = 200µA 0.8 x VCC VCC ≥ 2.25V, ISOURCE = 500µA 0.8 x VCC VCC ≥ 4.5V, ISOURCE = 800µA 0.8 x VCC V V VCC > VTH, reset not asserted, V RESET = 5.5V 1.0 µA DIGITAL INPUTS (MR, SET0, SET1, WDI, WDS) VIL VIH Input Logic Levels VIL 0.8 VCC ≥ 4.0V 2.4 VCC < 4.0V 0.3 x VCC VIH 0.7 x VCC MR Minimum Pulse Width 1 µs MR Glitch Rejection 100 MR to RESET Delay 200 MR Pullup Resistance V Pullup to VCC 12 WDI Minimum Pulse Width 20 ns ns 28 300 kΩ ns RESET IN RESET IN Threshold VRESET IN RESET IN Leakage Current IRESET IN RESET IN to RESET Delay TA = -40°C to +125°C 1.216 1.235 1.254 V -50 ±1 +50 nA RESET IN falling at 1mV/µs 20 µs Note 1: Production testing done at TA = +25°C. Over temperature limits are guaranteed by design. _______________________________________________________________________________________ 3 Typical Operating Characteristics (VCC = +5V, TA = +25°C, unless otherwise noted.) 1 1000 100 NORMAL MODE 10,000 1000 10,000 NORMALIZED RESET TIMEOUT PERIOD vs. TEMPERATURE NORMALIZED WATCHDOG TIMEOUT PERIOD vs. TEMPERATURE CSRT = 100pF 1.05 CSRT = 1500pF 0.95 0.90 -50 -25 0 25 50 75 100 MAX6746 toc05 1.15 125 1.10 1.05 CSWT = 100pF 1.00 CSWT = 1500pF 0.95 0.90 50 75 100 VCC = 1.8V VCC = 3.3V 2 1 1.008 0 25 50 75 TEMPERATURE (°C) 100 125 200 400 600 800 1000 RESET THRESHOLD OVERDRIVE (mV) VCC = 5V 1.006 1.004 1.002 1.000 0.998 0.996 RESET IN THRESHOLD vs. SUPPLY VOLTAGE 1.240 0.994 1.239 1.238 1.237 1.236 0.992 0.990 0 -25 VTH = 2.92V 0 125 RESET IN THRESHOLD (V) 4 1.010 NORMALIZED RESET THRESHOLD VOLTAGE MAX6746 toc07 VCC = 5V -50 50 NORMALIZED RESET IN THRESHOLD VOLTAGE vs. TEMPERATURE 6 3 75 TEMPERATURE (°C) SUPPLY CURRENT vs. TEMPERATURE 5 25 RESET OCCURS ABOVE THE CURVE 100 0 0 6 125 0.80 -25 5 150 25 -50 4 175 0.85 TEMPERATURE (°C) 3 MAXIMUM TRANSIENT DURATION vs. RESET THRESHOLD OVERDRIVE MAX6746 toc08 1.00 1.20 NORMALIZED TIMEOUT PERIOD MAX6746 toc04 1.10 2 SUPPLY VOLTAGE (V) CSWT (pF) 1.15 1 100,000 CSRT (pF) 1.20 2 0 100 100,000 3 MAX6746 toc08b 1000 TRANSIENT DURATION (µs) 100 4 1 1 0.1 0.1 NORMALIZED TIMEOUT PERIOD 5 EXTENDED MODE 10 MAX6746 toc03 10,000 MAX6746 toc06 10 MAX6746–MAX6751 SUPPLY CURRENT (µA) 100 6 MAX6746 toc02 MAX6746 toc01 1000 100,000 WATCHDOG TIMEOUT PERIOD (ms) RESET TIMEOUT PERIOD (ms) 10,000 4 SUPPLY CURRENT vs. SUPPLY VOLTAGE WATCHDOG TIMEOUT PERIOD vs. CSWT RESET TIMEOUT PERIOD vs. CSRT SUPPLY CURRENT (µA) MAX6746–MAX6753 µP Reset Circuits with Capacitor-Adjustable Reset/Watchdog Timeout Delay 1.235 -50 -25 0 25 50 75 TEMPERATURE (°C) 100 125 1 2 3 4 SUPPLY VOLTAGE (V) _______________________________________________________________________________________ 5 6 µP Reset Circuits with Capacitor-Adjustable Reset/Watchdog Timeout Delay RESET AND WATCHDOG TIMEOUT PERIOD vs. VCC 0.56 26.2 25.8 0.52 0.48 0.44 25.4 -50 -25 0 25 50 75 125 100 CSWT = CSRT = 1500pF 8.5 RESET 8.0 WATCHDOG 7.5 7.0 6.5 0.40 25.0 9.0 TIMEOUT PERIOD (ms) 26.6 CSWT = CSRT = 100pF MAX6746 toc11 0.60 MAX6746 toc09 VCC FALLING AT 1mV/µs TIMEOUT PERIOD (ms) VCC TO RESET DELAY (µs) 27.0 RESET AND WATCHING TIMEOUT PERIOD vs. VCC MAX6746 toc10 VCC TO RESET DELAY vs. TEMPERATURE (VCC FALLING) 6.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VCC (V) VCC (V) TEMPERATURE (°C) Pin Description PIN MAX6746 MAX6747 MAX6748– MAX6751 MAX6752 MAX6753 NAME 1 — — MR — 1 — RESET IN — — 1 SET0 FUNCTION Manual Reset Input. Pull MR low to manually reset the device. Reset remains asserted for the reset timeout period after MR is released. Reset Input. High-impedance input to the adjustable reset comparator. Connect RESET IN to the center point of an external resistor-divider to set the threshold of the externally monitored voltage. Logic Input. SET0 selects watchdog window ratio or disables the watchdog timer. See Table 1. Watchdog Timeout Input. MAX6746–MAX6751: Connect a capacitor between SWT and ground to set the basic watchdog timeout period (tWD). Determine the period by the formula tWD = 5.06 x 106 x CSWT with tWD in seconds and CSWT in Farads. Extend the basic watchdog timeout period by using the WDS input. Connect SWT to ground to disable the watchdog timer function. 2 2 2 SWT MAX6752/MAX6753: Connect a capacitor between SWT and ground to set the slow watchdog timeout period (tWD2). Determine the slow watchdog period by the formula: tWD2 = 0.65 x 109 x CSWT with tWD2 in seconds and CSWT in Farads. The fast watchdog timeout period is set by pinstrapping SET0 and SET1 (Connect SET0 high and SET1 low to disable the watchdog timer function.) See Table 1. 3 3 3 SRT Reset Timeout Input. Connect a capacitor from SRT to GND to select the reset timeout period. Determine the period as follows: tRP = 5.06 x 106 x CSRT with tRP in seconds and CSRT in Farads. 4 4 4 GND Ground _______________________________________________________________________________________ 5 MAX6746–MAX6753 Typical Operating Characteristics (continued) (VCC = +5V, TA = +25°C, unless otherwise noted.) µP Reset Circuits with Capacitor-Adjustable Reset/Watchdog Timeout Delay MAX6746–MAX6753 Pin Description (continued) PIN MAX6746 MAX6747 MAX6748– MAX6751 MAX6752 MAX6753 NAME FUNCTION 5 5 — WDS Watchdog Select Input. WDS selects the watchdog mode. Connect WDS to ground to select normal mode and the watchdog timeout period. Connect WDS to VCC to select extended mode, multiplying the basic timeout period by a factor of 128. A change in the state of WDS clears the watchdog timer. — — 5 SET1 Logic Input. SET1 selects the watchdog window ratio or disables the watchdog timer. See Table 1. Watchdog Input. MAX6746–MAX6751: A falling transition must occur on WDI within the selected watchdog timeout period or a reset pulse occurs. The watchdog timer clears when a transition occurs on WDI or whenever RESET is asserted. Connect SWT to ground to disable the watchdog timer function. 6 6 6 WDI MAX6752/MAX6753: WDI falling transitions within periods shorter than tWD1 or longer than tWD2 force RESET to assert low for the reset timeout period. The watchdog timer begins to count after RESET is deasserted. The watchdog timer clears when a valid transition occurs on WDI or whenever RESET is asserted. Connect SET0 high and SET1 low to disable the watchdog timer function. See the Watchdog Timer section. 6 7 7 7 RESET 8 8 8 VCC Push/Pull or Open-Drain Reset Output. RESET asserts whenever VCC or RESET IN drops below the selected reset threshold voltage (VTH or VRESET IN, respectively) or manual reset is pulled low. RESET remains low for the reset timeout period after all reset conditions are deasserted, and then goes high. The watchdog timer triggers a reset pulse (tRP) whenever a watchdog fault occurs. Supply Voltage. VCC is the power-supply input and the input for fixed threshold VCC monitor. _______________________________________________________________________________________ µP Reset Circuits with Capacitor-Adjustable Reset/Watchdog Timeout Delay GUARANTEED TO ASSERT RESET MAX6746–MAX6753 tWD1 (MIN) tWD1 (MAX) tWD2 (MIN) tWD2 (MAX) GUARANTEED TO GUARANTEED TO NOT ASSERT ASSERT RESET RESET *UNDETERMINED *UNDETERMINED WDI CONDITION 1 FAST FAULT WDI CONDITION 2 NORMAL OPERATION WDI CONDITION 3 SLOW FAULT *UNDETERMINED STATES MAY OR MAY NOT GENERATE A FAULT CONDITION Figure 1. MAX6752/MAX6753 Detailed Watchdog Input Timing Relationship Detailed Description The MAX6746–MAX6753 assert a reset signal whenever the VCC supply voltage or RESET IN falls below its reset threshold. The reset output remains asserted for the reset timeout period after VCC and RESET IN rise above its respective reset threshold. A watchdog timer triggers a reset pulse whenever a watchdog fault occurs. The reset and watchdog delays are adjustable with external capacitors. The MAX6746–MAX6751 contain a watchdog select input that extends the watchdog timeout period to 128x. The MAX6752 and MAX6753 have a sophisticated watchdog timer that detects when the processor is running outside an expected window of operation. The watchdog signals a fault when the input pulses arrive too early (faster that the selected tWD1 timeout period) or too late (slower than the selected tWD2 timeout period) (see Figure 1). RESET is guaranteed to be in the correct logic state for VCC greater than 1V. For applications requiring valid reset logic when VCC is less than 1V, see the section Ensuring a Valid RESET Output Down to VCC = 0V. RESET IN Threshold The MAX6748–MAX6751 monitor the voltage on RESET IN using an adjustable reset threshold (VRESET IN) set with an external resistor voltage-divider (Figure 2). Use the following formula to calculate the externally monitored voltage (VMON_TH): VMON_TH = VRESET IN x (R1 + R2) / R2 VMON_TH R1 Reset Output The reset output is typically connected to the reset input of a µP. A µP’s reset input starts or restarts the µP in a known state. The MAX6746–MAX6753 µP supervisory circuits provide the reset logic to prevent code-execution errors during power-up, power-down, and brownout conditions (see theTypical Operating Circuit). RESET changes from high to low whenever the monitored voltage, RESET IN and/or VCC drop below the reset threshold voltages. Once VRESET IN and/or VCC exceeds its respective reset threshold voltage(s), RESET remains low for the reset timeout period, then goes high. VCC VCC RESET IN R2 GND MAX6748 MAX6749 MAX6750 MAX6751 VMON_TH = 1.235 x (R1 + R2) / R2 Figure 2. Calculating the Monitored Threshold Voltage (VMON_TH) _______________________________________________________________________________________ 7 MAX6746–MAX6753 µP Reset Circuits with Capacitor-Adjustable Reset/Watchdog Timeout Delay guarantee RESET IN threshold accuracy and timing performance. The MAX6748 and MAX6749 can be configured to monitor VCC voltage by connecting VCC to VMON_TH. VMON_TH R1 Dual-Voltage Monitoring (MAX6750/MAX6751) VCC R2 GND The MAX6750 and MAX6751 contain both factorytrimmed threshold voltages and an adjustable reset threshold input, allowing the monitoring of two voltages, VCC and VMON_TH (see Figure 2). RESET is asserted when either of the voltages falls below it respective threshold voltages. VCC RESET IN MAX6748 MAX6749 MAX6750 MAX6751 Manual Reset (MAX6746/MAX6747) Figure 3. Adding an External Manual Reset Function to the MAX6748–MAX6751 where VMON_TH is the desired reset threshold voltage and VTH is the reset input threshold (1.235V). Resistors R1 and R2 can have very high values to minimize current consumption due to low leakage currents. Set R2 to some conveniently high value (500kΩ, for example) and calculate R1 based on the desired reset threshold voltage, using the following formula: R1 = R2 x (VMON_TH/VRESET IN - 1) (Ω) The MAX6748 and MAX6749 do not monitor VCC supply voltage, therefore, VCC must be greater than 1.5V to Many µP-based products require manual reset capability, to allow an operator or external logic circuitry to initiate a reset. The manual reset input (MR) can connect directly to a switch without an external pullup resistor or debouncing network. MR is internally pulled up to VCC and, therefore, can be left unconnected if unused. MR is designed to reject fast, falling transients (typically 100ns pulses) and it must be held low for a minimum of 1µs to assert the reset output. A 0.1µF capacitor from MR to ground provides additional noise immunity. After MR transitions from low to high, reset remains asserted for the duration of the reset timeout period. A manual reset option can easily be implemented with the MAX6748–MAX6751 by connecting a normally open momentary switch in parallel with R2 (Figure 3). When the switch is closed, the voltage on RESET IN goes to zero, initiating a reset. Similar to the MAX6746/ MAX6747 manual reset, reset remains asserted while the voltage at RESET IN is zero and for the reset timeout period after the switch is opened. VCC tWD WDI tRP OV VCC RESET OV NORMAL MODE (WDS = GND) Figure 4a. Watchdog Timing Diagram, WDS = GND 8 _______________________________________________________________________________________ µP Reset Circuits with Capacitor-Adjustable Reset/Watchdog Timeout Delay MAX6746–MAX6753 VCC tRP tWD x 128 WDI OV VCC RESET OV EXTENDED MODE (WDS = VCC) Figure 4b. Watchdog Timing Diagram, WDS = VCC Watchdog Timer MAX6746–MAX6751 The watchdog’s circuit monitors the µP’s activity. It the µP does not toggle the watchdog input (WDI) within tWD (user-selected), RESET asserts for the reset timeout period. The internal watchdog timer is cleared by any event that asserts RESET, by a falling transition at WDI (which can detect pulses as short as 300ns) or by a transition at WDS. The watchdog timer remains cleared while reset is asserted; as soon as reset is released, the timer starts counting. The MAX6746–MAX6751 feature two modes of watchdog operation: normal mode and extended mode. In normal mode (Figure 4a), the watchdog timeout period is determined by the value of the capacitor connected between SWT and ground. In extended mode (Figure 4b), the watchdog timeout period is multiplied by 128. For example, in extended mode, a 0.1µF capacitor gives a watchdog timeout period of 65s (see the ExtendedMode Watchdog Timeout Period vs. CSWT graph in the Typical Operating Characteristics). To disable the watchdog timer function, connect SWT to ground. MAX6752/MAX6753 The MAX6752 and MAX6753 have a windowed watchdog timer that asserts RESET for the adjusted reset timeout period when the watchdog recognizes a fast watchdog fault (tWDI < tWD1), or a slow watchdog fault (period > tWD2). The reset timeout period is adjusted independently of the watchdog timeout period. The slow watchdog period, tWD2 is calculated as follows: tWD2 = 0.65 x 109 x CSWT with tWD2 in seconds and CSWT in Farads. The fast watchdog period, tWD1, is selectable as a ratio from the slow watchdog fault period (tWD2). Select the fast watchdog period by pinstrapping SET0 and SET1, Table 1. Min/MAX Watchdog Setting SET0 SET1 RATIO LOW LOW 8 LOW HIGH 16 HIGH LOW Watchdog Disabled HIGH HIGH 64 where HIGH is VCC and LOW is GND. Table 1 illustrates the SET0 and SET1 configuration for the 8, 16, and 64 window ratio ( tWD2/tWD1). For example, if CSWT is 1500pF, and SET0 and SET1 are low, then tWD2 is 975ms (typ) and tWD1 is 122ms (typ). RESET asserts if the watchdog input has two falling edges too close to each other (faster than tWD1) (Figure 5a) or falling edges that are too far apart (slower than tWD2) (Figure 5b). Normal watchdog operation is displayed in (Figure 5c). The internal watchdog timer is cleared when a WDI falling edge is detected within the valid watchdog window or when RESET is deasserted. All WDI inputs are ignored while RESET is asserted. The watchdog timer begins to count after RESET is deasserted. The watchdog timer clears and begins to count after a valid WDI falling logic input. WDI falling transitions within periods shorter than tWD1 or longer than tWD2 force RESET to assert low for the reset timeout period. WDI falling transitions within the tWD1 and t WD2 window do not assert RESET. WDI transitions between t WD1(min) and t WD1(max) or t WD2(min) and tWD2(max) are not guaranteed to assert or deassert the RESET. To guarantee that the window watchdog does not assert the RESET, strobe WDI between tWD1(max) and tWD2(min). The watchdog timer is cleared when RESET is asserted or after a falling transition on WDI or after a state change on SET0 or SET1. Disable the watchdog timer by connecting SET0 high and SET1 low. _______________________________________________________________________________________ 9 MAX6746–MAX6753 µP Reset Circuits with Capacitor-Adjustable Reset/Watchdog Timeout Delay tWDI < tWD1 (MIN) 5V 3.3V VCC WDI 100kΩ MAX6747 MAX6749 MAX6451 MAX6753 RESET (a) FAST FAULT VCC RESET RESET µP N tWDI > tWD2 (MAX) GND GND WDI Figure 6. Interfacing to Other Voltage Levels RESET (b) SLOW FAULT tWD1 (MAX) < tWDI < tWD2 (MIN) normal mode operation, calculate the watchdog timeout capacitor as follows: CSWT = tWD/(5.06 x 106), with tRP in seconds and CSRT in Farads. For the MAX6752 and MAX6753 windowed watchdog function, calculate the slow watchdog period, tWD2 as follows: WDI tWD2 = 0.65 x 109 x CSWT CSRT and CSWT must be a low-leakage (<10nA) type capacitor. Ceramic capacitors are recommended. RESET (c) NORMAL OPERATION (NO PULSING, OUTPUT STAYS HIGH) Transient Immunity Figure 5. MAX6752/MAX6753 Window Watchdog Diagram Applications Information Selecting Reset/Watchdog Timeout Capacitor The reset timeout period is adjustable to accommodate a variety of µP applications. Adjust the reset timeout period (tRP) by connecting a capacitor (CSRT) between SRT and ground. Calculate the reset timeout capacitor as folllows: CSRT = tRP / (5.06 x 106), with tRP in seconds and CSRT in Farads. The watchdog timeout period is adjustable to accommodate a variety of µP applications. With this feature, the watchdog timeout can be optimized for software execution. The programmer can determine how often the watchdog timer should be serviced. Adjust the watchdog timeout period (tWD) by connecting a specific value capacitor (CSWT) between SWT and GND. For 10 In addition to issuing a reset to the µP during power-up, power-down, and brownout conditions, these supervisors are relatively immune to short-duration supply transients (glitches). The Maximum Transient Duration vs. Reset Threshold Overdrive graph in the Typical Operating Characteristics shows this relationship. The area below the curves of the graph is the region in which these devices typically do not generate a reset pulse. This graph was generated using a falling pulse applied to VCC , starting above the actual reset threshold (VTH) and ending below it by the magnitude indicated (reset-threshold overdrive). As the magnitude of the transient increases (farther below the reset threshold), the maximum allowable pulse width decreases. Typically, a VCC transient that goes 100mV below the reset threshold and lasts 50µs or less does not cause a reset pulse to be issued. ______________________________________________________________________________________ µP Reset Circuits with Capacitor-Adjustable Reset/Watchdog Timeout Delay The open-drain RESET output can be used to interface to a µP with other logic levels. As shown in Figure 6, the open-drain output can be connected to voltages from 0 to 6V. Generally, the pullup resistor connected to the RESET connects to the supply voltage that is being monitored at the IC’s VCC pin. However, some systems can use the open-drain output to level-shift from the monitored supply to reset circuitry powered by some other supply. Keep in mind that as the supervisor’s VCC decreases towards 1V, so does the IC’s ability to sink current at RESET. Also, with any pullup resistor, RESET is pulled high as VCC decays toward zero. The voltage where this occurs depends on the pullup resistor value and the voltage to which it is connected. Ensuring a Valid RESET Down to VCC = 0V (Push-Pull RESET) When VCC falls below 1V, RESET current sinking capabilities decline drastically. The high-impedance CMOSlogic inputs connected to RESET can drift to undetermined voltages. This presents no problems in most applications, since most µPs and other circuitry do not operate with VCC below 1V. In those applications where RESET must be valid down to 0V, add a pulldown resistor between RESET and GND for the MAX6746/MAX6748/MAX6750/MAX6752 push/pull outputs. The resistor sinks any stray leakage currents, holding RESET low (Figure 7). The value of the pulldown resistor is not critical; 100kΩ is large enough not to load RESET and small enough to pull RESET to ground. The external pulldown can not be used with the open-drain reset outputs. VCC VCC MAX6746 MAX6748 MAX6450 MAX6752 RESET 100kΩ GND Figure 7. Ensuring RESET Valid to VCC = 0 ______________________________________________________________________________________ 11 MAX6746–MAX6753 Interfacing to Other Voltages for Logic Compatibility MAX6746–MAX6753 µP Reset Circuits with Capacitor-Adjustable Reset/Watchdog Timeout Delay Table 2. Reset Threshold Voltage Suffix (TA = -40°C to +125°C) Table 3. Standard Version Table PART TOP MARK SUFFIX MIN TYP MAX MAX6746KA16 AEDI 50 4.900 5.000 5.100 MAX6746KA23 AEDJ 49 4.802 4.900 4.998 MAX6746KA26 AEDK 48 4.704 4.800 4.896 MAX6746KA29 AALN 47 4.606 4.700 4.794 MAX6746KA46 AEDL 46 4.533 4.625 4.718 MAX6747KA16 AALO 45 4.410 4.500 4.590 MAX6747KA23 AEDM 44 4.288 4.375 4.463 MAX6747KA26 AEDN 43 4.214 4.300 4.386 MAX6747KA29 AEDO AEDP 42 4.116 4.200 4.284 MAX6747KA46 41 4.018 4.100 4.182 MAX6748KA AALP 40 3.920 4.000 4.080 MAX6749KA AALQ 39 3.822 3.900 3.978 MAX6750KA16 AEDQ 38 3.724 3.800 3.876 MAX6750KA23 AALR 37 3.626 3.700 3.774 MAX6750KA26 AEDR 36 3.528 3.600 3.672 MAX6750KA29 AEDS 35 3.430 3.500 3.570 MAX6750KA46 AEDT 34 3.332 3.400 3.468 MAX6751KA16 AEDU 33 3.234 3.300 3.366 MAX6751KA23 AEDV 32 3.136 3.200 3.264 MAX6751KA26 AEDW 31 3.014 3.075 3.137 MAX6751KA29 AEDX 3.000 3.060 MAX6751KA46 AEDY 30 2.940 29 2.867 2.925 2.984 MAX6752KA16 AEDZ 28 2.744 2.800 2.856 MAX6752KA23 AEEA 27 2.646 2.700 2.754 MAX6752KA26 AALT AEEB 26 2.573 2.625 2.678 MAX6752KA29 25 2.450 2.500 2.550 MAX6752KA46 AEEC 24 2.352 2.400 2.448 MAX6753KA16 AEED AEEE 23 2.267 2.313 2.359 MAX6753KA23 22 2.144 2.188 2.232 MAX6753KA26 AEEF 21 2.058 2.100 2.142 MAX6753KA29 AEEG 20 1.960 2.000 2.040 MAX6753KA46 AEEH 19 1.862 1.900 1.938 18 1.764 1.800 1.836 17 1.632 1.665 1.698 16 1.544 1.575 1.607 Note: Standard versions are shown in bold. There is a 2500piece minimum order increment for standard versions. Sample stock is typically held on standard versions only. Nonstandard versions require a minimum order increment of 10,000 pieces. Contact factory for availability. 12 ______________________________________________________________________________________ µP Reset Circuits with Capacitor-Adjustable Reset/Watchdog Timeout Delay PART FIXED VCC RESET THRESHOLD ADJUSTABLE RESET THRESHOLD STANDARD WATCHDOG TIMER MIN/MAX WATCHDOG TIMER PUSH/ PULL RESET OPEN-DRAIN RESET MANUAL RESET INPUT MAX6746 * — * — * — * MAX6747 * — * — — * * MAX6748 — * * — * — — MAX6749 — * * — — * — MAX6750 * * * — * — — MAX6751 * * * — — * — MAX6752 * — — * * — — MAX6753 * — — * — * — Typical Operating Circuit Pin Configurations (continued) TOP VIEW VIN MAX6749 MAX4751 VCC SET0 1 8 VCC 7 RESET 6 WDI 5 SET1 R1 SWT RESET IN µP R2 GND 2 VCC MAX6748 MAX6749 MAX6750 MAX6751 SRT 3 MAX6752 MAX6753 GND 4 RESET RESET SOT23-8 SRT CSRT WDI SWT CSWT I/O Chip Information WDS WDS = 0 FOR NORMAL MODE WDS = VCC FOR EXTENDED MODE TRANSISTOR COUNT: 1100 PROCESS: BiCMOS ______________________________________________________________________________________ 13 MAX6746–MAX6753 Selector Guide Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) SEE DETAIL "A" CL CL E MIN MAX A A1 A2 0.90 0.00 0.90 1.45 0.15 1.30 b 0.28 0.45 C D E 0.09 2.80 2.60 0.20 3.00 3.00 SYMBOL e b CL E1 E1 1.50 L 0.30 L2 e PIN 1 I.D. DOT (SEE NOTE 6) SOT23, 8L .EPS MAX6746–MAX6753 µP Reset Circuits with Capacitor-Adjustable Reset/Watchdog Timeout Delay 1.75 0.60 0.25 BSC. 0.65 BSC. 1.95 REF. e1 0 0 8 e1 D C CL L2 A A2 GAUGE PLANE A1 SEATING PLANE C 0 L NOTE: 1. ALL DIMENSIONS ARE IN MILLIMETERS. 2. FOOT LENGTH MEASURED FROM LEAD TIP TO UPPER RADIUS OF HEEL OF THE LEAD PARALLEL TO SEATING PLANE C. 3. PACKAGE OUTLINE EXCLUSIVE OF MOLD FLASH & METAL BURR. 4. PACKAGE OUTLINE INCLUSIVE OF SOLDER PLATING. DETAIL "A" 5. COPLANARITY 4 MILS. MAX. 6. PIN 1 I.D. DOT IS 0.3 MM MIN. LOCATED ABOVE PIN 1. 7. SOLDER THICKNESS MEASURED AT FLAT SECTION OF LEAD BETWEEN 0.08mm AND 0.15mm FROM LEAD TIP. 8. MEETS JEDEC MO178. PROPRIETARY INFORMATION TITLE: PACKAGE OUTLINE, SOT-23, 8L BODY APPROVAL DOCUMENT CONTROL NO. 21-0078 REV. D 1 1 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 14 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2003 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.