DG441, DG442 ® Data Sheet November 20, 2006 Monolithic, Quad SPST, CMOS Analog Switches FN3281.10 Features • ON Resistance (Max) . . . . . . . . . . . . . . . . . . . . . . . . . 85Ω The DG441 and DG442 monolithic CMOS analog switches are drop-in replacements for the popular DG201A and DG202 series devices. They include four independent single pole single throw (SPST) analog switches, TTL and CMOS compatible digital inputs, and a voltage reference for logic thresholds. • Low Power Consumption (PD) . . . . . . . . . . . . . . . <1.6mW • Fast Switching Action - tON (Max) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250ns - tOFF (Max, DG441). . . . . . . . . . . . . . . . . . . . . . . . 120ns • Low Charge Injection These switches feature lower analog ON resistance (<85Ω) and faster switch time (tON <250ns) compared to the DG201A and DG202. Charge injection has been reduced, simplifying sample and hold applications. • Upgrade from DG201A, DG202 The improvements in the DG441 series are made possible by using a high voltage silicon-gate process. An epitaxial layer prevents the latch-up associated with older CMOS technologies. The 44V maximum voltage range permits controlling 40VP-P signals. Power supplies may be single ended from +5V to +34V, symmetrical supplies from ±5V to ±22V or asymmetrical supplies limited to a maximum differential voltage of 44V with a V+ max of 34V or a V- max of -25V. • Pb-Free Plus Anneal Available (RoHS Compliant) The four switches are bilateral, equally matched for AC or bidirectional signals. The ON resistance variation with analog signals is quite low over a ±5V analog input range. The switches in the DG441 and DG442 are identical, differing only in the polarity of the selection logic. • TTL, CMOS Compatible • Single or Split Supply Operation Applications • Audio Switching • Battery Operated Systems • Data Acquisition • Hi-Rel Systems • Sample and Hold Circuits • Communication Systems • Automatic Test Equipment Pinout DG441, DG442 (16 LD PDIP, SOIC, TSSOP) TOP VIEW IN1 1 16 IN2 D1 2 15 D2 S1 3 14 S2 V- 4 13 V+ GND 5 12 NC S4 6 11 S3 D4 7 10 D3 IN4 8 9 IN3 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2002-2006. All Rights Reserved DG441, DG442 Ordering Information PART NUMBER PART MARKING DG441DJ TEMP. RANGE (°C) PACKAGE PKG. DWG. # DG441DJ -40 to +85 16 Ld PDIP DG441DJZ (Note) DG441DJZ -40 to +85 16 Ld PDIP* (Pb-free) E16.3 DG441DY DG441DY -40 to +85 16 Ld SOIC M16.15 DG441DY-T DG441DY 16 Ld SOIC Tape and Reel DG441DYZ (Note) DG441DYZ DG441DYZ-T (Note) DG441DYZ DG441DYZA (Note) DG441DYZ DG441DYZA-T (Note) DG441DYZ DG441DVZ (Note) DG441DVZ -40 to +85 M16.15 16 Ld SOIC (Pb-free) 16 Ld SOIC Tape and Reel (Pb-free) -40 to +85 16 Ld SOIC (Pb-free) 16 Ld SOIC Tape and Reel (Pb-free) -40 to +85 E16.3 16 Ld TSSOP (Pb-free) M16.15 M16.15 M16.15 M16.15 M16.173 DG441DVZ-T (Note) DG441DVZ -40 to +85 16 Ld TSSOP Tape and Reel (Pb-free) M16.173 DG442DJ DG442DJ -40 to +85 16 Ld PDIP E16.3 DG442DJZ (Note) DG442DJZ -40 to +85 16 Ld PDIP* (Pb-free) E16.3 DG442DY DG442DY -40 to +85 16 Ld SOIC M16.15 DG442DY-T DG442DY 16 Ld SOIC Tape and Reel DG442DYZ (Note) DG442DYZ DG442DYZ-T (Note) DG442DYZ DG442DVZ (Note) DG442DVZ DG442DVZ-T (Note) DG442DVZ -40 to +85 M16.15 16 Ld SOIC (Pb-free) 16 Ld SOIC Tape and Reel (Pb-free) -40 to +85 16 Ld TSSOP (Pb-free) 16 Ld TSSOP Tape and Reel (Pb-free) M16.15 M16.15 M16.173 M16.173 *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. Functional Diagrams DG441 DG442 S1 S1 IN1 IN1 D1 S2 D1 S2 IN2 IN2 D2 S3 D2 S3 IN3 IN3 D3 S4 D3 S4 IN4 IN4 D4 D4 SWITCHES SHOWN FOR LOGIC “1” INPUT TRUTH TABLE LOGIC VIN DG441 DG442 0 ≤0.8V ON OFF 1 ≥2.4V OFF ON 2 FN3281.10 November 20, 2006 DG441, DG442 Schematic Diagram (One Channel) V+ S VV+ INX D GND 1 PER DIE COMMON TO EVERY CHANNEL V- Pin Descriptions PIN SYMBOL 1 IN1 Logic Control for Switch 1 2 D1 Drain (Output) Terminal for Switch 1 3 S1 Source (Input) Terminal for Switch 1 4 V- Negative Power Supply Terminal 5 GND 6 S4 Source (Input) Terminal for Switch 4 7 D4 Drain (Output) Terminal for Switch 4 8 IN4 Logic Control for Switch 4 9 IN3 Logic Control for Switch 3 10 D3 Drain (Output) Terminal for Switch 3 11 S3 Source (Input) Terminal for Switch 3 12 NC No Internal Connection 13 V+ Positive Power Supply Terminal (Substrate) 14 S2 Source (Input) Terminal for Switch 2 15 D2 Drain (Output) Terminal for Switch 2 16 IN2 Logic Control for Switch 2 3 DESCRIPTION Ground Terminal (Logic Common) FN3281.10 November 20, 2006 DG441, DG442 Absolute Maximum Ratings Thermal Information V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44.0V GND to V-. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -25V GND to V+ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+34V Digital Inputs, VS, VD (Note 1) . . . . . . . . (V-) -2V to (V+) + 2V or 30mA, Whichever Occurs First Continuous Current (Any Terminal) . . . . . . . . . . . . . . . . . . . . . 30mA Peak Current, S or D (Pulsed 1ms, 10% Duty Cycle Max) . . 100mA Thermal Resistance (Typical, Note 2) Operating Conditions *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C Signal Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20V (Max) Input Low Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.8V (Max) Input High Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4V (Min) Input Rise and Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .≤20ns θJA (°C/W) PDIP Package* . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 TSSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 Maximum Junction Temperature (Plastic Packages) . . . . . . +150°C Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . +300°C (SOIC and TSSOP- Lead Tips Only) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. Signals on SX, DX or INX exceeding V+ or V- will be clamped by internal diodes. Limit forward diode current to maximum current ratings. 2. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. Electrical Specifications (Dual Supply) Test Conditions: V+ = +15V, V- = -15V, VIN = 2.4V, 0.8V, VANALOG = VS , VD , Unless Otherwise Specified PARAMETER TEST CONDITIONS TEMP (°C) MIN (NOTE 3) TYP MAX UNITS +25 - 150 250 ns +25 - 90 120 ns - 110 210 ns DYNAMIC CHARACTERISTICS RL = 1kΩ, CL = 35pF, VS = ±10V, (Figure 1) Turn-ON Time, tON Turn-OFF Time, tOFF DG441 DG442 Charge Injection, Q (Figure 2) CL = 1nF, VG = 0V, RG = 0Ω +25 - -1 - pC OFF Isolation (Figure 4) RL = 50Ω, CL = 5pF, f = 1MHz +25 - 60 - dB +25 - -100 - dB +25 - 4 - pF Drain OFF Capacitance, CD(OFF) +25 - 4 - pF Channel ON Capacitance, CD(ON) + CS(ON) +25 - 16 - pF Crosstalk (Channel-to-Channel) (Figure 3) Source OFF Capacitance, CS(OFF) f = 1MHz, VANALOG = 0 (Figure 5) DIGITAL INPUT CHARACTERISTICS Input Current VIN Low, IIL VIN Under Test = 0.8V, All Others = 2.4V Full -0.5 -0.00001 0.5 μA Input Current VIN High, IIH VIN Under Test = 2.4V, All Others = 0.8V Full -0.5 0.00001 0.5 μA Full -15 - 15 V +25 - 50 85 Ω ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG Drain-Source ON Resistance, rDS(ON) IS = 10mA, VD = ±8.5V, V+ = 13.5V, V- = -13.5V Source OFF Leakage Current, IS(OFF) V+ = 16.5V, V- = -16.5V, VD = ±15.5V, VS = 15.5V Drain OFF Leakage Current, ID(OFF) V+ = 16.5V, V- = -16.5V, VS = VD = ±15.5V Channel ON Leakage Current, ID(ON) + IS(ON) 4 +85 - - 100 Ω +25 -0.5 0.01 0.5 nA +85 -5 - 5 nA +25 -0.5 0.01 0.5 nA +85 -5 - 5 nA +25 -0.5 0.08 0.5 nA +85 -10 - 10 nA FN3281.10 November 20, 2006 DG441, DG442 Electrical Specifications (Dual Supply) Test Conditions: V+ = +15V, V- = -15V, VIN = 2.4V, 0.8V, VANALOG = VS , VD , Unless Otherwise Specified (Continued) PARAMETER TEST CONDITIONS TEMP (°C) MIN (NOTE 3) TYP MAX UNITS Full - 15 100 μA +25 -1 -0.0001 - μA Full -5 - - μA Full -100 -15 - μA POWER SUPPLY CHARACTERISTICS V+ = 16.5V, V- = -16.5V, VIN = 0V or 5V Positive Supply Current, I+ Negative Supply Current, I- Ground Current, IGND Electrical Specifications (Single Supply) Test Conditions: V+ = 12V, V- = 0V, VIN = 2.4V, 0.8V, Unless Otherwise Specified PARAMETER TEST CONDITIONS TEMP (°C) MIN (NOTE 3) TYP MAX UNITS +25 - 300 450 ns +25 - 60 200 ns +25 - 2 - pC Full 0 - 12 V +25 - 100 160 Ω Full - - 200 Ω Full - 15 100 μA +25 -1 -0.0001 - μA Full -100 -0.0001 - μA Full -100 -15 - μA DYNAMIC CHARACTERISTICS Turn-ON Time, tON RL = 1kΩ, CL = 35pF, VS = 8V, (Figure 1) Turn-OFF Time, tOFF Charge Injection, Q (Figure 2) CL = 1nF, VG = 6V, RG = 0Ω ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG Drain-Source ON Resistance, rDS(ON) IS = 10mA, VD = 3V, 8V V+ = 10.8V POWER SUPPLY CHARACTERISTICS Positive Supply Current, I+ V+ = 13.2V, V- = 0V, VIN = 0V or 5V Negative Supply Current, I- Ground Current, IGND NOTES: 3. Typical values are for DESIGN AID ONLY, not guaranteed nor production tested. 5 FN3281.10 November 20, 2006 DG441, DG442 Test Circuits and Waveforms VO is the steady state output with the switch on. Feedthrough via switch capacitance may result in spikes at the leading and trailing edge of the output waveform. V+ tr < 20ns tf < 20ns 3V LOGIC INPUT 50% SWITCH INPUT 0V tOFF SWITCH OUTPUT VO IN1 SWITCH INPUT VS VO D1 S1 80% 80% CL RL LOGIC INPUT 3V GND V- 0V tON NOTE: Logic input waveform is inverted for switches that have the opposite logic sense. Repeat test for Channels 2, 3 and 4. For load conditions, see Specifications. CL includes fixture and stray capacitance. RL V O = V S -----------------------------------R L + r DS ( ON ) FIGURE 1B. TEST CIRCUIT FIGURE 1A. MEASUREMENT POINTS FIGURE 1. SWITCHING TIMES V+ SWITCH OUTPUT ΔVO INX (DG441) OFF RG D1 VO OFF ON VG CL V- INX (DG442) VIN = 3V ON Q = ΔVO x CL OFF OFF GND FIGURE 2A. MEASUREMENT POINTS FIGURE 2B. TEST CIRCUIT FIGURE 2. CHARGE INJECTION C SIGNAL GENERATOR 10dBm V+ +15V C SIGNAL GENERATOR 10dBm VS VD 50Ω IN1 IN2 0V, 2.4V V+ +15V VS 0V, 2.4V VD ANALYZER NC RL V- GND C -15V FIGURE 3. CROSSTALK TEST CIRCUIT 6 INX 0V, 2.4V VD ANALYZER RL V- GND C -15V FIGURE 4. OFF ISOLATION TEST CIRCUIT FN3281.10 November 20, 2006 DG441, DG442 Test Circuits and Waveforms (Continued) C V+ +15V VS INX IMPEDANCE ANALYZER 0V, 2.4V VD f = 1MHz V- C -15V GND FIGURE 5. SOURCE/DRAIN CAPACITANCES TEST CIRCUIT Application Information GAIN ERROR IS DETERMINED ONLY BY THE RESISTOR TOLERANCE. OP AMP OFFSET AND CMRR WILL LIMIT ACCURACY OF CIRCUIT. VIN +15V -15V FET INPUT 7 4 OP AMP 3 6 2 VOUT +15V 13 3 2 GAIN1 AV = 1 1 R1 90kΩ 15 GAIN2 AV = 10 14 +15V 16 R2 5kΩ 10 GAIN3 AV = 20 11 9 R3 4kΩ + - SX DX 8 CH R4 1kΩ V- GND 4 5 -15V VOUT + 6 7 GAIN4 AV = 100 1/4 DG442 VIN - -15V INX 1 = SAMPLE 0 = HOLD V OUT R1 + R2 + R3 + R4 ---------------- = ------------------------------------------------ = 100 with SW 4 closed V IN R4 FIGURE 6. PRECISION WEIGHTED RESISTOR PROGRAMMABLE GAIN AMPLIFIER 7 FIGURE 7. OPEN LOOP SAMPLE AND HOLD FN3281.10 November 20, 2006 DG441, DG442 Typical Performance Curves 100 80 ±5V V+ = +15V V- = -15V 70 80 60 ±8V ±10V rDS(ON) (Ω) rDS(ON) (Ω) +125°C 60 ±12V 40 ±15V ±20V 50 +85°C 40 +25°C 30 0°C -40°C -55°C 20 20 10 0 -20 0 VD (V) 0 -15 20 FIGURE 8. rDS(ON) vs VD AND POWER SUPPLY VOLTAGE 140 15 FIGURE 9. rDS(ON) vs VD AND TEMPERATURE 300 V+ = +12V V- = 0V 120 0 VD (V) V- = 0V +125°C 250 V+ = +5V +85°C 100 rDS(ON) (Ω) rDS(ON) (Ω) 200 80 +25°C 60 +10V +12V +15V +20V 50 20 0 +8V 100 0°C -40°C -55°C 40 150 0 6 VD (V) 0 12 FIGURE 10. rDS(ON) vs VD AND TEMPERATURE (SINGLE 12V SUPPLY) 0 10 VD (V) 20 FIGURE 11. rDS(ON) vs VD AND SINGLE SUPPLY VOLTAGE 105 105 104 104 I+, IGND 103 I+, I-, IGND (nA) IIN (pA) 103 102 10 102 10 1 -(I-) 0.1 1 0.1 0.01 -55 0 50 TEMPERATURE (°C) 100 FIGURE 12. INPUT CURRENT vs TEMPERATURE 8 125 0.001 -55 0 50 TEMPERATURE (°C) 100 125 FIGURE 13. SUPPLY CURRENT vs TEMPERATURE FN3281.10 November 20, 2006 DG441, DG442 Typical Performance Curves (Continued) 140 50 120 40 CROSSTALK SINGLE SUPPLY V+ = +12V V- = 0V 30 100 20 Q (pC) 80 (-dB) V+ = +15V V- = -15V OFF ISOLATION 60 10 CL = 10nF CL = 1nF 0 40 -10 20 0 100 V+ = +15V V- = -15V PGEN = 10dBm -20 1k 10k 100k FREQUENCY (Hz) 1M -30 -10 10M FIGURE 14. CROSSTALK AND OFF ISOLATION vs FREQUENCY 160 CL = 10nF CL = 1nF -5 0 VS (V) 5 10 FIGURE 15. CHARGE INJECTION vs SOURCE VOLTAGE 160 V+ = +15V V- = -15V tON (DG441) 140 140 tON 120 tON (DG442) 100 tON, tOFF (ns) tON, tOFF (ns) 120 tOFF (DG442) 80 80 tOFF 60 60 tOFF (DG441) 40 20 100 40 20 3 2 VIN (V) 4 10 5 FIGURE 16. SWITCHING TIMES vs INPUT VOLTAGE 12 14 16 18 SUPPLY VOLTAGE (±V) 20 22 FIGURE 17. SWITCHING TIME vs POWER SUPPLY VOLTAGE (DG441) 2.4 20 IS(OFF) , ID(OFF) 0 1.6 -40 VIN (V) IS, ID (pA) -20 IS(ON) + ID(ON) 0.8 -60 V+ = +15V V- = -15V FOR I(OFF) , VD = -VS -80 -100 -15 0 -10 -5 0 VS , VD (V) 5 10 FIGURE 18. LEAKAGE CURRENT vs ANALOG VOLTAGE 9 15 0 5 10 15 SUPPLY VOLTAGE (±V) 20 FIGURE 19. SWITCHING THRESHOLD vs SUPPLY VOLTAGE FN3281.10 November 20, 2006 DG441, DG442 Typical Performance Curves 25 (Continued) 20 V+ = +15V V- = -15V V+ = +12V V- = 0V CS(ON) + CD(ON) 20 15 15 CS , D (pF) CS , D (pF) CS(ON) + CD(ON) 10 CS(OFF) , CD(OFF) 5 -10 CS(OFF) , CD(OFF) 5 0 -15 10 -5 0 VA (V) 5 10 0 15 FIGURE 20. SOURCE/DRAIN CAPACITANCE vs ANALOG VOLTAGE 0 6 VA (V) 12 FIGURE 21. SOURCE/DRAIN CAPACITANCE vs ANALOG VOLTAGE (SINGLE 12V SUPPLY) 400 10 V+ = +12V V- = 0V tON (DG441) IS(OFF) , ID(OFF) 300 tON, tOFF (ns) IS , ID (pA) 0 -10 -20 IS(ON) + ID(ON) 0 200 100 V+ = +12V V- = 0V FOR ID , VS = 0 FOR IS , VD = 0 -30 -40 tON (DG442) 6 VS , VD (V) tOFF (DG442) tOFF (DG441) 0 12 FIGURE 22. SOURCE/DRAIN LEAKAGE CURRENTS (SINGLE 12V SUPPLY) 2 3 VIN (V) 4 5 FIGURE 23. SWITCHING TIME vs INPUT VOLTAGE (SINGLE 12V SUPPLY) 500 V- = 0V 400 tON, tOFF (ns) tON 300 200 100 tOFF 0 8 10 12 14 16 18 POSITIVE SUPPLY (V) 20 22 FIGURE 24. SWITCHING TIME vs SINGLE SUPPLY VOLTAGE (DG441) 10 FN3281.10 November 20, 2006 DG441, DG442 Die Characteristics DIE DIMENSIONS: PASSIVATION: 2160μm x 1760μm x 485μm Type: Nitride Thickness: 8kÅ ±1kÅ METALLIZATION: WORST CASE CURRENT DENSITY: Type: SiAl Thickness: 12kÅ ±1kÅ 9.1 x 104 A/cm2 Metallization Mask Layout DG441, DG442 D1 IN1 IN2 (2) (1) (16) (15) D2 S1 (3) (14) S2 V- (4) (13) V+ SUBSTRATE (12) NC GND (5) (11) S3 S4 (6) (7) D4 11 (8) IN4 (9) IN3 (10) D3 FN3281.10 November 20, 2006 DG441, DG442 Dual-In-Line Plastic Packages (PDIP) N E16.3 (JEDEC MS-001-BB ISSUE D) E1 INDEX AREA 1 2 3 16 LEAD DUAL-IN-LINE PLASTIC PACKAGE N/2 INCHES -B- SYMBOL -AE D BASE PLANE -C- SEATING PLANE A2 A L D1 e B1 D1 eA A1 eC B 0.010 (0.25) M C L C A B S C eB NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. MILLIMETERS MIN MAX MIN MAX NOTES A - 0.210 - 5.33 4 A1 0.015 - 0.39 - 4 A2 0.115 0.195 2.93 4.95 - B 0.014 0.022 0.356 0.558 - B1 0.045 0.070 1.15 1.77 8, 10 C 0.008 0.014 0.204 0.355 - D 0.735 0.775 18.66 19.68 5 D1 0.005 - 0.13 - 5 E 0.300 0.325 7.62 8.25 6 E1 0.240 0.280 6.10 7.11 5 e 0.100 BSC 2.54 BSC - 3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95. eA 0.300 BSC 7.62 BSC 6 eB - 0.430 - 10.92 7 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. L 0.115 0.150 2.93 3.81 4 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . N 16 16 9 Rev. 0 12/93 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). 12 FN3281.10 November 20, 2006 DG441, DG442 Small Outline Plastic Packages (SOIC) M16.15 (JEDEC MS-012-AC ISSUE C) N INDEX AREA H 0.25(0.010) M 16 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE B M INCHES E -B1 2 3 L SEATING PLANE -A- A D h x 45° -C- e A1 B 0.25(0.010) M C 0.10(0.004) C A M SYMBOL MIN MAX MIN MAX NOTES A 0.0532 0.0688 1.35 1.75 - A1 0.0040 0.0098 0.10 0.25 - B 0.013 0.020 0.33 0.51 9 C 0.0075 0.0098 0.19 0.25 - D 0.3859 0.3937 9.80 10.00 3 E 0.1497 0.1574 3.80 4.00 4 e α B S 0.050 BSC - 0.2284 0.2440 5.80 6.20 - h 0.0099 0.0196 0.25 0.50 5 L 0.016 0.050 0.40 1.27 6 α 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 1.27 BSC H N NOTES: MILLIMETERS 16 0° 16 8° 0° 7 8° Rev. 1 6/05 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. 13 FN3281.10 November 20, 2006 DG441, DG442 Thin Shrink Small Outline Plastic Packages (TSSOP) M16.173 N 16 LEAD THIN SHRINK SMALL OUTLINE PLASTIC PACKAGE INDEX AREA E 0.25(0.010) M E1 2 INCHES GAUGE PLANE -B1 B M 0.05(0.002) -A- SYMBOL MIN MAX MIN MAX NOTES A - 0.043 - 1.10 - A1 3 L A D -C- e α A1 b 0.10(0.004) M 0.25 0.010 SEATING PLANE c 0.10(0.004) C A M 0.05 0.15 - A2 0.033 0.037 0.85 0.95 - b 0.0075 0.012 0.19 0.30 9 c 0.0035 0.008 0.09 0.20 - B S 0.002 D 0.193 0.201 4.90 5.10 3 0.169 0.177 4.30 4.50 4 0.026 BSC E 0.246 L 0.020 N α NOTES: 0.006 E1 e A2 MILLIMETERS 0.65 BSC 0.256 6.25 0.028 0.50 16 0o - 6.50 - 0.70 6 16 8o 0o 7 8o 1. These package dimensions are within allowable dimensions of JEDEC MO-153-AB, Issue E. Rev. 1 2/02 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E1” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. (Angles in degrees) All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 14 FN3281.10 November 20, 2006