Revised November 1999 DM93L14 Quad Latch General Description Features The DM93L14 is a multifunctional 4-bit latch designed for general purpose storage applications in high speed digital systems. All outputs have active pull-up circuitry to provide high capacitance drive and to provide low impedance in both logic states for good noise immunity. ■ Can be used as single input D latches or set/reset latches ■ Active low enable gate input ■ Overriding master reset Ordering Code: Order Number Package Number DM93L14N N14A Package Description 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Logic Symbol Connection Diagram VCC = Pin 16 GND = Pin 8 Pin Descriptions Pin Names Description E Enable Input (Active LOW) D0 − D3 Data Inputs S0 − S3 Set Inputs (Active LOW) MR Master Reset Input (Active LOW) Q0 − Q3 Latch Outputs © 1999 Fairchild Semiconductor Corporation DS009612 www.fairchildsemi.com DM93L14 Quad Latch June 1989 DM93L14 Functional Description Truth Table The DM93L14 consists of four latches with a common active LOW Enable input and active LOW Master Reset input. When the Enable goes HIGH, data present in the latches is stored and the state of the latch is no longer affected by the Sn and Dn inputs. the Master Reset when activated overrides all other input conditions forcing all latch outputs LOW. Each of the four latches can be operated in one of two modes: D-TYPE LATCH—For D-type operation the S input of a latch is held LOW. While the common Enable is active the latch output follows the D input. Information present at the latch output is stored in the latch when the Enable goes HIGH. SET/RESET LATCH—During set/reset operation when the common Enable is LOW a latch is reset by a LOW on the D input, and can be set by a LOW on the S input if the D input is HIGH. If both S and D inputs are LOW, the D input will dominate and the latch will be reset. When the Enable goes HIGH, the latch remains in the last state prior to disablement. The two modes of latch operation are shown in the Truth Table. E D S Qn H L L L L H L H L L Qn-1 H H X X H L L L L H L H L H H L L H L H L H H Qn-1 H H X X Qn-1 L X X X L H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Qn−1 = Previous Output State Qn = Present Output State Logic Diagram www.fairchildsemi.com MR 2 Operation D Mode R/S Mode RESET Supply Voltage Note 1: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The Recommended Operating Conditions table will define the conditions for actual device operation. 7V Input Voltage 5.5V Operating Free Air Temperature Range 0°C to +70°C −65°C to +150°C Storage Temperature Range Recommended Operating Conditions Symbol Parameter VCC Supply Voltage VIH HIGH Level Input Voltage VIL LOW Level Input Voltage IOH HIGH Level Output Voltage Min Nom Max 4.5 5 5.5 2 IOL LOW Level Output Current TA Free Air Operating Temperature tS (H) Setup Time HIGH or LOW 10 tS (L) Dn to E 20 −55 Units V V 0.7 V −400 µA 4.8 mA 125 °C ns tH (H) Hold Time HIGH or LOW 0 tH (L) Dn to E 10 tS (H) Setup time HIGH, Dn to Sn 15 ns ns tH (L) Hold time LOW, Dn to Sn 5 ns tW (L) E Pulse Width LOW 30 ns tW (L) MR Pulse Width LOW 25 ns tREC Recovery time, MR to E 5 ns 3 www.fairchildsemi.com DM93L14 Absolute Maximum Ratings(Note 1) DM93L14 Electrical Characteristics Over recommended operating free air temperature range (unless otherwise noted) Symbol Parameter Conditions VI Input Clamp Voltage VCC = Min, II = −10 mA VOH HIGH Level Output Voltage VCC = Min, IOH = Max, LOW Level Output Voltage (Note 2) Input Current @ Max VCC = Min, IOL = Max, VCC = Max, VI = 5.5V Input Voltage IIH IIL IOS ICC HIGH Level Input Current LOW Level Input Current VCC = Max, VI = 2.4V VCC = Max, VI = 0.3V Short Circuit VCC = Max Output Current (Note 3) Supply Current VCC = Max (Note 4) Units −1.5 V V VIH = Min, VIL = Max II Max 2.4 VIL = Max, VIH = Min VOL Typ Min 0.3 V 1 mA Inputs 20 Dn 30 Inputs −400 Dn −600 −2.5 µA µA −25 mA 16.5 mA Note 2: All typicals are at VCC = 5V, TA = 25°C Note 3: Not more than one output should be shorted at a time, and the duration should not exceed one second. Note 4: ICC is measured with all outputs open and all inputs grounded. Switching Characteristics VCC = +5.0V, TA = +25°C (See Waveforms and Load Configurations) Symbol Parameter Min Max Units tPLH Propagation Delay 45 tPHL E to Qn 36 tPLH Propagation Delay 30 tPHL Dn to Qn 30 tPLH Propagation Delay, MR to Qn 30 ns tPHL Propagation Delay, Sn to Qn 33 ns www.fairchildsemi.com 4 ns ns DM93L14 Quad Latch Physical Dimensions inches (millimeters) unless otherwise noted 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N14A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 5 www.fairchildsemi.com