AD OP221 Dual low power operational amplifier, single or dual supply Datasheet

a
Dual Low Power Operational Amplifier,
Single or Dual Supply
OP221
FEATURES
Excellent TCV OS Match, 2 ␮V/ⴗC Max
Low Input Offset Voltage, 150 ␮V Max
Low Supply Current, 550 ␮A Max
Single Supply Operation, 5 V to 30 V
Low Input Offset Voltage Drift, 0.75 ␮V/ⴗC
High Open-Loop Gain, 1500 V/mV Min
High PSRR, 3 ␮V/V
Wide Common-Mode Voltage
Range, V– to within 1.5 V of V+
Pin Compatible with 1458, LM158, LM2904
Available in Die Form
PIN CONNECTIONS
8-Lead SOIC
(S-Suffix)
+IN A 1
8
–IN A
V– 2
7
OUT A
+IN B 3
6
V+
–IN B 4
5
OUT B
NC = NO CONNECT
GENERAL DESCRIPTION
The OP221 is a monolithic dual operational amplifier that can
be used either in single or dual supply operation. The wide
supply voltage range, wide input voltage range, and low supply
current drain of the OP221 make it well-suited for operation
from batteries or unregulated power supplies.
provide high performance in instrumentation amplifier designs.
The individual amplifiers feature very low input offset voltage,
low offset voltage drift, low noise voltage, and low bias current.
They are fully compensated and protected.
Matching between channels is provided on all critical parameters
including input offset voltage, tracking of offset voltage vs. temperature, non-inverting bias currents, and common-mode rejection.
The excellent specifications of the individual amplifiers combined
with the tight matching and temperature tracking between channels
SIMPLIFIED SCHEMATIC
V+
Q11
Q28
Q12
Q3
–IN
Q26
Q4
Q1
OUTPUT
Q2
Q9
+IN
Q27
Q10
Q7
Q4
Q29
Q6
Q5
Q13
NULL*
Q33
V–
*ACCESSIBLE IN CHIP FORM ONLY
REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2002
OP221–SPECIFICATIONS (Electrical Characteristics at V = ⴞ2.5 V to ⴞ15 V, T = 25ⴗC, unless otherwise noted.)
s
A
OP221G
Parameter
Symbol
Conditions
Input Offset Voltage
VOS
Input Offset Current
Ios
VCM = 0
Input Bias Current
IB
VCM = 0
Min
1
IVR
V+ = 5 V, V– = 0 V
VS = ± 15 V
Common-Mode
Rejection Ratio
CMRR
V+ = –5 V, V– = 0 V
0 V £ VCM £ 3.5 V
VS = ± 15 V
–15 V £ VCM £ 13.5 V
Power Supply
Rejection Ratio
PSRR
VS = ± 2.5 V to ± 15 V
V– = 0 V, V+ = 5 V to 30 V
Large-Signal
Voltage Gain
Avo
VS = ± 15 V, RL = 10 kW
VO = ± 10 V
Output Voltage
Swing
VO
V+ = 5 V, V– = 0 V
RL = 10 kW
VS = 15 V, RL = 10 kW
SR
Bandwidth
BW
Supply Current
(Both Amplifiers)
ISY
RL = 10 kW
Max
Unit
250
500
mV
1.5
7
nA
70
120
nA
0/3.5
–15/13.5
Input Voltage Range
Slew Rate
Typ
2
75
85
80
90
dB
32
57
–2–
100
180
mV/V
800
V/mV
0.8/4
V
± 13.5
0.2
VS = ± 2.5 V, No Load
VS = ± 15 V, No Load
V
0.3
V/mS
600
kHz
550
850
650
900
mA
REV. C
OP221
SPECIFICATIONS (Electrical Characteristics at V = ⴞ2.5 V to ⴞ15 V, –40ⴗC £ T £ +85ⴗC, unless otherwise noted.)
S
A
OP221G
Parameter
Symbol
Average Input
Offset Voltage Drift1
Conditions
Min
Typ
Max
Unit
TCVOS
2
3
mV/∞C
Input Offset Voltage
VOS
400
700
mV
Input Offset Current
IOS
VCM = 0
2
10
nA
Input Bias Current
IB
VCM = 0
80
140
nA
2
Input Voltage Range
IVR
V+ = 5 V, V– = 0 V
VS = ± 15 V
Common-Mode
Rejection Ratio
CMRR
V+ = –5 V, V– = 0 V
0 V £ VCM £ 3.5 V
VS = ± 15 V
–15 V £ VCM £ 13.5 V
0/3.2
–15/13.2
PSRR
VS = ± 2.5 V to ± 15 V
V– = 0 V, V+ = 5 V to 30 V
Large-Signal
Voltage Gain
AVO
VS = ± 15 V, RL = 10 kW
VO = ± 10 V
Output Voltage
Swing
VO
ISY
70
80
75
85
dB
Power Supply
Rejection Ratio
Supply Current
(Both Amplifiers)
V
V+ = 5 V, V– = 0 V
RL = 10 kW
VS = 15 V, RL = 10 kW
57
100
180
320
mV/V
V/mV
600
0.9/3.7
V
13.2
VS = ± 2.5 V, No Load
VS = ± 15 V, No Load
600
950
750
1000
mA
NOTES
1
Sample tested.
2
Guaranteed by CMRR test limits.
Matching Characteristics at Vs = ⴞ15 V, TA = 25ⴗC, unless otherwise noted.
OP221G
Parameter
Symbol
Input Offset
Voltage Match
DVOS
Average Noninverting
Bias Current
IB +
Noninverting Input
Offset Current
Conditions
Min
IOS+
Typ
Max
Unit
250
600
mV
120
nA
10
nA
4
Common-Mode
Rejection Ratio
Match1
DCMRR
VCM = –15 V to 13.5 V
Power Supply
Rejection Ratio
Match2
DPSRR
VS = ± 2.5 V to ± 15 V
72
dB
140
mV/V
NOTES
1
DCMRR is 20 log10 VCM/DCME, where VCM is the voltage applied to both noninverting inputs and DCME is the difference in common-mode input-referred error.
2
DPSRR is: Input-Referred Differential Error
DVS
REV. C
–3–
(Matching Characteristics at V = ⴞ15 V, –40ⴗC £ T £ +85ⴗC for OP221G, unless otherOP221–SPECIFICATIONS wise
noted. G is sample tested.)
s
A
.
OP221G
Parameter
Symbol
Input Offset
Voltage Match
DVOS
Conditions
Min
Average Noninverting
Bias Current
IB +
Input Offset
Voltage Tracking
ICDVOS
Noninverting Input
Offset Current
IOS+
VCM = 0
Common-Mode
Rejection Ratio
Match1
DCMRR
VCM = –15 V to 13.2 V
Power Supply
Rejection Ratio
Match2
DPSRR
Typ
Max
Unit
400
800
mV
140
nA
VCM = 0
72
3
5
mV∞C
6
12
nA
80
dB
140
mV/V
NOTES
1
DCMRR is 20 log10 VCM/DCME, where VCM is the voltage applied to both noninverting inputs and DCME is the difference in common-mode input-referred error.
2
DPSRR is: Input-Referred Differential Error
DVS
–4–
REV. C
OP221
ABSOLUTE MAXIMUM RATINGS (Note 1)
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 18 V
Differential Input Voltage . . . . . . . . . . 30 V or Supply Voltage
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . Supply Voltage
Output Short-Circuit Duration . . . . . . . . . . . . . . . . Indefinite
Storage Temperature Range . . . . . . . . . . . . –65∞C to +150∞C
Operating Temperature Range
OP221G . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40∞C to +85∞C
Lead Temperature (Soldering 60 sec) . . . . . . . . . . . . . . 300∞C
Junction Temperature (TJ) . . . . . . . . . . . . . –65∞C to +150∞C
Package Type
␪JA (Note 2)
␪JC
Unit
8-Lead SOIC(S)
158
43
∞C/W
NOTES
1
Absolute maximum ratings apply to both DICE and packaged parts, unless
otherwise noted.
2
␪JA is specified for device soldered to printed circuit board for SOIC package.
ORDERING GUIDE
TA = +25ⴗC
VOS MAX
(␮V)
Plastic
8-Lead
Operating
Temperature
Range
Package
Options
150
150
300
500
500
500
OP221GS
XIND
RN-8
Figure 1. Dice Characteristics
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the OP221 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
REV. C
–5–
WARNING!
ESD SENSITIVE DEVICE
OP221–Typical Perfomance Characteristics
140
140
140
dc
dc
120
100Hz
80
1kHz
60
40
VS = ⴞ15V
–25
100Hz
80
1kHz
60
40
VS = ⴞ15V
20
20
0
–50
10Hz
100
0
25
50
75
100
80
60
40
20
0
–50
125
TA = 25ⴗC
RL = 15k⍀
100
–25
0
25
50
75
100
0
125
ⴞ5
0
TEMPERATURE – ⴗC
TEMPERATURE – ⴗC
TPC 1. Open-Loop Gain at ± 15 V vs.
Temperature
ⴞ10
ⴞ15
SUPPLY VOLTAGE – V
TPC 2. Open-Loop Gain at ± 5 V vs.
Temperature
TPC 3. Open-Loop Gain at vs.
Supply Voltage
70
25
60
20
80
80
VS = ⴞ15V
60
VS = ⴞ5V
40
20
50
VOLTAGE GAIN – dB
100
CLOSED-LOOP GAIN – dB
OPEN-LOOP GAIN – dB
120
40
30
20
10
0
TA = 25ⴗC
VS = ⴞ15V
120
15
⵰m = 42ⴗ
140
10
160
5
GAIN
PHASE
0
180
–5
200
0
1
10
100
1k
10k 100k
220
–10
100k
1M 10M
1M
FREQUENCY – Hz
120
VS = ⴞ15V
PHASE MARGIN
850k
45
40
GAIN BANDWIDTH
800k
750k
650k
100
TA = 25ⴗC
VS = ⴞ15V
100
+PSRR
80
80
CMRR – Hz
50
10M
TPC 6. Gain and Phase Shift vs.
Frequency
120
55
60
–PSRR
60
40
40
SLEW RATE
0.30
20
0.25
0.20
–50
10
TPC 5. Closed-Loop Gain vs.
Frequency
700k
SLEW RATE –
V/␮sec
1
FREQUENCY – Hz
PSRR – dB
PHASE MARGIN –
Degrees
TPC 4. Open-Loop Gain at ± 15 V vs.
Frequency
0.35
–10
100 1k 10k 100k 1M 10M
FREQUENCY – Hz
GAIN BANDWIDTH – Hz
0.1
100
PHASE SHIFT – Degrees
10Hz
100
120
OPEN-LOOP GAIN – dB
OPEN-LOOP GAIN – dB
OPEN-LOOP GAIN – dB
120
–25
0
25
50
75
100
125
TEMPERATURE – ⴗC
TPC 7. Phase Margin, Gain Bandwidth,
and Slew Rate vs. Temperature
0
10
TA = 25ⴗC
VS = ⴞ15V
20
0
100
1k
10k
FREQUENCY – Hz
TPC 8. PSRR vs. Frequency
–6–
100k
1
10
100
1k
10k
100k
FREQUENCY – Hz
TPC 9. CMRR vs. Frequency
REV. C
OP221
16
28
24
20
16
12
8
2.0
12
POSITIVE
10
NEGATIVE
8
6
4
TA = 25ⴗC
VS = ⴞ2.5V
NEGATIVE
POSITIVE
1.0
2
4
0
100
0
1K
10k
100k
FREQUENCY – Hz
1M
TPC 10. Maximum Output Swing
vs. Frequency
1k
10k
LOAD RESISTANCE – ⍀
100k
10
CURRENT NOISE – pA Hz
80
70
60
50
40
30
20
10
1.0
0.1
1
10
100
1k
FREQUENCY – Hz
TPC 13. Voltage Noise Density vs.
Frequency
REV. C
1
10
100
1k
FREQUENCY – Hz
TPC 13. Current Noise Density vs.
Frequency
–7–
0
100
1k
10k
100k
LOAD RESISTANCE – ⍀
TPC 11. Maximum Output Voltage
vs. Load Resistance
100
VOLTAGE NOISE – nV/ Hz
TA = 25ⴗC
VS = ⴞ15V
14
MAXIMUM OUTPUT – V
TA = 25ⴗC
VS = ⴞ15V
RL = 10k⍀
MAXIMUM OUTPUT – V
PEAK-TO-PEAK AMPLITUTDE – V
30
TPC 12. Maximum Output Voltage
vs. Load Resistance
OP221
Figure 2a. Noninverting Step Response
Figure 3a. Inverting Step Response
Figure 2b. Noninverting Step Response
Figure 3b. Inverting Step Response
INPUT
10k⍀
OUTPUT
INPUT
10k⍀
10k⍀
OUTPUT
Figure 4. Noninverting Test Circuit
Figure 5. Inverting Test Circuit
–8–
REV. C
OP221
SPECIAL NOTES ON THE APPLICATION OF DUAL
MATCHED OPERATIONAL AMPLIFIERS
Advantages of Dual Monolithic Operational Amplifiers
Dual matched operational amplifiers provide the engineer with a
powerful tool for designing instrumentation amplifiers and many
other differential-input circuits. These designs are based on the
principle that careful matching between two operational amplifiers
can minimize the effect of dc errors in the individual amplifiers.
Reference to the circuit shown in Figure 6, a differential-in,
differential-out amplifier, shows how the reductions in error can
be accomplished. Assuming the resistors used are ideally matched,
the gain of each side will be identical. If the offset voltages of
each amplifier are perfectly matched, then the net differential
voltage at the amplifier’s output will be zero. Note that the output
offset error of this amplifier is not a function of the offset voltage
of the individual amplifiers, but only a function of the difference
(degree of matching) between the amplifiers’ offset voltages. This
error-cancellation principle holds for a considerable number of
input referred error parameters—offset voltage, offset voltage
drift, inverting and noninverting bias currents, common mode
and power supply rejection ratios. Note also that the impedances
of each input, both common-mode and differential-mode, are
high and tightly matched, an important feature not practical with
single operation amplifier circuits.
INSTRUMENTATION AMPLIFIER APPLICATIONS
Two-Op Amp Configuration
The two-op amp circuit (Figure 7) is recommended where the
common-mode input voltage range is relatively limited; the
common-mode and differential voltage both appear at V1. The
high open-loop gain of the OP221 is very important in achieving
good CMRR in this configuration. Finite open-loop gain of A1
(Ao1) causes undesired feedthrough of the common-mode input.
For Ad/Ao, << 1, the common-mode error (CME) at the output due to this effect is approximately (2 Ad/Ao1) x VCM. This
circuit features independent adjustment of CMRR and differential gain.
Three-Op Amp Configuration
The three-op amp circuit (Figure 8) has increased commonmode voltage range because the common-mode voltage is not
amplified as it is in Figure 7. The CMR of this amplifier is directly
proportional to the match of the CMR of the input op amps. CMRR
can be raised even further by trimming the output stage resistors.
R0
GAIN
ADJ
R2
R1
AD = 2 1+ R1
R0
1/2
OP221
R3
R4
V1
A1
VCM – 1/2VD
–
1/2
R3
OP221
Vd
R1
+
OP221
INPUT
VCM + 1/2VD
+
R4
VO = R3
OUTPUT
1+1
2
R2 + R3
R1 R4
–
R2
SIDE
‘R’
VO – ADVD
A2
+
SIDE
‘A’
+
R2 + R3
R0
Vd + R4
R3
R3 – R2
R4 R1
IF R1 = R2 = R3 = R4, THEN VO = 2 1 + R1 VD
R0
–
Figure 7. Two-Op Amp Circuit
R4
R1
VO = 2 1 +
Figure 6. Differential-In, Differential-Out Amplifier
VCM – 1/2VD
1/2
R0
V1
VD
V+
OP221
OP221
A3
R1
Vd
2R1
R0
R2
R2
A1
–
V+
R2
–
VCM + 1/2VD
A2
1/2
V2
OP221
V–
R2
V–
Figure 8. Three-Op Amp Circuit
REV. C
VCM
–9–
VO
OP221
OUTLINE DIMENSIONS
8-Lead Standard Small Outline Package [SOIC]
Narrow Body
(RN-8)
Dimensions shown in millimeters and (inches)
5.00 (0.1968)
4.80 (0.1890)
4.00 (0.1574)
3.80 (0.1497)
8
5
1
4
1.27 (0.0500)
BSC
0.25 (0.0098)
0.10 (0.0040)
COPLANARITY
SEATING
0.10
PLANE
6.20 (0.2440)
5.80 (0.2284)
1.75 (0.0688)
1.35 (0.0532)
0.51 (0.0201)
0.33 (0.0130)
0.50 (0.0196)
ⴛ 45ⴗ
0.25 (0.0099)
8ⴗ
0.25 (0.0098) 0ⴗ 1.27 (0.0500)
0.41 (0.0160)
0.19 (0.0075)
COMPLIANT TO JEDEC STANDARDS MS-012AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
–10–
REV. C
OP221
Revision History
Location
Page
10/02—Data Sheet changed from REV. B to REV. C.
Deleted 8-Lead CERDIP Package (Q-8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Universal
Edits to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–4
Edits to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Edits to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
6/02—Data Sheet changed from REV. A to REV. B.
Edits to 8-Lead SOIC Package (R-8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
09/01—Data Sheet changed from REV. 0 to REV. A.
Edits to PIN CONNECTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Global deletion of references to OP221B and OP221C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2, 3, 4
Edits to WAFER TEST LIMITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Edits to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Edits to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Edits to PACKAGE TYPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
REV. C
–11–
–12–
PRINTED IN U.S.A.
C00324–0–10/02(C)
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