HANBit HDD32M64F8 DDR SDRAM Module 256Mbyte (32Mx64bit), based on 32Mx8, 4Banks, 8K Ref., SMM, Part No. HDD32M64F8 GENERAL DESCRIPTION The HANBiT HDD32M64F8 is 32M bit x 64 Double Data Rate SDRAM high density memory modules. The HANBiT HDD32M64F8 consists of eight CMOS 32M x 8 bit with 4banks Double Data Rate SDRAMs in 66pin TSOP-II(400mil) packages mounted on a 200pin glass-epoxy substrate. Four 0.1uF decoupling capacitors are mounted on the printed circuit board in parallel for each DDR SDRAM. The HDD32M64F8 is Dual In-line Memory Modules and inten-ded for mounting into 200pin edge connector sockets. Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are possible on both edges of DQS. Range of operating frequencies, programmable latencies and burst lengths allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. FEATURES • Part Identification HDD32M64F8 – 10A : 100MHz (CL=2) HDD32M64F8 – 13A : 133MHz (CL=2) HDD32M64F8 – 13B : 133MHz (CL=2.5) • Power supply : VDD: 2.5V ± 0.2V, VDDQ: 2.5V ± 0.2V • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition • Programmable Read latency 2, 2.5 (clock) • Programmable Burst length (2, 4, 8) • Programmable Burst type (sequential & interleave) • Edge aligned data output, center aligned data input • Auto & Self refresh, 7.8us refresh interval(8K/64ms refresh) • Serial presence detect with EEPROM URL : www.hbe.co.kr REV 2.0 (November.2002) 1 HANBit Electronics Co.,Ltd. HANBit HDD32M64F8 PIN ASSIGNMENT P1 P2 PIN Symbol PIN Symbol PIN Symbol PIN Symbol PIN Symbol PIN Symbol 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 /CS0 NC VSS CKE0 NC NC VDD CK0 CK1 NC VSS NC DM0 DM4 VDDQ NC NC VSS NC DQS0 DQS4 VDD NC DQ0 DQ1 VSS DQ2 DQ3 VDDQ DQ4 DQ5 DQ6 VSS DQ7 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 DQ15 DQ14 VDDQ DQ13 DQ12 DQ11 VSS DQ10 DQ9 DQ8 VDD *SA0 *SA1 VSS *SA2 VDDQ VDD /RAS VSS /CAS /CK0 /CK1 VDD /CK2 CK2 /WE VSS NC DM1 DM5 VDDQ NC VREF VSS 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 NC DQS1 DQS5 VDD NC DQ39 DQ38 VSS DQ37 DQ36 VDDQ DQ35 DQ34 DQ33 VSS DQ32 DQ40 DQ41 VDDQ DQ42 DQ43 DQ44 VSS DQ45 DQ46 DQ47 *SCL *WP *VSPD VSS *SDA VDDIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 VDDQ A3 VSS A2 A1 A0 VDD A10 A11 BA0 VSS BA1 DM2 DM6 VDDQ NC NC VSS DQS7 DQS2 NC VDD DQ31 DQ30 DQ29 VSS DQ28 DQ27 VDDQ DQ26 DQ25 DQ24 VSS DQ16 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 DQ17 DQ18 VDDQ DQ19 DQ20 DQ21 VSS DQ22 DQ23 NC(CB6) VDD NC(CB4) NC(CB2) VSS NC(CB0) VDDQ VDD A4 VSS A5 A6 A7 VDD A8 A9 A12 VSS DM3 DM7 NC(DM8) VDDQ NC NC(A13) VSS 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 NC(DQS8) DQS3 DQS6 VDD DQ56 DQ57 DQ58 VSS DQ59 DQ60 VDDQ DQ61 DQ62 DQ63 VSS DQ55 DQ54 DQ53 VDDQ DQ52 DQ51 DQ50 VSS DQ49 DQ48 NC(CB7) VDD NC(CB5) NC(CB3) VSS NC(CB1) VDD * These pins should be NC in the system which does not support SPD PIN PIN DESCRIPTION PIN PIN DESCRIPTION A0~A12 Address input VDD Power supply(2.5V) BA0~BA1 Bank Select Address VDDQ Power supply for DQs(2.5V) DQ0~DQ63 Data input/output VREF Power supply for reference Serial EEPROM Power supply(3.3) CB0~CB7 Check bit(Data input/output) VSPD DQS0~DQS7 Data Strobe input/output VSS Ground DM0~DM7 Data-in Mask SA0~SA2 Address in EEPROM CK0~CK2,/CK0~/CK2 Clock input SDA Serial data I/O CKE0 Clock enable input SCL Serial clock /CS0 Chip Select input WP Write protection /RAS Row Address strobe VDDIN VDD indentification flag /CAS Column Address strobe NC No connection URL : www.hbe.co.kr REV 2.0 (November.2002) 2 HANBit Electronics Co.,Ltd. HANBit HDD32M64F8 FUNCTIONAL BLOCK DIAGRAM URL : www.hbe.co.kr REV 2.0 (November.2002) 3 HANBit Electronics Co.,Ltd. HANBit HDD32M64F8 PIN FUNCTION DESCRIPTION Pin CK, /CK Name Clock Input Function CK and /CK are differential clock inputs. All address and control input signals are sampled on the positive edge of CK and negative edge of CK. Output (read) data is referenced to both edges of CK. Internal clock signals are derived from CK/CK. CKE HIGH activates, and CKE LOW deactivates internal clock signals, and device input buffers and output drivers. Deactivating the clock provides PRECHARGE POWER-DOWN and SELF REFRESH operation (all banks idle), or ACTIVE CKE Clock Enable POWER-DOWN(row ACTIVE in any bank). CKE is synchronous for all functions except for disabling outputs, which is achieved asynchronously. Input buffers, excluding CK, CK and CKE are disabled during power-down and self refresh modes, providing low standby power. CKE will recognizean LVCMOS LOW level prior to VREF being stable on power-up. /CS enables(registered LOW) and disables(registered HIGH) the command decoder. /CS Chip Select All commands are masked when /CS is registered HIGH. /CS provides for external bank selection on systems with multiple banks. /CS is considered part of the command code. Row/column addresses are multiplexed on the same pins. A0 ~ A12 Address BA0 ~ BA1 Bank select address /RAS Row address strobe /CAS Columnaddress strobe /WE Write enable DQS0 ~ 7 Data Strobe Row address : RA0 ~ RA12, Column address : CA0 ~ CA9 BA0 and BA1 define to which bank an ACTIVE, READ, WRITE or PRE-CHARGE command is being applied. Latches row addresses on the positive going edge of the CLK with /RAS low. Enables row access & precharge. Latches column addresses on the positive going edge of the CLK with /CAS low. Enables column access. Enables write operation and row precharge. Latches data in starting from /CAS, /WE active. Output with read data, input with write data. Edge-aligned with read data, centered in write data. Used to capture write data. DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH along with that input data during a WRITE access. DM is sampled DM0~7 Input Data Mask on both edges of DQS. DM pins include dummy loading internally, to matches the DQ and DQS load-ing. DQ0 ~ 63 Data input/output Data inputs/outputs are multiplexed on the same pins. WP pin is connected to Vcc. WP Write Protection When WP is “high”, EEPROM Programming will be inhibited and the entire memory will be write-protected. VDDQ Supply DQ Power Supply : +2.5V ± 0.2V. VDD Supply Power Supply : +2.5V ± 0.2V (device specific). VSS Supply DQ Ground. VREF Supply SSTL_2 reference voltage. URL : www.hbe.co.kr REV 2.0 (November.2002) 4 HANBit Electronics Co.,Ltd. HANBit HDD32M64F8 ABSOLUTE MAXIMUM RATINGS PARAMETER SYMBOL RATING UNTE VIN, VOUT -0.5 ~ 3.6 V Voltage on VDD supply relative to Vss VDD -1.0 ~ 3.6 V Voltage on VDDQ supply relative to Vss VDDQ -0.5 ~ 3.6 V Storage temperature TSTG -55 ~ +150 °C PD 8.0 W Short circuit current IOS 50 Notes: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. mA Voltage on any pin relative to Vss Power dissipation Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. POWER & DC OPERATING CONDITIONS (Recommended operating conditions (Voltage referenced to Vss = 0V, TA = 0 to 70°C) ) PARAMETER Supply Voltage I/O Supply Voltage SYMBOL MIN MAX UNIT VDD 2.3 2.7 V VDDQ 2.3 2.7 V NOTE I/O Reference Voltage VREF VDDQ/2-50mV VDDQ/2+50mV V 1 I/O Termination Voltage(system) VTT VREF – 0.04 VREF + 0.04 V 2 Input High Voltage VIH (DC) VREF + 0.15 VREF + 0.3 V Input Low Voltage VIL (DC) -0.3 VREF - 0.15 V Input Voltage Level, CK and /CK inputs VIN (DC) -0.3 VDDQ + 0.3 V Input Differential Voltage, CK and /CK inputs VID (DC) 0.3 VDDQ + 0.6 V Input leakage current I LI -2 2 uA Output leakage current I OZ -5 5 uA Output High current (VOUT = 1.95V) I OH -16.8 mA Output Low current (VOUT = 0.35V) I OL 16.8 mA Output High Current(Half strengh driver) IOH -9 mA Output High Current(Half strengh driver) IOL 9 mA 3 Notes 1. Includes ± 25mV margin for DC offset on VREF, and a combined total of ± 50mV margin for all AC noise and DC offset on VREF, bandwidth limited to 20MHz. The DRAM must accommodate DRAM current spikes on VREF and internal DRAM noise coupled TO VREF, both of which may result in VREF noise. VREF should be de-coupled with an inductance of £ 3nH. 2. VTT is not applied directly to the device. V TT is a system supply for signal termination resistors, is expected to be set equal to VREF, and must track variations in the DC level of VREF 3. VID is the magnitude of the difference between the input level on CK and the input level on CK. 4. These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in simulation. The AC and DC input specifications are relative to a VREF envelop that has been bandwidth limited to 200MHZ. 5. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the dc level of the same. 6. These charactericteristics obey the SSTL-2 class II standards. URL : www.hbe.co.kr REV 2.0 (November.2002) 5 HANBit Electronics Co.,Ltd. HANBit HDD32M64F8 INPUT/OUTPUT CAPACITANCE (VDD = 2.5V, VDDQ = 2.5V, TA = 25°C, f = 1MHz) DESCRIPTION SYMBOL MIN MAX UNITS Input Capacitance(A0 ~ A12, BA0 ~ BA1,RAS,CAS, WE ) CIN1 49 57 pF Input Capacitance(CKE0) CIN2 42 50 pF Input Capacitance( CS0) CIN3 42 50 pF Input Capacitance( CLK0, CLK1,CLK2 ) CIN4 22 25 pF COUT1 6 8 pF CIN5 6 8 pF Data & DQS input/output Capacitance(DQ0~DQ63) Input Capacitance(DM0~DM8) AC OPERATING CONDITIONS PARAMETER/ CONDITION STMBOL MIN Input High (Logic 1) Voltage, DQ, DQS and DM signals VIH (AC) VREF + 0.31 Input Low (Logic 0) Voltage, DQ, DQS and DM signals. VIL (AC) Input Differential Voltage, CK and CK inputs VID (AC) Input Crossing Point Voltage, CK and CK inputs VIX (AC) MAX UNIT NOTE 3 VREF - 0.31 V 3 0.7 VDDQ+0.6 V 1 0.5*VDDQ-0.2 0.5*VDDQ+0.2 V 2 Note 1. VID is the magnitude of the difference between the input level on CK and the input on CK. 2. The value of V IX is expected to equal 0.5* VDDQ of the transmitting device and must track variations in the DC level of the same. 3. These parameters should be tested at the pim on actual components and may be checked at either the pin or the pad in simulation. the AC and DC input specificatims are refation to a VREF envelope that has been bandwidth limited 20MHz. AC OPERATING TEST CONDITIONS PARAMETER VALUE UNIT Input reference voltage for Clock 0.5 * VDDQ V Input signal maximum peak swing 1.5 V Input signal minimum slew rate 0.5 V/ns VREF+0.31/VREF-0.31 V Input timing measurement reference level VREF V Output timing measurement reference level VTT V See Load Circuit V Input Levels(VIH/VIL) Output load condition URL : www.hbe.co.kr REV 2.0 (November.2002) 6 NOTE HANBit Electronics Co.,Ltd. HANBit HDD32M64F8 AC TIMMING PARAMETERS & SPECIFICATIONS (THESEACCHARICTERISTICSWERETESTEDON THECOMPONENT) PARAMETER DDR200 DDR266A DDR266B -10A -13A -13B SYMBOL MIN MAX MIN MAX MIN UNIT NOTE MAX Row cycle time tRC 70 65 65 ns 1 Refresh row cycle time tRFC 80 75 75 ns 1,2 Row active time tRAS 48 ns 1,2 /RAS to /CAS delay tRCD 20 20 20 ns 3 Row precharge time tRP 20 20 20 ns 3 Row active to Row active delay tRRD 15 15 15 ns 3 Write recovery time tWR 2 2 2 tCK 3 Last data in to Read command tCDLR 1 1 1 tCK 2 Col. address to Col. address delay tCCD 1 1 1 tCK CL=2.0 Clock cycle time 10 120K 45 120K 45 120K 12 7.5 12 10 12 ns 12 7.5 12 7.5 12 ns tCK CL=2.5 Clock high level width tCH 0.45 0.55 0.45 0.55 0.45 0.55 tCK Clock low level width tCL 0.45 0.55 0.45 0.55 0.45 0.55 tCK tDQSCK -0.8 +0.8 -0.75 +0.75 -0.75 +0.75 ns Output data access time from CK/CK tAC -0.8 +0.8 -0.75 +0.75 -0.75 +0.75 ns Data strobe edge to ouput data edge tDQSQ - +0.6 - +0.5 - +0.5 ns Read Preamble tRPRE 0.9 1.1 0.9 1.1 0.9 1.1 tCK Read Postamble tRPST 0.4 0.6 0.4 0.6 0.4 0.6 tCK Data out high impedence time from CK-/CK tHZQ -0.8 +0.8 -0.75 +0.75 -0.75 +0.75 ns CK to valid DQS-in tDQSS 0.75 1.25 0.75 1.25 0.75 1.25 tCK DQS-in setup time tWPRES 0 0 0 ns DQS-in hold time tWPREH 0.25 0.25 0.25 tCK DQS-in falling edge to CK rising-setup time tDSS 0.2 0.2 0.2 tCK DQS-in falling edge to CK rising hold time tDSH 0.2 0.2 0.2 tCK DQS-in high level width tDQSH 0.35 0.35 0.35 tCK DQS-in low level width tDQSL 0.35 0.35 0.35 tCK DQS-in cycle time tDSC 0.9 Address and Control Input setup time tIS 1.1 0.9 0.9 ns Address and Control Input hold time tIH 1.1 0.9 0.9 ns Mode register set cycle time tMRD 16 15 15 ns DQ & DM setup time to DQS tDS 0.6 0.5 0.5 ns DQ & DM hold time to DQS tDH 0.6 0.5 0.5 ns DQ & DM input pulse width tDIPW 2 1.75 1.75 ns Power down exit time tPDEX 10 10 10 ns DQS-out access time from CK/CK URL : www.hbe.co.kr REV 2.0 (November.2002) 7 1.1 0.9 1.1 0.9 1.1 tCK HANBit Electronics Co.,Ltd. 2 3 HANBit HDD32M64F8 Exit self refresh to write command tXSW 116 95 ns Exit self refresh to bank active command tXSA 80 75 75 ns Exit self refresh to read command tXSR 200 200 200 Cycle Refresh interval time tREF 15.6 15.6 15.6 us Output DQS valid window tQH 0.35 0.35 0.35 tCK DQS write postamble time tWPST 0.25 0.25 0.25 tCK Notes : 1. Maximum burst refresh cycle : 8 2. The specific requirement is that DQS be valid(High or Low) on or before this CK edge. The case shown(DQS going from High_Z to logic Low) applies when no writes were previously in progress on the bus. If a previous write was in progress, DQS could be High at this time, depending on tDQSS. 3. The maximum limit for this parameter is not a device limit. The device will operate with a great value for this parameter, but system performance (bus turnaround) will degrade accordingly. 4. A write command can be applied with tRCD satisfied after this command. 5. For registered DIMMs, tCL and tCH are ≥ 45% of the period including both the half period jitter (tJIT(HP) ) of the PLL and the half jitter due to crosstalk (tJIT(crosstalk) ) on the DIMM. 6. Input Setup/Hold Slew Rate Derating Input Setup/Hold Slew Rate Δ tIS (V/ns) (ps) 0.5 0 0.4 +50 0.3 +100 Δ tIH (ps) 0 +50 +100 This derating table is used to increase tDS/tDH in the case where the input slew rate is below 0.5V/ns. Input setup/hold slew rate based on the lesser of AC-AC slew rate and DC-DC slew rate. 7. I/O Setup/Hold Slew Rate Derating Input Setup/Hold Slew Rate Δ tIS (V/ns) (ps) 0.5 0 0.4 +75 0.3 +150 Δ tIH (ps) 0 +75 +150 This derating table is used to increase tDS/tDH in the case where the I/O slew rate is below 0.5V/ns. I/O setup/hold slew rate based on the lesser of AC-AC slew rate and DC-DC slew rate. 8. I/O Setup/Hold Plateau Derating I/O Input Level Δ tDS (mV) (ps) +50 ± 280 Δ tDH (ps) +50 This derating table is used to increase tDS/tDH in the case where the input level is flat below VREF ± 310mV for a duration of up to 2ns. 9. I/O Delta Rise/Fall Rate(1/slew-rate) Derating Delta Rise/Fall Rate Δ tDS (ns/V) (ps) 0 0 ±0.25 +50 ±0.5 +100 Δ tDH (ps) 0 +50 +100 This derating table is used to increase tDS/tDH in the case where the DQ and DQS slew rates differ. The Delta Rise/Fall Rate is calated as 1/SlewRate1-1/SlewRate2. For example, if slew rate 1 = 5V/ns and slew rate 2 =.4V/ns then the Delta Rise/Fall Rate =-0/5ns/V. Input S/H slew rate based on larger of AC-AC delta rise/fall rate and DC-DC delta rise/fall rate. 10. This parameter is fir system simulation purpose. It is guranteed by design. 11. For each of the terms, if not already an integer, round to the next highest integer. tCK is actual to the system clock cycle time. URL : www.hbe.co.kr REV 2.0 (November.2002) 8 HANBit Electronics Co.,Ltd. 1 4 HANBit HDD32M64F8 COMMAND TRUTH TABLE (V=VALID, X=DOν¢ T CARE, H=LOGIC HIGH, L=LOGIC LOW) COMMAND CKE n-1 CKE n /CS /RAS /CAS /WE DM BA 0,1 A10/ AP A11 A9~A0 NOTE Register Extended MRS H X L L L L X OP code 1,2 Register Mode register set H X L L L L X OP code 1,2 L L L H X X X X Auto refresh Refresh Self refresh Entry Exit Bank active & Row Addr. Read & column address Write & column address Auto precharge Auto L H H X L H H H H X X X L L H H H X L H L precharge disable Auto X V H X precharge X L H L X L H H L X H X L L H L X Entry H L H X X X L V V V Exit L H X X X X Entry H L H X X X L H H H H X X X L V V V H X X X L H H H Bank selection All banks active power down Precharge power Exit DM No operation command L H H H X X X 3 H (A0 ~ A9) 4 4 Column 4 Address Address (A0 ~ A9) H H 3 Column V L 3 L L X 3 Row address V H H enable Clock suspend or down mode L eable Burst Stop Precharge H precharge disable Auto H 4,6 X V L X H 7 X X X X X X V X X X Note : 1. OP Code : Operand Code. A0 ~ A12 & BA0 ~ BA1 : Program keys. (@EMRS/MRS) 2. EMRS/ MRS can be issued only at all banks precharge state. A new command can be issued 2 clock cycles after EMRS or MRS. 3. Auto refresh functions are same as the CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. 4. BA0 ~ BA1 : Bank select addresses. If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected. If BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank B is selected. If BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank C is selected. If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected. 5. If A10/AP is "High" at row precharge, BA0 and BA1 are ignored and all banks are selected. 6. During burst write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at tRP after the end of burst. 7. Burst stop command is valid at every burst length. 8. DM sampled at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0). 9. This combination is not defined for any function, which means "No Operation(NOP)" in DDR SDRAM. URL : www.hbe.co.kr REV 2.0 (November.2002) 9 5 HANBit Electronics Co.,Ltd. 8 HANBit HDD32M64F8 PACKAGE DIMENSIONS Unit : mm Front – Side Rear-Side URL : www.hbe.co.kr REV 2.0 (November.2002) 10 HANBit Electronics Co.,Ltd. HANBit HDD32M64F8 ORDERING INFORMATION Part Number Density Org. Package Ref. Vcc MODE MAX.frq HDD32M64F8-10A 256MByte 32M x 64 200PIN SMM 8K 2.5V DDR 100MHz/CL2 HDD32M64F8-13A 256MByte 32M x 64 200PIN SMM 8K 2.5V DDR 133MHz/CL2 HDD32M64F8-13B 256MByte 32M x 64 200PIN SMM 8K 2.5V DDR 133MHz/CL2.5 URL : www.hbe.co.kr REV 2.0 (November.2002) 11 HANBit Electronics Co.,Ltd.