GAL26CV12 High Performance E2CMOS PLD Generic Array Logic™ Features Functional Block Diagram • HIGH PERFORMANCE E2CMOS® TECHNOLOGY — 7.5 ns Maximum Propagation Delay — Fmax = 142.8 MHz — 4.5ns Maximum from Clock Input to Data Output — TTL Compatible 16 mA Outputs — UltraMOS® Advanced CMOS Technology I/CLK INPUT RESET 8 I OLMC I/O/Q OLMC I/O/Q OLMC I/O/Q OLMC I/O/Q OLMC I/O/Q OLMC I/O/Q OLMC I/O/Q OLMC I/O/Q OLMC I/O/Q OLMC I/O/Q OLMC I/O/Q OLMC I/O/Q 8 • ACTIVE PULL-UPS ON ALL PINS I • LOW POWER CMOS — 90 mA Typical Icc I 8 PROGRAMMABLE AND-ARRAY (122X52) 8 • E2 CELL TECHNOLOGY — Reconfigurable Logic — Reprogrammable Cells — 100% Tested/100% Yields — High Speed Electrical Erasure (<100ms) — 20 Year Data Retention I I I • TWELVE OUTPUT LOGIC MACROCELLS — Uses Standard 22V10 Macrocells — Maximum Flexibility for Complex Logic Designs I 10 12 12 10 I • PRELOAD AND POWER-ON RESET OF REGISTERS — 100% Functional Testability 8 I • APPLICATIONS INCLUDE: — DMA Control — State Machine Control — High Speed Graphics Processing — Standard Logic Speed Upgrade 8 I 8 I 8 • ELECTRONIC SIGNATURE FOR IDENTIFICATION I PRESET Description Pin Configuration The GAL26CV12, at 7.5 ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest performance 28-pin PLD available on the market. E2 technology offers high speed (<100ms) erase times, providing the ability to reprogram or reconfigure the device quickly and efficiently. DIP I/CLK 4 I 2 I/O/Q I/O/Q I I/CLK I I Expanding upon the industry standard 22V10 architecture, the GAL26CV12 eliminates the learning curve typically associated with using a new device architecture. The generic architecture provides maximum design flexibility by allowing the Output Logic Macrocell (OLMC) to be configured by the user. The GAL26CV12 OLMC is fully compatible with the OLMC in standard bipolar and CMOS 22V10 devices. I PLCC 28 25 I VCC 7 I I Unique test circuitry and reprogrammable cells allow complete AC, DC, and functional testing during manufacture. As a result, Lattice Semiconductor delivers100% field programmability and functionality of all GAL products. In addition, 100 erase/write cycles and data retention in excess of 20 years are specified. GAL26CV12 23 Top View 21 9 I 11 I/O/Q I/O/Q I/O/Q I 19 18 16 I/O/Q 14 I 12 I I I/O/Q I/O/Q I I/O/Q Vcc I/O/Q I I/O/Q GAL 26CV12 I I/O/Q 28 I I 26 5 1 I 7 I I/O/Q I/O/Q I/O/Q I/O/Q 21 GND GND I I/O/Q I/O/Q I I/O/Q I/O/Q I I/O/Q I I/O/Q I I I/O/Q 14 15 I/O/Q Copyright © 2000 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com 26cv12_03 1 June 2000 Specifications GAL26CV12 GAL26CV12 Ordering Information Commercial Grade Specifications Tpd (ns) Tsu (ns) Tco (ns) 7.5 6 4.5 Icc (mA) Ordering # Package 130 GAL26CV12C-7LP 28-Pin Plastic DIP 130 GAL26CV12C-7LJ 28-Lead PLCC GAL26CV12B-10LP 28-Pin Plastic DIP 10 7 7 130 130 GAL26CV12B-10LJ 28-Lead PLCC 15 10 8 130 GAL26CV12B-15LP 28-Pin Plastic DIP 130 GAL26CV12B-15LJ 28-Lead PLCC 20 12 12 130 GAL26CV12B-20LP 28-Pin Plastic DIP 130 GAL26CV12B-20LJ 28-Lead PLCC Industrial Grade Specifications Tpd (ns) Tsu (ns) Tco (ns) Icc (mA) Ordering # Package 10 7 7 150 150 GAL26CV12C-10LJI 28-Lead PLCC 15 10 8 150 GAL26CV12B-15LPI 28-Pin Plastic DIP 150 GAL26CV12B-15LJI 28-Lead PLCC 20 12 12 150 GAL26CV12B-20LPI 28-Pin Plastic DIP 150 GAL26CV12B-20LJI 28-Lead PLCC GAL26CV12C-10LPI 28-Pin Plastic DIP Part Number Description XXXXXXXX _ XX X X X GAL26CV12C Device Name GAL26CV12B Grade Speed (ns) L = Low Power Power Blank = Commercial I = Industrial Package P = Plastic DIP J = PLCC 2 Specifications GAL26CV12 Output Logic Macrocell (OLMC) The GAL26CV12 has a variable number of product terms per OLMC. Of the twelve available OLMCs, two OLMCs have access to twelve product terms (pins 20 and 22), two have access to ten product terms (pins 19 and 23), and the other eight OLMCs have eight product terms each. In addition to the product terms available for logic, each OLMC has an additional product term dedicated to output enable control. The GAL26CV12 has a product term for Asynchronous Reset (AR) and a product term for Synchronous Preset (SP). These two product terms are common to all registered OLMCs. The Asynchronous Reset sets all registered outputs to zero any time this dedicated product term is asserted. The Synchronous Preset sets all registers to a logic one on the rising edge of the next clock pulse after this product term is asserted. The output polarity of each OLMC can be individually programmed to be true or inverting, in either combinatorial or registered mode. This allows each output to be individually configured as either active high or active low. NOTE: The AR and SP product terms will force the Q output of the flip-flop into the same state regardless of the polarity of the output. Therefore, a reset operation, which sets the register output to a zero, may result in either a high or low at the output pin, depending on the pin polarity chosen. A R D Q CLK 4 TO 1 MUX Q SP 2 TO 1 MUX GAL26CV12 OUTPUT LOGIC MACROCELL (OLMC) Output Logic Macrocell Configurations Each of the Macrocells of the GAL26CV12 has two primary functional modes: registered, and combinatorial I/O. The modes and the output polarity are set by two bits (SO and S1), which are normally controlled by the logic compiler. Each of these two primary modes, and the bit settings required to enable them, are described below and on the the following page. NOTE: In registered mode, the feedback is from the /Q output of the register, and not from the pin; therefore, a pin defined as registered is an output only, and cannot be used for dynamic I/O, as can the combinatorial pins. COMBINATORIAL I/O In combinatorial mode the pin associated with an individual OLMC is driven by the output of the sum term gate. Logic polarity of the output signal at the pin may be selected by specifying that the output buffer drive either true (active high) or inverted (active low). Output tri-state control is available as an individual product term for each output, and may be individually set by the compiler as either “on” (dedicated output), “off” (dedicated input), or “product term driven” (dynamic I/O). Feedback into the AND array is from the pin side of the output enable buffer. Both polarities (true and inverted) of the pin are fed back into the AND array. REGISTERED In registered mode the output pin associated with an individual OLMC is driven by the Q output of that OLMC’s D-type flip-flop. Logic polarity of the output signal at the pin may be selected by specifying that the output buffer drive either true (active high) or inverted (active low). Output tri-state control is available as an individual product term for each OLMC, and can therefore be defined by a logic equation. The D flip-flop’s /Q output is fed back into the AND array, with both the true and complement of the feedback available as inputs to the AND array. 3 Specifications GAL26CV12 Registered Mode AR AR Q D CLK Q D Q CLK SP Q SP ACTIVE LOW ACTIVE HIGH S0 = 0 S1 = 0 S0 = 1 S1 = 0 Combinatorial Mode ACTIVE LOW ACTIVE HIGH S0 = 0 S1 = 1 S0 = 1 S1 = 1 4 Specifications GAL26CV12 GAL26CV12 Logic Diagram/JEDEC Fuse Map DIP & PLCC Package Pinouts 1 0 4 8 12 16 20 24 28 32 36 40 44 48 ASYNCHRONOUS RESET (TO ALL REGISTERS) 0000 0052 . . . 0468 8 0520 . . . 0936 8 0988 . . . 1404 8 1456 . . . 1872 8 1924 . . . . 2444 10 2496 . . . . . 3120 12 OLMC 3172 . . . . . 3796 12 OLMC 3848 . . . . 4368 10 OLMC 4420 . . . 4836 8 4888 . . . 5304 8 5356 . . . 5772 8 OLMC S0 6344 S1 6345 2 OLMC S0 6346 S1 6347 3 OLMC S0 6348 S1 6349 4 OLMC S0 6350 S1 6351 5 OLMC S0 6352 S1 6353 6 S0 6354 S1 6355 28 27 26 25 24 23 22 8 S0 6356 S1 6357 20 9 S0 6358 S1 6359 10 OLMC S0 6360 S1 6361 11 OLMC S0 6362 S1 6363 12 OLMC S0 6364 S1 6365 13 5824 . . . 6240 8 OLMC S0 6366 S1 6367 14 6292 19 18 17 16 15 SYNCHRONOUS PRESET (TO ALL REGISTERS) 6368, 6369 ... Electronic Signature ... 6430, 6431 Byte 7 Byte 6 Byte 5 Byte 4 Byte 3 Byte 2 Byte 1 Byte 0 M S B L S B 5 Specifications SpecificationsGAL26CV12C GAL26CV12 Absolute Maximum Ratings(1) Recommended Operating Conditions Supply voltage VCC ...................................... –0.5 to +7V Input voltage applied .......................... –2.5 to VCC +1.0V Off-state output voltage applied ......... –2.5 to VCC +1.0V Storage Temperature ................................ –65 to 150°C Ambient Temperature with Power Applied ........................................... –55 to 125°C Commercial Devices: Ambient Temperature (TA) ............................. 0 to +75°C Supply voltage (VCC) with Respect to Ground ..................... +4.75 to +5.25V Industrial Devices: Ambient Temperature (TA) ........................... –40 to 85°C Supply voltage (VCC) with Respect to Ground ......................... +4.5 to +5.5V 1. Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress only ratings and functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications). DC Electrical Characteristics Over Recommended Operating Conditions (Unless Otherwise Specified) SYMBOL VIL VIH IIL1 IIH VOL VOH IOL IOH IOS2 MIN. TYP.3 MAX. UNITS Input Low Voltage Vss – 0.5 — 0.8 V Input High Voltage 2.0 — Vcc+1 V PARAMETER CONDITION Input or I/O Low Leakage Current 0V ≤ VIN ≤ VIL (MAX.) — — –100 µA Input or I/O High Leakage Current 3.5V ≤ VIN ≤ VCC — — 10 µA Output Low Voltage IOL = MAX. Vin = VIL or VIH — — 0.5 V Output High Voltage IOH = MAX. Vin = VIL or VIH 2.4 — — V Low Level Output Current — — 16 mA High Level Output Current — — –3.2 mA –30 — –130 mA L-7 — 90 130 mA L-10 — 90 150 mA Output Short Circuit Current COMMERCIAL ICC Operating Power Supply Current INDUSTRIAL ICC Operating Power Supply Current VCC = 5V VOUT = 0.5V TA = 25°C VIL = 0.5V VIH = 3.0V ftoggle = 15MHz Outputs Open VIL = 0.5V VIH = 3.0V ftoggle = 15MHz Outputs Open 1) The leakage current is due to the internal pull-up on all pins. See Input Buffer section for more information. 2) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems caused by tester ground degradation. Characterized but not 100% tested. 3) Typical values are at Vcc = 5V and TA = 25 °C. 6 Specifications SpecificationsGAL26CV12C GAL26CV12 AC Switching Characteristics Over Recommended Operating Conditions (Unless Otherwise Specified) PARAM TEST COND.1 tpd tco tcf2 tsu1 tsu2 th fmax3 twh twl ten tdis tar tarw tarr tspr COM IND -7 -10 DESCRIPTION MIN. MAX. MIN. MAX. UNITS A Input or I/O to Comb. Output 1 7.5 1 10 ns A Clock to Output Delay 1 4.5 1 7 ns — Clock to Feedback Delay — 2.5 — 2.5 ns — Setup Time, Input or Fdbk before Clk ↑ 6 — 7 — ns — Setup Time, SP before Clock ↑ 6 — 7 — ns — Hold Time, Input or Fdbk after Clk ↑ 0 — 0 — ns A Maximum Clock Frequency with External Feedback, 1/(tsu + tco) 95.2 — 71.4 — MHz A Maximum Clock Frequency with Internal Feedback, 1/(tsu + tcf) 117.6 — 105 — MHz A Maximum Clock Frequency with No Feedback 142.8 — 105 — MHz — Clock Pulse Duration, High 3.5 — 4 — ns — Clock Pulse Duration, Low 3.5 — 4 — ns B Input or I/O to Output Enabled 1 7.5 1 10 ns C Input or I/O to Output Disabled 1 7.5 1 9 ns A Input or I/O to Asynch. Reset of Reg. 1 9 1 13 ns — Asynchronous Reset Pulse Duration 7 — 8 — ns — Asynch. Reset to Clk↑ Recovery Time 5 — 8 — ns — Synch. Preset to Clk ↑ Recovery Time 5 — 10 — ns 1) Refer to Switching Test Conditions section. 2) Calculated from fmax with internal feedback. Refer to fmax Specification section. 3) Refer to fmax Specification section. Capacitance (TA = 25°C, f = 1.0 MHz) SYMBOL PARAMETER MAXIMUM* UNITS TEST CONDITIONS CI Input Capacitance 8 pF VCC = 5.0V, VI = 2.0V CI/O I/O Capacitance 8 pF VCC = 5.0V, VI/O = 2.0V *Characterized but not 100% tested. 7 Specifications SpecificationsGAL26CV12B GAL26CV12 Absolute Maximum Ratings(1) Recommended Operating Conditions Supply voltage VCC ...................................... –0.5 to +7V Input voltage applied .......................... –2.5 to VCC +1.0V Off-state output voltage applied ......... –2.5 to VCC +1.0V Storage Temperature ................................ –65 to 150°C Ambient Temperature with Power Applied ........................................... –55 to 125°C Commercial Devices: Ambient Temperature (TA) ............................. 0 to +75°C Supply voltage (VCC) with Respect to Ground ..................... +4.75 to +5.25V Industrial Devices: Ambient Temperature (TA) ........................... –40 to 85°C Supply voltage (VCC) with Respect to Ground ......................... +4.5 to +5.5V 1. Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress only ratings and functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications). DC Electrical Characteristics Over Recommended Operating Conditions (Unless Otherwise Specified) SYMBOL VIL VIH IIL1 IIH VOL VOH IOL IOH IOS2 MIN. TYP.3 MAX. UNITS Input Low Voltage Vss – 0.5 — 0.8 V Input High Voltage 2.0 — Vcc+1 V PARAMETER CONDITION Input or I/O Low Leakage Current 0V ≤ VIN ≤ VIL (MAX.) — — –100 µA Input or I/O High Leakage Current 3.5V ≤ VIN ≤ VCC — — 10 µA Output Low Voltage IOL = MAX. Vin = VIL or VIH — — 0.5 V Output High Voltage IOH = MAX. Vin = VIL or VIH 2.4 — — V Low Level Output Current — — 16 mA High Level Output Current — — –3.2 mA –30 — –130 mA L-10/-15/-20 — 90 130 mA L-15/-20 — 90 150 mA Output Short Circuit Current COMMERCIAL ICC Operating Power Supply Current INDUSTRIAL ICC Operating Power Supply Current VCC = 5V VOUT = 0.5V TA = 25°C VIL = 0.5V VIH = 3.0V ftoggle = 15MHz Outputs Open VIL = 0.5V VIH = 3.0V ftoggle = 15MHz Outputs Open 1) The leakage current is due to the internal pull-up on all pins. See Input Buffer section for more information. 2) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems caused by tester ground degradation. Characterized but not 100% tested. 3) Typical values are at Vcc = 5V and TA = 25 °C. 8 Specifications SpecificationsGAL26CV12B GAL26CV12 AC Switching Characteristics Over Recommended Operating Conditions PARAMETER tpd tco tcf2 tsu1 tsu2 th fmax3 twh twl ten tdis tar tarw tarr tspr TEST COND.1 COM COM / IND COM / IND -10 -15 -20 MIN. MAX. MIN. MAX. MIN. MAX. DESCRIPTION UNITS A Input or I/O to Combinatorial Output 3 10 3 15 3 20 ns A Clock to Output Delay 2 7 2 8 2 12 ns — Clock to Feedback Delay — 2.5 — 2.5 — 10 ns — Setup Time, Input or Feedback before Clock ↑ 7 — 10 — 12 — ns — Setup Time, SP before Clock ↑ 10 — 10 — 12 — ns — Hold Time, Input or Feedback after Clock ↑ 0 — 0 — 0 — ns A Maximum Clock Frequency with External Feedback, 1/(tsu + tco) 71.4 — 55.5 — 41.6 — MHz A Maximum Clock Frequency with Internal Feedback, 1/(tsu + tcf) 105 — 80 — 45.4 — MHz A Maximum Clock Frequency with No Feedback 105 — 83.3 — 62.5 — MHz — Clock Pulse Duration, High 4 — 6 — 8 — ns — Clock Pulse Duration, Low 4 — 6 — 8 — ns B Input or I/O to Output Enabled 3 10 3 15 3 20 ns C Input or I/O to Output Disabled 3 10 3 15 3 20 ns A Input or I/O to Asynchronous Reset of Register 3 13 3 20 3 25 ns — Asynchronous Reset Pulse Duration 8 — 10 — 15 — ns — Asynchronous Reset to Clock Recovery Time 8 — 10 — 15 — ns — Synchronous Preset to Clock Recovery Time 10 — 10 — 12 — ns 1) Refer to Switching Test Conditions section. 2) Calculated from fmax with internal feedback. Refer to fmax Specification section. 3) Refer to fmax Specification section. Capacitance (TA = 25°C, f = 1.0 MHz) SYMBOL PARAMETER MAXIMUM* UNITS TEST CONDITIONS CI Input Capacitance 8 pF VCC = 5.0V, VI = 2.0V CI/O I/O Capacitance 8 pF VCC = 5.0V, VI/O = 2.0V *Characterized but not 100% tested. 9 Specifications GAL26CV12 Switching Waveforms INPUT or I/O FEEDBACK INPUT or I/O FEEDBACK VALID INPUT VALID INPUT ts u th t pd CLK COMBINATORIAL OUTPUT tc o REGISTERED OUTPUT Combinatorial Output 1 / fm a x (external fdbk) Registered Output INPUT or I/O FEEDBACK t dis t en OUTPUT CLK 1/ f max (internal fdbk) Input or I/O to Output Enable/Disable tsu t cf REGISTERED FEEDBACK fmax with Feedback tw l tw h CLK 1 / fm a x (w/o fdbk) Clock Width INPUT or I/O FEEDBACK DRIVING SP INPUT or I/O FEEDB ACK DRIVI NG AR tsu t spr th tarw CLK CLK tarr tco R E G I S T ER E D OUTPUT REGISTERED OUTPUT tar Synchronous Preset Asynchronous Reset 10 Specifications GAL26CV12 fmax Definitions CL K CLK LOGIC ARR AY LOGIC ARRAY R EG I S T E R REGISTER ts u tc o fmax with External Feedback 1/(tsu+tco) t cf t pd Note: fmax with external feedback is calculated from measured tsu and tco. fmax with Internal Feedback 1/(tsu+tcf) CLK LOGIC ARRAY Note: tcf is a calculated value, derived by subtracting tsu from the period of fmax w/internal feedback (tcf = 1/fmax - tsu). The value of tcf is used primarily when calculating the delay from clocking a register to a combinatorial output (through registered feedback), as shown above. For example, the timing from clock to a combinatorial output is equal to tcf + tpd. REGISTER tsu + th fmax with No Feedback Note: fmax with no feedback may be less than 1/(twh + twl). This is to allow for a clock duty cycle of other than 50%. Switching Test Conditions Input Pulse Levels Input Rise and Fall Times GND to 3.0V C-7/-10/-15 1.5ns 10% – 90% B-10/-15/-20 3ns 10% – 90% Input Timing Reference Levels +5V R1 1.5V Output Timing Reference Levels 1.5V Output Load See Figure FROM OUTPUT (O/Q) UNDER TEST 3-state levels are measured 0.5V from steady-state active level. GAL26CV12 Output Load Conditions (see figure) Test Condition A B C R1 R2 TEST POINT R2 C L* CL 300Ω 390Ω 50pF Active High ∞ 390Ω 50pF Active Low 300Ω 390Ω 50pF Active High ∞ 390Ω 5pF Active Low 300Ω 390Ω 5pF *C L INCLUDES TEST FIXTURE AND PROBE CAPACITANCE 11 Specifications GAL26CV12 Electronic Signature Output Register Preload An electronic signature is provided in every GAL26CV12 device. It contains 64 bits of reprogrammable memory that can contain user-defined data. Some uses include user ID codes, revision numbers, or inventory control. The signature data is always available to the user independent of the state of the security cell. When testing state machine designs, all possible states and state transitions must be verified in the design, not just those required in normal machine operation. This is because certain events may occur during system operation that throw the logic into an illegal state (power-up, line voltage glitches, brown-outs, etc.). To test a design for proper treatment of these conditions, a way must be provided to break the feedback paths, and force any desired (i.e., illegal) state into the registers. Then the machine can be sequenced and the outputs tested for correct next state conditions. Security Cell A security cell is provided in every GAL26CV12 device to prevent unauthorized copying of the array patterns. Once programmed, this cell prevents further read access to the functional bits in the device. This cell can only be erased by re-programming the device, so the original configuration can never be examined once this cell is programmed. The Electronic Signature is always available to the user, regardless of the state of this control cell. The GAL26CV12 device includes circuitry that allows each registered output to be synchronously set either high or low. Thus, any present state condition can be forced for test sequencing. If necessary, approved GAL programmers capable of executing test vectors perform output register preload automatically. Input Buffers Latch-Up Protection GAL26CV12 devices are designed with TTL level compatible input buffers. These buffers have a characteristically high impedance, and present a much lighter load to the driving logic than bipolar TTL logic. GAL26CV12 devices are designed with an on-board charge pump to negatively bias the substrate. The negative bias minimizes the potential for latch-up caused by negative input undershoots. Additionally, outputs are designed with n-channel pull-ups instead of the traditional p-channel pull-ups in order to eliminate latch-up due to output overshoots. The input and I/O pins also have built-in active pull-ups. As a result, floating inputs will float to a TTL high (logic 1). However, Lattice Semiconductor recommends that all unused inputs and tri-stated I/O pins be connected to an adjacent active input, Vcc, or ground. Doing so will tend to improve noise immunity and reduce Icc for the device. Device Programming GAL devices are programmed using a Lattice Semiconductorapproved Logic Programmer, available from a number of manufacturers (see the the GAL Development Tools section). Complete programming of the device takes only a few seconds. Erasing of the device is transparent to the user, and is done automatically as part of the programming cycle. I n p u t C u r r e n t (u A ) Typical Input Current 0 -20 -40 -60 0 1.0 2.0 3.0 In p u t V o lt ag e ( V o lt s) 12 4.0 5.0 Specifications GAL26CV12 Power-Up Reset Vcc (min.) Vcc t su t wl CLK t pr INTERNAL REGISTER Q - OUTPUT Internal Register Reset to Logic "0" ACTIVE LOW OUTPUT REGISTER Device Pin Reset to Logic "1" ACTIVE HIGH OUTPUT REGISTER Device Pin Reset to Logic "0" provide a valid power-up reset of the device. First, the VCC rise must be monotonic. Second, the clock input must be at static TTL level as shown in the diagram during power up. The registers will reset within a maximum of tpr time. As in normal system operation, avoid clocking the device until all input and feedback path setup times have been met. The clock must also meet the minimum pulse width requirements. Circuitry within the GAL26CV12 provides a reset signal to all registers during power-up. All internal registers will have their Q outputs set low after a specified time (tpr, 1µs MAX). As a result, the state on the registered output pins (if they are enabled) will be either high or low on power-up, depending on the programmed polarity of the output pins. This feature can greatly simplify state machine design by providing a known state on power-up. Because of the asynchronous nature of system power-up, some conditions must be met to Input/Output Equivalent Schematics PIN PIN Feedback Vcc Active Pull-up Circuit Active Pull-up Circuit (Vref Typical = 3.2V) Vcc Vref (Vref Typical = 3.2V) Tri-State Control Vcc Vcc Vref ESD Protection Circuit Data Output PIN ESD Protection Circuit PIN Feedback (To Input Buffer) Typical Input Typical Output 13 Specifications GAL26CV12 GAL26CV12C: Typical AC and DC Characteristic Diagrams Normalized Tpd vs Vcc 1.2 1.1 1 0.9 0.8 Normalized Tsu 1.2 Normalized Tco 1.1 1 0.9 0.8 4.50 4.75 5.00 5.25 5.50 1 0.9 4.75 5.00 5.25 4.50 5.50 4.75 5.00 5.25 5.50 Supply Voltage (V) Supply Voltage (V) Supply Voltage (V) Normalized Tpd vs Temp Normalized Tco vs Temp Normalized Tsu vs Temp 1.3 1.2 1.2 Normalized Tco 1.3 1.1 1 0.9 0.8 0.7 1.4 1.1 1 0.9 0.8 0.7 -25 0 25 50 75 100 -25 0 25 50 75 1.2 1.1 1 0.9 0.8 100 125 -55 -25 Temperature (deg. C) Delta Tpd vs # of Outputs Switching Delta Tco (ns) 0 -0.25 -0.5 -0.75 -0.25 -0.5 -0.75 -1 -1 1 2 3 4 5 6 7 8 9 10 11 12 1 Number of Outputs Switching 2 3 4 5 6 7 8 9 10 11 12 Number of Outputs Switching Delta Tpd vs Output Loading Delta Tco vs Output Loading 12 RISE 8 FALL Delta Tco (ns) 12 10 6 4 2 10 RISE 8 FALL 6 4 2 0 0 -2 -2 0 50 100 150 200 250 300 0 Output Loading (pF) 50 100 150 200 250 Output Loading (pF) 14 0 25 50 75 100 Temperature (deg. C) Delta Tco vs # of Outputs Switching 0 Delta Tpd (ns) 1.3 0.7 -55 125 Temperature (deg. C) Delta Tpd (ns) -55 1.1 0.8 4.50 Normalized Tsu Normalized Tpd 1.2 Normalized Tpd Normalized Tsu vs Vcc Normalized Tco vs Vcc 300 125 Specifications GAL26CV12 GAL26CV12C: Typical AC and DC Characteristic Diagrams Vol vs Iol Voh vs Ioh 3 5 1 3.75 Voh (V) 1.5 3 2 0 0 0.00 20.00 40.00 60.00 80.00 100.00 3.5 3.25 1 0.5 3 0.00 10.00 20.00 30.00 40.00 50.00 60.00 0.00 2.00 3.00 Ioh(mA) Ioh(mA) Normalized Icc vs Vcc Normalized Icc vs Temp Normalized Icc vs Freq. 1.3 1.50 1.2 1.2 1.40 1.1 1 0.9 0.8 0.7 Normalized Icc 1.3 4.50 1.00 Iol (mA) Normalized Icc Normalized Icc 4 4 2 Voh (V) Vol (V) 2.5 1.1 1 0.9 0.8 4.75 5.00 5.25 5.50 -25 0 25 50 75 100 125 Temperature (deg. C) 0 10 Iik (mA) 6 4 2 20 30 40 50 0 60 0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00 Vin (V) 1.20 1.10 1.00 -2.00 -1.50 -1.00 Vik (V) 15 -0.50 0 25 50 75 Frequency (MHz) Input Clamp (Vik) Delta Icc vs Vin (1 input) 8 1.30 0.80 -55 10 4.00 0.90 0.7 Supply Voltage (V) Delta Icc (mA) Voh vs Ioh 0.00 100 Specifications GAL26CV12 GAL26CV12B: Typical AC and DC Characteristic Diagrams Normalized Tpd vs Vcc 1.2 1.1 1 0.9 0.8 Normalized Tsu 1.2 Normalized Tco Normalized Tpd 1.2 1.1 1 0.9 4.75 5.00 5.25 5.50 4.50 4.75 Supply Voltage (V) Normalized Tpd vs Temp 1.2 1.2 1.1 1 0.9 0.8 0.7 5.00 5.25 -25 0 25 50 75 100 4.50 1 0.9 0.8 -25 0 25 50 75 1.2 1.1 1 0.9 0.8 100 125 -55 -25 0 Delta Tco (ns) 0 -0.5 -1 -1.5 -2 -0.5 -1 -1.5 -2 4 5 6 7 8 9 10 11 12 1 Number of Outputs Switching 2 3 4 5 6 7 8 9 10 11 12 Number of Outputs Switching Delta Tpd vs Output Loading Delta Tco vs Output Loading 12 RISE 8 FALL Delta Tco (ns) 12 10 6 4 2 10 RISE 8 FALL 6 4 2 0 0 -2 -2 0 50 100 150 200 250 300 Output Loading (pF) 0 50 100 150 200 250 Output Loading (pF) 16 25 50 75 100 Temperature (deg. C) Delta Tco vs # of Outputs Switching 0 Delta Tpd (ns) 1.3 0.7 -55 3 5.50 1.4 Delta Tpd vs # of Outputs Switching 2 5.25 Normalized Tsu vs Temp Temperature (deg. C) 1 5.00 Normalized Tco vs Temp Temperature (deg. C) Delta Tpd (ns) 4.75 Supply Voltage (V) 1.1 125 0.9 Supply Voltage (V) 0.7 -55 1 5.50 Normalized Tsu 1.3 Normalized Tco 1.3 1.1 0.8 0.8 4.50 Normalized Tpd Normalized Tsu vs Vcc Normalized Tco vs Vcc 300 125 Specifications GAL26CV12 GAL26CV12B: Typical AC and DC Characteristic Diagrams Vol vs Iol Voh vs Ioh 5 3 4.5 4 1.5 1 4.25 Voh (V) 2 Voh (V) 3 2 0 0 0.00 20.00 40.00 60.00 80.00 10.00 20.00 30.00 40.00 50.00 60.00 1.00 2.00 3.00 Ioh(mA) Ioh(mA) Normalized Icc vs Vcc Normalized Icc vs Temp Normalized Icc vs Freq. Normalized Icc 1.1 1 0.9 1.2 1.1 1 0.9 0.8 0.7 4.75 5.00 5.25 5.50 Supply Voltage (V) -25 0 25 50 75 100 125 Temperature (deg. C) 0 10 20 Iik (mA) 30 6 4 40 50 60 70 2 80 0 90 100 0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00 Vin (V) 1.00 0.90 -2.00 -1.50 -1.00 Vik (V) 17 -0.50 0 25 50 75 Frequency (MHz) Input Clamp (Vik) Delta Icc vs Vin (1 input) 8 1.10 0.80 -55 10 4.00 1.20 1.3 0.8 Delta Icc (mA) 0.00 Iol (mA) 1.2 4.50 3.5 0.00 100.00 4 3.75 1 0.5 Normalized Icc Vol (V) 2.5 Normalized Icc Voh vs Ioh 0.00 100