Rohm BU9847GUL-W Wl-csp eeprom family i2c bus Datasheet

High Reliability Series Serial EEPROMs
WL-CSP EEPROM family
I2C BUS
No.10001EAT14
BU9847GUL-W
●Description
2
BU9847GUL-W series is a serial EEPROM of I C BUS interface method. 1.7V single power source action and actions
available at 400kHz.
●Features
2
1) Completely conforming to the world standard I C BUS. All controls available by 2 ports of serial clock (SCL)
and serial data(SDA)
2) Other devices than EEPROM can be connected to the same port, saving microcontroller port.
3) Actions available at 400kHz clock (1.7V～5.5V)
4) 1.7～5.5V single power source action most suitable for battery use.
5) Page write mode useful for initial value write at factory shipment.
6) Auto erase and auto end function at data rewrite.
7) Low current consumption
At write action (5V)
: 1.2mA (Typ.)
At read action (5V)
: 0.2mA (Typ.)
At standby action (5V) : 0.1μA (Typ.)
8) Write mistake prevention function
●Page write
Write (write protect) function added.
Write mistake prevention function at low voltage.
Number of pages
16Byte
9) Data rewrite up to 1,000,000times.
10) Data kept for 40 years.
Product number
BU9847GUL-W
11) Noise filter built in SCL / SDA terminal
12) Shipment data all address FFh.
●BU9847GUL-W
Capacity
Bit format
Type
Power source voltage
VCSP50L1
512×8
BU9847GUL-W
1.7~5.5V
●
4Kbit
●Absolute maximum ratings (Ta=25°C)
Parameter
Impressed voltage
Permissible dissipation
Symbol
Ratings
Unit
Vcc
-0.3~+6.5
V
Pd
220
*1
mW
Storage temperature range
Tstg
-65~125
℃
Operating temperature range
Topr
-40~85
℃
-
-0.3~Vcc+1.0
V
Symbol
Ratings
Unit
Vcc
1.7~5.5
Vin
0~Vcc
Terminal voltage
*
When using at Ta=25℃ or higher, 2.2mW (*1) to be reduced per 1℃
●Recommended action conditions
Parameter
Power source
voltage
Input voltage
V
●Memory cell characteristics (Ta=25°C, Vcc=1.7~5.5V)
Parameter
Number of data rewrite times *1
Data hold years
Limits
Max
Unit
Min
Typ.
1,000,000
-
-
Times
40
-
-
Years
*1 Not 100% TESTED
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© 2010 ROHM Co., Ltd. All rights reserved.
1/18
2010.09 - Rev.A
Technical Note
BU9847GUL-W
●Electrical characteristics
(Unless otherwise specified, Ta=-40~+85°C, Vcc=1.7~5.5V)
Limits
Parameter
Symbol
Min.
Typ.
Max.
Unit
Conditions
“HIGH” input voltage1
VIH1
0.7Vcc
-
Vcc+1.0
V
2.5V≤Vcc≤5.5V
“LOW” Input voltage1
VIL1
-0.3
-
0.3Vcc
V
2.5V≤Vcc≤5.5V
“HIGH” input voltage2
VIH2
0.8Vcc
-
Vcc+1.0
V
1.8V≤Vcc<2.5V
“LOW” input voltage2
VIL2
-0.3
-
0.2Vcc
V
1.8V≤Vcc<2.5V
“HIGH” input voltage3
VIH3
0.9Vcc
-
Vcc+1.0
V
1.7V≤Vcc<1.8V
“LOW” input voltage3
VIL3
-0.3
-
0.1Vcc
V
1.7V≤Vcc<1.8V
“LOW” output voltage1
VOL1
-
-
0.4
V
IOL=3.0mA, 2.5V≤Vcc≤5.5V, (SDA)
“LOW output voltage2
VOL2
-
-
0.2
V
IOL=0.7mA, 1.7V≤Vcc<2.5V, (SDA)
Input leak current
ILI
-1
-
1
μA
VIN=0V~Vcc
Output leak current
ILO
-1
-
1
μA
VOUT=0V~Vcc(SDA)
ICC1
-
-
2.0
mA
ICC2
-
-
0.5
mA
ISB
-
-
2.0
μA
Current consumption
at action
Standby current
Vcc=5.5V, fSCL=400kHz, tWR=5ms,
Byte write, Page write
Vcc=5.5V, fSCL=400kHz
Random read, vurrent read, sequential read
Vcc=5.5V, SDA·SCL=Vcc,
A2=GND, WP=GND
◎Radiation resistance design is not made.
●Action timing characteristics
(Unless otherwise specified, Ta=-40～+85°C、Vcc=1.7～5.5V)
Parameter
FAST-MODE
1.7V≤Vcc≤5.5V
Symbol
Unit
Min.
Typ.
Max.
SCL frequency
fSCL
-
-
400
kHz
Data clock “HIGH“ time
tHIGH
0.6
-
-
μs
Data clock “LOW“ time
tLOW
1.2
-
-
μs
SDA, SCL rise time *1
tR *1
-
-
0.3
μs
SDA< SCL fall time *1
tF *1
-
-
0.3
μs
Start condition hold time
tHD:STA
0.6
-
-
μs
Start condition setup time
tSU:STA
0.6
-
-
μs
Input data hold time
tHD:DAT
0
-
-
ns
Input data setup time
tSU:DAT
100
-
-
ns
tPD
0.1
-
0.9
μs
Output data delay time
Output data hold time
tDH
0.1
-
-
μs
tSU:STO
0.6
-
-
μs
Bus release time before transfer start
tBUF
1.2
-
-
μs
Internal write cycle time
tWR
-
-
5
ms
tI
-
-
0.1
μs
Stop condition setup time
Noise removal valid period (SDA, SCL terminal)
WP hold time
tHD:WP
0
-
-
ns
WP setup time
tSU:WP
0.1
-
-
μs
WP valid time
tHIGH:WP
1.0
-
-
μs
*1 Not 100% tested.
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© 2010 ROHM Co., Ltd. All rights reserved.
2/18
2010.09 - Rev.A
Technical Note
BU9847GUL-W
●Sync data input / output timing
tR
tF
tHIGH
SCL
SCL
tHD:STA
tSU:DAT
tLOW
DATA(1)
tHD:DAT
SDA
(Input)
SDA
tBUF
tPD
D1
DATA(n)
D0
ACK
ACK
ｔWR
tDH
stop
condition
ストップコンディション
WP
SDA
(Output)
○Input read at the rise edge of SCL
○Data output in sync with the fall of SCL
tSU：WP
ｔHD：WP
fig.1-(d) WP timing at write execution
Fig.-1(a) Sync data input / output timing
SCL
SCL
tSU:STA
tHD:STA
DATA(n)
DATA(1)
tSU:STO
SDA
SDA
D1
D0
ACK
ACK
tHIGH:WP
START BIT
STOP BIT
tWR
WP
Fig.1-(b) Start – stop bit timing
Fig.1-(e) WP timing at write cancel
○At write execution, in the area from the DO taken clock rise of the first DATA (1),
to tWR, set WP=”LOW”
○By setting WP “HIGH” in the area, write can be cancelled.
When it is set WP=”HIGH” during tWR, write is forcibly ended, and data of
address under access is not guaranteed, therefore write it once again.
SCL
SDA
D0
ACK
tWR
Write data
（ｎ-th address）
Stop condition
Start condition
Fig.1-(c) Write cycle timing
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© 2010 ROHM Co., Ltd. All rights reserved.
3/18
2010.09 - Rev.A
Technical Note
BU9847GUL-W
●Block diagram
VCC
4Kbit EEPROM array
GND
8bit
9bit
Address
decoder
Slave – word
address register
9bit
START
A2
Data
register
WP
STOP
SCL
Control circuit
ACK
High voltage
generating circuti
Power source
voltage detection
SDA
Fig.2 Block diagram
●Pin assignment and description
B2
B3
B1
○
○
○
A2
A3
A1
○
○
○
B
A
INDEX Post
3
2
1
Fig.3 BU9847GUL-W(bottom view)
Land No.
Terminal name
Input/ Output
Function
B3
A2
Input
B2
GND
-
B1
SDA
Input/Output
A3
Vcc
-
A2
WP
Input
Write protect terminal
A1
SCL
Input
Serial clock input
Slave address setting terminal
Reference voltage of al input / output, 0V
Slave and word address, Serial data input serial data output.
Connect the power source.
6
5
5
4
4
SPEC
3
2
0.8
3
Ta=85°C
Ta=-40°
2
Ta=85°C
Ta=-40°
1
1
VOL2[V]
6
VIL1,2,3[V]
VIH1,2,3[V]
●Characteristic data (The following values are Typ. ones.)
0.2
SPEC
Ta=-40°
0
0
2
3
4
5
Ta=85°C
SPEC
1
0
1
Ta=25°C
0.4
Ta=25°C
Ta=25°C
0
0.6
6
Vcc[V]
Fig.4 H input voltage VIH1,2,3
(A2,SCL,SDA,WP)
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© 2010 ROHM Co., Ltd. All rights reserved.
0
1
2
3
4
5
6
Vcc[V]
Fig.5 L input voltage VIL1,2,3
(A2,SCL,SDA,WP)
4/18
0
1
2
3
4
5
6
IOL2[mA]
Fig.6 L output voltage VOL2-IOL2
(VCC=1.7V)
2010.09 - Rev.A
Technical Note
BU9847GUL-W
1.2
1
1.2
1
0.8
SPEC
SPEC
1
SPEC
0.4
Ta=25°C
Ta=85°C
0.8
ILO[μA]
ILI[μA]
VOL1[V]
0.8
0.6
0.6
0.4
0.4
Ta=85°C
Ta=85°C
0.2
Ta=25°C
0.2
Ta=-40°
0
0
1
2
3
4
5
6
0
0
1
2
3
4
5
6
0
Fig.8 Input leak current
ILI(A2,SCL, WP)
Fig.7 L input voltage
VOL1-IOL1 (Vcc=2.5V)
0.5
fSCL=400kHz
DATA=AAh
ICC2[mA]
4
Ta=25°C
0.3
Ta=85°C
Ta=-40°
6
SPEC
2
1.5
1
0.2
0.5
5
fSCL=400kHz
DATA=AAh
0.4
Ta=25°C
Ta=85°C
3
Vcc[V]
2.5
SPEC
ISB[μA]
SPEC
1
2
Fig.9 Output leak current
ILO (SDA)
0.6
2.5
1.5
1
Vcc[V]
IOL1[mA]
2
Ta=25°C
0.2
Ta=-40°
Ta=-40°
0
ICC1[mA]
0.6
Ta=85°C
0.1
0.5
Ta=-40°
Ta=25°C
Ta=-40°
0
0
0
1
2
3
4
5
0
0
6
1
2
3
4
5
6
0
1
2
3
Vcc[V]
Vcc[V]
Fig.10 Consumption current
at write action Icc1 (fSCL=400kHz)
5
6
Vcc[V]
Fig.11 Consumption current
at write action Icc2 (fSCL=400kHz)
10000
4
Fig.12 Standby current
ISB
1.6
1
Ta=-40°
Ta=25°C
0.8
SPEC
0.6
tHIGH [μs]
fSCL[kHz]
SPEC
100
SPEC
1.2
Ta=85°C
tLOW[μs]
1000
Ta=85°C
0.4
0.8
Ta=85°C
Ta=25°C
Ta=-40°
Ta=25°C
10
0.4
0.2
Ta=-40°
1
0
0
0
1
2
3
4
5
6
0
1
2
Vcc[V]
Fig.13 SCL frequency
fSCL
5
0
6
Ta=25°C
0.2
Ta=85°C
0.2
3
4
5
6
Ta=25°C
Ta=-40°
-200
0
1
2
Vcc[V]
3
4
5
0
6
1
2
1
SPEC
4
5
6
Fig.18 Input data hold time
tHD:DAT
Fig.17 Start condition setup time
tSU:STA
200
3
Vcc[V]
Vcc[V]
Fig.16 Start condition hold time
tHD:STA
100
Ta=85°C
-150
Ta= 40°C
-0.2
2
6
-50
-100
Ta=25°C
0
0
5
SPEC
0.4
Ta=-40°C
4
0
SPEC
tHD:DAT(HIGH)[ns]
Ta=85°C
0.4
1
3
50
0.6
tHD:DAT(HIGH)[ns]
SPEC
0
2
Fig.15 Data clock “L” time
tLOW
0.8
0.6
1
Vcc[V]
1
0.8
1
SPEC
0.8
SPEC
0.8
Ta=-40°C
Ta=85°C
0
tPD0 [μs]
Ta=85°C
Ta=25°C
0.6
tPD1 [μs]
tHD:STA[μs]
4
Fig.14 Data clock “H” time
tHIGH
1
tSU:DAT(HIGH)[ns]
3
Vcc[V]
Ta=25°C
0.4
0.6
Ta=85°C
Ta=25°C
0.4
Ta=-40°
-100
Ta=-40°
0.2
0.2
SPEC
SPEC
-200
0
0
1
2
3
4
5
6
Vcc[V]
Fig.19 Input data setup time
tSU:DAT
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0
0
1
2
3
4
Vcc[V]
5
6
Fig.20 Output data delay time
tPD0
5/18
0
1
2
3
4
5
6
Vcc[V]
Fig.21 Output data delay time
tPD1
2010.09 - Rev.A
Technical Note
BU9847GUL-W
4
1
Ta=85°C
4
3
Ta=-40°C
0.4
2
Ta=85°C
2
3
4
5
6
0
1
3
5
6
0
1
4
tWR[ms]
Ta=-40°
2
C
SPEC
Ta=-40°
3
Ta=25°C
Ta=85°C
2
T
0
3
4
5
6
0
1
2
Vcc[V]
3
0.6
0.5
0.5
0.2
0.2
SPEC
0.3
Ta=85°C
0.2
SPEC
2
3
4
5
6
1
2
3
4
5
6
Vcc[V]
Fig.28 Noise removal time
tI (SCL L)
4
5
6
0.6
Ta=-40°
0.4
0.3
Ta=25°C
Ta=85°C
0.2
SPEC
0
0
Vcc[V]
3
Fig.27 Noise removal time
tI (SCL H)
0.1
0
1
2
Vcc[V]
Ta=25°C
0.1
0
0
1
0.5
Ta=85°C
0.1
Ta=85°C
SPEC
0
6
Ta=-40°
0.4
tI(SDA H) [μs]
0.4
Ta=-40°
5
Fig.26 Internal write cycle time
tWR
0.6
Ta=25°C
Ta=25°C
Ta=-40°
0.3
Vcc[V]
Fig.25 Bus release time
before transfer start tBUF
0.3
4
tI(SDA L) [μs]
2
6
0
0
1
5
0.4
0.1
1
8 °C
4
0.6
Ta=25°C
1
3
0.5
3
0
2
Fig.24 Stop condition setup time
tSU:STO
SPEC
5
Ta=-40°C
Vcc[V]
6
4
tBUF[μs]
5
Fig.23 Output data hold time
tDH1
Fig.22 Output data hold time
tDH1
tI(SCL L) [μs]
4
Vcc[V]
Vcc[V]
Fig.29 Noise removal time
tI (SDA H)
0
1
2
3
4
5
6
Vcc[V]
Fig.30 Noise removal time
tI (SDA L)
1.2
0.2
1
SPEC
SPEC
-0.2
tHIGH:WP[μs]
0
tSU:WP[μs]
SPEC
0
2
tI(SCL H) [μs]
1
Ta=85°C
Ta=25°C
SPEC
0
0
2
1
Ta=-40°C
SPEC
0
3
Ta=25°C
1
0.2
tSU:STO[μs]
Ta=25°C
0.6
tDH1[μs]
tDH0[μs]
0.8
5
Ta=85°C
-0.4
0.8
0.6
Ta=-40°C
0.4
Ta=25°C
Ta=25°C
Ta=-40°
0.2
-0.6
Ta=85°C
0
0
1
2
3
4
5
6
Vcc[V]
Fig.31 WP setup time
tSU:WP
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0
1
2
3
4
5
6
Vcc[V]
Fig.32 WP valid time
tHIGH: WP
6/18
2010.09 - Rev.A
Technical Note
BU9847GUL-W
●I2C BUS communication
2
○I C BUS data communication
2
I C BUS data communication starts by start condition input, and ends by stop condition input. Data is always 8bit long,
and acknowledge is always required after each byte.
I2C BUS carries out data transmission with plural devices connected by 2 communication lines of serial data (SDA) and
serial clock (SCL).
Among devices, there are “master” that generates clock and control communication start and end, and “slave” that is
controlled by addresses peculiar to devices.
EEPROM becomes “slave”. And the device that outputs data to bys during data communication is called “transmitter”,
and the device that receives data is called “receiver “.
SDA
1-7
SCL
S
START ADDRESS
condition
8
9
R/W
ACK
1-7
8
DATA
9
ACK
1-7
DATA
8
9
ACK
P
STOP
condition
Fig.33 Data transfer timing
○Start condition (start bit recognition)
・Before executing each command, start condition (start bit) where SDA goes from “HIGH” down to “LOW” when SCL is
“HIGH” is necessary.
・This IC always detects whether SDA and SCL are in start condition (start bit) of not, therefore, unless this condition is
satisfied, any command is executed.
○Stop condition (stop bit recognition)
・Each command can be ended by SDA rising from “LOW” to “HIGH” when stop condition (stop bit), namely, SCL is
“HIGH”.
○Acknowledge (ACK) signal
・This acknowledge (ACK) signal is a software rule to show whether data transfer has been made normally or not. In
master and slave, the device (μ-COM at slave address input of write command, read command, and this IC at data
output of read command) at the transmitter (sending) side releases the bus after output of 8bit data.
・This device (this IC at slave address input of write command , read command , and μ-COM at data output of read
command) at the receiver (receiving) side sets SDA “LOW” during 9 clock cycles, and outputs acknowledge signal
(ACK signal) showing that it has received the 8bit data.
・This IC, after recognizing start condition and slave address (8bit), outputs acknowledge signal (ACK signal) “LOW”.
・Each write action outputs acknowledge signal (ACK signal) “LOW”, at receiving 8bit data (word address and write data).
・Each read action outputs 8bit data (read data), and detects acknowledge signal (ACK signal) “LOW”.
・When acknowledge signal (ACK signal) is detected, and stop condition is not sent from the master (μ-COM) side, this IC
continues data output. When acknowledge signal (ACK signal) is not detected, this IC stops data transfer, and
recognizes stop condition (stop bit), and ends read action.
And this IC gets in standby status.
○Device addressing
・Output slave address after start condition from master.
・The significant 4 bits of slave address are used for recognizing a device type.
The device code of this IC is fixed to “1010”.
・Next slave addressed (A2 --- device address) are for selecting devices, and plural ones can be used on a same bus
according to the number of device addresses.
・The most insignificant bit ( R / W --- READ / WRITE ) of slave address is used for designating write or read action, and is
as shown below.
Setting R / W to 0 --- write (setting 0 to word address setting of random read)
Setting R / W to 1 --- read
Type
BU9847GUL-W
Maximum number
of connected buses
Slave address
1
0
1
0
A2
0
PS R / W
PS is page select bits.
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7/18
2
B
SDA
GND
A2
A
SCL
WP
Vcc
1
2
3
2010.09 - Rev.A
Technical Note
BU9847GUL-W
●Command
○Write cycle
・Arbitrary data is written to EEPROM. When to write only 1 byte, byte write is normally used, and when to write
continuous data of 2 bytes or more, simultaneous write is possible by page write cycle.
S
T
A
R
T
SDA
LINE
W
R
I
T
E
SLAVE
ADDRESS
1 0 1 0 A2 0 PＳ
WORD
ADDRESS
WA
7
S
T
O
P
DATA
WA
0
R A
/ C
W K
D7
D0
A
C
K
A
C
K
WP
Fig.34 Byte write cycle
S
T
A
R
T
SDA
LINE
SLAVE
ADDRESS
W
R
I
T
E
WORD
ADDRESS(n)
WA
7
1 0 1 0 A2 0 PＳ
R A
/ C
W K
WA
0
D7
S
T
O
P
DATA(n+15)
DATA(n)
D0
D0
A
C
K
A
C
K
A
C
K
WP
Fig.35 Page write cycle
・Data is written to the address designated by word address (n-th address).
・By issuing stop bit after 8bit data input, write to memory cell inside starts.
・When internal write is started, command is not accepted for tWR (5ms at maximum).
・By page write cycle, the following can be written in bulk. Up to 16 bytes.
And when data of the maximum bytes or higher is sent, data from the first byte is overwritten.
(Refer to “Internal address increment” of “Notes on page write cycle” in P8/16.)
・As for page write cycle of BU9847GUL-W, after page select bit (PS) of slave address is designated arbitrarily, by
continuing data input of 2 bytes or more, the address of insignificant 4 bits is incremented internally, and data up to 16
bytes can be written.
Note)
1 0 1 0 A2 0 PS
Fig.36 Difference of slave address of each type
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8/18
2010.09 - Rev.A
Technical Note
BU9847GUL-W
○Notes on write cycle continuous input
S
T
A
R
T
SDA
LINE
W
R
I
T
E
SLAVE
ADDRESS
At STOP (stop bit),
Writ e starts .
WORD
ADDRESS(n)
WA
0
WA
7
1 0 1 0 A2 0 PS
R A
/ C
WK
DATA(n+15)
DATA(n)
D7
D0
A
C
K
S
T
A
R
T
S
T
O
P
D0
A
C
K
1 0 1 0
A
C
K
Next command
t WR (maximum : 5ms)
Command is not accept ed for this period.
Fig.37 Page write cycle
Note)
1 0 1 0 A2 0 PS
Fig.38 Difference of each type of slave address
○Internal address increment Page write mode
○Notes on page write cycle
List of numbers of page write
Number of Pages
16Byte
WA3
0
0
0
WA2
0
0
0
The above numbers are maximum bytes for respective types.
Any types below these can be written.
0Eh
0
0
0
-------------
WA1
0
0
0
WA0
0
0
0
Increment
---------
BU9847GUL-W
WA4
0
0
0
---------
Product number
WA7 ----0
----0
----0
-----
0
0
0
1
1
0
1
1
0
1
1
0
0
1
0
1page = 16 bytes, but the page write cycle write time is 5ms at maximum
for 16byte bulk write.
It does not stand 5ms at maximum x 16 bytes = 80ms (Max.).
Significant bit is fixed.
No digit up
For example, when it is started from address 0Eh,
therefore, increment is made as below,
0Eh→0Fh→00h→01h ---, which please note.
*0Eh --- 0E in hexadecimal, therefore, 00001110
becomes a binary number.
○Write protect terminal (WP)
・Write protect function
When WP terminal is set Vcc (H level), data rewrite of all addresses is prohibited. When it is set GND (L level), data
rewrite of all addresses is enabled. Be sure to connect this terminal to Vcc or GND, or control it to H level or L level. Do
not use it open.
At extremely low voltage at power ON/OFF, by setting the WP terminal “H”, mistake write can be prevented.
During tWR, set the WP terminal always to “L”. If it is set “H”, write is forcibly terminated.
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© 2010 ROHM Co., Ltd. All rights reserved.
9/18
2010.09 - Rev.A
Technical Note
BU9847GUL-W
●Command
○Read cycle
Data of EEPROM is read. In read cycle, there are random read cycle and current read cycle.
Random read cycle is a command to read data by designating address, and is used generally.
Current read cycle is a command to read data of internal address register without designating address, and is used when
to verify just after write cycle. In both the read cycles, sequential read cycle is available, and the next address data next
address data can be read in succession.
S
T
A
R
T
SDA
LINE
W
R
I
T
E
SLAVE
ADDRESS
WORD
ADDRESS(n)
WA
0
WA
7
1 0 1 0 A2 0 PＳ
S
T
A
R
T
R A
/ C
W K
R
E
A
D
SLAVE
ADDRESS
DATA(n)
1 0 1 0 A2 0 0
A
C
K
S
T
O
P
D7
It is necessary to input “H”
to the last ACK.
D0
A
C
K
R A
/ C
W K
Fig.39 Random Read cycle
S
T
A
R
T
SDA
LINE
R
E
A
D
SLA VE
ADDRES S
1
0
1
0 A2 0 PS
D7
R
/
W
S
T
O
P
DATA
It is necessary to input “H”
to the last ACK.
D0
A
C
K
A
C
K
Fig.40 Current read cycle
S
T
A
R
T
SDA
LINE
R
E
A
D
SLAVE
ADDRESS
1 0 1 0 A2 0 PS
DATA(n+x)
DATA(n)
D7
D0
R A
/ C
W K
S
T
O
P
D7
A
C
K
A
C
K
D0
A
C
K
Fig.41 Sequential read cycle
・In random read cycle, data of designated word address can be read.
・When the command just before current read cycle is random read cycle, current read cycle (each including sequential
read cycle), data of incremented last read address (n-th) address, i.e., data of the (n+1)-th address is output.
・When ACK signal “LOW” after D0 is detected, and stop condition is not sent from the master (μ-COM) side, the next
address data can be read in succession.
・Read cycle is ended by stop condition where “H” is input to ACK signal after D0 and SDA signal is started at
SCL signal “H”.
・When “H” is not input to ACK signal after D0, sequential read gets in, and the next data is output.
Therefore, read command cycle cannot be ended. When to end read command cycle, be sure input stop condition to
input “H” to ACK signal after D0, and to start SDA at SCL signal “H”.
・Sequential read is ended by stop condition where “H” is input to ACK signal after arbitrary D0 and SDA is started at SCL
signal “H”.
Note)
1 0 1 0 A2 0 PS
Fig.42 Difference of slave address of each type
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© 2010 ROHM Co., Ltd. All rights reserved.
10/18
2010.09 - Rev.A
Technical Note
BU9847GUL-W
●Software reset
Software reset is executed when to avoid malfunction after power on, and to reset during command input. Software reset
has several kinds, and 3 kinds of them are shown in the figure below. (Refer to Fig.43(a), Fig.43(b) and Fig.43(c).) In
dummy clock input area, release the SDA bus (“H” by pull up). In dummy clock area, ACK output and read data “0” (both “L”
level) may be output from EEPROM, therefore, if “H” is input forcibly, output may conflict and over current may flow, leading
to instantaneous power failure of system power source or influence upon devices.
Dummy clock x14
SCL
1
2
Start x2
13
Normal command
14
SDA
Normal command
Fig.43-(a) The case of dummy clock + START + START + command input
SCL
Start
Dummy clock x9
Start
1
2
8
9
Normal command
SDA
Normal command
Fig.43-(b) The case of START + 9 dummy clocks + START + command input
Start x 9
SCL
2
1
7
3
8
9
Normal command
SDA
Normal command
Fig.43-(c) START x 9 + command input
* Start normal command from START input.
●Acknowledge polling
During internal write execution, all input commands are ignored, therefore ACK is not sent back. During internal automatic
write execution after write cycle input, next command (slave address) is sent, and if the first ACK signal sends back “L”,
then it means end of write action, while if it sends back “H”, it means now in writing. By use of acknowledge polling, next
command can be executed without waiting for tWR=5ms.
When to write continuously, R / W = 0, when to carry out current read cycle after write, slave address R / W = 1 is sent,
and if ACK signal sends back “L”, then execute word address input and data output and so forth.
During internal write,
First write command
S
T
A
R
T
Write command
ACK = HIGH is sent back.
S
T
O
P
S
T
A
R
T
S
Slave
T
A address
R
T
A
C
address K
H
Slave
…
A
C
K
H
tWR
Second write command
…
S
T
A
R
T
A
C
address K
H
Slave
S
T Slave
A
R address
T
A
C
K
L
Word
address
A
C
K
L
Data
A
C
K
L
S
T
O
P
tWR
After completion of internal write,
ACK = LOW is sent back, so input
next word address and data in
succession.
Fig.44 Case to continuously write by acknowledge polling
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11/18
2010.09 - Rev.A
Technical Note
BU9847GUL-W
●WP valid timing (write cancel)
WP is usually to “H” or “L”, but when WP is used to cancel write cycle and so forth, pay attention to the following
WP valid timing.
During write cycle execution, in cancel valid area, by setting WP = “H”, write cycle can be cancelled. In both byte write cycle
and page write cycle, the area from the first start condition of command to the rise of clock to taken in D0 of data (in page
write cycle, the first byte data) is cancel invalid area.
WP input in this area becomes don’t care. Set the setup time to rise of D0 taken SCL 100ns or more. The area from the rise
of SCL to take in D0 to the end of internal automatic write (tWR) is cancel valid area. And, when it is set WP = “H” during
tWR, write is ended forcibly, data of address under access is not guaranteed, therefore, write it once again. (Refer to
Fig.45.) After execution of forced end by WP, standby status gets in, so there is no need to wait for tWR (5ms at maximum).
·Rise of D0 taken clock
SCL
SCL
·Rise of SDA
SDA
D1
D0
SDA
ACK
Enlarged view
SDA
S
A
A
T Slave C Word C
D7 D6 D5 D4 D3 D2 D1 D0
A
K
K
R address L address L
T
WP cancel invalid area
A
C
K
L
D0
ACK
Enlarged view
Data
A
C
K
L
S
T
O
P
tWR
WP cancel valid area
Write forced end
Data is not written
Data not guaranteed
WP
Fig. 45 WP valid timing
●Command cancel by start condition and stop condition
During command input, by continuously inputting start condition and stop condition, command can be cancelled.
(Refer to fig.46)
However, in ACK output area and during data read, SDA bus may output “L”, and in this case, start condition and stop
condition cannot be input, so reset is not available. Therefore, execute software reset. and when command is cancelled by
start, stop condition, during random read cycle, sequential read cycle, or current read cycle, internal setting address is not
determined, therefore, it is not possible to carry out current read cycle in succession. When to carry out read cycle in
succession, carry out random read cycle.
SCL
SDA
1
0
1
0
Start condition
Stop condition
Fig. 46 Case of cancel by start, stop condition during slave address input
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© 2010 ROHM Co., Ltd. All rights reserved.
12/18
2010.09 - Rev.A
Technical Note
BU9847GUL-W
●I/O peripheral circuit
○Pull up resistance of SDA terminal
SDA is NMOS open drain, so requires pull up resistance. As for this resistance value (RPU), select an appropriate value to
this resistance value from microcontroller VIL, IL, and VOL-IOL characteristics of this IC. If RPU is large, action frequency is
limited. The smaller the RPU, the larger the consumption current at action.
○Maximum value of RPU
The maximum value of RPU is determined by the following factors.
(1) SDA rise time to be determined by the capacity (CBUS) of bus line of RPU and SDA should be tR or below.
And AC timing should be satisfied even when SDA rise time is late.
A to be determined by input leak total (IL) of device connected to bus at output of “H” to
(2) The bus electric potential ○
SDA bus and RPU should sufficiently secure the input “H” level (VIH) of microcontroller and EEPROM including
recommended noise margin 0.2Vcc.
VCC-ILRPU-0.2 VCC ≥ VIH
RPU ≤
∴
BU9847GUL-W
Microcontroller
0.8VCC-VIH
IL
RPU
Ex.) When VCC =3V, IL=10μA, VIH=0.7 Vcc
from (2)
R PU ≤
≤
0.8×3-0.7×3
10×10
SDA terminal
A
IL
IL
-6
Bus line
capacity CBUS
300 ［kΩ］
Fig.47 I/O circuit diagram
○Minimum value of RPU
The minimum value of RPU is determined by the following factors.
(1) When IC outputs LOW, it should be satisfied that VOLMAX = 0.4V and IOLMAX = 3mA.
VCC-VOL
≤ IOL
∴RPU≥
VCC-VOL
IOL
RPU
(2) VOLMAX = 0.4V should secure the input “L” level (VIL) of microcontroller and EEPROM including recommended
noise margin 0.1VCC.
VOLMAX ≤ VIL – 0.1VCC
Ex.) When VCC = 3V, VOL = 0.4V, IOL = 3mA, microcontroller, EEPROM VIL = 0.3VCC
From (1),
And
∴RPU≥
3-0.4
-3
3 x 10
≥867[Ω]
VOL = 0.4[V]
VIL = 0.3 x 3
=0.9 [V]
Therefore, the condition (2) is satisfied.
○Pull up resistance of SCL terminal
When SCL control is made at CMOS output port, there is no need, but in the case there is timing where SCL becomes
“Hi-Z”, add a pull up resistance. As for the pull up resistance, one of several kΩ ~ several ten kΩ is recommended in
consideration of drive performance of output port of microcontroller.
●A2, WP process
○Process of device address terminals (A2)
Check whether the set device address coincides with device address input sent from the master side or not, and select
one among plural devices connected to a same bus. Connect this terminal to pull up of pull down, or VCC or GND.
○Process of WP terminal
WP terminal is the terminal that prohibits and permits write in hardware manner. In “H” status, only READ is available and
WRITE of all addresses is prohibited. In the case of “L”, both are available. In the case to use it as an ROM, it is
recommended to connect it to pull up or VCC. In the case to use both READ and WRITE, control WP terminal or connect it
to pull down or GND.
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© 2010 ROHM Co., Ltd. All rights reserved.
13/18
2010.09 - Rev.A
Technical Note
BU9847GUL-W
●Cautions on microcontroller connection
○Rs
2
In I C BUS, it is recommended that SDA port is of open drain input / output. However, when to use COMS input / output
of tri state to SDA port, insert a series resistance Rs between the pull up resistance RPU and the SDA terminal of
EEPROM. This controls over protection of SDA terminal against surge. Therefore, even when SDA port is open drain
input / output, Rs can be used.
ACK
SCL
RPU
RS
Microcontroller
SDA
“H” output of
microcontroller
“L” output of EEPROM
Over current flows to SDA line by “H” output of
microcontroller and “L” output of EEPROM.
EEPROM
Fig.49 Input / output collision timing
Fig.48 I/O circuit diagram
○Maximum value of Rs
The maximum value of Rs is determined by the following relations.
(1) SDA rise time to be determined by the capacity (CBUS) of bus line of RPU and SDA should be tR or below.
And AC timing should be satisfied even when SDA rise time is late.
(2) The bus electric potential A to be determined by RPU and Rs at the moment when EEPROM outputs “L” to SDA bus
should sufficiently secure the input “L” level (VIL) of microcontroller including recommended noise margin 0.1VCC.
(VCC-VOL)×RS
RPU+RS
VCC
RPU A
RS
∴ RS
IOL
VIL-VOL-0.1VCC
1.1VCC-VIL
≤
VOL
VIL
×
RPU
Example) When VCC=3V, VIL=0.3VCC, VOL=0.4V, RPU=20kΩ
Bus line
capacity CBUS
From (2)
VIL
+ VOL+0.1VCC≤
RS
0.3×3-0.4-0.1×3
1.1×3-0.3×3
≤
×
20×10
3
EEPROM
Microcontroller
≤ 1.67［kΩ］
Fig.50 I/O circuit diagram
○Minimum value of Rs
The minimum value of Rs is determined by over current at bus collision. When over current flows, noises in power source
line, and instantaneous power failure of power source may occur. When allowable over current is defined as I, the
following relation must be satisfied. Determine the allowable current in consideration of impedance of power source line
in set and so forth. Set the over current to EEPROM 10mA or below.
RPU
RS
VCC
RS
"L" output
∴ RS ≥
Over current I
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VCC
I
RS
EEPROM
Fig.51 I/O Circuit diagram
© 2010 ROHM Co., Ltd. All rights reserved.
I
Example) When Vcc =3V, I = 10mA,
"H" output
Microcontroller
≤
14/18
≥
3
-3
10×10
≥
300［Ω］
2010.09 - Rev.A
Technical Note
BU9847GUL-W
●I2C BUS input / output circuit
○Input (A2,SCL)
Fig.52 Input pin circuit diagram
○Input / output (SDA)
Fig.53 Input / output pin circuit diagram
○Input (WP)
Fig.54 Input pin circuit diagram
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15/18
2010.09 - Rev.A
Technical Note
BU9847GUL-W
●Notes on power ON
At power on, in IC internal circuit and set, Vcc rises through unstable low voltage area, and IC inside is not completely reset,
and malfunction may occur. To prevent this, function of POR circuit and LVCC circuit are equipped. To assure the action,
observe the following conditions at power on.
1. Set SDA= “H” and SCL = “L” or “H”.
2. Start power source so as to satisfy the recommended conditions of tR, tOFF, and Vbot for operating POR circuit.
tR
VCC
Recommended conditons of tR, tOFF, Vbot
tOFF
Vbot
0
tR
tOFF
Vbot
10ms or below
10ms or higher
0.3V or below
100ms or below
10ms or higher
0.2V or below
Fig. 55 Rise waveform diagram
3. Set SDA and SCL so as not to become “Hi-Z”.
When the above conditions 1 and 2 cannot be observed, take the following countermeasures.
a) In the case when the above condition 1 cannot be observed. When SDA becomes “L” at power on.
→ Control SCL and SDA as shown below, to make SCL and, “H” and “H”.
V CC
tLOW
SCL
SDA
After Vcc becomes stable
After Vcc becomes stable
tDH
tSU:DAT
Fig.56 When SCL =”H” and SDA = “L”
tSU:DAT
Fig.57 When SCL = “H” and SDA = “L”
b) In the case when the above condition 2 cannot be observed.
→ After power source becomes stable, execute software reset (P10).
c) In the case when the above conditions 1 and 2 cannot be observed.
→ Carry out a), and then carry out b).
●Low voltage malfunction prevention function
LVCC circuit prevents data rewrite action at low power, and prevents wrong write. At LVCC voltage (Typ. = 1.2V) or below, it
prevent data rewrite.
●Vcc noise countermeasures
○Bypass capacitor
When noise or surge gets in the power source line, malfunction may occur, therefore, for removing tese, it is
recommended to attach a by pass capacitor (0.1μF) between IC Vcc and GND. At that moment , attach it as close to IC
as possible. And, it is also recommended to attach a bypass capacitor between board Vcc and GND.
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© 2010 ROHM Co., Ltd. All rights reserved.
16/18
2010.09 - Rev.A
Technical Note
BU9847GUL-W
●Cautions on use
(1) Described numeric values and data are design representative values, and the values are not guaranteed.
(2) We believe that application circuit examples are recommendable, however, in actual use, confirm characteristics further
sufficiently. In the case of use by changing the fixed number of external parts, make your decision with sufficient margin in
consideration of static characteristics and transition characteristics and fluctuations of external parts and our LSI.
(3) Absolute maximum ratings
If the absolute maximum ratings such as impressed voltage and action temperature range and so forth are exceeded, LSI
may be destructed. Do not impress voltage and temperature exceeding the absolute maximum ratings. In the case of fear
exceeding the absolute maximum ratings, take physical safety countermeasures such as fuses, and see to it that
conditions exceeding the absolute maximum ratings should not be impressed to LSI.
(4) GND electric potential
Set the voltage of GND terminal lowest at any action condition. Make sure that each terminal voltage is lower than that of
GND terminal.
(5) Thermal design
In considereation of permissible loss in actual use condition, carry out heat design with sufficient margin.
(6) Terminal to terminal shortcircuit and wrong packaging
When to package LSI onto a board, pay sufficient attention to LSI direction and displacement. Wrong packaging may
destruct LSI. And in the case of shortcircuit between LSI terminals and terminals and power source, terminal and GND
owing to foreign matter, LSI may be destructed.
(7) Use in a strong electromagnetic field may cause malfunction, therefore, evaluate design sufficiently.
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© 2010 ROHM Co., Ltd. All rights reserved.
17/18
2010.09 - Rev.A
Technical Note
BU9847GUL-W
●Ordering part number
B
U
Part No.
9
8
4
7
Part No.
G
U
L
Package
GUL : VCSP50L1
- W
W-CELL
E
2
Packaging and forming specification
E2: Embossed tape and reel
VCSP50L1(BU9847GUL-W)
<Tape and Reel information>
Tape
Embossed carrier tape
Quantity
3000pcs
Direction
of feed
0.55MAX
1.06±0.05
1.95±0.05
0.10±0.05
1PIN MARK
E2
The direction is the 1pin of product is at the upper left when you hold
( reel on the left hand and you pull out the tape on the right hand
)
0.08 S
(φ0.15)INDEX POST
6-φ0.25±0.05
0.05 A B
A
0.5
B B
A
1
0.475±0.05
0.28 ±0.05
S
2
3
1pin
P=0.5×2
(Unit : mm)
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© 2010 ROHM Co., Ltd. All rights reserved.
Reel
18/18
Direction of feed
∗ Order quantity needs to be multiple of the minimum quantity.
2010.09 - Rev.A
Notice
Notes
No copying or reproduction of this document, in part or in whole, is permitted without the
consent of ROHM Co.,Ltd.
The content specified herein is subject to change for improvement without notice.
The content specified herein is for the purpose of introducing ROHM's products (hereinafter
"Products"). If you wish to use any such Product, please be sure to refer to the specifications,
which can be obtained from ROHM upon request.
Examples of application circuits, circuit constants and any other information contained herein
illustrate the standard usage and operations of the Products. The peripheral conditions must
be taken into account when designing circuits for mass production.
Great care was taken in ensuring the accuracy of the information specified in this document.
However, should you incur any damage arising from any inaccuracy or misprint of such
information, ROHM shall bear no responsibility for such damage.
The technical information specified herein is intended only to show the typical functions of and
examples of application circuits for the Products. ROHM does not grant you, explicitly or
implicitly, any license to use or exercise intellectual property or other rights held by ROHM and
other parties. ROHM shall bear no responsibility whatsoever for any dispute arising from the
use of such technical information.
The Products specified in this document are intended to be used with general-use electronic
equipment or devices (such as audio visual equipment, office-automation equipment, communication devices, electronic appliances and amusement devices).
The Products specified in this document are not designed to be radiation tolerant.
While ROHM always makes efforts to enhance the quality and reliability of its Products, a
Product may fail or malfunction for a variety of reasons.
Please be sure to implement in your equipment using the Products safety measures to guard
against the possibility of physical injury, fire or any other damage caused in the event of the
failure of any Product, such as derating, redundancy, fire control and fail-safe designs. ROHM
shall bear no responsibility whatsoever for your use of any Product outside of the prescribed
scope or not in accordance with the instruction manual.
The Products are not designed or manufactured to be used with any equipment, device or
system which requires an extremely high level of reliability the failure or malfunction of which
may result in a direct threat to human life or create a risk of human injury (such as a medical
instrument, transportation equipment, aerospace machinery, nuclear-reactor controller, fuelcontroller or other safety device). ROHM shall bear no responsibility in any way for use of any
of the Products for the above special purposes. If a Product is intended to be used for any
such special purpose, please contact a ROHM sales representative before purchasing.
If you intend to export or ship overseas any Product or technology specified herein that may
be controlled under the Foreign Exchange and the Foreign Trade Law, you will be required to
obtain a license or permit under the Law.
Thank you for your accessing to ROHM product informations.
More detail product informations and catalogs are available, please contact us.
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R1010A