THIS SPEC IS OBSOLETE Spec No: 38-07333 Spec Title: CY22K7 133-MHz Spread Spectrum Clock Generator For Use With the AMD-K7® Processor and AMD-750 Chipset Sunset Owner: Rose Galindez (RGL) Replaced by: None 1CY22K7 CY22K7 133-MHz Spread Spectrum Clock Generator For Use With the AMD-K7® Processor and AMD-750 Chipset Features Benefits • Multiple output clocks running at different frequencies Main clock generator for PC motherboard designs using the ® — Three open-drain differential CPU outputs running up AMD-K7 processor and AMD-750 Chipset to 133 MHz — Supports up to two CPUs and chipset — Eight 3.3V synchronous PCI clocks (one free running) — Support for 4 PCI slots and chipset — Two 3.3V AGP clocks at 2xPCI — Supports designs using AGP — One dedicated 3.3V USB clock at 48 MHz — Supports designs using USB — One 3.3V USB/IO clock at 48 MHz or 24 MHz, selectable — Allows for one additional USB output or support for I/O via power-on latch input chip from various vendors — One 3.3V SDRAM clock output running at the CPU fre— Supports SDRAM memory architecture with external quency PLL buffer — Two 3.3V Reference clocks at 14.318 MHz — Supports ISA slots and I/O chip • Spread Spectrum clocking — 33 kHz modulation frequency — −0.6% downspread margin EMI reduction • Dedicated inputs for various functions — PCI_STOP — CPU_STOP — PWR_DWN — SPREAD — TEST — USB/IO — FS [0:1] Provides system design flexibility and power management — Stops all PCI clocks (except PCICLK_F0) when LOW — Stops all CPU clocks when LOW — Power is removed from internal logic when LOW — Activates Spread Spectrum for lower EMI — Used to enter Test Mode — Selects USB or SuperIO Clock — Power-on latched inputs for frequency select options • Serial Programming Interface Dynamic control of output clock signals via SMBus • 48-Pin SSOP package Industry-standard package provides cost and space savings Logic Block Diagram XTALIN XTALOUT 14.318 MHz Xtal Oscillator REF [0:1] SDRAM_OUT CPU_STOP SPREAD CPUCLKT [0:2] CPUCLKC [0:2] STOP LOGIC CPU PLL FSO FS1 TEST DIVIDER CONTROL LOGIC AGPCLK [0:1] 2X STOP LOGIC SCLK SDATA PCICLK [0:6] PCICLK_F PCI_STOP USB0 SYSTEM PLL /2 USB/IO PWR_DWN LATCH USB/IO Cypress Semiconductor Corporation Document #: 38-07333 Rev. OBS • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Revised December 01, 2004 CY22K7 Pin Configuration 48-pin SSOP Top View FS0/REF0 FS1/REF1 VSSREF XTALIN 1 2 3 48 47 46 4 VDDREF VSSSDRAM SDRAM_OUT VDDSDRAM 5 6 43 PCICLK_F 7 42 CPUCLKC2 CPUCLKT2 41 VSSCPU 40 39 38 CPUCLKC1 PCICLK1 PCICLK2 VSSPCI 8 9 10 11 12 PCICLK3 13 PCICLK4 VDDPCI PCICLK5 14 15 37 36 35 34 CPUCLKC0 CPUCLKT0 RESERVED 16 33 PCICLK6 VDDAGP AGP0 AGP1 17 32 PCI_STOP 18 31 CPU_STOP 19 20 30 29 PWR_DWN SPREAD VSSAGP VDDUSB 21 28 22 27 USB0 USB/IO (SELECT) 23 24 26 25 TEST SDATA SCLK PCICLK0 VDDPCI CY22K7 XTALOUT VSSPCI 45 44 RESERVED CPUCLKT1 VSSCPU AVDD AVSS VSSUSB Pin Summary[1] Pin Number Pin Name Type Description 34 AVDD PWR Isolated power for core 33 AVSS PWR Isolated ground for core 48 VDDREF PWR Power for REF[0:1], XTALIN, XTALOUT 3 VSSREF PWR Ground for REF[0:1] outputs 1, 2 FS[0:1]/REF[0:1] IN/OUT Frequency select input at power-on/14.318-MHz output 4 XTALIN[2] IN 14.318-MHz reference crystal input 5 XTALOUT OUT 14.318-MHz reference crystal feedback 9, 15 VDDPCI PWR Power for PCICLK outputs 6, 12 VSSPCI PWR Ground for PCICLK outputs 7 PCICLK_F OUT Free running PCI output 8, 10, 11, 13, 14, 16, 17 PCICLK[0:6] OUT PCI clock outputs, TTL compatible 3.3V 18 VDDAGP PWR Power for AGP outputs 21 VSSAGP PWR Ground for AGP outputs 19, 20 AGP[0:1] OUT AGP clock outputs 22 VDDUSB PWR Power for USB outputs 25 VSSUSB PWR Ground for USB outputs 23 USB0 OUT USB clock output 24 USB/IO (SELECT) IN/OUT USB or Super I/O output selected at power-on by latched input resistor: LOW = 48 MHz, HIGH = 24 MHz 26 SCLK IN/OUT SMBus Clock 27 SDATA IN/OUT SMBus Data 28 TEST IN Three-state or Test Mode when LOW Document #: 38-07333 Rev. OBS Page 2 of 12 CY22K7 Pin Summary[1] (continued) Pin Number Pin Name Type Description 29 SPREAD IN Enables spread spectrum when LOW 30 PWR_DWN[3] IN Power-down when LOW, removes power from internal logic 31 CPU_STOP IN Stops CPU clocks when LOW IN Stops PCI clocks when LOW [2] 32 PCI_STOP 45 VDDSDRAM PWR Power for SDRAM_OUT 47 VSSSDRAM PWR Ground for SDRAM_OUT 46 SDRAM_OUT OUT CPU reference clock for SDRAM zero delay buffer 38, 41 VSSCPU PWR Ground for CPU outputs shorted to SDRAM ground 36, 39, 42 CPUCLKT[0:2] OUT “True” clocks of differential pair for CPU and host clock outputs 37, 40, 43 CPUCLKC[0:2] OUT “Complementary” clocks of differential pair for CPU and host clock outputs 35, 44 RESERVED − Reserved for future CPU power rail Function Table TEST FS1 FS0 CPUCLK SDRAM_OUT PCICLK PCICLK_F AGP USB/IO REF 0 0 0 Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z 0 0 1 50 25 50 48/24 14.318 0 1 0 66 33 66 48/24 14.318 TCLK 0 1 1 TCLK/2 TCLK/6 TCLK/3 TCLK/4[4] 1 0 0 90 30 60 48/24 14.318 1 0 1 133 33.3 66.6 48/24 14.318 1 1 0 120 30 60 48/24 14.318 1 1 1 100 33.3 66.6 48/24 14.318 Power Management Modes PCI_ PWR_DWN CPU_STOP STOP CPU+ CPU- PCICLK PCICLK_ F Other Clocks Oscillator PLLs 0 X X Low High Low Low Low Off Off 1 0 0 Low High Low Running Running Running Running 1 0 1 Low High Running Running Running Running Running 1 1 0 Running Running Low Running Running Running Running 1 1 1 Running Running Running Running Running Running Running Notes: 1. All control pins have internal pull-ups of 56K including: USB/IO, TEST, SPREAD, PWR_DWN, CPU_STOP, PCI_STOP. 2. Part will go into test mode if three rising edges come on PCI_STOP while XTALIN is held LOW. 3. Part will consume more shutdown current if external pull-ups are connected on latched input/outputs during power-down. 4. TCLK/4 if Select = 0; TCLK/8 if Select = 1. Document #: 38-07333 Rev. OBS Page 3 of 12 CY22K7 Spread Spectrum Clocking Spread Spectrum Disabled Amplitude (dB) Spread Spectrum Enabled Frequency (MHz) Description Output Min Max Unit CPUCLK, PCICLK, SDRAM_OUT, AGPCLK 30.0 33.0 kHz Downspread margin at the fundamental frequency CPUCLK, PCICLK, SDRAM_OUT, AGPCLK 0.0 −0.6 % Modulation Frequency Document #: 38-07333 Rev. OBS Page 4 of 12 CY22K7 Serial Configuration Map • SPI Address for the CY22K7 is: • The Serial bits will be read by the clock driver in the following order: Byte 0 - Bits 7, 6, 5, 4, 3, 2, 1, 0 A6 A5 A4 A3 A2 A1 A0 R/W 1 1 0 1 0 0 1 − Bytes 0 to 3 will be ignored. Byte 1 - Bits 7, 6, 5, 4, 3, 2, 1, 0 Byte N - Bits 7, 6, 5, 4, 3, 2, 1, 0 Byte 4: Clock Control Register (1 = Active, 0 = Inactive) Bit Pin # Default Description 7 1 Active REF0 6 24 Active USB/IO 5 23 Active USB0 4 20 Active AGP1 3 19 Active AGP0 2 42, 43 Active CPUCLK2 (both of differential pair, “True” and “Complementary”) 1 39, 40 Active CPUCLK1 (both of differential pair, “True” and “Complementary”) 0 36, 37 Active CPUCLK0 (both of differential pair, “True” and “Complementary”) Byte 5: PCI/REF Clock Control Register (1 = Active, 0 = Inactive) Bit Pin # Default Description 7 2 Active REF1 6 17 Active PCICLK6 5 16 Active PCICLK5 4 14 Active PCICLK4 3 13 Active PCICLK3 2 11 Active PCICLK2 1 10 Active PCICLK1 0 8 Active PCICLK0 Byte 6: SDRAM Clock & Generator Mode Control Register (1 = Active, 0 = Inactive) Bit Pin # Default 7 − Inactive 6 − Active 5 − Active 4 − Active 3 − Active Reserved 2 − Active Reserved 1 − Inactive 0 46 Active Document #: 38-07333 Rev. OBS Description Spread Spectrum Bits[6:4] correspond to the Function Table on page 3 Bit 6 = TEST, Bit 5 = FS1, Bit 4 = FS0 example: Bits[6:4] = ‘111’ -- 100-MHz CPUCLK and SDRAM_OUT clocks SPI (directs the generator to utilize either SPI feature selection if bit is enabled or pin-based feature if bit is disabled) SDRAM_OUT Page 5 of 12 CY22K7 Maximum Ratings Storage Temperature (Non-Condensing) .. – 65°C to +150°C (Above which the useful life may be impaired. For user guidelines, not tested.) Junction Temperature............................................... +150°C Supply Voltage .................................................– 0.5 to +4.0V Package Power Dissipation........................................... 0.7W Input Voltage ........................................... – 0.5V to VDD + 0.5 Static Discharge Voltage (per MIL-STD-883, Method 3015) ............................. >2000V CY22K7 DC Operating Conditions Over which the DC Characteristics are Guaranteed Parameter Description VDD 3.3V Power Supply Voltages TA Operating Temperature, Ambient CL Maximum Capacitive Load on SDRAM_OUT PCICLK PCICLK_F AGPCLK USB, REF fREF Reference Frequency, Oscillator Nominal Value tPU Power-up time for all VDD's to reach minimum specified voltage (power ramps must be monotonic) Min. Max. Unit 3.135 3.465 V 0 70 °C pF 30 30 30 30 20 14.318 14.318 MHz 0.05 50 ms Electrical Characteristics Over the Operating Range Parameter Description Test Conditions Min. Max. Unit VIH High-level Input Voltage VIL Low-level Input Voltage Except Crystal Pads 0.8 V IIH Input High Current 0 < VIN < VDD 10 µA IIL Input Low Current 0 < VIN < VDD 50 µA IOH High-level Output Current mA IOL Low-level Output Current Except Crystal Pads. Threshold voltage for crystal pads = VDD/2 V SDRAM_OUT VOUT = 2.0V −19 PCICLK VOUT = 2.0V −26 PCICLK_F VOUT = 2.0V −19 AGPCLK VOUT = 2.0V −26 USB, USB/IO, REF VOUT = 2.0V −22 CPUCLK VOUT = 0.3V 16 SDRAM_OUT VOUT = 0.8V 12 PCICLK VOUT = 0.8V 19 PCICLK_F VOUT = 0.8V 12 AGPCLK VOUT = 0.8V 19 USB, USB/IO, REF VOUT = 0.8V 16 IOZ Output Leakage Current IDD IDDPD 3.3V Power Supply Current VDD = 3.465V, FCPU = 133 MHz 3.3V Shutdown Current VDD = 3.465V VIHS SMBus Input High Level VILS SMBus Input Low Level Document #: 38-07333 Rev. OBS 2.0 Three-state mA 10 µA 175 mA 200 µA 0.7 V 0.3 V Page 6 of 12 CY22K7 Electrical Characteristics Over the Operating Range Parameter Description Test Conditions Min. Max. Unit CY22K7 CPUCLK Driver Characteristics (Open Drain)[7] Parameter Description Conditions Min. Typ. 0.4 Max. Unit Vpullup (External) + 0.6 V VDIF Differential Voltage See Note 5 Vx Differential Crossover Voltage Vpullup is to 1.5V 550 750 950 mV VX Differential Crossover Voltage Vpullup (External) = 1.4 to 1.9V Min. = (Vpullup (External)/2) – 150 mV Max. = (Vpullup (External)/2) + 150 mV 550 750 1100 mV CY22K7 Switching Characteristics[6, 7] Over the Operating Range @ 100 MHz Parameter Output Description Test Conditions Min. Typ. Max. Unit 55 % t1 All Output Duty Cycle t1A/t1B[8] t2 CPU Rising Edge Rate At Output of CY22K7 CPU± 1.0 V/ns t2 CPU Rising Edge Rate As measured at Observation Point in Figure 1 0.4 V/ns t2 PCI Rise Time Between 0.4V and 2.4V t2 SDRAM_OUT Rise Time Between 0.4V and 2.4V t2 AGP Rise Time Between 0.4V and 2.4V t2 USB, REF Rise Time Between 0.4V and 2.4V t3 CPU Falling Edge Rate At Output of CY22K7 CPU± 1.0 V/ns t3 CPU Falling Edge Rate As measured at Observation Point in Figure 1 0.4 V/ns t3 PCI Fall Time Between 2.4V and 0.4V t3 SDRAM_OUT Fall Time Between 2.4V and 0.4V t3 AGP Fall Time Between 2.4V and 0.4V t3 USB, REF Fall Time Between 2.4V and 0.4V t4 CPU, PCI CPU-PCI Offset Load shown in Figure 1 & Figure 2 500 t4 CPU, SDRAM CPU-SDRAM Skew Load shown in Figure 1 & Figure 2 500 t4 CPU, AGP CPU-AGP Skew Load shown in Figure 1 & Figure 2 t4 CPU, CPU CPU-CPU Skew Load shown in Figure 1 250 ps t4 PCI, PCI PCI-PCI Skew Load shown in Figure 2 500 ps t5 CPU Cycle-Cycle Clock Jitter Measured at VX, t5A–t5B 250 ps 45 0.4 0.4 2.0 ns 2.0 ns 2.0 ns 4.0 ns 2.0 ns 2.0 ns 2.0 ns 4.0 ns 700 ps 700 ps 1000 ps Notes: 5. VDIF specifies the minimum input differential voltages (VTR – VCP) required for switching, where VTR is the ‘true’ input level and VCP is the ‘complement’ input level. 6. All parameters specified with loaded outputs. 7. All parameters for CPU are measured at observation point shown in Figure 1 on page 10 and parameters for PCI, SDRAM & AGP are measured at observation point shown in Figure 2 on page 11 unless otherwise mentioned. 8. For 133-MHz Output Duty Cycle will be guaranteed at 40% Min., 60% Max. Document #: 38-07333 Rev. OBS Page 7 of 12 CY22K7 Switching Waveforms Differential Clock Parameters VDDCPU VTR VDIF VCP VX VSS Duty Cycle Timing t1A t1B OUTPUT All Outputs Rise/Fall Time VDD OUTPUT 0V t2 t3 Output_A-Output_B Clock Skew OUTPUT_A OUTPUT_B t4 Cycle-Cycle Clock Jitter t5A t5B CLK CLK Document #: 38-07333 Rev. OBS Page 8 of 12 CY22K7 Switching Waveforms (continued) CPU_STOP Timing [9,10] CPUCLK (Internal) PCICLK (Internal) PCICLK (Free-Running) CPU_STOP CPU, CPU/2, AGP (External) PCI_STOP CPUCLK (Internal) PCICLK (Internal) PCICLK (Free-Running) PCI_STOP PCICLK (External) PWR_DOWN [11] CPUCLK (Internal) PCICLK (Internal) PWR_DWN CPUCLK (External) PCICLK (External) VCO Crystal Shaded section on the VCO and Crystal waveforms indicates that the VCO and crystal oscillator are active, and there is a valid clock. Notes: 9. CPUCLK on and CPUCLK off latency is 2 or 3 CPUCLK cycles. 10. CPU_STOP may be applied asynchronously. It is synchronized internally. 11. USB, USB/IO, REF are not synchronized when entering/leaving power-down. Document #: 38-07333 Rev. OBS Page 9 of 12 CY22K7 VDDCPU VDD V1 V2 VDD VDD T1 R8 VDDCPU R1 R11 T2 C1 T3 R4 Observation Point CPUCLK_T R5 R2 T5 T4 R9 C3 VDDCPU C2 T6 R6 CPUCLK_C R7 CY22K7 R3 R10 K7 CLOCK INPUT VDD VDD C4 Figure 1. AMD CPU Load Circuit Component Values Symbol Value V1 3.3V V2 1.5V R1,3 95Ω R2 360Ω R4,5,6,7 500Ω R8,9 50Ω R10,11 150Ω C1,2 680 pF C3,4 20 pF T1,4 Z0 = 50Ω length = 5” T2,5 Z0 = 50Ω length = 3” T3,6 Z0 = 50Ω length = 1” Document #: 38-07333 Rev. OBS Page 10 of 12 CY22K7 Observation Point PCI, SDRAM, AGP 33Ω Zo=50Ω, 5" 12 pF Figure 2. Test Circuit for PCI/SDRAM/AGP Ordering Information Ordering Code CY22K7PVC-1 Package Name O48 Package Type 48-pin SSOP Operating Range Commercial Package Diagram 48-Lead Shrunk Small Outline Package O48 51-85061-B AMD-K7 is a registered trademark of Advanced Micro Devices. Document #: 38-07333 Rev. OBS Page 11 of 12 © Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY22K7 Revision History Document Title: CY22K7 133-MHz Spread Spectrum Clock Generator For Use With the AMD-K7® Processor and AMD-750 Chipset Document Number: 38-07333 REV. ECN NO. Issue Date Orig. of Change ** 111732 12/16/01 DSG Change from Spec number: 38-00745 to 38-07333 *A 121856 12/14/02 RBI Power up requirements added to Operating Conditions Information OBS 294235 See ECN RGL To Obsolete the DS Document #: 38-07333 Rev. OBS Description of Change Page 12 of 12