LINER LTC2492CDE-TRPBF 24-bit 2-/4-channel î î£ adc with easy drive input current cancellation Datasheet

LTC2492
24-Bit 2-/4-Channel ΔΣ
ADC with Easy Drive Input
Current Cancellation
FEATURES
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DESCRIPTION
Up to 2 Differential or 4 Single-Ended Inputs
Easy Drive Technology Enables Rail-to-Rail Inputs
with Zero Differential Input Current
Directly Digitizes High Impedance Sensors with
Full Accuracy
600nV RMS Noise
Integrated High Accuracy Temperature Sensor
GND to VCC Input/Reference Common Mode Range
Programmable 50Hz, 60Hz, or Simultaneous
50Hz/60Hz Rejection Mode
2ppm INL, No Missing Codes
1ppm Offset and 15ppm Full-Scale Error
2x Speed Mode/Reduced Power Mode (15Hz Using
Internal Oscillator and 80μA at 7.5Hz Output)
No Latency: Digital Filter Settles in a Single Cycle,
Even After a New Channel is Selected
Single Supply 2.7V to 5.5V Operation (0.8mW)
Internal Oscillator
Tiny DFN 4mm × 3mm Package
The LTC®2492 is a 4-channel (2-channel differential),
24-bit, No Latency Δ∑™ ADC with Easy Drive™ technology.
The patented sampling scheme eliminates dynamic input
current errors and the shortcomings of on-chip buffering
through automatic cancellation of differential input current.
This allows large external source impedances and rail-torail input signals to be directly digitized while maintaining
exceptional DC accuracy.
The LTC2492 includes a high accuracy temperature sensor
and an integrated oscillator. This device can be conﬁgured
to measure an external signal (from combinations of
4 analog input channels operating in single-ended or
differential modes) or its internal temperature sensor. It
can be programmed to reject line frequencies of 50Hz,
60Hz, or simultaneous 50Hz/60Hz and conﬁgured to double
its output rate. The integrated temperature sensor offers
1/30th °C resolution and 2°C absolute accuracy.
The LTC2492 allows a wide common mode input range
(0V to VCC), independent of the reference voltage. Any
combination of single-ended or differential inputs can
be selected and the ﬁrst conversion after a new channel
selection is valid.
APPLICATIONS
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Direct Sensor Digitizer
Direct Temperature Measurement
Instrumentation
Industrial Process Control
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
No Latency Δ∑ and Easy Drive are trademarks of Linear Technology Corporation. All other
trademarks are the property of their respective owners.
TYPICAL APPLICATION
Absolute Temperature Error
Data Acquisition System with Temperature Compensation
5
2.7V TO 5.5V
4
4-CHANNEL
MUX
CH2
IN+
REF+
24-BIT Δ∑ ADC
WITH EASY-DRIVE
IN–
CH3
0.1μF
REF –
SDI
SCK
SDO
CS
4-WIRE
SPI INTERFACE
3
ABSOLUTE ERROR (°C)
10μF
VCC
CH0
CH1
2
1
0
–1
–2
–3
COM
–4
TEMPERATURE
SENSOR
FO
OSC
2492 TA01a
–5
–55
–30
–5
20
45
70
TEMPERATURE (°C)
95
120
2492 TA01b
2492fb
1
LTC2492
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Notes 1, 2)
Supply Voltage (VCC) ...................................– 0.3V to 6V
Analog Input Voltage
(CH0 to CH3, COM) ................. – 0.3V to (VCC + 0.3V)
REF +, REF – .................................. – 0.3V to (VCC + 0.3V)
Digital Input Voltage..................... – 0.3V to (VCC + 0.3V)
Digital Output Voltage .................. – 0.3V to (VCC + 0.3V)
Operating Temperature Range
LTC2492C ................................................ 0°C to 70°C
LTC2492I..............................................– 40°C to 85°C
Storage Temperature Range...................– 65°C to 150°C
FO
1
14 REF –
SDI
2
13 REF +
SCK
3
CS
4
SDO
5
10 CH2
GND
6
9 CH1
COM
7
8 CH0
12 VCC
11 CH3
15
DE PACKAGE
14-LEAD (4mm s 3mm) PLASTIC DFN
TJMAX = 125°C, θJA = 37°C/W
EXPOSED PAD (PIN 15) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC2492CDE#PBF
LTC2492CDE#TRPBF
2492
14-Lead (4mm × 3mm) Plastic DFN
0°C to 70°C
LTC2492IDE#PBF
LTC2492IDE#TRPBF
2492
14-Lead (4mm × 3mm) Plastic DFN
–40°C to 85°C
Consult LTC Marketing for parts speciﬁed with wider operating temperature ranges. *The temperature grade is identiﬁed by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based ﬁnish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel speciﬁcations, go to: http://www.linear.com/tapeandreel/
ELECTRICAL CHARACTERISTICS (NORMAL SPEED)
The ● denotes the speciﬁcations which
apply over the full operating temperature range, otherwise speciﬁcations are at TA = 25°C. (Notes 3, 4)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Resolution (No Missing Codes)
0.1V ≤ VREF ≤ VCC , –FS ≤ VIN ≤ +FS (Note 5)
Integral Nonlinearity
5V ≤ VCC ≤ 5.5V, VREF = 5V, VIN(CM) = 2.5V (Note 6)
2.7V ≤ VCC ≤ 5.5V, VREF = 2.5V, VIN(CM) = 1.25V (Note 6)
●
2
1
10
ppm of VREF
ppm of VREF
Offset Error
2.5V ≤ VREF ≤ VCC , GND ≤ IN+ = IN– ≤ VCC (Note 14)
●
0.5
2.5
μV
25
ppm of VREF
, GND ≤ IN+ = IN– ≤ V
24
Bits
Offset Error Drift
2.5V ≤ VREF ≤ VCC
Positive Full-Scale Error
2.5V ≤ VREF ≤ VCC , IN+ = 0.75VREF, IN– = 0.25VREF
Positive Full-Scale Error Drift
2.5V ≤ VREF ≤ VCC , IN+ = 0.75VREF, IN– = 0.25VREF
Negative Full-Scale Error
2.5V ≤ VREF ≤ VCC , IN+ = 0.25VREF, IN– = 0.75VREF
Negative Full-Scale Error Drift
2.5V ≤ VREF ≤ VCC , IN+ = 0.25VREF, IN– = 0.75VREF
0.1
ppm of VREF/°C
Total Unadjusted Error
5V ≤ VCC ≤ 5.5V, VREF = 2.5V, VIN(CM) = 1.25V
5V ≤ VCC ≤ 5.5V, VREF = 5V, VIN(CM) = 2.5V
2.7V ≤ VCC ≤ 5.5V, VREF = 2.5V, VIN(CM) = 1.25V
15
15
15
ppm of VREF
ppm of VREF
ppm of VREF
Output Noise
5.5V < VCC < 2.7V, 2.5V ≤ VREF ≤ VCC ,
GND ≤ IN + = IN – ≤ VCC (Note 13)
0.6
μVRMS
Internal PTAT Signal
TA = 27°C (Note 14)
Internal PTAT Temperature Coefﬁcient
10
CC
●
nV/°C
0.1
●
ppm of VREF/°C
25
27.8
28.0
93.5
28.2
ppm of VREF
mV
μV/°C
2492fb
2
LTC2492
ELECTRICAL CHARACTERISTICS (2X SPEED)
The ● denotes the speciﬁcations which apply over the
full operating temperature range, otherwise speciﬁcations are at TA = 25°C. (Notes 3, 4)
PARAMETER
CONDITIONS
Resolution (No Missing Codes)
0.1V ≤ VREF ≤ VCC , –FS ≤ VIN ≤ +FS (Note 5)
MIN
TYP
MAX
UNITS
Integral Nonlinearity
5V ≤ VCC ≤ 5.5V, VREF = 5V, VIN(CM) = 2.5V (Note 6)
2.7V ≤ VCC ≤5.5V, VREF = 2.5V, VIN(CM) = 1.2V (Note 6)
●
●
Offset Error
2.5V ≤ VREF ≤ VCC , GND ≤ IN+ = IN – ≤ VCC (Note 14)
●
Offset Error Drift
2.5V ≤ VREF ≤ VCC , GND ≤ IN+ = IN – ≤ VCC
Positive Full-Scale Error
2.5V ≤ VREF ≤ VCC , IN+ = 0.75VREF, IN – = 0.25VREF
Positive Full-Scale Error Drift
2.5V ≤ VREF ≤ VCC , IN+ = 0.75VREF, IN – = 0.25VREF
Negative Full-Scale Error
2.5V ≤ VREF ≤ VCC , IN+ = 0.25VREF, IN – = 0.75VREF
Negative Full-Scale Error Drift
2.5V ≤ VREF ≤ VCC , IN+ = 0.25VREF, IN – = 0.75VREF
0.1
ppm of VREF/°C
Output Noise
5V ≤ VCC ≤ 2.5V, VREF = 5V, GND ≤ IN + = IN – ≤ VCC
0.85
μVRMS
24
Bits
2
1
10
0.2
2
ppm of VREF
ppm of VREF
mV
100
nV/°C
●
25
0.1
ppm of VREF
ppm of VREF/°C
●
25
ppm of VREF
CONVERTER CHARACTERISTICS
The ● denotes the speciﬁcations which apply over the full operating
temperature range, otherwise speciﬁcations are at TA = 25°C. (Note 3)
PARAMETER
CONDITIONS
Input Common Mode Rejection DC
2.5V ≤ VREF ≤ VCC , GND ≤ IN+ = IN – ≤ VCC (Note 5)
MIN
, GND ≤ IN+ = IN – ≤ V
TYP
MAX
UNITS
●
140
dB
Input Common Mode Rejection 50Hz ±2%
2.5V ≤ VREF ≤ VCC
CC (Note 5)
●
140
dB
Input Common Mode Rejection 60Hz ±2%
2.5V ≤ VREF ≤ VCC , GND ≤ IN+ = IN – ≤ VCC (Note 5)
●
140
dB
110
120
dB
110
120
dB
, GND ≤ IN+ = IN – ≤ V
Input Normal Mode Rejection 50Hz ±2%
2.5V ≤ VREF ≤ VCC
CC (Notes 5, 7)
●
Input Normal Mode Rejection 60Hz ±2%
2.5V ≤ VREF ≤ VCC , GND ≤ IN+ = IN – ≤ VCC (Notes 5, 8)
●
, GND ≤ IN+ = IN – ≤ V
Input Normal Mode Rejection 50Hz/60Hz ±2%
2.5V ≤ VREF ≤ VCC
Reference Common Mode Rejection DC
2.5V ≤ VREF ≤ VCC , GND ≤ IN+ = IN – ≤ VCC (Note 5)
CC (Notes 5, 9)
= 2.5V, IN+ = IN – = GND
●
87
●
120
dB
140
dB
Power Supply Rejection DC
VREF
120
dB
Power Supply Rejection, 50Hz ±2%
VREF = 2.5V, IN+ = IN – = GND (Notes 7, 9)
120
dB
Power Supply Rejection, 60Hz ±2%
VREF = 2.5V, IN+ = IN – = GND (Notes 8, 9)
120
dB
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LTC2492
ANALOG INPUT AND REFERENCE
The ● denotes the speciﬁcations which apply over the full operating
temperature range, otherwise speciﬁcations are at TA = 25°C. (Note 3)
SYMBOL
PARAMETER
IN +
Absolute/Common Mode IN + Voltage
(IN+ Corresponds to the Selected Positive Input Channel)
CONDITIONS
GND – 0.3V
MIN
TYP
VCC + 0.3V
MAX
UNITS
V
IN –
Absolute/Common Mode IN – Voltage
(IN– Corresponds to the Selected Negative Input Channel)
GND – 0.3V
VCC + 0.3V
V
VIN
Input Differential Voltage Range (IN + – IN –)
●
–FS
+FS
V
FS
Full Scale of the Differential Input (IN + – IN –)
●
0.5VREF
LSB
Least Signiﬁcant Bit of the Output Code
●
FS/224
REF +
Absolute/Common Mode REF+ Voltage
●
0.1
VCC
V
REF –
Absolute/Common Mode REF – Voltage
●
GND
REF+ – 0.1V
V
●
0.1
V
VREF
Reference Voltage Range (REF + – REF –)
CS(IN+)
IN + Sampling Capacitance
CS(IN –)
IN – Sampling Capacitance
11
pF
CS(VREF)
VREF Sampling Capacitance
11
pF
IDC_LEAK(IN+)
IN + DC Leakage Current
Sleep Mode, IN + = GND
●
–10
1
10
nA
IDC_LEAK(IN–)
IDC_LEAK(REF+)
IDC_LEAK(REF–)
IN – DC Leakage Current
Sleep Mode, IN – = GND
●
–10
1
10
nA
REF + DC Leakage Current
Sleep Mode, REF + = VCC
Sleep Mode, REF – = GND
●
–100
1
100
nA
●
–100
1
100
nA
tOPEN
MUX Break-Before-Make
QIRR
MUX Off Isolation
VCC
V
11
REF – DC Leakage Current
VIN = 2VP-P DC to 1.8MHz
pF
50
ns
120
dB
DIGITAL INPUTS AND DIGITAL OUTPUTS
The ● denotes the speciﬁcations which apply over the
full operating temperature range, otherwise speciﬁcations are at TA = 25°C. (Note 3)
SYMBOL
PARAMETER
CONDITIONS
VIH
High Level Input Voltage (`C`S, FO, SDI)
2.7V ≤ VCC ≤ 5.5V
●
MIN
VIL
Low Level Input Voltage (`C`S, FO, SDI)
2.7V ≤ VCC ≤ 5.5V
●
VIH
High Level Input Voltage (SCK)
2.7V ≤ VCC ≤ 5.5V (Notes 10, 15)
●
VIL
Low Level Input Voltage (SCK)
2.7V ≤ VCC ≤ 5.5V (Notes 10, 15)
●
IIN
Digital Input Current (`C`S, FO, SDI)
0V ≤ VIN ≤ VCC
●
–10
IIN
Digital Input Current (SCK)
0V ≤ VIN ≤ VCC (Notes 10, 15)
●
–10
CIN
Digital Input Capacitance (`C`S, FO, SDI)
CIN
Digital Input Capacitance (SCK)
(Notes 10, 15)
VOH
High Level Output Voltage (SDO)
IO = –800μA
●
VOL
Low Level Output Voltage (SDO)
IO = 1.6mA
●
VOH
High Level Output Voltage (SCK)
IO = –800μA (Notes 10, 17)
●
IO = 1.6mA (Notes 10, 17)
●
VOL
Low Level Output Voltage (SCK)
IOZ
Hi-Z Output Leakage (SDO)
●
TYP
MAX
UNITS
VCC – 0.5
V
0.5
V
VCC – 0.5
V
0.5
V
10
μA
10
μA
10
pF
10
pF
VCC – 0.5
V
0.4
V
VCC – 0.5
V
–10
0.4
V
10
μA
POWER REQUIREMENTS
The ● denotes the speciﬁcations which apply over the full operating temperature
range, otherwise speciﬁcations are at TA = 25°C. (Note 3)
SYMBOL
PARAMETER
VCC
Supply Voltage
ICC
Supply Current
CONDITIONS
MIN
●
Conversion Current (Note 12)
Temperature Measurement (Note 12)
Sleep Mode (Note 12)
●
●
●
TYP
MAX
5.5
V
160
200
1
275
300
2
μA
μA
μA
2.7
UNITS
2492fb
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LTC2492
DIGITAL INPUTS AND DIGITAL OUTPUTS
The ● denotes the speciﬁcations which apply over the
full operating temperature range, otherwise speciﬁcations are at TA = 25°C. (Note 3)
SYMBOL
PARAMETER
CONDITIONS
fEOSC
External Oscillator Frequency Range
(Note 16)
tHEO
tLEO
tCONV_1
Conversion Time for 1x Speed Mode
tCONV_2
Conversion Time for 2x Speed Mode
fISCK
MAX
UNITS
●
MIN
10
4000
kHz
External Oscillator High Period
●
0.125
100
μs
External Oscillator Low Period
●
0.125
100
μs
50Hz Mode
60Hz Mode
Simultaneous 50/60Hz Mode
External Oscillator
●
●
●
157.2
131
144.1
160.3
133.6
146.9
41036/fEOSC (in kHz)
163.5
136.3
149.9
ms
ms
ms
ms
50Hz Mode
60Hz Mode
Simultaneous 50/60Hz Mode
External Oscillator
●
●
●
78.7
65.6
72.2
80.3
66.9
73.6
81.9
68.2
75.1
20556/fEOSC (in kHz)
ms
ms
ms
ms
38.4
fEOSC/8
kHz
kHz
Internal SCK Frequency
Internal Oscillator (Notes 10, 17)
External Oscillator (Notes 10, 11, 15)
TYP
DISCK
Internal SCK Duty Cycle
(Notes 10, 17)
●
fESCK
External SCK Frequency Range
(Notes 10, 11, 15)
●
tLESCK
External SCK Low Period
(Notes 10, 11, 15)
●
125
ns
tHESCK
External SCK High Period
(Notes 10, 11, 15)
●
125
ns
tDOUT_ISCK
Internal SCK 32-Bit Data Output Time
Internal Oscillator (Notes 10, 17)
External Oscillator (Notes 10, 11, 15)
●
0.81
tDOUT_ESCK
External SCK 32-Bit Data Output Time
(Notes 10, 11, 15)
t1
CS↓ to SDO Low
●
0
200
ns
t2
CS↑ to SDO Hi-Z
●
0
200
ns
t3
CS↓ to SCK↓
Internal SCK Mode
●
0
200
t4
CS↓ to SCK↑
External SCK Mode
●
50
tKQMAX
SCK↓ to SDO Valid
tKQMIN
SDO Hold After SCK↓
t5
SCK Set-Up Before CS↓
t7
SDI Setup Before SCK↑
t8
SDI Hold After SCK↑
45
0.83
256/fEOSC (in kHz)
55
%
4000
kHz
0.85
32/fESCK (in kHz)
●
ms
ms
ms
ns
ns
200
ns
●
15
ns
●
50
ns
(Note 5)
●
100
ns
(Note 5)
●
100
ns
(Note 5)
Note 1: Stresses beyond those listed under Absolute Maximum Ratings may
cause permanent damage to the device. Exposure to any Absolute Maximum
Rating condition for extended periods may affect device reliability and lifetime.
Note 2: All voltage values are with respect to GND.
Note 3: Unless otherwise speciﬁed:
VCC = 2.7V to 5.5V
VREFCM = VREF /2, FS = 0.5VREF
VIN = IN+ – IN –, VIN(CM) = (IN+ – IN –)/2,
where IN+ and IN – are the selected input channels.
Note 4: Use internal conversion clock or external conversion clock source
with fEOSC = 307.2kHz unless other wise speciﬁed.
Note 5: Guaranteed by design, not subject to test.
Note 6: Integral nonlinearity is deﬁned as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 7: 50Hz mode (internal oscillator) or fEOSC = 256kHz ±2% (external
oscillator).
Note 8: 60Hz mode (internal oscillator) or fEOSC = 307.2kHz ±2% (external
oscillator).
Note 9: Simultaneous 50Hz/60Hz mode (internal oscillator) or fEOSC =
280kHz ±2% (external oscillator).
Note 10: The SCK can be conﬁgured in external SCK mode or internal SCK
mode. In external SCK mode, the SCK pin is used as a digital input and the
driving clock is fESCK . In the internal SCK mode, the SCK pin is used as a
digital output and the output clock signal during the data output is fISCK .
Note 11: The external oscillator is connected to the FO pin. The external
oscillator frequency, fEOSC , is expressed in kHz.
Note 12: The converter uses its internal oscillator.
Note 13: The output noise includes the contribution of the internal
calibration operations.
Note 14: Guaranteed by design and test correlation.
Note 15: The converter is in external SCK mode of operation such that the
SCK pin is used as a digital input. The frequency of the clock signal driving
SCK during the data output is fESCK and is expressed in Hz.
Note 16: Refer to Applications Information section for performance vs
data rate graphs.
Note 17: The converter in internal SCK mode of operation such that the
SCK pin is used as a digital output.
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LTC2492
TYPICAL PERFORMANCE CHARACTERISTICS
Integral Nonlinearity
(VCC = 5V, VREF = 5V)
25°C
0
85°C
–1
–2
1
–45°C, 25°C, 90°C
0
–1
2
–3
–1.25
2.5
–0.75
Total Unadjusted Error
(VCC = 5V, VREF = 2.5V)
VCC = 5V
VREF = 2.5V
VIN(CM) = 1.25V
FO = GND
8
85°C
25°C
TUE (ppm OF VREF)
TUE (ppm OF VREF)
12
4
0
–45°C
–4
–8
2
12
85°C
8
–45°C
0
–4
Noise Histogram (6.8sps)
12
12
NUMBER OF READINGS (%)
4
–0.75
–0.25
0.25
0.75
INPUT VOLTAGE (V)
–4
1.2
1.8
2492 G07
–0.75
–0.25
0.25
0.75
INPUT VOLTAGE (V)
2492 G06
Long-Term ADC Readings
VCC = 5V, VREF = 5V, VIN = 0V, VIN(CM) = 2.5V
4 TA = 25°C, RMS NOISE = 0.60μV
10,000 CONSECUTIVE
READINGS
RMS = 0.59μV
VCC = 2.7V
AVERAGE = –0.19μV
VREF = 2.5V
10 VIN = 0V
TA = 25°C
3
8
6
4
–3 –2.4 –1.8 –1.2 –0.6 0 0.6
OUTPUT READING (μV)
1.25
5
2
1
0
–1
–2
–3
–4
0
0
85°C
–45°C
–12
–1.25
1.25
2
2
25°C
0
Noise Histogram (7.5sps)
14
–3 –2.4 –1.8 –1.2 –0.6 0 0.6
OUTPUT READING (μV)
4
2492 G05
14
6
1.25
2492 G03
–8
2492 G04
8
–0.25
0.25
0.75
INPUT VOLTAGE (V)
VCC = 2.7V
VREF = 2.5V
VIN(CM) = 1.25V
FO = GND
25°C
4
–12
–1.25
2.5
10,000 CONSECUTIVE
READINGS
RMS = 0.60μV
VCC = 5V
AVERAGE = –0.69μV
VREF = 5V
10 VIN = 0V
TA = 25°C
–0.75
Total Unadjusted Error
(VCC = 2.7V, VREF = 2.5V)
–8
–12
–2.5 –2 –1.5 –1 –0.5 0 0.5 1 1.5
INPUT VOLTAGE (V)
NUMBER OF READINGS (%)
–1
2492 G02
Total Unadjusted Error
(VCC = 5V, VREF = 5V)
8
–45°C, 25°C, 90°C
0
–3
–1.25
1.25
–0.25
0.25
0.75
INPUT VOLTAGE (V)
2492 G01
VCC = 5V
VREF = 5V
VIN(CM) = 2.5V
FO = GND
1
–2
–2
–3
–2.5 –2 –1.5 –1 – 0.5 0 0.5 1 1.5
INPUT VOLTAGE (V)
12
INL (ppm OF VREF)
–45°C
2
VCC = 2.7V
VREF = 2.5V
VIN(CM) = 1.25V
FO = GND
2
TUE (ppm OF VREF)
1
VCC = 5V
VREF = 2.5V
VIN(CM) = 1.25V
FO = GND
ADC READING (μV)
INL (ppm OF VREF)
2
Integral Nonlinearity
(VCC = 2.7V, VREF = 2.5V)
3
3
VCC = 5V
VREF = 5V
VIN(CM) = 2.5V
FO = GND
INL (ppm OF VREF)
3
Integral Nonlinearity
(VCC = 5V, VREF = 2.5V)
1.2
1.8
2492 G08
–5
0
10
30
40
20
TIME (HOURS)
50
60
2492 G09
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LTC2492
TYPICAL PERFORMANCE CHARACTERISTICS
RMS Noise
vs Input Differential Voltage
VCC = 5V
VREF = 5V
VIN(CM) = 2.5V
TA = 25°C
RMS NOISE (μV)
VCC = 5V
VREF = 5V
VIN = 0V
TA = 25°C
0.9
0.8
0.7
0.6
RMS Noise vs Temperature (TA)
1.0
0.8
0.7
0.6
0.5
–1
0
2
1
3
5
4
0.8
RMS NOISE (μV)
RMS NOISE (μV)
VCC = 5V
VIN = 0V
VIN(CM) = GND
TA = 25°C
0.9
0.7
0.6
0.5
0.5
3.5
3.9 4.3
VCC (V)
4.7
5.1
0
5.5
1
2
3
VREF (V)
–0.1
–0.2
0 15 30 45 60
TEMPERATURE (°C)
–0.1
–0.2
–1
75
90
2492 G16
0
1
3
2
VIN(CM) (V)
5
4
0.2
0.1
Offset Error vs VREF
0.3
REF+ = 2.5V
– = GND
REF
VIN = 0V
VIN(CM) = GND
TA = 25°C
0
VCC = 5V
REF – = GND
VIN = 0V
VIN(CM) = GND
TA = 25°C
0.2
0.1
0
–0.1
–0.1
–0.2
–0.3
2.7
6
2492 G15
OFFSET ERROR (ppm OF VREF)
0
–0.3
–45 –30 –15
0
Offset Error vs VCC
0.3
OFFSET ERROR (ppm OF VREF)
OFFSET ERROR (ppm OF VREF)
0.1
0.1
2492 G14
Offset Error vs Temperature
0.2
0.2
5
4
2492 G13
VCC = 5V
VREF = 5V
VIN = 0V
VIN(CM) = GND
FO = GND
VCC = 5V
VREF = 5V
VIN = 0V
TA = 25°C
–0.3
0.4
3.1
90
Offset Error vs VIN(CM)
0.3
OFFSET ERROR (ppm OF VREF)
VREF = 2.5V
VIN = 0V
VIN(CM) = GND
TA = 25°C
0.6
75
2492 G12
RMS Noise vs VREF
0.7
0 15 30 45 60
TEMPERATURE (°C)
2492 G11
1.0
0.4
2.7
0.4
–45 –30 –15
6
VIN(CM) (V)
0.8
0.3
0.6
0.4
2.5
RMS Noise vs VCC
0.9
0.7
0.5
2492 G10
1.0
0.8
0.5
0.4
–2.5 –2 –1.5 –1 –0.5 0 0.5 1 1.5 2
INPUT DIFFERENTIAL VOLTAGE (V)
VCC = 5V
VREF = 5V
VIN = 0V
VIN(CM) = GND
0.9
RMS NOISE (μV)
0.9
RMS Noise vs VIN(CM)
1.0
RMS NOISE (μV)
1.0
–0.2
–0.3
3.1
3.5
3.9 4.3
VCC (V)
4.7
5.1
5.5
2492 G17
0
1
2
3
VREF (V)
4
5
2492 G18
2492fb
7
LTC2492
TYPICAL PERFORMANCE CHARACTERISTICS
On-Chip Oscillator Frequency
vs VCC
310
310
306
304
VCC = 4.1V
VREF = 2.5V
VIN = 0V
VIN(CM) = GND
FO = GND
300
–45 –30 –15
306
304
300
0 15 30 45 60
TEMPERATURE (°C)
75
90
2.5
3.0
3.5
4.0
VCC (V)
4.5
5.0
–80
–120
–120
–140
30600
30650
30700
30750
FREQUENCY AT VCC (Hz)
Sleep Mode Current
vs Temperature
SUPPLY CURRENT (μA)
SLEEP MODE CURRENT (μA)
120
1.0
0.8
VCC = 2.7V
250
3
2
VCC = 5V
VCC = 3V
2492 G25
VCC = 5V
VREF = 5V
VIN(CM) = 2.5V
FO = GND
0
25°C, 90°C
–1
– 45°C
–2
100
90
90
1
200
150
75
75
Integral Nonlinearity (2x Speed
Mode; VCC = 5V, VREF = 5V)
0.4
0.2
0 15 30 45 60
TEMPERATURE (oC)
2492 G24
450
VCC = 5V
VCC = 5V
VCC = 2.7V
140
100
–45 –30 –15
30800
500
VREF = VCC
IN+ = GND
IN – = GND
400 SCK = NC
SDO = NC
350 SDI = GND
CS GND
F = EXT OSC
300 O
TA = 25°C
1M
160
Conversion Current
vs Output Data Rate
2.0
0 15 30 45 60
TEMPERATURE (°C)
180
FO = GND
CS = GND
SCK = NC
SDO = NC
SDI = GND
2492 G23
2492 G22
FO = GND
1.8 CS = VCC
SCK = NC
1.6
SDO = NC
1.4 SDI = GND
10k 100k
1k
100
FREQUENCY AT VCC (Hz)
2492 G21
200
–60
–100
0 20 40 60 80 100 120 140 160 180 200 220
FREQUENCY AT VCC (Hz)
10
Conversion Current
vs Temperature
VCC = 4.1V DC ±0.7V
= 2.5V
V
–20 INREF
+ = GND
– = GND
IN
–40 FO = GND
TA = 25°C
–100
0
–45 –30 –15
1
CONVERSION CURRENT (μA)
–80
0.6
–140
0
VCC = 4.1V DC ±1.4V
VREF = 2.5V
IN+ = GND
IN – = GND
FO = GND
TA = 25°C
1.2
5.5
PSRR vs Frequency at VCC
–60
–140
–80
2492 G20
REJECTION (dB)
REJECTION (dB)
–40
–60
–120
PSRR vs Frequency at VCC
–20
–40
–100
302
2492 G19
0
VCC = 4.1V DC
VREF = 2.5V
IN+ = GND
IN– = GND
FO = GND
TA = 25°C
–20
INL (ppm OF VREF)
302
VREF = 2.5V
VIN = 0V
VIN(CM) = GND
FO = GND
TA = 25°C
308
FREQUENCY (kHz)
FREQUENCY (kHz)
308
PSRR vs Frequency at VCC
0
REJECTION (dB)
On-Chip Oscillator Frequency
vs Temperature
0
10 20 30 40 50 60 70 80 90 100
OUTPUT DATA RATE (READINGS/SEC)
2492 G26
–3
–2.5 –2 –1.5 –1 –0.5 0 0.5 1 1.5
INPUT VOLTAGE (V)
2
2.5
2492 G27
2492fb
8
LTC2492
TYPICAL PERFORMANCE CHARACTERISTICS
Integral Nonlinearity (2x Speed
Mode; VCC = 5V, VREF = 2.5V)
2
INL (ppm OF VREF)
2
INL (ppm OF VREF)
3
VCC = 5V
VREF = 2.5V
VIN(CM) = 1.25V
FO = GND
1
90°C
0
–45°C, 25°C
–1
–2
16
VCC = 2.7V
VREF = 2.5V
VIN(CM) = 1.25V
FO = GND
1
90°C
0
–45°C, 25°C
–1
–2
–3
–1.25
–0.75
–0.25
0.25
0.75
INPUT VOLTAGE (V)
–3
–1.25
1.25
–0.75
–0.25
0.25
0.75
INPUT VOLTAGE (V)
196
OFFSET ERROR (μV)
RMS NOISE (μV)
0.8
0.6
0.4
VCC = 5V
VIN = 0V
VIN(CM) = GND
FO = GND
TA = 25°C
194
240
VCC = 5V
VREF = 5V
VIN = 0V
FO = GND
TA = 25°C
230
192
190
188
186
220
VCC = 5V
VREF = 5V
VIN = 0V
VIN(CM) = GND
FO = GND
210
200
190
170
182
2492 G31
188.6
180
180
5
183.8
186.2
OUTPUT READING (μV)
Offset Error
vs Temperature (2x Speed Mode)
184
4
181.4
2492 G30
OFFSET ERROR (μV)
198
3
2
VREF (V)
4
0
179
1.25
200
1
6
Offset Error
vs VIN(CM) (2x Speed Mode)
1.0
0
8
2492 G29
RMS Noise
vs VREF (2x Speed Mode)
0.2
RMS = 0.85μV
10,000 CONSECUTIVE
AVERAGE = 0.184mV
14 READINGS
VCC = 5V
12 VREF = 5V
VIN = 0V
T = 25°C
10 A
2
2492 G28
0
Noise Histogram
(2x Speed Mode)
NUMBER OF READINGS (%)
3
Integral Nonlinearity (2x Speed
Mode; VCC = 2.7V, VREF = 2.5V)
–1
0
1
3
VIN(CM) (V)
2
4
5
6
2492 G32
160
–45 –30 –15
0 15 30 45 60
TEMPERATURE (°C)
75
90
2492 G33
2492fb
9
LTC2492
TYPICAL PERFORMANCE CHARACTERISTICS
Offset Error
vs VCC (2x Speed Mode)
Offset Error
vs VREF (2x Speed Mode)
VCC = 5V
VIN = 0V
VIN(CM) = GND
FO = GND
TA = 25°C
230
OFFSET ERROR (μV)
OFFSET ERROR (μV)
200
0
240
VREF = 2.5V
VIN = 0V
VIN(CM) = GND
FO = GND
TA = 25°C
150
100
220
–40
210
200
190
2
2.5
3
4
3.5
VCC (V)
4.5
5.5
5
160
–140
0
1
2
4
3
VREF (V)
2492 G34
–40
–60
10k 100k
1k
100
FREQUENCY AT VCC (Hz)
1M
2492 G36
0
VCC = 4.1V DC ±1.4V
REF + = 2.5V
REF – = GND
IN + = GND
IN – = GND
FO = GND
TA = 25°C
VCC = 4.1V DC ±0.7V
REF + = 2.5V
REF – = GND
IN+ = GND
–40 IN– = GND
FO = GND
–60 TA = 25°C
–20
–80
–80
–100
–100
–120
–120
–140
10
PSRR vs Frequency at VCC
(2x Speed Mode)
REJECTION (dB)
RREJECTION (dB)
–20
1
5
2492 G35
PSRR vs Frequency at VCC
(2x Speed Mode)
0
–80
–120
170
0
–60
–100
180
50
VCC = 4.1V DC
REF + = 2.5V
REF – = GND
IN+ = GND
IN– = GND
FO = GND
TA = 25°C
–20
REJECTION (dB)
250
PSRR vs Frequency at VCC
(2x Speed Mode)
0 20 40 60 80 100 120 140 160 180 200 220
FREQUENCY AT VCC (Hz)
2492 G37
–140
30600
30650
30700
30750
FREQUENCY AT VCC (Hz)
30800
2492 G38
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10
LTC2492
PIN FUNCTIONS
FO (Pin 1): Frequency Control Pin. Digital input that controls
the internal conversion clock rate. When FO is connected
to GND, the converter uses its internal oscillator running at
307.2kHz. The conversion clock may also be overridden by
driving the FO pin with an external clock in order to change
the output rate and the digital ﬁlter rejection null.
this pin is used as the conversion status output. When
the conversion is in progress this pin is HIGH; once the
conversion is complete SDO goes low. The conversion
status is monitored by pulling CS LOW.
SDI (Pin 2): Serial Data Input. This pin is used to select
the line frequency rejection mode, 1× or 2× speed mode,
temperature sensor, as well as the input channel. The serial
data input is applied under control of the serial clock (SCK)
during the data output/input operation. The ﬁrst conversion
following a new input or mode change is valid.
COM (Pin 7): The common negative input (IN –) for all
single-ended multiplexer conﬁgurations. The voltage on
CH0 to CH3 and COM pins can have any value between
GND – 0.3V to VCC + 0.3V. Within these limits, the two
selected inputs (IN+ and IN –) provide a bipolar input range
(VIN = IN+ – IN –) from –0.5 • VREF to 0.5 • VREF . Outside
this input range, the converter produces unique over-range
and under-range output codes.
SCK (Pin 3): Bidirectional, Digital I/O, Clock Pin. In Internal
Serial Clock Operation mode, SCK is generated internally
and is seen as an output on the SCK pin. In External Serial
Clock Operation mode, the digital I/O clock is externally
applied to the SCK pin. The Serial Clock operation mode
is determined by the logic level applied to the SCK pin at
power up and during the most recent falling edge of CS.
CS (Pin 4): Active LOW Chip Select. A LOW on this pin
enables the digital input/output and wakes up the ADC.
Following each conversion, the ADC automatically enters
the Sleep mode and remains in this low power state as
long as CS is HIGH. A LOW-to-HIGH transition on CS
during the data output aborts the data transfer and starts
a new conversion.
SDO (Pin 5): Three-State Digital Output. During the data
output period, this pin is used as the serial data output.
When the chip select pin is HIGH, the SDO pin is in a high
impedance state. During the conversion and sleep periods,
GND (Pin 6): Ground. Connect this pin to a common ground
plane through a low impedance connection.
CH0 to CH3 (Pins 8-11): Analog Inputs. May be
programmed for single-ended or differential mode.
VCC (Pin 12): Positive Supply Voltage. Bypass to GND with
a 10μF tantalum capacitor in parallel with a 0.1μF ceramic
capacitor as close to the part as possible.
REF+ (Pin 13), REF – (Pin 14): Differential Reference Input.
The voltage on these pins can have any value between
GND and VCC as long as the reference positive input, REF+,
remains more positive than the negative reference input,
REF –, by at least 0.1V. The differential voltage (VREF = REF+
– REF –) sets the fullscale range for all input channels.
When performing an on-chip temperature measurement,
the minimum value of REF = 2V.
Exposed Pad (Pin 15): Ground. This pin is ground and
must be soldered to the PCB ground plane. For prototyping
purposes, this pin may remain ﬂoating.
2492fb
11
LTC2492
FUNCTIONAL BLOCK DIAGRAM
VCC
INTERNAL
OSCILLATOR
TEMP
SENSOR
GND
FO
(INT/EXT)
AUTOCALIBRATION
AND CONTROL
REF +
REF –
CH0
CH1
CH2
CH3
COM
–
IN +
MUX
+
DIFFERENTIAL
3RD ORDER
Δ∑ MODULATOR
IN –
SERIAL
INTERFACE
SDI
SCK
SDO
CS
DECIMATING FIR
ADDRESS
2492 BD
Figure 1. Functional Block Diagram
TEST CIRCUITS
VCC
1.69k
SDO
SDO
1.69k
Hi-Z TO VOH
VOL TO VOH
VOH TO Hi-Z
CLOAD = 20pF
2492 TC01
CLOAD = 20pF
Hi-Z TO VOL
VOH TO VOL
VOL TO Hi-Z
2492 TC02
2492fb
12
LTC2492
TIMING DIAGRAMS
Timing Diagram Using Internal SCK (SCK HIGH with CS↓)
CS
t1
t2
SDO
Hi-Z
Hi-Z
tKQMIN
t3
tKQMAX
SCK
t7
t8
SDI
SLEEP
DATA IN/OUT
CONVERSION
2492 TD01
Timing Diagram Using External SCK (SCK LOW with CS↓)
CS
t1
t2
SDO
Hi-Z
Hi-Z
t5
tKQMIN
t4
tKQMAX
SCK
t7
t8
SDI
SLEEP
DATA IN/OUT
CONVERSION
2492 TD02
2492fb
13
LTC2492
APPLICATIONS INFORMATION
CONVERTER OPERATION
Converter Operation Cycle
The LTC2492 is a multi-channel, low power, deltasigma analog-to-digital converter with an easy to use
4-wire interface and automatic differential input current
cancellation. Its operation is made up of four states (See
Figure 2). The converter operating cycle begins with the
conversion, followed by the sleep state and ends with the
data input/output cycle. The 4-wire interface consists of
serial data output (SDO), serial clock (SCK), chip select
(CS) and serial data input (SDI).The interface, timing,
operation cycle, and data output format is compatible with
Linear’s entire family of SPI Δ∑ converters.
Initially, at power up, the LTC2492 performs a conversion.
Once the conversion is complete, the device enters the
sleep state. While in this sleep state, if CS is HIGH, power
consumption is reduced by two orders of magnitude. The
part remains in the sleep state as long as CS is HIGH. The
conversion result is held indeﬁnitely in a static shift register
while the part is in the sleep state.
Once CS is pulled LOW, the device powers up, exits the
sleep state, and enters the data input/output state. If CS
is brought HIGH before the ﬁrst rising edge of SCK, the
device returns to the sleep state and the power is reduced.
If CS is brought HIGH after the ﬁrst rising edge of SCK, the
POWER UP
IN+= CH0, IN–= CH1
50/60Hz,1X
CONVERT
SLEEP
CS = LOW
AND
SCK
data output cycle is aborted and a new conversion cycle
begins. The data output corresponds to the conversion
just completed. This result is shifted out on the serial
data output pin (SDO) under the control of the serial
clock pin (SCK). Data is updated on the falling edge of
SCK allowing the user to reliably latch data on the rising
edge of SCK (See Figure 3). The conﬁguration data for
the next conversion is also loaded into the device at this
time. Data is loaded from the serial data input pin (SDI)
on each rising edge of SCK. The data input/output cycle
concludes once 32 bits are read out of the ADC or when
CS is brought HIGH. The device automatically initiates a
new conversion and the cycle repeats.
Through timing control of the CS and SCK pins, the LTC2492
offers several ﬂexible modes of operation (internal or
external SCK and free-running conversion modes). These
various modes do not require programming and do not
disturb the cyclic operation described above. These modes
of operation are described in detail in the Serial Interface
Timing Modes section.
Ease of Use
The LTC2492 data output has no latency, ﬁlter settling
delay, or redundant data associated with the conversion
cycle. There is a one-to-one correspondence between the
conversion and the output data. Therefore, multiplexing
multiple analog inputs is straight forward. Each conversion,
immediately following a newly selected input or mode,
is valid and accurate to the full speciﬁcations of the
device.
The LTC2492 automatically performs offset and full scale
calibration every conversion cycle independent of the
input channel selected. This calibration is transparent
to the user and has no effect with the operation cycle
described above. The advantage of continuous calibration
is extreme stability of offset and full-scale readings with
respect to time, supply voltage variation, input channel,
and temperature drift.
CHANNEL SELECT
CONFIGURATION SELECT
DATA OUTPUT
2492 F02
Figure 2. LTC2492 State Transition Diagram
2492fb
14
LTC2492
APPLICATIONS INFORMATION
Easy Drive Input Current Cancellation
Reference Voltage Range
The LTC2492 combines a high precision delta-sigma ADC
with an automatic, differential, input current cancellation
front end. A proprietary front end passive sampling network
transparently removes the differential input current. This
enables external RC networks and high impedance sensors
to directly interface to the LTC2492 without external
ampliﬁers. The remaining common mode input current
is eliminated by either balancing the differential input
impedances or setting the common mode input equal to the
common mode reference (see Automatic Differential Input
Current Cancellation Section). This unique architecture
does not require on-chip buffers, thereby enabling
signals to swing beyond ground and VCC . Moreover, the
cancellation does not interfere with the transparent offset
and full-scale auto-calibration and the absolute accuracy
(full scale + offset + linearity + drift) is maintained even
with external RC networks.
This converter accepts a truly differential external reference
voltage. The absolute/common mode voltage range for
REF+ and REF – pins covers the entire operating range of
the device (GND to VCC). For correct converter operation,
VREF must be positive (REF+ > REF –).
Power-Up Sequence
The LTC2492 automatically enters an internal reset
state when the power supply voltage VCC drops below
approximately 2V. This feature guarantees the integrity of
the conversion result, input channel selection, and serial
clock mode.
When VCC rises above this threshold, the converter creates
an internal power-on-reset (POR) signal with a duration
of approximately 4ms. The POR signal clears all internal
registers. The conversion immediately following a POR
cycle is performed on the input channel IN+ = CH0, IN – =
CH1, simultaneous 50Hz/60Hz rejection and 1× output
rate. The ﬁrst conversion following a POR cycle is accurate
within the speciﬁcation of the device if the power supply
voltage is restored to (2.7V to 5.5V) before the end of the
POR interval. A new input channel, rejection mode, speed
mode, or temperature selection can be programmed into
the device during this ﬁrst data input/output cycle.
The LTC2492 differential reference input range is 0.1V to
VCC . For the simplest operation, REF + can be shorted to VCC
and REF– can be shorted to GND. The converter output noise
is determined by the thermal noise of the front end circuits,
and as such, its value in nanovolts is nearly constant with
reference voltage. A decrease in reference voltage will not
signiﬁcantly improve the converter’s effective resolution.
On the other hand, a decreased reference will improve the
converter’s overall INL performance.
Input Voltage Range
The analog inputs are truly differential with an absolute,
common mode range for the CH0 to CH3 and COM input
pins extending from GND – 0.3V to VCC + 0.3V. Outside
these limits, the ESD protection devices begin to turn
on and the errors due to input leakage current increase
rapidly. Within these limits, the LTC2492 converts the
bipolar differential input signal VIN = IN + – IN – (where
IN+ and IN– are the selected input channels), from –FS =
–0.5 • VREF to +FS = 0.5 • VREF where VREF = REF + – REF –.
Outside this range, the converter indicates the overrange
or the underrange condition using distinct output codes
(see Table 1).
Signals applied to the input (CH0 to CH3, COM) may
extend 300mV below ground and above VCC . In order to
limit any fault current, resistors of up to 5k may be added
in series with the input. The effect of series resistance on
the converter accuracy can be evaluated from the curves
presented in the Input Current/Reference Current sections.
In addition, series resistors will introduce a temperature
dependent error due to input leakage current. A 1nA
input leakage current will develop a 1ppm offset error
on a 5k resistor if VREF = 5V. This error has a very strong
temperature dependency.
2492fb
15
LTC2492
APPLICATIONS INFORMATION
SERIAL INTERFACE PINS
the duration of the sleep state, and set the SCK mode.
The LTC2492 transmits the conversion result, reads the
input conﬁguration, and receives a start of conversion
command through a synchronous 3- or 4-wire interface.
During the conversion and sleep states, this interface
can be used to access the converter status. During the
data output state, it is used to read the conversion result,
program the input channel, rejection frequency, speed
multiplier, and select the temperature sensor.
At the conclusion of a conversion cycle, while CS is HIGH,
the device remains in a low power sleep state where the
supply current is reduced several orders of magnitude. In
order to exit the sleep state and enter the data output state,
CS must be pulled low. Data is now shifted out the SDO pin
under control of the SCK pin as described previously.
Serial Clock Input/Output (SCK)
The serial clock pin (SCK) is used to synchronize the data
input/output transfer. Each bit is shifted out of the SDO
pin on the falling edge of SCK and data is shifted into the
SDI pin on the rising edge of SCK.
The serial clock pin (SCK) can be conﬁgured as either a
master (SCK is an output generated internally) or a slave
(SCK is an input and applied externally). Master mode
(Internal SCK) is selected by simply ﬂoating the SCK pin.
Slave mode (External SCK) is selected by driving SCK low
during power up and each falling edge of CS. Speciﬁc
details of these SCK modes are described in the Serial
Interface Timing Modes section.
Serial Data Output (SDO)
The serial data output pin (SDO) provides the result of the
last conversion as a serial bit stream (MSB ﬁrst) during
the data output state. In addition, the SDO pin is used as
an end of conversion indicator during the conversion and
sleep states.
When CS is HIGH, the SDO driver is switched to a high
impedance state in order to share the data output line with
other devices. If CS is brought LOW during the conversion
phase, the EOC bit (SDO pin) will be driven HIGH. Once
the conversion is complete, if CS is brought LOW, EOC will
be driven LOW indicating the conversion is complete and
the result is ready to be shifted out of the device.
Chip Select (CS)
A new conversion cycle is initiated either at the conclusion
of the data output cycle (all 32 data bits read) or by pulling
CS HIGH any time between the ﬁrst and 32nd rising edges
of the serial clock (SCK). In this case, the data output is
aborted and a new conversion begins.
Serial Data Input (SDI)
The serial data input (SDI) is used to select the input
channel, rejection frequency, speed multiplier and to
access the integrated temperature sensor. Data is shifted
into the device during the data output/input state on the
rising edge of SCK while CS is low.
OUTPUT DATA FORMAT
The LTC2492 serial output stream is 32 bits long. The
ﬁrst bit indicates the conversion status, the second bit is
always zero, and the third bit conveys sign information.
The next 24 bits are the conversion result, MSB ﬁrst. The
remaining 5 bits are sub LSBs beyond the 24-bit level
that may be included in averaging or discarded without
loss of resolution.
Bit 31 (ﬁrst output bit) is the end of conversion (EOC)
indicator. This bit is available on the SDO pin during the
conversion and sleep states whenever CS is LOW. This bit
is HIGH during the conversion cycle, goes LOW once the
conversion is complete, and is HI-Z when CS is HIGH.
Bit 30 (second output bit) is a dummy bit (DMY) and is
always LOW.
Bit 29 (third output bit) is the conversion result sign indicator
(SIG). If the selected input (VIN = IN+ – IN –) is greater than
0V, this bit is HIGH. If VIN < 0, this bit is LOW.
The active low CS pin is used to test the conversion status,
enable I/O data transfer, initiate a new conversion, control
2492fb
16
LTC2492
APPLICATIONS INFORMATION
Bit 28 (fourth output bit) is the most signiﬁcant bit (MSB) of
the result. This bit in conjunction with Bit 29 also provides
underrange and overrange indication. If both Bit 29 and
Bit 28 are HIGH, the differential input voltage is above
+FS. If both Bit 29 and Bit 28 are LOW, the differential
input voltage is below –FS. The function of these bits is
summarized in Table 1.
Table 1. LTC2492 Status Bits
Input Range
Bit 31
EOC
Bit 30
DMY
Bit 29
SIG
Bit 28
MSB
VIN ≥ 0.5 • VREF
0
0
1
1
0V ≤ VIN < 0.5 • VREF
0
0
1
0
–0.5 • VREF ≤ VIN < 0V
0
0
0
1
VIN < –0.5 • VREF
0
0
0
0
an external microcontroller. Bit 31 (EOC) can be captured
on the ﬁrst rising edge of SCK. Bit 30 is shifted out of the
device on the ﬁrst falling edge of SCK. The ﬁnal data bit
(Bit 0) is shifted out on the on the falling edge of the 31st
SCK and may be latched on the rising edge of the 32nd SCK
pulse. On the falling edge of the 32nd SCK pulse, SDO goes
HIGH indicating the initiation of a new conversion cycle.
This bit serves as EOC (Bit 31) for the next conversion
cycle. Table 2 summarizes the output data format.
As long as the voltage on the IN+ and IN – pins remains
between –0.3V and VCC + 0.3V (absolute maximum
operating range) a conversion result is generated for any
differential input voltage VIN from –FS = –0.5 • VREF to
+FS = 0.5 • VREF . For differential input voltages greater
than +FS, the conversion result is clamped to the value
corresponding to +FS + 1LSB. For differential input voltages
below –FS, the conversion result is clamped to the value
–FS – 1LSB.
Bits 28 to 5 are the 24-bit conversion result MSB ﬁrst.
Bit 5 is the least signiﬁcant bit (LSB24).
Bits 4 to 0 are sub LSBs below the 24-bit level. Bits 4 to
0 may be included in averaging or discarded without loss
of resolution.
Data is shifted out of the SDO pin under control of the
serial clock (SCK) (see Figure 3). Whenever CS is HIGH,
SDO remains high impedance and SCK is ignored.
In order to shift the conversion result out of the device,
CS must ﬁrst be driven LOW. EOC is seen at the SDO pin
of the device once CS is pulled LOW. EOC changes in real
time as a function of the internal oscillator or the clock
applied to the fO pin from HIGH to LOW at the completion
of a conversion. This signal may be used as an interrupt for
INPUT DATA FORMAT
The LTC2492 serial input word is 13 bits long and contains
two distinct sets of data. The ﬁrst set (SGL, ODD, A2, A1, A0)
is used to select the input channel. The second set of data
(IM, FA, FB, SPD) is used to select the frequency rejection,
speed mode (1×, 2×), and temperature measurement.
After power up, the device initiates an internal reset cycle
which sets the input channel to CH0 to CH1 (IN+ = CH0, IN– =
CH1), the frequency rejection to simultaneous 50Hz/60Hz,
and 1× output rate (auto-calibration enabled). The ﬁrst
CS
1
2
3
4
5
1
0
EN
SGL
ODD
EOC
“0”
SIG
MSB
6
7
8
9
A2
A1
A0
EN2
10
11
12
13
14
32
SCK
(EXTERNAL)
SDI
DON'T CARE
SDO
IM
FA
FB
SPD
DON'T CARE
BIT 31 BIT 30 BIT 29 BIT 28 BIT 27 BIT 26 BIT 25 BIT 24 BIT 23 BIT 22 BIT 21 BIT 20 BIT 19 BIT 18 BIT 17
CONVERSION
SLEEP
BIT 0
DATA INPUT/OUTPUT
2492 F03
Figure 3. Channel Selection, Conﬁguration Selection and Data Output Timing
2492fb
17
LTC2492
APPLICATIONS INFORMATION
Table 2. Output Data Format
Differential Input Voltage
VIN*
Bit 31
`E`O`C
Bit 30
DMY
Bit 29
SIG
Bit 28
MSB
Bit 27
Bit 26
Bit 25
…
Bit 5
LSB
Bits 4 to 0
SUB LSBs
VIN* ≥ 0.5 • VREF**
0
0
1
1
0
0
0
…
0
00000
0.5 • VREF** – 1LSB
0
0
1
0
1
1
1
…
1
XXXXX
0.25 • VREF**
0
0
1
0
1
0
0
…
0
XXXXX
0.25 • VREF** – 1LSB
0
0
1
0
0
1
1
…
1
XXXXX
0
0
0
1
0
0
0
0
…
0
XXXXX
–1LSB
0
0
0
1
1
1
1
…
1
XXXXX
–0.25 • VREF**
0
0
0
1
1
0
0
…
0
XXXXX
–0.25 • VREF** – 1LSB
0
0
0
1
0
1
1
…
1
XXXXX
–0.5 • VREF**
0
0
0
1
0
0
0
…
0
XXXXX
VIN* < –0.5 • VREF**
0
0
0
0
1
1
1
…
1
11111
*The differential input voltage VIN = IN+ – IN–. **The differential reference voltage VREF = REF+ – REF–.
** Sub LSBs are below the 24-bit level. They may be included in averaging, or discarded without loss of resolution.
conversion automatically begins at power up using this
default conﬁguration. Once the conversion is complete,
a new word may be written into the device.
The ﬁrst three bits shifted into the device consist of two
preamble bits and an enable bit. These bits are used to
enable the device conﬁguration and input channel selection.
Valid settings for these three bits are 000, 100 and 101.
Other combinations should be avoided. If the ﬁrst three bits
are 000 or 100, the following data is ignored (don’t care)
and the previously selected input channel and conﬁguration
remain valid for the next conversion.
If the ﬁrst three bits shifted into the device are 101, then
the next ﬁve bits select the input channel for the next
conversion cycle (see Table 3).
Table 3 Channel Selection
MUX ADDRESS
CHANNEL SELECTION
ODD/
SIGN
A2
A1
A0
0
1
*0
0
0
0
0
IN+
IN –
0
0
0
0
1
0
1
0
0
0
0
1
0
0
1
SGL
1
0
0
0
0
1
0
0
0
1
1
1
0
0
0
1
1
0
0
1
*Default at power up
IN –
2
3
IN+
IN –
IN –
IN+
COM
IN+
IN+
IN –
IN+
IN –
IN+
IN –
IN+
IN –
The ﬁrst input bit (SGL) following the 101 sequence
determines if the input selection is differential (SGL =
0) or single-ended (SGL = 1). For SGL = 0, two adjacent
channels can be selected to form a differential input. For
SGL = 1, one of four channels is selected as the positive
input. The negative input is COM for all single-ended
operations. The remaining four bits (ODD, A2, A1, A0)
determine which channel(s) is/are selected and the polarity
(for a differential input).
The next serial input bit immediately following the input
channel selection is the enable bit for the conversion
conﬁguration (EN2). If this bit is set to 0, then the next
conversion is performed using the previously selected
converter conﬁguration.
A new conﬁguration can be loaded into the device by
setting EN2 = 1 (see Table 4). The ﬁrst bit (IM) is used
to select the internal temperature sensor. If IM = 1, the
following conversion will be performed on the internal
temperature sensor rather than the selected input channel.
The next two bits (FA and FB) are used to set the rejection
frequency. The ﬁnal bit (SPD) is used to select either the
1x output rate if SPD = 0 (auto-calibration is enabled and
the offset is continuously calibrated and removed from
the ﬁnal conversion result) or the 2x output rate if SPD
= 1 (offset calibration disabled, multiplexing output rates
up to 15Hz with no latency). When IM = 1 (temperature
measurement) SPD will be ignored and the device will
operate in 1× mode. The conﬁguration remains valid until
2492fb
18
LTC2492
APPLICATIONS INFORMATION
Table 4. Converter Conﬁguration
1
0
EN
SGL
ODD
A2
A1
A0
EN2
IM
FA
FB
SPD
CONVERTER CONFIGURATION
1
0
0
X
X
X
X
X
X
X
X
X
X
Keep Previous
1
0
1
X
X
X
X
X
0
X
X
X
X
Keep Previous
0
0
0
X
X
X
X
X
X
X
X
X
X
Keep Previous
1
0
1
X
X
X
X
X
1
0
0
0
0
External Input (See Table 3)
50Hz/60Hz Rejection, 1x
1
0
1
X
X
X
X
X
1
0
0
1
0
External Input (See Table 3)
50Hz Rejection, 1x
1
0
1
X
X
X
X
X
1
0
1
0
0
External Input (See Table 3)
60Hz Rejection, 1x
1
0
1
X
X
X
X
X
1
0
0
0
1
External Input (See Table 3)
50Hz/60Hz Rejection, 2x
1
0
1
X
X
X
X
X
1
0
0
1
1
External Input (See Table 3)
50Hz Rejection, 2x
1
0
1
X
X
X
X
X
1
0
1
0
1
External Input (See Table 3)
60Hz Rejection, 2x
1
0
1
X
X
X
X
X
1
1
0
0
X
Measure Temperature
50Hz/60Hz Rejection, 1x
1
0
1
X
X
X
X
X
1
1
0
1
X
Measure Temperature
50Hz Rejection, 1x
1
0
1
X
X
X
X
X
1
1
1
0
X
Measure Temperature
60Hz Rejection, 1x
1
0
1
X
X
X
X
X
1
X
1
1
X
Reserved, Do Not Use
a new input word with EN = 1 (the ﬁrst three bits are 101)
and EN2 = 1 is shifted into the device.
Rejection Mode (FA, FB)
The LTC2492 includes a high accuracy on-chip oscillator
with no required external components. Coupled with an
integrated 4th order digital low pass ﬁlter, the LTC2492
rejects line frequency noise. In the default mode, the
LTC2492 simultaneously rejects 50Hz and 60Hz by at least
87dB. If more rejection is required, the LTC2492 can be
conﬁgured to reject 50Hz or 60Hz to better than 110dB.
Speed Mode (SPD)
Every conversion cycle, two conversions are combined to
remove the offset (default mode). This result is free from
offset and drift. In applications where the offset is not
critical, the auto-calibration feature can be disabled with
the beneﬁt of twice the output rate. While operating in the
2x mode (SPD = 1), the linearity and full-scale errors are
unchanged from the 1× mode performance. In both the
1× and 2× mode there is no latency. This enables input
steps or multiplexer changes to settle in a single conversion
cycle, easing system overhead and increasing the effective
conversion rate. During temperature measurements, the 1×
mode is always used independent of the value of SPD.
Temperature Sensor
The LTC2492 includes an integrated temperature sensor.
The temperature sensor is selected by setting IM = 1. The
digital output is proportional to the absolute temperature
of the device. This feature allows the converter to perform
cold junction compensation for external thermocouples or
continuously remove the temperature effects of external
sensors.
The internal temperature sensor output is 28mV at 27°C
(300°K), with a slope of 93.5μV/°C independent of VREF
(see Figures 4 and 5). Slope calibration is not required if
the reference voltage (VREF) is known. A 5V reference has
a slope of 314 LSBs24/°C. The temperature is calculated
2492fb
19
LTC2492
APPLICATIONS INFORMATION
from the output code (DATAOUT24) for a 5V reference
using the following formula:
All Kelvin temperature readings can be converted to TC
(°C) using the fundamental equation:
TK = DATAOUT24/314 in Kelvin
TC = TK – 273
If a different value of VREF is used, the temperature output
is:
TK = DATAOUT24 • VREF/1570 in Kelvin
If the value of VREF is not known, the slope is determined by
measuring the temperature sensor at a known temperature
TN (in °K) and using the following formula:
SLOPE = DATAOUT24/TN
This value of slope can be used to calculate further
temperature readings using:
TK = DATAOUT24/SLOPE
SERIAL INTERFACE TIMING MODES
The LTC2492’s 4-wire interface is SPI and MICROWIRE
compatible. This interface offers several ﬂexible modes
of operation. These include internal/external serial clock,
3- or 4-wire I/O, single cycle or continuous conversion. The
following sections describe each of these timing modes
in detail. In all cases, the converter can use the internal
oscillator (FO = LOW) or an external oscillator connected
to the FO pin. For each mode, the operating cycle, data
input format, data output format, and performance remain
the same. Refer to Table 5 for a summary.
140000
5
VCC = 5V
VREF = 5V
120000 SLOPE = 314 LSB /K
24
4
ABSOLUTE ERROR (°C)
3
DATAOUT24
100000
80000
60000
40000
2
1
0
–1
–2
–3
20000
0
–4
0
100
–5
–55
400
200
300
TEMPERATURE (K)
–30
–5
20
45
70
TEMPERATURE (°C)
2492 F04
95
120
2492 F05
Figure 4. Internal PTAT Digital Output vs Temperature
Figure 5. Absolute Temperature Error
Table 5. Serial Interface Timing Modes
CONFIGURATION
SCK
CONVERSION
DATA OUTPUT CONNECTION AND
SOURCE CYCLE CONTROL
CONTROL
WAVEFORMS
External SCK, Single Cycle
Conversion
External
CS and SCK
CS and SCK
Figures 6, 7
External SCK, 3-Wire I/O
External
SCK
SCK
Figure 8
Internal SCK, Single Cycle
Conversion
Internal
CS↓
CS↓
Figures 9, 10
Internal SCK, 3-Wire I/O,
Continuous Conversion
Internal
Continuous
Internal
Figure 11
2492fb
20
LTC2492
APPLICATIONS INFORMATION
External Serial Clock, Single Cycle Operation
When the device is in the sleep state, its conversion result
is held in an internal static shift register. The device remains
in the sleep state until the ﬁrst rising edge of SCK is seen
while CS is LOW. The input data is then shifted in via the
SDI pin on each rising edge of SCK (including the ﬁrst rising
edge). The channel selection and converter conﬁguration
mode will be used for the following conversion cycle. If
the input channel or converter conﬁguration is changed
during this I/O cycle, the new settings take effect on the
conversion cycle following the data input/output cycle.
The output data is shifted out the SDO pin on each falling
edge of SCK. This enables external circuitry to latch the
output on the rising edge of SCK. EOC can be latched on the
ﬁrst rising edge of SCK and the last bit of the conversion
result can be latched on the 32nd rising edge of SCK. On
the 32nd falling edge of SCK, the device begins a new
conversion and SDO goes HIGH (EOC = 1) indicating a
conversion is in progress.
This timing mode uses an external serial clock to shift out
the conversion result and CS to monitor and control the
state of the conversion cycle (see Figure 6).
The external serial clock mode is selected during the powerup sequence and on each falling edge of CS. In order to
enter and remain in the external SCK mode of operation,
SCK must be driven LOW both at power up and on each
CS falling edge. If SCK is HIGH on the falling edge of CS,
the device will switch to the internal SCK mode.
The serial data output pin (SDO) is Hi-Z as long as CS is
HIGH. At any time during the conversion cycle, CS may be
pulled LOW in order to monitor the state of the converter.
While CS is LOW, EOC is output to the SDO pin.
EOC = 1 while a conversion is in progress and EOC = 0 if
the conversion is complete and the device is in the sleep
state. Independent of CS, the device automatically enters
the sleep state once the conversion is complete; however,
in order to reduce the power, CS must be HIGH.
At the conclusion of the data cycle, CS may remain LOW
and EOC monitored as an end-of-conversion interrupt.
2.7V TO 5.5V
12
VCC
= EXTERNAL OSCILLATOR
= INTERNAL OSCILLATOR
1
FO
LTC2492
10μF
13
REFERENCE
VOLTAGE
0.1V TO VCC
0.1μF
14
8
9
10
ANALOG
INPUTS
11
7
REF +
REF –
2
SDI
3
SCK
4-WIRE
SPI INTERFACE
CH0
CH1
CS
CH2
SDO
4
5
CH3
COM
GND
6
CS
1
2
3
4
5
6
7
8
9
1
0
EN
SGL
ODD
A2
A1
A0
EN2
EOC
“0”
SIG
MSB
10
11
12
13
14
32
SCK
(EXTERNAL)
SDI
DON'T CARE
SDO
IM
FA
SLEEP
SPD
DON'T CARE
Hi-Z
BIT 31 BIT 30 BIT 29 BIT 28 BIT 27 BIT 26 BIT 25 BIT 24 BIT 23 BIT 22 BIT 21
CONVERSION
FB
BIT 20 BIT 19
DATA INPUT/OUTPUT
BIT 18 BIT 17
BIT 0
CONVERSION
2492 F06
Figure 6. External Serial Clock, Single Cycle Operation
2492fb
21
LTC2492
APPLICATIONS INFORMATION
Typically, CS remains LOW during the data output/input
state. However, the data output state may be aborted by
pulling CS HIGH any time between the 1st falling edge
and the 32nd falling edge of SCK (see Figure 7). On the
rising edge of CS, the device aborts the data output state
and immediately initiates a new conversion. In order to
program a new input channel, 8 SCK clock pulses are
required. If the data output sequence is aborted prior to
the 8th falling edge of SCK, the new input data is ignored
and the previously selected input channel remains valid.
If the rising edge of CS occurs after the 8th falling edge of
SCK, the new input channel is loaded and valid for the next
conversion cycle. If CS goes high between the 8th falling
edge and the 16th falling edge of SCK, the new channel
is still loaded, but the converter conﬁguration remains
unchanged. In order to program both the input channel
and converter conﬁguration, CS must go high after the
16th falling edge of SCK (at this point all data has been
shifted into the device).
External Serial Clock, 3-Wire I/O
This timing mode uses a 3-wire serial I/O interface. The
conversion result is shifted out of the device by an externally
generated serial clock (SCK) signal (see Figure 8). CS is
permanently tied to ground, simplifying the user interface
or isolation barrier.
The external serial clock mode is selected at the end of
the power-on reset (POR) cycle. The POR cycle typically
concludes 4ms after VCC exceeds 2V. The level applied to
SCK at this time determines if SCK is internally generated
or externally applied. In order to enter the external SCK
mode, SCK must be driven LOW prior to the end of the
POR cycle.
Since CS is tied LOW, the end-of-conversion (EOC) can be
continuously monitored at the SDO pin during the convert
and sleep states. EOC may be used as an interrupt to an
external controller. EOC = 1 while the conversion is in
progress and EOC = 0 once the conversion is complete.
2.7V TO 5.5V
12
= EXTERNAL OSCILLATOR
= INTERNAL OSCILLATOR
1
FO
LTC2492
10μF
0.1μF
VCC
REFERENCE
VOLTAGE
0.1V TO VCC
13
REF +
14
–
8
9
ANALOG
INPUTS
10
11
7
REF
2
SDI
3
SCK
4-WIRE
SPI INTERFACE
CH0
CH1
CS
CH2
SDO
4
5
CH3
COM
GND
6
CS
1
2
3
4
5
6
7
8
1
0
EN
SGL
ODD
A2
A1
A0
EOC
“0”
SIG
MSB
SCK
(EXTERNAL)
SDI
DON'T CARE
SDO
Hi-Z
BIT 31 BIT 30 BIT 29 BIT 28 BIT 27 BIT 26 BIT 25 BIT 24
CONVERSION
SLEEP
DON'T CARE
DATA INPUT/OUTPUT
BIT 23
CONVERSION
SLEEP
2492 F07
Figure 7. External Serial Clock, Reduced Output Data Length and Valid Channel Selection
2492fb
22
LTC2492
APPLICATIONS INFORMATION
2.7V TO 5.5V
12
= EXTERNAL OSCILLATOR
= INTERNAL OSCILLATOR
1
FO
LTC2492
10μF
0.1μF
VCC
REFERENCE
VOLTAGE
0.1V TO VCC
13
REF +
14
–
8
9
ANALOG
INPUTS
10
11
7
REF
2
SDI
3
SCK
3-WIRE
SPI INTERFACE
CH0
CH1
SDO
CH2
CS
5
4
CH3
COM
GND
6
CS
1
2
3
4
5
6
7
8
9
1
0
EN
SGL
ODD
A2
A1
A0
EN2
EOC
“0”
SIG
MSB
10
11
12
13
14
32
SCK
(EXTERNAL)
SDI
DON'T CARE
SDO
IM
FA
BIT 31 BIT 30 BIT 29 BIT 28 BIT 27 BIT 26 BIT 25 BIT 24 BIT 23 BIT 22 BIT 21
CONVERSION
FB
SPD
BIT 20 BIT 19
DATA INPUT/OUTPUT
SLEEP
DON'T CARE
BIT 18 BIT 17
BIT 0
CONVERSION
2492 F08
Figure 8. External Serial Clock, 3-Wire Operation (`C`S = 0)
On the falling edge of EOC, the conversion result is
loading into an internal static shift register. The output
data can now be shifted out the SDO pin under control
of the externally applied SCK signal. Data is updated on
the falling edge of SCK. The input data is shifted into the
device through the SDI pin on the rising edge of SCK. On
the 32nd falling edge of SCK, SDO goes HIGH, indicating
a new conversion has begun. This data now serves as
EOC for the next conversion.
Internal Serial Clock, Single Cycle Operation
This timing mode uses the internal serial clock to shift out
the conversion result and CS to monitor and control the
state of the conversion cycle (see Figure 9).
In order to select the internal serial clock timing mode,
the serial clock pin (SCK) must be ﬂoating or pulled HIGH
before the conclusion of the POR cycle and prior to each
falling edge of CS. An internal weak pull-up resistor is active
on the SCK pin during the falling edge of CS; therefore,
the internal SCK mode is automatically selected if SCK is
not externally driven.
The serial data output pin (SDO) is Hi-Z as long as CS is
HIGH. At any time during the conversion cycle, CS may be
pulled low in order to monitor the state of the converter.
Once CS is pulled LOW, SCK goes LOW and EOC is output
to the SDO pin. EOC = 1 while the conversion is in progress
and EOC = 0 if the device is in the sleep state.
When testing EOC, if the conversion is complete (EOC =
0), the device will exit sleep state. In order to return to the
sleep state and reduce the power consumption, CS must be
pulled HIGH before the device pulls SCK HIGH. When the
device is using its own internal oscillator (FO is tied LOW),
the ﬁrst rising edge of SCK occurs 12μs (tEOCTEST = 12μs)
after the falling edge of CS. If FO is driven by an external
oscillator of frequency fEOSC, then tEOCTEST = 3.6/fEOSC.
If CS remains LOW longer than tEOCTEST , the ﬁrst rising
edge of SCK will occur and the conversion result is shifted
out the SDO pin on the falling edge of SCK. The serial
input word (SDI) is shifted into the device on the rising
edge of SCK.
After the 32nd rising edge of SCK a new conversion
automatically begins. SDO goes HIGH (EOC = 1) and SCK
2492fb
23
LTC2492
APPLICATIONS INFORMATION
2.7V TO 5.5V
12
VCC
= EXTERNAL OSCILLATOR
= INTERNAL OSCILLATOR
1
FO
LTC2492
10μF
REFERENCE
VOLTAGE
0.1V TO VCC
0.1μF
13
REF +
14
REF –
8
9
10
ANALOG
INPUTS
11
7
VCC
2
SDI
OPTIONAL
10k
3
SCK
4-WIRE
SPI INTERFACE
CH0
CH1
CS
CH2
SDO
4
5
CH3
COM
GND
6
<tEOCTEST
CS
1
2
3
4
5
6
7
8
9
1
0
EN
SGL
ODD
A2
A1
A0
EN2
EOC
“0”
SIG
MSB
10
11
12
13
14
32
SCK
(INTERNAL)
SDI
DON'T CARE
SDO
IM
FA
SLEEP
SPD
DON'T CARE
Hi-Z
BIT 31 BIT 30 BIT 29 BIT 28 BIT 27 BIT 26 BIT 25 BIT 24 BIT 23 BIT 22 BIT 21
CONVERSION
FB
BIT 20 BIT 19
BIT 18 BIT 17
BIT 0
DATA INPUT/OUTPUT
CONVERSION
2492 F09
Figure 9. Internal Serial Clock, Single Cycle Operation
remains HIGH for the duration of the conversion cycle.
Once the conversion is complete, the cycle repeats.
Internal Serial Clock, 3-Wire I/O, Continuous
Conversion.
Typically, CS remains LOW during the data output state.
However, the data output state may be aborted by pulling
CS HIGH any time between the 1st rising edge and the 32nd
falling edge of SCK (see Figure 10). On the rising edge of
CS, the device aborts the data output state and immediately
initiates a new conversion. In order to program a new input
channel, 8 SCK clock pulses are required. If the data output
sequence is aborted prior to the 8th falling edge of SCK,
the new input data is ignored and the previously selected
input channel remains valid. If the rising edge of CS occurs
after the 8th falling edge of SCK, the new input channel is
loaded and valid for the next conversion cycle. If CS goes
high between the 8th falling edge and the 16th falling edge
of SCK, the new channel is still loaded, but the converter
conﬁguration remains unchanged. In order to program
both the input channel and converter conﬁguration, CS
must go high after the 16th falling edge of SCK (at this
point all data has been shifted into the device).
This timing mode uses a 3-wire interface. The conversion
result is shifted out of the device by an internally generated
serial clock (SCK) signal (see Figure 11). In this case, CS is
permanently tied to ground, simplifying the user interface
or transmission over an isolation barrier.
The internal serial clock mode is selected at the end of the
power-on reset (POR) cycle. The POR cycle is concluded
approximately 4ms after VCC exceeds 2V. An internal
weak pull-up is active during the POR cycle; therefore, the
internal serial clock timing mode is automatically selected
if SCK is ﬂoating or driven HIGH.
During the conversion, the SCK and the serial data output
pin (SDO) are HIGH (EOC = 1). Once the conversion is
complete, SCK and SDO go LOW (EOC = 0) indicating
the conversion has ﬁnished and the device has entered
the sleep state. The device remains in the sleep state a
minimum amount of time (1/2 the internal SCK period)
then immediately begins outputting and inputting data.
2492fb
24
LTC2492
APPLICATIONS INFORMATION
2.7V TO 5.5V
12
VCC
= EXTERNAL OSCILLATOR
= INTERNAL OSCILLATOR
1
FO
LTC2492
10μF
REFERENCE
VOLTAGE
0.1V TO VCC
0.1μF
13
REF +
14
REF –
8
9
10
ANALOG
INPUTS
11
7
VCC
2
SDI
OPTIONAL
10k
3
SCK
4-WIRE
SPI INTERFACE
CH0
CH1
CS
CH2
SDO
4
5
CH3
COM
GND
6
<tEOCTEST
CS
1
2
3
4
5
6
7
8
9
10
1
0
EN
SGL
ODD
A2
A1
A0
EN2
EOC
“0”
SIG
MSB
11
12
13
14
15
16
SCK
(INTERNAL)
SDI
DON'T CARE
SDO
IM
FA
FB
DON'T CARE
Hi-Z
BIT 31 BIT 30 BIT 29 BIT 28 BIT 27 BIT 26 BIT 25 BIT 24 BIT 23 BIT 22 BIT 21
CONVERSION
SPD
SLEEP
BIT 20 BIT 19 BIT 18
BIT17 BIT 19 BIT 19
DATA INPUT/OUTPUT
CONVERSION
2492 F10
Figure 10. Internal Serial Clock, Reduced Data Output Length with Valid Channel and Conﬁguration Selection
2.7V TO 5.5V
12
0.1μF
VCC
= EXTERNAL OSCILLATOR
= INTERNAL OSCILLATOR
1
FO
LTC2492
10μF
REFERENCE
VOLTAGE
0.1V TO VCC
REF+
SDI
14
REF –
SCK
8
9
ANALOG
INPUTS
VCC
13
10
11
7
2
OPTIONAL
10k
3
3-WIRE
SPI INTERFACE
CH0
CH1
SDO
CH2
CS
5
4
CH3
COM
GND
6
CS
1
2
3
4
5
6
7
8
9
1
0
EN
SGL
ODD
A2
A1
A0
EN2
EOC
“0”
SIG
MSB
10
11
12
13
14
32
SCK
(INTERNAL)
SDI
DON'T CARE
SDO
IM
FA
BIT 31 BIT 30 BIT 29 BIT 28 BIT 27 BIT 26 BIT 25 BIT 24 BIT 23 BIT 22 BIT 21
CONVERSION
FB
SPD
BIT 20 BIT 19
DATA INPUT/OUTPUT
DON'T CARE
BIT 18 BIT 17
BIT 0
CONVERSION
2492 F11
Figure 11. Internal Serial Clock, Continuous Operation
2492fb
25
LTC2492
APPLICATIONS INFORMATION
The input data is shifted through the SDI pin on the rising
edge of SCK (including the ﬁrst rising edge) and the
output data is shifted out the SDO pin on the falling edge
of SCK. The data input/output cycle is concluded and a
new conversion automatically begins after the 32nd rising
edge of SCK. During the next conversion, SCK and SDO
remain HIGH until the conversion is complete.
The Use of a 10k Pull-Up on SCK for Internal SCK
Selection
If CS is pulled HIGH while the converter is driving SCK
LOW, the internal pull-up is not available to restore SCK
to a logic HIGH state if SCK is ﬂoating. This will cause the
device to exit the internal SCK mode on the next falling
edge of CS. This can be avoided by adding an external 10k
pull-up resistor to the SCK pin.
Whenever SCK is LOW, the LTC2492’s internal pull-up at
SCK is disabled. Normally, SCK is not externally driven if
the device is operating in the internal SCK timing mode.
However, certain applications may require an external
driver on SCK. If the driver goes Hi-Z after outputting a
LOW signal, the internal pull-up is disabled. An external
10k pull-up resistor prevents the device from exiting the
internal SCK mode under this condition.
A similar situation may occur during the sleep state when CS
is pulsed HIGH-LOW-HIGH in order to test the conversion
status. If the device is in the sleep state (EOC = 0), SCK
will go LOW. If CS goes HIGH before the time tEOCtest ,
the internal pull-up is activated. If SCK is heavily loaded,
the internal pull-up may not restore SCK to a HIGH state
before the next falling edge of CS. The external 10k pull-up
resistor prevents the device from exiting the internal SCK
mode under this condition.
PRESERVING THE CONVERTER ACCURACY
The LTC2492 is designed to reduce as much as possible
sensitivity to device decoupling, PCB layout, anti-aliasing
circuits, line frequency perturbations, and temperature
sensitivity. In order to achieve maximum performance a
few simple precautions should be observed.
Digital Signal Levels
The LTC2492’s digital interface is easy to use. Its digital
inputs SDI, FO , CS, and SCK (in external serial clock mode)
accept standard CMOS logic levels. Internal hysteresis
circuits can tolerate edge transition times as slow as
100μs.
The digital input signal range is 0.5V to VCC – 0.5V. During
transitions, the CMOS input circuits draw dynamic current.
For optimal performance, application of signals to the
serial data interface should be reserved for the sleep and
data output periods.
During the conversion period, overshoot and undershoot
of fast digital signals applied to both the serial digital
interface and the external oscillator pin (FO) may degrade
the converter performance. Undershoot and overshoot
occur due to impedance mismatch of the circuit board
trace at the converter pin when the transition time of an
external control signal is less than twice the propagation
delay from the driver to the input pin. For reference, on a
regular FR-4 board, the propagation delay is approximately
183ps/inch. In order to prevent overshoot, a driver with
a 1ns transition time must be connected to the converter
through a trace shorter than 2.5 inches. This becomes
difﬁcult when shared control lines are used and multiple
reﬂections occur.
Parallel termination near the input pin of the LTC2492 will
eliminate this problem, but will increase the driver power
dissipation. A series resistor from 27Ω to 54Ω (depending
on the trace impedance and connection) placed near
the driver will also eliminate over/under shoot without
additional driver power dissipation.
For many applications, the serial interface pins (SCK, SDI,
CS, FO) remain static during the conversion cycle and
no degradation occurs. On the other hand, if an external
oscillator is used (FO driven externally) it is active during
the conversion cycle. Moreover, the digital ﬁlter rejection
is minimal at the clock rate applied to FO . Care must be
taken to ensure external inputs and reference lines do not
cross this signal or run near it. These issues are avoided
when using the internal oscillator.
2492fb
26
LTC2492
APPLICATIONS INFORMATION
Driving the Input and Reference
The input and reference pins of the LTC2492 are connected
directly to a switched capacitor network. Depending on
the relationship between the differential input voltage and
the differential reference voltage, these capacitors are
switched between these four pins. Each time a capacitor
is switched between two of these pins, a small amount
of charge is transferred. A simpliﬁed equivalent circuit is
shown in Figure 12.
terminals in order to ﬁlter unwanted noise (anti-aliasing)
results in incomplete settling.
Automatic Differential Input Current Cancellation
In applications where the sensor output impedance is
low (up to 10kΩ with no external bypass capacitor or up
to 500Ω with 0.001μF bypass), complete settling of the
input occurs. In this case, no errors are introduced and
direct digitization is possible.
When using the LTC2492’s internal oscillator, the input
capacitor array is switched at 123kHz. The effect of the
charge transfer depends on the circuitry driving the input/
reference pins. If the total external RC time constant is less
than 580ns the errors introduced by the sampling process
are negligible since complete settling occurs.
For many applications, the sensor output impedance
combined with external input bypass capacitors produces
RC time constants much greater than the 580ns required
for 1ppm accuracy. For example, a 10kΩ bridge driving a
0.1μF capacitor has a time constant an order of magnitude
greater than the required maximum.
Typically, the reference inputs are driven from a low
impedance source. In this case, complete settling occurs
even with large external bypass capacitors. The inputs (CH0
to CH3, COM), on the other hand, are typically driven from
larger source resistances. Source resistances up to 10k
may interface directly to the LTC2492 and settle completely;
however, the addition of external capacitors at the input
The LTC2492 uses a proprietary switching algorithm that forces
the average differential input current to zero independent of
external settling errors. This allows direct digitization of high
impedance sensors without the need of buffers.
IIN+
IN+
INPUT
MULTIPLEXER
100Ω
The switching algorithm forces the average input current
on the positive input (IIN+) to be equal to the average input
current on the negative input (IIN–). Over the complete
INTERNAL
SWITCH
NETWORK
( )
I IN+
10k
AVG
(
I REF +
IIN–
IN–
)
( )
= I IN–
AVG
≈
AVG
VIN(CM) − VREF(CM)
=
0.5 • REQ
(
1.5VREF + VREF(CM) – VIN(CM)
0.5 • REQ
)–
VIN2
VREF • REQ
where :
100Ω
VREF = REF + − REF −
10k
⎛ REF + – REF −
VREF(CM) = ⎜
⎜⎝
2
IREF+
REF+
CEQ
12pF
10k
VIN = IN+ − IN− , WHERE IN+ AND IN− ARE THE SELECTED INPUT CHANNELS
⎛ IN+ – IN− ⎞
VIN(CM) = ⎜
⎟
⎜⎝
⎟⎠
2
REQ = 2.71MΩ INTERNAL OSCILLATOR 60Hz MODE
REQ = 2.98MΩ INTERNAL OSCILLATOR 50Hz/60Hz MODE
(
IREF–
REF–
⎞
⎟
⎟⎠
)
REQ = 0.833 • 1012 /fEOSC EXTERNAL OSCILLATOR
10k
2492 F12
SWITCHING FREQUENCY
fSW = 123kHz INTERNAL OSCILLATOR
fSW = 0.4 • fEOSC EXTERNAL OSCILLATOR
Figure 12. LTC2492 Equivalent Analog Input Circuit
2492fb
27
LTC2492
APPLICATIONS INFORMATION
In applications where the input common mode voltage is
constant but different from the reference common mode
voltage, the differential input current remains zero while
the common mode input current is proportional to the
difference between VIN(CM) and VREF(CM). For a reference
common mode voltage of 2.5V and an input common mode
of 1.5V, the common mode input current is approximately
0.74μA. This common mode input current does not degrade
the accuracy if the source impedances tied to IN + and
IN – are matched. Mismatches in source impedance lead
to a ﬁxed offset error but do not effect the linearity or full
scale reading. A 1% mismatch in a 1k source resistance
leads to a 74μV shift in offset voltage.
In applications where the common mode input voltage
varies as a function of the input signal level (single-ended
type sensors), the common mode input current varies
proportionally with input voltage. For the case of balanced
input impedances, the common mode input current effects
are rejected by the large CMRR of the LTC2492, leading to little
degradation in accuracy. Mismatches in source impedances
lead to gain errors proportional to the difference between
the common mode input and common mode reference.
1% mismatches in 1k source resistances lead to gain
errors on the order of 15ppm. Based on the stability of the
internal sampling capacitors and the accuracy of the internal
oscillator, a one-time calibration will remove this error.
In addition to the input sampling current, the input ESD
protection diodes have a temperature dependent leakage
current. This current, nominally 1nA (±10nA Max), results
in a small offset shift. A 1k source resistance will create a
1μV typical and a 10μV maximum offset voltage.
Similar to the analog inputs, the LTC2492 samples the
differential reference pins (REF+ and REF–) transferring
small amounts of charge to and from these pins, thus
producing a dynamic reference current. If incomplete
settling occurs (as a function the reference source
resistance and reference bypass capacitance) linearity
and gain errors are introduced.
For relatively small values of external reference capacitance
(CREF < 1nF), the voltage on the sampling capacitor settles
for reference impedances of many kΩ (if CREF = 100pF up
to 10kΩ will not degrade the performance) (see Figures
13 and 14).
90
VCC = 5V
VREF = 5V
VIN+ = 3.75V
VIN– = 1.25V
FO = GND
TA = 25°C
80
70
60
+FS ERROR (ppm)
In applications where the input common mode voltage
is equal to the reference common mode voltage, as in
the case of a balanced bridge, both the differential and
common mode input currents are zero. The accuracy of
the converter is not compromised by settling errors.
Reference Current
50
CREF = 0.01μF
CREF = 0.001μF
CREF = 100pF
CREF = 0pF
40
30
20
10
0
–10
0
10
1k
100
RSOURCE (Ω)
10k
100k
2492 F13
Figure 13. +FS Error vs RSOURCE at VREF (Small CREF)
10
0
–10
–FS ERROR (ppm)
conversion cycle, the average differential input current
(IIN+ – IIN–) is zero. While the differential input current is
zero, the common mode input current (IIN+ + IIN–)/2 is
proportional to the difference between the common mode
input voltage (VIN(CM)) and the common mode reference
voltage (VREF(CM)).
–20
–30
CREF = 0.01μF
CREF = 0.001μF
CREF = 100pF
CREF = 0pF
–40
–50
VCC = 5V
–60 VREF = 5V
V + = 1.25V
–70 VIN– = 3.75V
IN
–80 FO = GND
TA = 25°C
–90
10
0
1k
100
RSOURCE (Ω)
10k
100k
2492 F14
Figure 14. –FS Error vs RSOURCE at VREF (Small CREF)
2492fb
28
LTC2492
APPLICATIONS INFORMATION
500
VCC = 5V
VREF = 5V
VIN+ = 3.75V
VIN– = 1.25V
FO = GND
TA = 25°C
+FS ERROR (ppm)
400
300
CREF = 1μF, 10μF
CREF = 0.1μF
CREF = 0.01μF
100
0
200
600
400
RSOURCE (Ω)
800
1000
2492 F15
Figure 15. +FS Error vs RSOURCE at VREF (Large CREF)
–100
–FS ERROR (ppm)
R = 1k
2
R = 500Ω
0
R = 100Ω
–2
–4
–6
–8
–10
–0.5
–0.3
0.1
–0.1
VIN/VREF
0.3
0.5
Figure 17. INL vs Differential Input Voltage and Reference
Source Resistance for CREF > 1μF
common mode voltages are different, the errors increase.
A 1V difference in between common mode input and
common mode reference results in a 6.7ppm INL error
for every 100Ω of reference resistance.
In addition to the reference sampling charge, the reference
ESD protection diodes have a temperature dependent
leakage current. This leakage current, nominally 1nA
(±10nA max) results in a small gain error. A 100Ω reference
resistance will create a 0.5μV full scale error.
Normal Mode Rejection and Anti-aliasing
0
CREF = 0.01μF
–200
CREF = 1μF, 10μF
–300
VCC = 5V
VREF = 5V
VIN+ = 1.25V
VIN– = 3.75V
FO = GND
TA = 25°C
–400
–500
VCC = 5V
8 VREF = 5V
VIN(CM) = 2.5V
6 T = 25°C
A
4 CREF = 10μF
2492 F17
200
0
10
INL (ppm OF VREF)
In cases where large bypass capacitors are required on
the reference inputs (CREF > 0.01μF) full-scale and linearity
errors are proportional to the value of the reference
resistance. Every ohm of reference resistance produces a
full-scale error of approximately 0.5ppm (while operating
in simultaneous 50Hz/60Hz mode) (see Figures 15 and 16).
If the input common mode voltage is equal to the reference
common mode voltage, a linearity error of approximately
0.67ppm per 100Ω of reference resistance results (see
Figure 17). In applications where the input and reference
0
200
CREF = 0.1μF
600
400
RSOURCE (Ω)
800
One of the advantages delta-sigma ADCs offer over
conventional ADCs is on-chip digital ﬁltering. Combined
with a large oversample ratio, the LTC2492 signiﬁcantly
simpliﬁes anti-aliasing ﬁlter requirements. Additionally,
the input current cancellation feature allows external low
pass ﬁltering without degrading the DC performance of
the device.
1000
2492 F16
Figure 16. –FS Error vs RSOURCE at VREF (Large CREF)
2492fb
29
LTC2492
APPLICATIONS INFORMATION
The SINC4 digital ﬁlter provides excellent normal mode
rejection at all frequencies except DC and integer multiples
of the modulator sampling frequency (fS) (see Figures
18 and 19). The modulator sampling frequency is fS =
15,360Hz while operating with its internal oscillator and
fS = FEOSC/20 when operating with an external oscillator
of frequency FEOSC.
The user can expect to achieve this level of performance
using the internal oscillator, as shown in Figures 22, 23,
and 24. Measured values of normal mode rejection are
shown superimposed over the theoretical values in all
three rejection modes.
0
0
–10
–10
INPUT NORMAL MODE REJECTION (dB)
INPUT NORMAL MODE REJECTION (dB)
When using the internal oscillator, the LTC2492 is designed
to reject line frequencies. As shown in Figure 20, rejection
nulls occur at multiples of frequency fN, where fN is
determined by the input control bits FA and FB (fN = 50Hz
or 60Hz or 55Hz for simultaneous rejection). Multiples of
the modulator sampling rate (fS = fN • 256) only reject noise
to 15dB (see Figure 21); if noise sources are present at
these frequencies anti-aliasing will reduce their effects.
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
0 fS 2fS 3fS 4fS 5fS 6fS 7fS 8fS 9fS 10fS11fS12fS
DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)
0
–10
INPUT NORMAL MODE REJECTION (dB)
INPUT NORMAL MODE REJECTION (dB)
0
–20
–40
–50
–60
–70
–80
–90
–100
–110
–120
0 fS 2fS 3fS 4fS 5fS 6fS 7fS 8fS 9fS 10fS
DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)
2492 F19
Figure 19. Input Normal Mode Rejection, Internal Oscillator
and 60Hz Rejection Mode
fN
2fN 3fN 4fN 5fN 6fN 7fN
INPUT SIGNAL FREQUENCY (Hz)
8fN
Figure 20. Input Normal Mode Rejection at DC
–10
–30
0
2492 F20
2492 F18
Figure 18. Input Normal Mode Rejection, Internal Oscillator
and 50Hz Rejection Mode
fN = fEOSC/5120
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
250fN 252fN 254fN 256fN 258fN 260fN 262fN
INPUT SIGNAL FREQUENCY (Hz)
2492 F21
Figure 21. Input Normal Mode Rejection at fS = 256 • fN
2492fb
30
LTC2492
APPLICATIONS INFORMATION
MEASURED DATA
CALCULATED DATA
–20
–40
VCC = 5V
VREF = 5V
VIN(CM) = 2.5V
VIN(P-P) = 5V
TA = 25°C
–60
–80
–100
–120
0
15
30
45
60
75
90 105 120 135 150 165 180 195 210 225 240
INPUT FREQUENCY (Hz)
2492 F22
Figure 22. Input Normal Mode Rejection vs Input Frequency with
Input Perturbation of 100% (60Hz Notch)
NORMAL MODE REJECTION (dB)
0
MEASURED DATA
CALCULATED DATA
–20
–40
VCC = 5V
VREF = 5V
VIN(CM) = 2.5V
VIN(P-P) = 5V
TA = 25°C
–60
–80
–100
–120
0
Traditional high order delta-sigma modulators suffer from
potential instabilities at large input signal levels. The
proprietary architecture used for the LTC2492 third order
modulator resolves this problem and guarantees stability
with input signals 150% of full-scale. In many industrial
applications, it is not uncommon to have microvolt level
signals superimposed over unwanted error sources with
several volts of peak-to-peak noise. Figures 25 and 26
show measurement results for the rejection of a 7.5V
peak-to-peak noise source (150% of full scale) applied
to the LTC2492. From these curves, it is shown that the
rejection performance is maintained even in extremely
noisy environments.
0
NORMAL MODE REJECTION (dB)
NORMAL MODE REJECTION (dB)
0
–20
–60
–80
–100
0
15
30
45
60
75
90 105 120 135 150 165 180 195 210 225 240
INPUT FREQUENCY (Hz)
2492 F23
2492 F25
Figure 25. Measure Input Normal Mode Rejection vs Input
Frequency with Input Perturbation of 150% (60Hz Notch)
Figure 23. Input Normal Mode Rejection vs Input Frequency with
Input Perturbation of 100% (50Hz Notch)
MEASURED DATA
CALCULATED DATA
–20
–40
VCC = 5V
VREF = 5V
VIN(CM) = 2.5V
VIN(P-P) = 5V
TA = 25°C
–60
–80
–100
–120
0
20
40
60
80
100
120
140
INPUT FREQUENCY (Hz)
160
180
200
220
2492 F24
Figure 24. Input Normal Mode Rejection vs Input Frequency with
Input Perturbation of 100% (50Hz/60Hz Notch)
0
NORMAL MODE REJECTION (dB)
NORMAL MODE REJECTION (dB)
0
VCC = 5V
VREF = 5V
VIN(CM) = 2.5V
TA = 25°C
–40
–120
12.5 25 37.5 50 62.5 75 87.5 100 112.5 125 137.5 150 162.5 175 187.5 200
INPUT FREQUENCY (Hz)
VIN(P-P) = 5V
VIN(P-P) = 7.5V
(150% OF FULL SCALE)
VIN(P-P) = 5V
VIN(P-P) = 7.5V
(150% OF FULL SCALE)
–20
VCC = 5V
VREF = 5V
VIN(CM) = 2.5V
TA = 25°C
–40
–60
–80
–100
–120
0
12.5 25 37.5 50 62.5 75 87.5 100 112.5 125 137.5 150 162.5 175 187.5 200
INPUT FREQUENCY (Hz)
2492 F26
Figure 26. Measure Input Normal Mode Rejection vs Input
Frequency with input Perturbation of 150% (50Hz Notch)
2492fb
31
LTC2492
APPLICATIONS INFORMATION
Using the 2x speed mode of the LTC2492 alters the rejection
characteristics around DC and multiples of fS . The device
bypasses the offset calibration in order to increase the
output rate. The resulting rejection plots are shown in
Figures 27 and 28. 1x type frequency rejection can be
achieved using the 2x mode by performing a running
average of the conversion results (see Figure 29).
Output Data Rate
When using its internal oscillator, the LTC2492 produces up
to 7.5 samples per second (sps) with a notch frequency of
60Hz. The actual output data rate depends upon the length
of the sleep and data output cycles which are controlled
by the user and can be made insigniﬁcantly short. When
operating with an external conversion clock (FO connected
to an external oscillator), the LTC2492 output data rate
can be increased. The duration of the conversion cycle is
41036/fEOSC. If fEOSC = 307.2kHz, the converter behaves
as if the internal oscillator is used.
An increase in fEOSC over the nominal 307.2kHz will translate
into a proportional increase in the maximum output data
rate (up to a maximum of 100sps). The increase in output
rate leads to degradation in offset, full-scale error, and
effective resolution as well as a shift in frequency rejection.
When using the integrated temperature sensor, the internal
oscillator should be used or an external oscillator, fEOSC =
307.2kHz maximum.
A change in fEOSC results in a proportional change in the
internal notch position. This leads to reduced differential
mode rejection of line frequencies. The common mode
rejection of line frequencies remains unchanged, thus fully
differential input signals with a high degree of symmetry
on both the IN+ and IN– pins will continue to reject line
frequency noise.
An increase in fEOSC also increases the effective dynamic
input and reference current. External RC networks will
continue to have zero differential input current, but the
time required for complete settling (580ns for fEOSC =
307.2kHz) is reduced, proportionally.
Once the external oscillator frequency is increased
above 1MHz (a more than 3x increase in output rate) the
effectiveness of internal auto calibration circuits begins
to degrade. This results in larger offset errors, full scale
errors, and decreased resolution (see Figures 30 to 37).
0
INPUT NORMAL REJECTION (dB)
INPUT NORMAL REJECTION (dB)
0
–20
–40
–60
–80
–100
–120
0
fN
2fN 3fN 4fN 5fN 6fN 7fN
INPUT SIGNAL FREQUENCY (fN)
8fN
2492 F27
Figure 27. Input Normal Mode Rejection 2x Speed Mode
–20
–40
–60
–80
–100
–120
248 250 252 254 256 258 260 262 264
INPUT SIGNAL FREQUENCY (fN)
2492 F28
Figure 28. Input Normal Mode Rejection 2x Speed Mode
2492fb
32
LTC2492
APPLICATIONS INFORMATION
50
NO AVERAGE
–90
WITH
RUNNING
AVERAGE
–100
–110
–120
–130
3500
VIN(CM) = VREF(CM)
VCC = VREF = 5V
VIN = 0V
FO = EXT CLOCK
40
3000
+FS ERROR (ppm OF VREF)
–80
OFFSET ERROR (ppm OF VREF)
NORMAL MODE REJECTION (dB)
–70
30
TA = 85°C
20
10
VIN(CM) = VREF(CM)
VCC = VREF = 5V
FO = EXT CLOCK
2500
TA = 85°C
2000
1500
TA = 25°C
1000
0
500
TA = 25°C
–140
0
–10
60
62
54 56
58
48 50
52
DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)
0
10 20 30 40 50 60 70 80 90 100
OUTPUT DATA RATE (READINGS/SEC)
2492 F29
0 10 20 30 40 50 60 70 80 90 100
OUTPUT DATA RATE (READINGS/SEC)
2492 F31
2492 F30
Figure 29. Input Normal Mode Rejection
2x Speed Mode with and Without Running
Averaging
Figure 30. Offset Error vs Output Data
Rate and Temperature
Figure 31. +FS Error vs Output Data
Rate and Temperature
24
0
22
TA = 25°C
22
–500
20
TA = 25°C
–1500
TA = 85°C
–2000
–2500
–3000
–3500
VIN(CM) = VREF(CM)
VCC = VREF = 5V
FO = EXT CLOCK
20
18
16
14
12
10
0 10 20 30 40 50 60 70 80 90 100
OUTPUT DATA RATE (READINGS/SEC)
VIN(CM) = VREF(CM)
VCC = VREF = 5V
VIN = 0V
FO = EXT CLOCK
RES = LOG 2 (VREF/NOISERMS)
TA = 85°C
14
2492 F34
Figure 33. Resolution (NoiseRMS ≤ 1LSB)
vs Output Data Rate and Temperature
Figure 34. Resolution (INLMAX ≤ 1LSB)
vs Output Data Rate and Temperature
24
20
VIN(CM) = VREF(CM)
VIN = 0V
15 FO = EXT CLOCK
TA = 25°C
TA = 25°C
16
2492 F33
Figure 32.–FS Error vs Output Data Rate
and Temperature
22
VCC = VREF = 5V
22
RESOLUTION (BITS)
OFFSET ERROR (ppm OF VREF)
18
VIN(CM) = VREF(CM)
12 VCC = VREF = 5V
FO = EXT CLOCK
RES = LOG 2 (VREF/INLMAX)
10
0 10 20 30 40 50 60 70 80 90 100
OUTPUT DATA RATE (READINGS/SEC)
0 10 20 30 40 50 60 70 80 90 100
OUTPUT DATA RATE (READINGS/SEC)
2492 F32
10
VCC = VREF = 5V
5
0
–5
VCC = 5V, VREF = 2.5V
–10
RESOLUTION (BITS)
RESOLUTION (BITS)
–1000
0 10 20 30 40 50 60 70 80 90 100
OUTPUT DATA RATE (READINGS/SEC)
2492 F35
Figure 35. Offset Error vs Output Data
Rate and Reference Voltage
20
20
VCC = 5V, VREF = 2.5V
18
16
14 VIN(CM) = VREF(CM)
VIN = 0V
FO = EXT CLOCK
12 T = 25°C
A
RES = LOG 2 (VREF/NOISERMS)
10
0 10 20 30 40 50 60 70 80 90 100
OUTPUT DATA RATE (READINGS/SEC)
2492 F36
Figure 36. Resolution (NoiseRMS ≤ 1LSB)
vs Output Data Rate and Reference
Voltage
RESOLUTION (BITS)
–FS ERROR (ppm OF VREF)
TA = 85°C
18
VCC = VREF = 5V
16
VCC = 5V, VREF = 2.5V
VIN(CM) = VREF(CM)
14
VIN = 0V
REF– = GND
12 FO = EXT CLOCK
TA = 25°C
RES = LOG 2 (VREF/INLMAX)
10
0 10 20 30 40 50 60 70 80 90 100
OUTPUT DATA RATE (READINGS/SEC)
2492 F37
Figure 37. Resolution (INLMAX ≤ 1LSB)
vs Output Data Rate and Reference
Voltage
2492fb
33
LTC2492
APPLICATIONS INFORMATION
Easy Drive ADCs Simplify Measurement of High
Impedance Sensors
Delta-Sigma ADCs, with their high accuracy and high noise
immunity, are ideal for directly measuring many types
of sensors. Nevertheless, input sampling currents can
overwhelm high source impedances or low-bandwidth,
micropower signal conditioning circuits. The LTC2492
solves this problem by balancing the input currents, thus
simplifying or eliminating the need for signal conditioning
circuits.
A common application for a delta-sigma ADC is thermistor
measurement. Figure 38 shows two examples of thermistor
digitization beneﬁting from the Easy Drive technology.
The ﬁrst circuit (applied to input channels CH0 and CH1)
uses balanced reference resistors in order to balance the
common mode input/reference voltage and balance the
differential input source resistance. If reference resistors
R1 and R4 are exactly equal, the input current is zero and
no errors result. If these resistors have a 1% tolerance,
the maximum error in measured resistance is 1.6Ω due
to a shift in common mode voltage; far less than the 1%
error of the reference resistors themselves. No ampliﬁer
is required, making this an ideal solution in micropower
applications.
Easy Drive also enables very low power, low bandwidth
ampliﬁers to drive the input to the LTC2492. As shown in
Figure 38, CH2 is driven by the LT1494. The LT1494 has
excellent DC specs for an ampliﬁer with 1.5μA supply
current (the maximum offset voltage is 150μV and the
open loop gain is 100,000). Its 2kHz bandwidth makes
it unsuitable for driving conventional delta sigma ADCs.
Adding a 1kΩ, 0.1μF ﬁlter solves this problem by providing
a charge reservoir that supplies the LTC2492 instantaneous
current, while the 1k resistor isolates the capacitive load
from the LT1494.
Conventional delta sigma ADCs input sampling current
lead to DC errors as a result of incomplete settling in the
external RC network.
The Easy Drive technology cancels the differential input
current. By balancing the negative input (CH3) with a 1kΩ,
0.1μF network errors due to the common mode input
current are cancelled.
2492fb
34
LTC2492
PACKAGE DESCRIPTION
DE Package
14-Lead Plastic DFN (4mm × 3mm)
(Reference LTC DWG # 05-08-1708 Rev A)
0.70 ±0.05
3.30 ±0.05
3.60 ±0.05
2.20 ±0.05
1.70 ± 0.05
PACKAGE
OUTLINE
0.25 ± 0.05
0.50 BSC
3.00 REF
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
R = 0.115
TYP
4.00 ±0.10
(2 SIDES)
R = 0.05
TYP
3.00 ±0.10
(2 SIDES)
0.40 ± 0.10
8
14
3.30 ±0.10
1.70 ± 0.10
PIN 1 NOTCH
R = 0.20 OR
0.35 s 45°
CHAMFER
PIN 1
TOP MARK
(SEE NOTE 6)
(DE14) DFN 0806 REV B
7
0.200 REF
1
0.25 ± 0.05
0.50 BSC
0.75 ±0.05
3.00 REF
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WGED-3) IN JEDEC
PACKAGE OUTLINE MO-229
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
2492fb
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation
that the interconnection of its circuits as described herein will not infringe on existing patent rights.
35
LTC2492
TYPICAL APPLICATION
5V
5V
R1
51.1k
C4
0.1μF
12
10μF
IIN+ = 0
R3
10k TO 100k
IIN– = 0
R4
51.1k
14
8
5V
9
10
5V
102k
11
+
0.1μF
10k TO 100k
7
1k
LT1494
REF +
REF –
CH0
2
SDI
3
SCK
SDO
3-WIRE
SPI INTERFACE
5
CH1
CH2
4
CS
CH3
COM
GND
6
2492 F38
0.1μF
–
= EXTERNAL OSCILLATOR
= INTERNAL OSCILLATOR
1
FO
LTC2492
13
0.1μF
C3
0.1μF
VCC
1k
0.1μF
Figure 38. Easy Drive ADCs Simplify Measurement of High Impedance Sensors
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LT1236A-5
Precision Bandgap Reference, 5V
0.05% Max Initial Accuracy, 5ppm/°C Drift
LT1460
Micropower Series Reference
0.075% Max Initial Accuracy, 10ppm/°C Max Drift
LT1790
Micropower SOT-23 Low Dropout Reference Family
0.05% Max Initial Accuracy, 10ppm/°C Max Drift
LTC2400
24-Bit, No Latency Δ∑ ADC in SO-8
0.3ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200μA
LTC2410
24-Bit, No Latency Δ∑ ADC with Differential Inputs
0.8μVRMS Noise, 2ppm INL
LTC2411/
LTC2411-1
24-Bit, No Latency Δ∑ ADCs with Differential Inputs in MSOP
1.45μVRMS Noise, 4ppm INL, Simultaneous 50Hz/60Hz
Rejection (LTC2411-1)
LTC2413
24-Bit, No Latency Δ∑ ADC with Differential Inputs
Simultaneous 50Hz/60Hz Rejection, 800nVRMS Noise
LTC2440
High Speed, Low Noise 24-Bit Δ∑ ADC
3.5kHz Output Rate, 200nV Noise, 24.6 ENOBs
LTC2442
24-Bit, High Speed 2-Channel and 4-Channel Δ∑ ADC with
Integrated Ampliﬁer
8kHz Output Rate, 220nV Noise, Simultaneous 50Hz/60Hz Rejection
LTC2449
24-Bit, High Speed 8-Channel and 16-Channel Δ∑ ADC
8kHz Output Rate, 200nV Noise, Simultaneous 50Hz/60Hz Rejection
LTC2480
16-Bit Δ∑ ADC with Easy Drive Inputs, 600nV Noise,
Programmable Gain, and Temperature Sensor
Pin Compatible with LTC2482/LTC2484
LTC2481
16-Bit Δ∑ ADC with Easy Drive Inputs, 600nV Noise, I2C
Interface, Programmable Gain, and Temperature Sensor
Pin Compatible with LTC2483/LTC2485
LTC2482
16-Bit Δ∑ ADC with Easy Drive Inputs
Pin Compatible with LTC2480/LTC2484
LTC2483
16-Bit Δ∑ ADC with Easy Drive Inputs, and I2C Interface
Pin Compatible with LTC2481/LTC2485
LTC2484
24-Bit Δ∑ ADC with Easy Drive Inputs
Pin Compatible with LTC2480/LTC2482
LTC2485
24-Bit Δ∑ ADC with Easy Drive Inputs, I2C Interface, and
Temperature Sensor
Pin Compatible with LTC2481/LTC2483
LTC2488
2-Channel and 4-Channel 16-Bit Δ∑ ADC with Easy Drive Inputs Pin Compatible with LTC2492
LTC2496/
LTC2498
16-Channel/8-Channel 16-Bit/24-Bit Δ∑ ADC with Easy Drive
Inputs, and SPI Interface
Timing Compatible with LTC2492
2492fb
36 Linear Technology Corporation
LT 1008 REV B• PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2006

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