Micro Linear ML4822IP Zvs average current pfc controller Datasheet

May 1997
ML4822*
ZVS Average Current PFC Controller
GENERAL DESCRIPTION
FEATURES
The ML4822 is a PFC controller designed specifically for
high power applications. The controller contains all of the
functions necessary to implement an average current
boost PFC converter, along with a Zero Voltage Switch
(ZVS) controller to reduce diode recovery and MOSFET
turn-on losses.
■
The average current boost PFC circuit provides high
power factor (>98%) and low Total Harmonic Distortion
(THD). Built-in safety features include undervoltage
lockout, overvoltage protection, peak current limiting, and
input voltage brownout protection.
The ZVS control section drives an external ZVS MOSFET
which, combined with a diode and inductor, soft switches
the boost regulator. This technique reduces diode reverse
recovery and MOSFET switching losses to reduce EMI and
maximize efficiency.
■
■
■
■
■
■
Average current sensing, continuous boost, leading
edge PFC for low total harmonic distortion and near
unity power factor
Built-in ZVS switch control with fast response for high
efficiency at high power levels
Average line voltage compensation with brownout
control
Current fed gain modulator improves noise immunity
and provides universal input operation
Overvoltage comparator eliminates output “runaway”
due to load removal
UVLO, current limit, and soft-start
Precision 1% reference
*This Part Is End Of Life As Of August 1, 2000
BLOCK DIAGRAM (Pin configuration shown for 14-pin package)
VEAO
FB
–
14
2.5V
IAC
4
+
1
8
2
GND
FB
R+
+
+
VCC
OVP
VCCZ
12
13.5V
IEA
2.7V
–
+
GAIN
MODULATOR
–
–
VRMS
5
IEAO
VEA
S
Q
I LIMIT
R–
–1V
ISENSE
+
R
–
3
PFC OUT
11
RTCT
6
OSC
S
Q
R
Q
VCCZ
REF
13
ZV SENSE
7
ZVS OUT
REF
10
+
S
Q
R
Q
––
PWR GND
9
1
ML4822
PIN CONFIGURATION
ML4822
16-Pin SOIC (S16W)
ML4822
14-Pin DIP (P14)
VEAO
IEAO
ISENSE
1
2
3
14
13
12
FB
VEAO
1
16
FB
REF
IEAO
2
15
REF
ISENSE
3
14
VCC
4
13
PFC OUT
VCC
IAC
4
11
PFC OUT
IAC
VRMS
5
10
ZVS OUT
VRMS
5
12
ZVS OUT
RTCT
6
9
PWR GND
RTCT
6
11
PWR GND
ZV SENSE
7
8
GND
ZV SENSE
7
10
GND
N/C
8
9
N/C
TOP VIEW
TOP VIEW
PIN DESCRIPTION (Pin number in parentheses is for 16-pin package)
PIN
NAME
FUNCTION
1 (1)
VEAO
Transconductance voltage error
amplifier output.
2 (2)
IEAO
Transconductance current error
amplifier output.
3 (3)
ISENSE
Current sense input to the PFC
current limit comparator.
11 (13) PFC OUT PFC MOSFET driver output.
4 (4)
IAC
PFC gain modulator reference input.
12 (14) VCC
Shunt-regulated supply voltage.
5 (5)
VRMS
Input for RMS line voltage
compensation.
13 (15) REF
Buffered output for the internal
7.5V reference.
6 (6)
RTCT
Connection for oscillator frequency
setting components.
14 (16) FB
Transconductance voltage error
amplifier input.
7 (7)
ZV SENSE
Input to the high speed zero voltage
crossing comparator.
2
PIN
NAME
8 (10) GND
FUNCTION
Analog signal ground.
9 (11) PWR GND Return for the PFC and ZVS driver
outputs.
10 (12) ZVS OUT ZVS MOSFET driver output.
ML4822
ABSOLUTE MAXIMUM RATINGS
Absolute maximum ratings are those values beyond which
the device could be permanently damaged. Absolute
maximum ratings are stress ratings only and functional
device operation is not implied.
Lead Temperature (Soldering, 10 sec) ..................... 150°C
Thermal Resistance (θJA)
Plastic DIP ....................................................... 80°C/W
Plastic SOIC ....................................................110°C/W
Shunt Regulator Current (ICC ) ................................. 55mA
Peak Driver Output Current ............................... ±500mA
Analog Inputs ................................................... –0.3 to 7V
Junction Temperature ............................................. 150°C
Storage Temperature Range ..................... –65°C to 150°C
OPERATING CONDITIONS
Temperature Range
ML4822CX ................................................ 0°C to 70°C
ML4822IX .............................................. –40°C to 85°C
ELECTRICAL CHARACTERISTICS
Unless otherwise specified, RT = 52.3kΩ, CT = 470pF, TA = Operating Temperature Range (Note 1)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
7
V
VOLTAGE ERROR AMPLIFIER
0
Ω
Input Voltage Range
Transconductance
VNON-INV = VINV, VEAO = 3.75V
50
70
120
µ
Feedback Reference Voltage
VEAO = VFB
2.4
2.5
2.6
V
60
75
dB
60
75
dB
Open Loop Gain
PSRR
VCCZ – 3V < VCC < VCCZ – 0.5V
Output Low
0.65
Output High
1
V
6.0
6.7
V
Source Current
∆VIN = ±0.5V, VOUT = 6V
–40
–80
µA
Sink Current
∆VIN = ±0.5V, VOUT = 1.5V
40
80
mA
CURRENT ERROR AMPLIFIER
Transconductance
–1.5
VNON-INV = VINV, IEAO = 3.75V
130
Input Offset Voltage
Open Loop Gain
PSRR
VCCZ – 3V < VCC < VCCZ – 0.5V
2
V
195
310
µ
±3
±15
mV
60
75
dB
60
75
dB
Output Low
0.65
Output High
Ω
Input Voltage Range
1
V
6.0
6.7
V
Source Current
∆VIN = ±0.5V, VOUT = 6V
–40
–80
µA
Sink Current
∆VIN = ±0.5V, VOUT = 1.5V
40
80
µA
Threshold Voltage
2.6
2.7
2.8
V
Hysteresis
80
120
150
mV
–0.8
–1.0
–1.15
V
150
300
ns
OVP COMPARATOR
ISENSE COMPARATOR
Threshold Voltage
Delay to Output
3
ML4822
ELECTRICAL CHARACTERISTICS (Continued)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
50
ns
7.65
V
ZV SENSE COMPARATOR
Propagation Delay
100mV Overdrive
Threshold Voltage
7.35
Input Capacitance
7.5
6
pF
GAIN MODULATOR
Gain (Note 2)
IIAC = 100mA, VVRMS = 0V,
VFB = 0V
0.36
0.51
0.66
IIAC = 50mA, VVRMS = 1.2V,
VFB = 0V
1.20
1.72
2.24
IIAC = 100µA, VVRMS = 1.8V,
VFB = 0V
0.55
0.78
1.01
IIAC = 100µA, VVRMS = 3.3V,
VFB = 0V
0.14
0.20
0.26
Bandwidth
IIAC = 250µA
Output Voltage
VFB = 0V, VVRMS = 1.15V,
IIAC = 250µA
10
MHz
0.72
0.8
0.9
V
74
80
86
kHz
OSCILLATOR
Initial Accuracy
TA = 25°C
Voltage Stability
VCCZ – 3V < VCC < VCCZ – 0.5V
Temperature Stability
Total Variation
Line, temperature
1
%
2
%
72
Ramp Valley to Peak Voltage
88
2.5
kHz
V
Dead Time
100
300
450
ns
CT Discharge Current
4.5
7.5
9.5
mA
7.425
7.5
7.575
V
REFERENCE
Output Voltage
TA = 25°C, IREF = 1mA
Line Regulation
VCCZ – 3V < VCC < VCCZ – 0.5V
2
10
mV
Load Regulation
1mA < IREF, < 20mA
2
15
mV
Temperature Stability
0.4
Total Variation
Line, load, and temperature
Long Term Stability
Tj = 125°C, 1000 hours
Short Circuit Current
VCC < VCCZ – 0.5V, VREF = 0V
7.395
–15
%
7.605
V
5
25
mV
–40
–100
mA
0
%
PFC COMPARATOR
Minimum Duty Cycle
VIEAO > 6.7V
Maximum Duty Cycle
VIEAO < 1.2V
4
90
95
%
ML4822
ELECTRICAL CHARACTERISTICS (Continued)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
IOUT = –20mA
0.3
0.8
V
IOUT = –100mA
0.6
3.0
V
IOUT = –10mA, VCC = 8V
0.8
1.5
V
MOSFET DRIVER OUTPUTS
Output Low Voltage
Output High Voltage
Output Rise/Fall Time
IOUT = 20mA
9.5
10.3
V
IOUT = 100mA
9
10.3
V
40
ns
VCCZ – 0.9 VCCZ – 0.6 VCCZ – 0.2
V
CL = 1000pF
UNDERVOLTAGE LOCKOUT
Threshold Voltage
Hysteresis
2.5
2.8
3.2
V
12.8
13.5
14.2
V
±150
±300
mV
14.6
V
SUPPLY
Shunt Voltage (VCCZ)
ICC =25mA
Load Regulation
25mA < ICC < 55mA
Total Variation
Load and temperature
Start-up Current
VCC < 12.3V
0.7
1.1
mA
Operating Current
VCC = VCCZ – 0.5V
22
28
mA
Note 1:
Note 2:
12.4
Limits are guaranteed by 100% testing, sampling, or correlation with worst-case test conditions.
Gain = K x 5.3 V; K = (IGAINMOD – IOFFSET) x IAC x (VEAO – 1.5)–1.
5
ML4822
FUNCTIONAL DESCRIPTION
capacitance of D1 and Q1 (or optional ZVS capacitor
CZVS). At t3, the voltage across Q1 is sufficiently low that
the controller turns Q2 off and Q1 on. Q1 then behaves
as an ordinary PFC switch, storing energy in the boost
inductor L1. The energy stored in L2 is completely
discharged into the boost capacitor via D2 during the Q1
off-time and the value of L2 must be selected for
discontinuous-mode operation.
Switching losses of wide input voltage range PFC boost
converters increase dramatically as power levels increase
above 200 watts. The use of zero-voltage switching (ZVS)
techniques improves the efficiency of high power PFCs by
significantly reducing the turn-on losses of the boost
MOSFET. ZVS is accomplished by using a second, smaller
MOSFET, together with a storage element (inductor) to
convert the turn-on losses of the boost MOSFET into
useful output power.
COMPONENT SELECTION
Q1 Turn-Off
The basic function of the ML4822 is to provide a power
factor corrected, regulated DC bus voltage using
continuous, average current-mode control. Like Micro
Linear’s family of PFC/PWM controllers, the ML4822
employs leading-edge pulse width modulation to reduce
system noise and permit frequency synchronization to a
trailing edge PWM stage for the highest possible DC bus
voltage bandwidth. For minimization of switching losses,
circuitry has been incorporated to control the switching of
the ZVS FET.
Because the ML4822 uses leading edge modulation, the
PFC MOSFET (Q1) is always turned off at the end of each
oscillator ramp cycle. For proper operation, the internal
ZVS flip-flop must be reset every cycle during the
oscillator discharge time. This is done by automatically
resetting the ZVS comparator a short time after the drain
voltage of the main Q has reached zero (refer to Figure 1
sense circuit). This sense circuit terminates the ZVS on
time by sensing the main Q drain voltage reaching zero. It
is then reset by way of a resistor pull-up to VCC (R6). The
advantage of this circuit is that the ZVS comparator is not
reset at the main Q turn off which occurs at the end of the
clock cycle. This avoids the potential for improper reset of
the internal ZVS flip-flop.
THEORY OF OPERATION
Figure 1 shows a simplified schematic of the output and
control sections of a high power PFC circuit. Figure 2
shows the relationship of various waveforms in the circuit.
Q1 functions as the main switching FET and Q2 provides
the ZVS action. During each cycle, Q2 turns on before
Q1, diverting the current in L1 away from D1 into L2. The
current in L2 increases linearly until at t2 it equals the
current through L1. When these currents are equal, L1
ceases discharging current and is now charged through L2
and Q2. At time t 2, the drain voltage of Q1 begins to fall.
The shape of the voltage waveform is sinusoidal due to
the interaction of L2 and the combined parasitic
Another concern is the proper operation of the ZVS
comparator during discontinuous mode operation (DCM),
which will occur at the cusps of the rectified AC
waveform and at light loads. Due to the nature of the
voltage seen at the drain of the main boost Q during DCM
operation, the ZVS comparator can be fooled into forcing
the ZVS Q on for the entire period. By adding a circuit
which limits the maximum on time of the ZVS Q, this
problem can be avoided. Q3 in Figure 1 provides this
function.
L1
D1
+
C1
VREF
13 VREF
L2
ML4822
CZVS(OPT)
12 VCC
D2
Q1
R3
22k
R5
220
R6
22k
PFC OUT 11
7 ZV SENSE
C3
33pF
R4
51k
C4
330pF
R1
Q2
ZVS OUT 10
PWR GND 9
8 GND
MAX ZVS
ON TIME LIMIT
R2
Q3
C5
Figure 1. Simplified PFC/ZVS Schematic.
6
C2
ML4822
Q1 Turn-On
The turn-on event consists of the time it takes for the
current through L2 to ramp to the L1 current plus the
resonant event of L2 and the ZVS capacitor. The total
event should occur in a minimum of 350–450ns, but can
be longer at the risk of increasing the total harmonic
distortion. Setting these times equal should minimize
conducted and radiated emissions.
tQ1(OFF) = tIL2 + tRES = 400ns
A. SYSTEM
CLOCK
(INTERNAL)
(1)
B. RTCT
Where IL2 is equal to IL1.
The value of L2 is calculated to remain in discontinuousmode:
V
× VRMS(MIN) × tIL2
L2 = BUS
(2)
2 × POUT
The resonant event occurs in 1/4 of a full sinusoidal cycle.
For example, when a 1/4 cycle occurs in 200ns, the
frequency is 1.25MHz.
1
1
fRES =
=
4
×
tRES
(3)
2π L2 × CZVS
C. ZVS GATE (Q2)
Rearranging and solving for L2:
2
L2 =
4 × tRES
2
π × CZVS
D. VDS (Q2)
(4)
The resonant capacitor (CZVS) value is found by setting
equations 2 and 4 equal to each other and solving for
CZVS.
2
4 × tRES × 2 × POUT
CZVS =
π2 × VBUS × VRMS(MIN) × tIL2
(5)
E. PFC GATE (Q1)
APPLICATION
Figure 3 displays a typical application circuit for a 500W
ZVS PFC supply. Full design details are covered in
application note 33, ML4822 Power Factor Correction
With Zero Voltage Resonant Switching.
F. VDS (Q1)
G. IL2
t1
t3
t2
Figure 2. Timing Diagrams
7
8
Figure 3. ML4822 Scematic
R25
51kΩ
R24
22kΩ
NEUTRAL
C19
330pF
50V
R16
8.25kΩ
1%
R27
220
D10
BYV26C
C14
0.47µF
250VAC
LINE 8AMP
250VAC
F1
C20
2.2nF
50V
250JB6L
D13
1N5401
R26
22kΩ
C13
100pF
50V
C18
33pF
50V
R15
16.2kΩ
1%
R23
402kΩ
1%
R13
402kΩ
1%
R19
10kΩ
C11
0.068µF
50V
C12
2.2nF
50V
D7
1N5401
R18
0.0732 5W 1%
B1
C6
0.47µF
16V
C22
100pF
ZV SENSE
RTCT
VRMS
IAC
ISENSE
IEAO
C4
0.1µF
50V
VCC
REF
FB
R4
10kΩ
1N4148
R29
10kΩ
GND
PWR GND
ZVS OUT
PFC OUT
ML4822
VEAO
Q3
2N7000
7
6
5
4
3
2
1
R17
220kΩ
C7
0.68µF 50V
R14
100kΩ 1%
R22
453kΩ 1%
R12
453kΩ 1%
10
11
12
13
14
8
9
Q1
IRFP460
D5
D1N4747
L1
420uH @ 10A
n = 57
C5
1µF
50V
D8
PRLL5819
D9
PRLL5819
C8
2.2µF
50V
C2
470pF
1600V
D6
D1N4747
R3
10
L2
8.5µ @ 14A
HFA15TB60
D1
4
3
2
1
IN B
VS RTN
IN A
NC
OUT B
VS
OUT A
NC
R1
3.3kΩ
3W
TC4427
R6
10kΩ
Q2
IRF830
D3
MUR460
R7
47
C9
1µF
50V
C15
1500µF
25V
5
6
7
8
C1
330µF
450V
D4
BYV26C
C21
0.1µF
200V
HFA08TB60
D2
C17
1µF
50V
C3
1000pF
50V
400VDC
C10
1µF
50V
D12
BYM12-50
D11
BYM 12-50
R21
39kΩ
2W
400VDC RTN
R11
2.37kΩ
1%
R2
10Ω
C16
1µF
50V
+
R20
93.1kΩ 1%
R9
93.1kΩ 1%
R8
93.1kΩ 1%
R10
102kΩ 1%
L1
n = 2.5
R5
39kΩ
2W
ML4822
ML4822
PHYSICAL DIMENSIONS inches (millimeters)
Package: P14
14-Pin PDIP
0.740 - 0.760
(18.79 - 19.31)
14
0.240 - 0.260 0.295 - 0.325
(6.09 - 6.61) (7.49 - 8.25)
PIN 1 ID
0.070 MIN
(1.77 MIN)
(4 PLACES)
1
0.050 - 0.065
(1.27 - 1.65)
0.100 BSC
(2.54 BSC)
0.015 MIN
(0.38 MIN)
0.170 MAX
(4.32 MAX)
0.125 MIN
(3.18 MIN)
0.016 - 0.022
(0.40 - 0.56)
SEATING PLANE
0º - 15º
0.008 - 0.012
(0.20 - 0.31)
11
ML4822
PHYSICAL DIMENSIONS inches (millimeters)
Package: S16W
16-Pin Wide SOIC
0.400 - 0.414
(10.16 - 10.52)
16
0.291 - 0.301 0.398 - 0.412
(7.39 - 7.65) (10.11 - 10.47)
PIN 1 ID
1
0.024 - 0.034
(0.61 - 0.86)
(4 PLACES)
0.050 BSC
(1.27 BSC)
0.095 - 0.107
(2.41 - 2.72)
0º - 8º
0.090 - 0.094
(2.28 - 2.39)
0.012 - 0.020
(0.30 - 0.51)
SEATING PLANE
0.005 - 0.013
(0.13 - 0.33)
0.022 - 0.042
(0.56 - 1.07)
0.009 - 0.013
(0.22 - 0.33)
ORDERING INFORMATION
PART NUMBER
TEMPERATURE RANGE
PACKAGE
ML4822CP
ML4822CS
0°C to 70°C
0°C to 70°C
14-Pin PDIP (P14) (EOL)
16-Pin Wide SOIC (S16W) (EOL)
ML4822IP
ML4822IS
–40°C to 85°C
–40°C to 85°C
14-Pin PDIP (P14) (EOL)
16-Pin Wide SOIC (S16W) (EOL)
© Micro Linear 1997
Micro Linear is a registered trademark of Micro Linear Corporation
Products described in this document may be covered by one or more of the following patents, U.S.: 4,897,611; 4,964,026; 5,027,116; 5,281,862; 5,283,483; 5,418,502; 5,508,570; 5,510,727; 5,523,940;
5,546,017; 5,559,470; 5,565,761; 5,592,128; 5,594,376; Japan: 2598946; 2619299. Other patents are pending.
Micro Linear reserves the right to make changes to any product herein to improve reliability, function or design.
Micro Linear does not assume any liability arising out of the application or use of any product described herein,
neither does it convey any license under its patent right nor the rights of others. The circuits contained in this
data sheet are offered as possible applications only. Micro Linear makes no warranties or representations as to
whether the illustrated circuits infringe any intellectual property rights of others, and will accept no responsibility
or liability for use of any application herein. The customer is urged to consult with appropriate legal counsel
before deciding on a particular application.
10
2092 Concourse Drive
San Jose, CA 95131
Tel: 408/433-5200
Fax: 408/432-0295
DS4822-01
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