IPB80N06S4L-05 IPI80N06S4L-05, IPP80N06S4L-05 OptiMOS®-T2 Power-Transistor Product Summary V DS 60 V R DS(on),max (SMD version) 4.8 mΩ ID 80 A Features • N-channel - Enhancement mode PG-TO263-3-2 PG-TO262-3-1 PG-TO220-3-1 • AEC Q101 qualified • MSL1 up to 260°C peak reflow • 175°C operating temperature • Green Product (RoHS compliant) • 100% Avalanche tested Type Package Marking IPB80N06S4L-05 PG-TO263-3-2 4N06L05 IPI80N06S4L-05 PG-TO262-3-1 4N06L05 IPP80N06S4L-05 PG-TO220-3-1 4N06L05 Maximum ratings, at T j=25 °C, unless otherwise specified Parameter Symbol Continuous drain current ID Conditions Value T C=25°C, V GS=10V1) 80 T C=100°C, V GS=10V2) 78 Unit A Pulsed drain current2) I D,pulse T C=25°C 320 Avalanche energy, single pulse2) E AS I D=40A 152 mJ Avalanche current, single pulse I AS - 80 A Gate source voltage V GS - ±16 V Power dissipation P tot T C=25°C 107 W Operating and storage temperature T j, T stg - -55 ... +175 °C - 55/175/56 IEC climatic category; DIN IEC 68-1 Rev. 1.0 page 1 2009-03-24 IPB80N06S4L-05 IPI80N06S4L-05, IPP80N06S4L-05 Parameter Symbol Values Conditions Unit min. typ. max. Thermal characteristics2) Thermal resistance, junction - case R thJC - - - 1.4 Thermal resistance, junction ambient, leaded R thJA - - - 62 SMD version, device on PCB R thJA minimal footprint - - 62 6 cm2 cooling area3) - - 40 K/W Electrical characteristics, at T j=25 °C, unless otherwise specified Static characteristics Drain-source breakdown voltage V (BR)DSS V GS=0V, I D= 1mA 60 - - Gate threshold voltage V GS(th) V DS=V GS, I D=60µA 1.2 1.7 2.2 Zero gate voltage drain current I DSS V DS=60V, V GS=0V - 0.01 1 - 5 100 V DS=60V, V GS=0V, T j=125°C2) V µA Gate-source leakage current I GSS V GS=16V, V DS=0V - - 100 nA Drain-source on-state resistance R DS(on) V GS=4.5V, I D=40A - 5.7 8.5 mΩ V GS=4.5V, I D=40A, SMD version - 5.4 8.2 V GS=10 V, I D=80 A - 4.2 5.1 V GS=10 V, I D=80 A, SMD version - 3.9 4.8 Rev. 1.0 page 2 2009-03-24 IPB80N06S4L-05 IPI80N06S4L-05, IPP80N06S4L-05 Parameter Symbol Values Conditions Unit min. typ. max. - 6290 8180 - 1350 1755 Dynamic characteristics2) Input capacitance C iss Output capacitance C oss Reverse transfer capacitance Crss - 60 120 Turn-on delay time t d(on) - 14 - Rise time tr - 4 - Turn-off delay time t d(off) - 80 - Fall time tf - 13 - Gate to source charge Q gs - 23 30 Gate to drain charge Q gd - 8 16 Gate charge total Qg - 83 110 Gate plateau voltage V plateau - 3.7 - V - - 80 A - - 320 V GS=0V, V DS=25V, f =1MHz V DD=30V, V GS=10V, I D=80A, R G=3.5Ω pF ns Gate Charge Characteristics2) V DD=48V, I D=80A, V GS=0 to 10V nC Reverse Diode Diode continous forward current2) IS Diode pulse current2) I S,pulse Diode forward voltage V SD V GS=0V, I F=80A, T j=25°C 0.6 0.95 1.3 V Reverse recovery time2) t rr V R=30V, I F=80A, di F/dt =100A/µs - 36 - ns Reverse recovery charge2) Q rr - 41 - nC T C=25°C 1) Current is limited by bondwire; with an R thJC = 1.4K/W the chip is able to carry 112A at 25°C. 2) Specified by design. Not subject to production test. 3) Device on 40 mm x 40 mm x 1.5 mm epoxy PCB FR4 with 6 cm 2 (one layer, 70 µm thick) copper area for drain connection. PCB is vertical in still air. Rev. 1.0 page 3 2009-03-24 IPB80N06S4L-05 IPI80N06S4L-05, IPP80N06S4L-05 1 Power dissipation 2 Drain current P tot = f(T C); V GS ≥ 6 V I D = f(T C); V GS ≥ 6 V; SMD 120 100 100 80 80 I D [A] P tot [W] 60 60 40 40 20 20 0 0 0 50 100 150 200 0 50 100 T C [°C] 150 200 T C [°C] 3 Safe operating area 4 Max. transient thermal impedance I D = f(V DS); T C = 25 °C; D = 0; SMD Z thJC = f(t p) parameter: t p parameter: D =t p/T 1000 101 1 µs 100 10 µs 0.5 Z thJC [K/W] 100 I D [A] 100 µs 0.1 10-1 0.05 0.01 10 10-2 1 ms single pulse 10-3 1 0.1 1 10 100 10-5 10-4 10-3 10-2 10-1 100 t p [s] V DS [V] Rev. 1.0 10-6 page 4 2009-03-24 IPB80N06S4L-05 IPI80N06S4L-05, IPP80N06S4L-05 5 Typ. output characteristics 6 Typ. drain-source on-state resistance I D = f(V DS); T j = 25 °C; SMD R DS(on) = f(I D); T j = 25 °C; SMD parameter: V GS parameter: V GS 320 15 10 V 6V 5V 4.5 V 4V 280 13 240 5V 11 R DS(on) [mΩ] I D [A] 200 4.5 V 160 4V 120 9 7 80 6V 5 40 10 V 0 3 0 1 2 3 4 5 6 0 80 160 V DS [V] 240 320 I D [A] 7 Typ. transfer characteristics 8 Typ. drain-source on-state resistance I D = f(V GS); V DS = 6V R DS(on) = f(T j); I D = 80 A; V GS = 10 V; SMD parameter: T j 8 320 -55 °C 25 °C 280 7 175 °C 240 6 R DS(on) [mΩ] I D [A] 200 160 120 5 4 80 3 40 0 0 1 2 3 4 5 6 V GS [V] Rev. 1.0 2 -60 -20 20 60 100 140 180 T j [°C] page 5 2009-03-24 IPB80N06S4L-05 IPI80N06S4L-05, IPP80N06S4L-05 9 Typ. gate threshold voltage 10 Typ. capacitances V GS(th) = f(T j); V GS = V DS C = f(V DS); V GS = 0 V; f = 1 MHz parameter: I D 104 2.5 Ciss 2 1.5 C [pF] V GS(th) [V] 600 µA 60 µA Coss 103 1 102 Crss 0.5 101 0 -60 -20 20 60 100 140 0 180 5 10 15 20 25 30 V DS [V] T j [°C] 11 Typical forward diode characteristicis 12 Avalanche characteristics IF = f(VSD) I A S= f(t AV) parameter: T j parameter: T j(start) 100 103 25 °C 100 °C 102 I F [A] I AV [A] 150 °C 175 °C 25 °C 0.6 0.8 10 1 10 100 1 0 0.2 0.4 1 1.2 1.4 V SD [V] Rev. 1.0 0.1 1 10 100 1000 t AV [µs] page 6 2009-03-24 IPB80N06S4L-05 IPI80N06S4L-05, IPP80N06S4L-05 13 Avalanche energy 14 Drain-source breakdown voltage E AS = f(T j); I D = 40 A V BR(DSS) = f(T j); I D = 1 mA 66 160 64 V BR(DSS) [V] E AS [mJ] 120 80 62 60 40 58 56 0 25 75 125 -55 175 -15 T j [°C] 25 65 105 145 T j [°C] 15 Typ. gate charge 16 Gate charge waveforms V GS = f(Q gate); I D = 80 A pulsed parameter: V DD 10 V GS 9 Qg 8 12 V 48 V 7 V GS [V] 6 5 V g s(th) 4 3 2 Q g (th) Q sw 1 Q gs 0 0 20 40 60 80 Q gate Q gd 100 Q gate [nC] Rev. 1.0 page 7 2009-03-24 IPB80N06S4L-05 IPI80N06S4L-05, IPP80N06S4L-05 Published by Infineon Technologies AG 81726 Munich, Germany © Infineon Technologies AG 2009 All Rights Reserved. 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Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. Rev. 1.0 page 8 2009-03-24 IPB80N06S4L-05 IPI80N06S4L-05, IPP80N06S4L-05 Revision History Version Date Changes Revision 1.0 Rev. 1.0 24.03.2009 Final data sheet page 9 2009-03-24