TI1 HD3SS2522 Usb type-c ss mux Datasheet

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HD3SS2522
SLLSEM6B – APRIL 2015 – REVISED AUGUST 2015
HD3SS2522 USB Type-C SS MUX with DFP Controller
1 Features
3 Description
•
•
HD3SS2522 is a 2:1 USB mux with Configuration
Channel (CC) logic with Downstream Facing Port
(DFP) support. The HD3SS2522 presents itself as a
DFP according to the USB Type-C Spec. The CC
logic block monitors the CC1 and CC2 pins voltages
to determine when a USB port has been attached.
Once a USB port has been attached, the CC logic
also determines the orientation of the cable and
configures the USB SS mux accordingly.
1
•
•
•
•
•
•
Compliant to USB Type-C Specification 1.1
Mode Configuration
– Host Only – DFP
Channel Configuration (CC)
– Attach of USB Port Detection
– Cable Orientation Detection
– Type-C Current Mode (Default, Mid, High)
Supply Voltage 3.3 V ± 10%
2:1 Mux Solution for USB 3.1 Signaling
Operates up to 10 Gbps with Wide -3 dB BW of 8
GHz
Excellent Dynamic Characteristics at 2.5 GHz
– Crosstalk = –39 dB
– Off Isolation = –22 dB
– Insertion Loss = –1.2 dB
– Input Return Loss = –12 dB
Low Active (2 mW) and Standby Power (50 μW)
Consumption
The HD3SS2522 provides an VBUS_EN signal to
control legacy power switch to provide 5 V to VBUS.
The device also provides control signals needed to
support 5 V VCONN sourcing for ecosystems
implementing USB Type-C.
Excellent dynamic characteristics of the device allow
high speed switching with minimum attenuation to the
signal eye diagram and little added jitter. The device
also has low current consumption in Standby mode.
Device Information(1)
PART NUMBER
HD3SS2522
2 Applications
•
•
•
PACKAGE
WQFN (56)
BODY SIZE (NOM)
11.00 mm x 5.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Desktop and Notebook PCs
USB Type-C DFP Applications
Motherboards
Simplified Schematic
5V
VBUS
VCONN
VBUS_EN
VCTL1
CC1
DFP
CC Controller
CC2
CRX1
USB TypeC Port
VCC
VCTL2
CTX1
USB SS MUX
CRX2
CTX2
USB
Host
USB SS Signals
HD3SS2522
USB 2.0 Signals
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
HD3SS2522
SLLSEM6B – APRIL 2015 – REVISED AUGUST 2015
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Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
5
6.1
6.2
6.3
6.4
6.5
6.6
6.7
5
5
5
5
6
7
9
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Timing Requirements ................................................
Switching Characteristics ..........................................
Detailed Description ............................................ 10
7.1 Overview ................................................................. 10
7.2 Functional Block Diagram ....................................... 10
7.3 Feature Description................................................. 11
7.4 Device Functional Modes........................................ 11
8
Application and Implementation ........................ 12
8.1 Application Information............................................ 12
8.2 USB Type-C DFP Typical Application..................... 12
9 Power Supply Recommendations...................... 15
10 Layout................................................................... 15
10.1 Layout Guidelines ................................................. 15
10.2 Layout Example .................................................... 16
11 Device and Documentation Support ................. 17
11.1
11.2
11.3
11.4
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
17
17
17
17
12 Mechanical, Packaging, and Orderable
Information ........................................................... 17
4 Revision History
Changes from Revision A (July 2015) to Revision B
•
Page
Changed Features From: Compliant to USB Type-C Specification 1.0 To: Compliant to USB Type-C Specification 1.1..... 1
Changes from Original (April 2015) to Revision A
Page
•
Changed the Description of VBUS_EN in the Pin Functions table. ...................................................................................... 4
•
Changed the Description of VCTRL1 and VCTRL2 in the Pin Functions table. ................................................................... 4
2
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5 Pin Configuration and Functions
VCC
VCC
NC
NC
NC
NC
50
49
GND
GND
53
NC
NC
NC
NC
54
51
NC
NC
55
52
NC
NC
56
RHU Package
Top View
NC
NC
1
48
B0p
B0p
A0p
A0p
2
47
B0n
B0n
A0n
A0n
3
46
B1p
B1p
VCC
VCC
4
45
B1n
B1n
A1p
A1p
5
44
C0p
C0p
A1n
A1n
6
43
C0n
C0n
SS_SEL_IN
SS_SEL_IN
7
42
C1p
C1p
SS_Oen_IN
SS_Oen_IN
8
41
C1n
C1n
CC_Oen_IN
CC_Oen_IN
9
40
VCC
VCC
RSVD
RSVD
10
39
GND
GND
CC_OUT
CC_OUT
11
38
RSVD
RSVD
CC_SEL_IN
CC_SEL_IN
12
37
CC1
CC1
VCC
VCC
13
36
RSVD
RSVD
VCC
VCC
14
35
CC2
CC2
MODE_LED
MODE_LED
Thermal PAD
GPIO2
GPIO2
GPIO1
GPIO1
29
28
20
27
SS_SEL_OUT
SS_SEL_OUT
IMODE2
IMODE2
RST
RST
26
30
25
19
IMODE1
IMODE1
CC_SEL_OUT
CC_SEL_OUT
RSVD
RSVD
RSVD
RSVD
24
CC_OEn_OUT/VconnEnPol
CC_OEn_OUT/VconnEnPol
31
NC
NC
32
18
VCTRL2
VCTRL2
17
CC_IN
CC_IN
23
VCONN_FAULT#
VCONN_FAULT#
22
GND
GND
21
SS_OEn_OUT/VBUSEnPol
SS_OEn_OUT/VBUSEnPol
33
VCTRL1
VCTRL1
34
16
VBUS_EN
VBUS_EN
15
VBUS_FAULT#
VBUS_FAULT#
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
A0p
2
I/O
Port A0, High Speed Positive Signal
A0n
3
I/O
Port A0, High Speed Negative Signal
A1p
5
I/O
Port A1, High Speed Positive Signal
A1n
6
I/O
Port A1, High Speed Negative Signal
B0p
48
I/O
Port B0, High Speed Positive Signal
B0n
47
I/O
Port B0, High Speed Negative Signal
B1p
46
I/O
Port B1, High Speed Positive Signal
B1n
45
I/O
Port B1, High Speed Negative Signal
C0p
44
I/O
Port C0, High Speed Positive Signal
C0n
43
I/O
Port C0, High Speed Negative Signal
C1p
42
I/O
Port C1, High Speed Positive Signal
C1n
41
I/O
Port C1, High Speed Negative Signal
CC_IN
18
I/O
Selected CC signal back to the device as input - connect to CC_OUT pin
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Pin Functions (continued)
PIN
NAME
NO.
I/O
DESCRIPTION
CC_OUT
11
I/O
CC_SEL_IN
12
I
Selected CC signal as output - connect to CC_IN pin
CC Signal select pin input – Connect to CC_SEL_OUT
CC_SEL_OUT
19
O
CC Signal select pin output – Connect to CC_SEL_IN
CC_OEn_IN
9
I
Active Low CC MUX Enable input – connect to CC_OEn_OUT
CC_OEn_OUT /
VconnEnPol
32
I/O
Active Low CC MUX Enable output – connect to CC_OEn. The pin is also sampled
upon reset to set the polarity of the VCTRL1 and VCTRL2.
0 = VCTRL1/2 polarity is active high.
1 = VCTRL1/2 polarity is active low.
CC1
37
I/O
USB Type-C configuration channel for position 1
CC2
35
I/O
USB Type-C configuration channel for position 2
GND
33 , 39, 53
G
Ground
GPIO1
28
I/O
GPIO or SCL for FW update
GPIO2
29
I/O
GPIO or SDA for FW update
IMODE1
IMODE2
MODE_LED
26
27
15
RST
O
Low
Current Mode
Default
Low
High
Mid (1.5 A)
High
Low
Reserved
High
High
High (3A)
High when UFP attach detected
Not connected
30
I
10, 25, 31, 36, 38
I/O
SS_OEn_IN
8
I
SS_OEn_OUT /
VBUSEnPol
34
I/O
RSVD
IMODE2
Low
I
1, 24, 49, 50, 51,
54, 55, 56
NC
IMODE1
CC Controller Reset
Reserved
Active Low SS MUX Enable input – connect to SS_OEn_OUT
Active Low SS MUX Enable output – connect to SS_OEn_IN. The pin is also sampled
upon reset to set the polarity of the VBUS_EN.
0 = VBUS_EN polarity is active high.
1 = VBUS_EN polarity is active low.
SS_SEL_IN
7
I
SS Port select pin input – Connect to SS_SEL_OUT
SS_SEL_OUT
20
O
SS Port select pin output – Connect to SS_SEL_IN
VBUS_EN
21
O
Polarity programmable via VBUSEnPol pin (pin 34). Driven low or high when UFP
attach is detected.
VBUS_FAULT#
16
I
VBUS Fault signal in from VBUS Power switch. Active low.
4 , 13, 14, 40, 52
P
3.3V Power
VCONN_FAULT#
17
I
VCONN Fault signal in from VCONN switches. Active low.
VCTRL1
22
O
Polarity programmable via VconnEnPol pin (pin 32). Driven low or high when active
cable is detected.
VCTRL2
23
O
Polarity programmable via VconnEnPol pin (pin 32). Driven low or high when active
cable is detected.
VCC
4
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
Power supply voltage range, VCC
Voltage Range
(1)
MIN
MAX
–0.4
4
UNIT
Differential I/O (High bandwidth signal path, AxP/N, BxP/N, CxP/N)
–0.4
2.4
Control Pins and Single Ended I/Os including CC1 and CC2
–0.4
VCC + 0.4
V
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
3
3.3
3.6
V
2
VCC
V
–0.1
0.8
V
0
1.6
VPP
Switch I/O common mode voltage
0
2
V
Input / output voltage
CC_OUT, CC_IN, and selected CC pin for
configuration
0
VCC
V
VIN
Input voltage
Selected CC pin for VCONN
0
5.5
V
TA
Operating free-air temperature
HD3SS2522RHU
0
70
°C
VCC
Supply voltage
VIH
Input high voltage
Control/Status pins
VIL
Input low voltage
Control/Status pins
VI/O(Diff)
Differential voltage
Switch I/O diff voltage
VI/O(CM)
Common voltage
VI/O
UNIT
6.4 Thermal Information
HD3SS2521A
THERMAL METRIC
(1)
RHU
UNIT
56 PINS
RθJA
Junction-to-ambient thermal resistance
31.6
RθJC(top)
Junction-to-case (top) thermal resistance
15.9
RθJB
Junction-to-board thermal resistance
8.5
ψJT
Junction-to-top characterization parameter
0.5
ψJB
Junction-to-board characterization parameter
8.5
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
(1)
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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6.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
1
ICC
Supply current
VCC = 3.6 V,
SS_OEn, CC_OEn = GND
0.6
I(STANDBY)
Standby current
VCC = 3.3 V, SS_OEN, CC_OEn =
VCC
15
UNIT
mA
µA
VBUS_FAULT#, VCONN_FAULT#, IMODE1, IMODE2, RST, RSVD, GPIO1, GPIO2
VIT+
Positive-going input threshold
voltage
0.45 x VCC
0.75 x VCC
V
VIT-
Negative-going input threshold
voltage
0.25 x VCC
0.55 x VCC
V
Vhys
nput voltage hysteresis (VIT+ – VIT–)
VCC = 3 V
0.3
1
V
RPULL
Pullup/pulldown resistor
Pullup: VIN = GND,
Pulldown: VIN = VCC, VCC = 3 V
20
50
kΩ
CI
Input capacitance
VIN = GND or VCC
High-impedance leakage current
VIN = GND or VCC, VCC = 3 V,
Pullup/Pulldown disabled
ILGK
35
5
pF
±50
nA
VCTRL1, VCTRL2, VBUS_EN
VOL
(1)
Low-level output voltage
IOL(max) = 6 mA
High-level output voltage
IOH(max) = –6 mA
GND + 0.3
V
VCC – 0.3
V
GND + 0.3
V
MODE_LED
VOH
VOL
Low-level output voltage
IOL(max) = 6 mA
(1)
(1)
AxP/N, BxP/N, CxP/N
ILGK
High-impedance leakage current
VCC = 3.6 V, VIN = 0 V, VOUT = 2 V
(ILKG on open outputs Port B and C)
130
µA
VCC = 3.6 V, VIN = 0 V, VOUT = 2 V
(ILKG on open outputs Port A)
4
µA
VCC = 3.6 V, VIN = 0 V,
VOUT = 0 V to 4 V
1
µA
CC1, CC2
ILGK
(1)
6
High-impedance leakage current
The maximum total current, IOH(max) and IOL(max), for all outputs combined should not exceed ±48 mA to hold the maximum voltage drop
specified.
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6.6 Timing Requirements
MIN
NOM
MAX
UNIT
85
ps
70
250
ns
70
250
ns
AxP/N, BxP/N, CxP/N HIGH-BANDWIDTH SIGNAL PATH
tPD
Switch Propagation Delay
tON
SS_SEL_IN -to-Switch tON
tOFF
SS_SEL_IN -to-Switch tOFF
RSC and RL = 50 Ω
RSC and RL = 50 Ω
50%
HS_SEL_IN/SS_SEL_IN90%
90%
10%
VOUT
tON
tOFF
Figure 1. Select to Switch tON and tOFF
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VCC
50 O
HD3SS2522
Ax(p)
Bx/Cx(p)
50 O
50 O
Ax(n)
Bx/Cx(n)
50 O
Bx/Cx(p)
Ax(p)
Bx/Cx(n)
Ax(n)
SEL
Cx/Bx (p)
50%
50%
Cx/Bx (n)
Ax (p)
50%
50%
Ax (n)
tP1
tP2
Inter-pair skew
tPD = Max(tp1, tp2)
tSK(O) = Difference between tPD for any two pairs of outputs
t1
t3
t2
t4
DCx/DBx/DAx (p)
50%
Cx/Bx/Ax (n)
Cx/Bx/Ax (p)
tSK(O)
Cx/Bx/Ax (n)
Intra-pair skew
tSK(b-b) = 0.5 X |(t4 t t3) + (t1 t t2)|
(1)
Measurements based on an ideal input with zero intra-pair skew on the input, i.e. the input at A to B/C or the input at
B/C to A
(2)
Inter-pair skew is measured from lane to lane on the same channel, e.g. C0 to C1
(3)
Intra-pair skew is defined as the relative difference from the p and n signals of a single lane
Figure 2. Propagation Delay and Skew
8
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6.7 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
AxP/N, BxP/N, CxP/N
tSK(O)
Inter-pair output skew
(channel-channel)
tSK(b-b)
Inter-pair output skew (bit-bit)
CON
Outputs ON capacitance
VIN = 0 V, outputs open, switch ON
1.5
pF
COFF
Outputs OFF capacitance
VIN = 0 V, outputs open, switch OFF
1
pF
Output ON resistance
VCC = 3.3 V, VCM = 0.5 V – 1.5 V,
IO = –8 mA
5
RON
ΔRON
On resistance match between
channels
On resistance match between pairs
of the same channel
R(FLAT_ON)
On resistance flatness
[RON(MAX) – RON(MIN)]
RL
Differential input return loss
(VCM = 0 V)
XTALK
Differential crosstalk (VCM = 0 V)
OIRR
Differential off-isolation (VCM = 0 V)
IL
BW
RSC and RL = 50 Ω
20
ps
8
ps
Ω
8
2
VCC = 3.3 V; –0.35 V ≤ VIN ≤ 1.2 V;
IO = –8 mA
Ω
0.7
VCC = 3.3 V; –0.35 V ≤ VIN ≤ 1.2 V
Ω
1.15
f = 2.5 GHz
–12
f = 4 GHz
–11
f = 2.5 GHz
–39
f = 4 GHz
–35
f = 2.5 GHz
–22
f = 4 GHz
–19
Differential insertion loss
(VCM = 0 V)
f = 2.5 GHz
–1.1
f = 4 GHz
–1.5
Bandwidth
At 3 dB
6
dB
dB
dB
dB
GHz
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7 Detailed Description
7.1 Overview
HD3SS2522 is a 10-Gbps USB mux with Configuration Channel (CC) logic with DFP support. The HD3SS2522
presents itself as a DFP according to the USB Type-C Spec. The CC logic block monitors the CC1 and CC2 pin
voltages to determine when a USB port has been attached. Once a USB port has been attached, the CC logic
also determines the orientation of the cable and configures the USB SS mux accordingly.
The device provides an VBUS_EN signal to control legacy power switch to provide 5 V to VBUS. The device also
provides IOs needed to support 5 V VCONN sourcing for ecosystems implementing USB Type-C.
Excellent dynamic characteristics of the device allow high speed switching with minimum attenuation to the
signal eye diagram and little added jitter. The device also has low current consumption in Standby mode.
7.2 Functional Block Diagram
5V
VBUS
VCTL1
VCONN_
FAULT
VCTL2
VBUS_FAULT
VBUS_EN
VCONN
CC1
CC2
SS_OEn_OUT
DFP
CC
Controller
SS_OEn_IN
CC_OUT
CC_IN
USB TypeC Port
CC_OEn_OUT
CC_OEn_IN
CC_SEL_OUT
SS_SEL_OUT
CC_SEL_IN
SS_SEL_IN
MODE_LED
CRX1
VCC
CTX1
USB SS
MUX
USB
Host
USB SS Signals
CRX2
CTX2
HD3SS2522
USB 2.0 Signals
10
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7.3 Feature Description
7.3.1 Adaptive Common Mode Tracking for USB 3.1 MUX
The device provides an integrated USB 3.1 2:1 passive MUX. The MUX provides adaptive common mode
tracking allowing RX and TX channels to have different common mode voltage. This feature allows simpler
system implementation.
7.3.2 DFP-to-UFP Attach/Detach Detection
The HD3SS2522 monitors the CC lines as a Type-C DFP port. When the device senses that one of the CC has
a resistance to GND, it detects that an UFP is attached. The device provides an emulated ID signal (VBUS_EN)
in the event of a UFP attach.
The device also monitors specified pull down resistor according to Type-C specifications to determine if an active
cable is attached. In the event of active cable detection, HD3SS2522 provides necessary control signals for
VCONN switches that provide 5-V VCONN power to appropriate CC pin.
7.3.3 Plug Orientation/Cable Twist Detection
According to USB Type-C specifications plug can be inserted into a receptacle in either one of two orientations.
HD3SS2522 monitors for a pull-down resistors from an attached UFP port determining the MUX orientation.
7.3.4 VBUS Fault
HD3SS2522 does not take any action in case of a VBUS fault. VBUS fault needs to be handled by legacy power
management implementations.
7.3.5 VCONN Fault
If a VCONN fault is determined by the external power switch and fed into the device through VCONN_FAULT
pin, HD3SS2522 will latch it off until the cable is unplugged if there is a fault that does not clear within 5 ms.
Which is a sufficient amount of time to charge the 10-µF inrush capacitance.
7.4 Device Functional Modes
7.4.1 Unattached.DFP State
In this state, the HD3SS2522 as a DFP port is waiting to detect the presence of a UFP. The device injects pullup currents to both of the CC lines.
7.4.2 Attached.DFP State
When HD3SS2522 is in the Attached.DFP state, the port is attached and operating as a DFP. The device
continues to monitor the CC pins to make sure the appropriate pin is within vRd range specified by Type-C
specification. The device source current on one of the this CC pins and monitor its voltage. The port advertises
one of the three levels of VBUS power capability as specified in Type-C spec according to GPIO pins IMODE1
and IMODE2.
The device controls the VCONN power switches to apply VCONN to the unused CC pin if the voltage on the
unused CC pin is within the vRa range as specified in Type-C specification.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The HD3SS2522 is a high speed switch with integrated DFP CC controller. The HD3SS2522 can be
implemented in any USB Type-C DFP applications in conjunction with VBUS and VCONN switches.
8.2 USB Type-C DFP Typical Application
This section depicts the typical Type-C system with a USB Host or Hub. The Type C receptacle in this system is
a DFP only providing VBUS and VCONN upon the connection of UFP device. The HD3SS2522 DFP CC
controller determines the UFP attachment and provides VBUS and VCONN based upon the Type-C specification
state diagram and timing definition.
VBUS Switch
VBUS
5V
Vconn Switch
5V
Vconn Switch
CC1
CC2
CC_OUT
CC Switch
CC Pull-up Resistor value
per Type C Specification
Current Advertisement
definition
CC_SEL
CC_IN
VCTRL2
VCTRL1
VBUS_EN
USB Host /
Hub
Type C
Receptacle
Digital Logic
SS_EN
SS_SEL
TX1
RX1
TX
RX
2:1 High
Speed switch
TX2
RX2
HD3SS2522
D+
D-
This Figure represents high level block diagram of the Type C DFP implementation not a circuit level implementation.
Figure 3. USB Type-C DFP
12
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USB Type-C DFP Typical Application (continued)
8.2.1 Design Requirements
For this design example, use the parameters shown in Table 1.
Table 1. Design Parameters
PARAMETER
VALUE
VCC
3.3 V
AxP/N, BxP/N, CxP/N VCM Voltage
0V–2V
CC_IN, CC_OUT, CC1, CC2
0 V –3.3 V
Control Pin Vmax for Low
0.8 V
Control Pin Vmax for High
2V
8.2.2 Detailed Design Procedure
8.2.2.1 USB Type-C Current Advertising
HD3SS2522 can be used to advertise USB Type-C current in conjunction with pull up resistors to CC1 and CC2
pins. These pull up resistors must meet the Type C spec requirements. The IMODE1 and IMODE2 setting must
match the CC resistor configuration for the current mode: default, mid or high.
8.2.2.2 VCONN and VBUS Power Switch Control
VCTRL1# and VCTRL2# are outputs from the HD3SS2522 CC controller to enable or disable the VCONN switch
based upon the orientation detection, audio accessory termination Ra detection, and/or fault condition.
VBUS_EN is an output from the HD3SS2522 CC controller to enable VBUS switch. Upon detection of UFP
attachment, the VBUS_EN is asserted to enable VBUS switch.
8.2.2.3 Firmware Upgradability
If necessary, the CC controller firmware (FW) can be updated via GPIO1, GPIO2 and SYS_COM_REQ. Contact
Texas Instruments for further assistance with upgrading the FW.
8.2.3 USB Type-C DFP Circuit Schematics with a Type C Receptacle
The schematics below depicts the circuit level implementation of the Type C system with HD3SS2522 and a DFP
only Type C connector. The system should select a power switch that complies with the Type C specification and
application requirements. The power switch can be controlled by the HD3SS2522. See the Detailed Design
Procedure section of the datasheet for design details.
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3P3V_VCC
Place near the part
C1
0.1uF
C2
0.1uF
C3
0.1uF
10V
C4
C5
0.1uF
0.1uF
10V
4
13
14
40
52
3P3V_VCC
VCC
VCC
VCC
VCC
VCC
U1
2
3
USB3_RX0N
USB3_RX0P
5
6
B0P
B0N
A0P
A0N
C0P
C0N
B1P
B1N
A1P
A1N
C1P
C1N
SS_SEL
SS_SEL_IN
SS_SEL_OUT
11
3P3V
18
R6
19
D3
100K
3.3K
GPIO1
GPIO2
SYS_COM_REQ
A2
B11
SSRXP1
SSRXP2
A3
B10
SSRXN1
SSRXN2
VBUS
A4
B9
VBUS
CC1
A5
B8
SBU2
DP1
A6
B7
VBUS1
VBUS2
VBUS3
VBUS4
CC1
CC2
SBU1
SBU2
DN1
DP1
DP2
DN2
SSTXP1
SSTXN1
DN2
DN1
A7
B6
DP2
SBU1
A8
B5
CC2
VBUS
A9
B4
VBUS
SSRXN2
SSRXN1
A10
B3
SSTXN2
SSTXN1
SSRXP2
SSRXP1
A11
B2
SSTXP2
SSTXP1
GND
A12
B1
GND
15
28
29
25
MODE_LED
GPIO1
GPIO2
SYS_COM_REQ
VBUS_EN
VCTRL1#
VCTRL2#
RST
44
43
CTX1N
CTX1P
46
45
CRX2P
CRX2N
42
41
CRX1P
CRX1N
7
Connect to
Type C USB3
TX/RX pins
3P3V
SS_SEL
20
35
CC2
37
CC1
9
8
CC_OE#
SS_OE#
32
34
26
27
IMODE1
IMODE2
21
ID
22
23
17
16
VCTRL1#
VCTRL2#
VCONN_FAULT#
VBUS_FAULT#
Connect to
Type C CC pins 3P3V
and VCONN
switch
R8
R7
R13
R14
100K
100K
NC, 100K
NC, 100K
Configured for
Active Low
Vconn_EN and
VBUS_EN
Pull-up or pull-down
resistor based upon
current configuration
Connect to VBUS
switch control signal
Connect to VCONN
switch control signal
Connect to Vconn/VBUS switch
for fault condition detection
57
10
36
38
31
NC7
NC8
NC9
RSVD
PAD
NC
NC0
NC1
NC2
NC3
NC4
NC5
NC6
30
CTX2P
CTX2N
HD3SS2522
J3
GND
SSTXN1
SSTXN2
CC_SEL_OUT
33
39
53
VBUS
SSTXP1
SSTXP2
CC_OE#_OUT/VConnEnPol
SS_OE#_OUT/VBUSEnPol
1
24
49
50
51
54
55
56
RST
TypeC Connector Pin Mapping
B12
CC_OE#_IN
SS_OE#_IN
CC_SEL_IN
VCONN_FAULT#
VBUS_FAULT#
Resets CC Control
logic
A1
CC_IN
IMODE1
IMODE2
MODE_LED
R10
100K
GND
CC1
GND
GND
GND
R11
Add headers
for field
upgradability
12
3P3V
Optional LED
for debug
purposes
LED
R9
Green
660R
3.3K
R12
3P3V
CC2
CC_OUT
48
47
R3
USB3_TX0N
USB3_TX0P
NC, 100K
Connect to
USB3 Host
SSRXP2
SSRXN2
8
7
6
5
4
3
2
1
SSTXP2
SSTXN2
Shield8
Shield7 SSRXP1
Shield6 SSRXN1
Shield5
Shield4
GND0
Shield3
GND1
Shield2
GND2
Shield1
GND3
A4
A9
B4
B9
A5
B5
A8
B8
A7
A6
C8
10uF
CC1
CC2
CSBU1
CSBU2
USB2_N0
USB2_P0
B6
B7
A2
A3
CTX1P
CTX1N
A11
A10
CRX2P
CRX2N
B2
B3
CTX2N
CTX2P
B11
B10
CRX1P
CRX1N
A1
A12
B1
B12
USB_TypeC_Receptacle_
Figure 4. Example Schematics With a Type-C Receptacle
14
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9 Power Supply Recommendations
The HD3SS2522 does not have any special requirement for power supply as long as it is within the
recommended range. The device also does not have any special reset requirement.
10 Layout
10.1 Layout Guidelines
10.1.1 Critical Routes
The high speed differential signals must be routed with great care to minimize signal quality degradation between
the connector and the source or sink of the high speed signals by following the guidelines provided in this
document. Depending on the configuration schemes, the speed of each differential pair can reach a maximum
speed of 10 Gbps. These signals are to be routed first before other signals with highest priority.
• Each differential pair should be routed together with controlled differential impedance of 85 to 90-Ω and 50-Ω
common mode impedance. Keep away from other high speed signals. The number of vias should be kept to
minimum. Each pair should be separated from adjacent pairs by at least 3 times the signal trace width. Route
all differential pairs on the same group of layers (Outer layers or inner layers) if not on the same layer. No 90
degree turns on any of the differential pairs. If bends are used on high speed differential pairs, the angle of
the bend should be greater than 135 degrees.
• Length matching:
– Keep high speed differential pairs lengths within 5 mil of each other to keep the intra-pair skew minimum.
The inter-pair matching of the differential pairs is not as critical as intra-pair matching. The SSTX and
SSRX pairs do not have to match while they need to be routed as short as possible.
• Keep high speed differential pair traces adjacent to ground plane.
• Do not route differential pairs over any plane split.
• ESD components on the high speed differential lanes should be placed nearest to the connector in a pass
through manner without stubs on the differential path.
• For ease of routing, the P and N connection of the USB3.1 differential pairs to the HD3SS2522 pins can be
swapped.
10.1.2 General Routing/Placement Rules
• Route all high-speed signals first on un-routed PCB. The stub on USB2 D+ and D- pairs should not exceed
3.5 mm.
• Follow 20H rule (H is the distance to ref-plane) for separation of the high speed trace from the edge of the
plane
• Minimize parallelism of high speed clocks and other periodic signal traces to high speed lines
• All differential pairs should be routed on the top or bottom layer (microstrip traces) if possible or on the same
group of layers. Vias should only be used in the breakout region of the device to route from the top to bottom
layer when necessary. Avoid using vias in the main region of the board at all cost. Use a ground reference via
next to signal via. Distance between ground reference via and signal need to be calculated to have similar
impedance as traces.
• All differential signals should not be routed over plane split. Changing signal layers is preferable to crossing
plane splits.
• Use of and proper placement of stitching caps when split plane crossing is unavoidable to account for highfrequency return current path
• Route differential traces over a continuous plane with no interruptions.
• Do not route differential traces under power connectors or other interface connectors, crystals, oscillators, or
any magnetic source.
• Route traces away from etching areas like pads, vias, and other signal traces. Try to maintain a 20 mil keepout distance where possible.
• Decoupling caps should be placed next to each power terminal on the HD3SS2522. Care should be taken to
minimize the stub length of the trace connecting the capacitor to the power pin.
• Avoid sharing vias between multiple decoupling caps.
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Layout Guidelines (continued)
•
•
•
Place vias as close as possible to the decoupling cap solder pad.
Widen VCC/GND planes to reduce effect of static and dynamic IR drop.
The VBUS traces/planes must be wide enough to carry max current for the application.
10.2 Layout Example
B0p
A0p
B0n
A0n
B1p
To USB
Host/Hub
B1n
A1p
C0p
A1n
C0n
To TypeC
Connector
C1p
C1n
Thermal PAD
Figure 5. Layout
16
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11 Device and Documentation Support
11.1 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.2 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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17-Aug-2015
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
HD3SS2522RHU
PREVIEW
WQFN
RHU
56
250
TBD
Call TI
Call TI
0 to 70
HD3SS2522RHUR
ACTIVE
WQFN
RHU
56
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
0 to 70
HD3S2522
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
17-Aug-2015
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Aug-2015
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
HD3SS2522RHUR
Package Package Pins
Type Drawing
WQFN
RHU
56
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2000
330.0
24.4
Pack Materials-Page 1
5.3
B0
(mm)
K0
(mm)
P1
(mm)
11.3
1.0
8.0
W
Pin1
(mm) Quadrant
24.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Aug-2015
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
HD3SS2522RHUR
WQFN
RHU
56
2000
367.0
367.0
45.0
Pack Materials-Page 2
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