Maxim MAX3761C/D Low-power, 622mbps limiting amplifiers with chatter-free power detect for lan Datasheet

19-1097; Rev 3; 7/04
KIT
ATION
EVALU
E
L
B
A
IL
AVA
Low-Power, 622Mbps Limiting Amplifiers
with Chatter-Free Power Detect for LANs
____________________________Features
The MAX3761/MAX3762 limiting amplifiers, with 4mV
sensitivity and PECL data outputs, are optimized for
operation in low-cost, 622Mbps, LAN/ATM LAN fiber
optics applications.
An integrated power detector senses the input signal’s
amplitude. A received-signal-strength indicator (RSSI)
gives an analog indication of the power level, while the
complementary loss-of-signal (LOS) outputs indicate if
the input power level exceeds the programmed
threshold level. The LOS threshold can be adjusted to
detect signal amplitudes between 3mVp-p and
100mVp-p, providing a 15dB LOS adjustment in fiber
optic receivers. The LOS outputs have 3.5dB of
hysteresis, which prevents chatter when input signal
levels are small. The MAX3761’s LOS outputs are compatible with TTL-logic levels. The MAX3762 has PECL
LOS outputs.
DISABLE and LOS can be used to implement a squelch
function, which turns off the data outputs when the
input signal is below the programmed threshold.
♦ Chatter-Free Power Detector with Programmable
Loss-of-Signal Outputs
________________________Applications
622Mbps LAN/ATM LAN Receivers
♦ 4mV Input Sensitivity (PECL Loss-of-Signal
Interface Logic—MAX3766
♦ PECL Data Outputs
♦ Single 5V Power Supply
♦ 250ps Output Edge Speed
♦ Low 15ps Pulse-Width Distortion
♦ TTL Loss-of-Signal Interface Logic—MAX3761
Ordering Information
TEMP RANGE
PIN-PACKAGE
MAX3761EEP
PART
-40°C to +85°C
20 QSOP
MAX3761C/D
MAX3762EEP
MAX3762EEP+
MAX3762C/D
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
Dice*
20 QSOP
20 QSOP
Dice*
*Dice are designed to operate from -40°C to +85°C, but are
tested and guaranteed only at TA = +25°C.
+Denotes lead free package.
155Mbps LAN/ATM LAN Receivers
__________________Pin Configuration
TOP VIEW
_________Typical Operating Circuits
+5V
FILTER 1
20 DISABLE
RSSI 2
19 LOS+
EN 3
18 LOS-
VCC 4
17 VCC
VIN+ 5
VIN- 6
CZN
MAX3761
MAX3762
16 VCCO
10nF
14 OUT-
SUB 8
13 GNDO
CZP 9
12 VTH
CZN 10
11 INV
QSOP
LOS+
VCCO
LOS-
CIN
5.6nF
OUTVIN+
CIN
5.6nF
15 OUT+
GND 7
DISABLE
RSSI
100pF
BYPASS
SUPPLY
VIN-
OUT+
MAX3761
CFILTER
50Ω
50Ω
GNDO
FILTER
100pF
CAZ
150pF
CZP
VCC
EN
GND
INV
VTH
VCC - 2V
SUB
+VCC
R1
100kΩ
R2
22kΩ
MAX3762 at end of data sheet.
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1
MAX3761/MAX3762
_______________General Description
MAX3761/MAX3762
Low-Power, 622Mbps Limiting Amplifiers
with Chatter-Free Power Detect for LANs
ABSOLUTE MAXIMUM RATINGS
VCC, VCCO............................................................-0.5V to +7.0V
FILTER, RSSI, EN, VIN+, VIN-, CZP, CZN,
DISABLE, LOS+, LOS-, INV, VTH...............-0.5V to (VCC + 0.5V)
PECL Output Current (OUT+, OUT-, LOS+, LOS-) ............50mA
Continuous Power Dissipation (TA = +85°C)
QSOP (derate 9.1mW/°C above +85°C) .......................591mW
Operating Junction Temperature Range ...........-40°C to +150°C
Processing Temperature (die) .........................................+400°C
Storage Temperature Range .............................-65°C to +160°C
Lead Temperature (soldering, 10sec) .............................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(VCC = +4.5V to +5.5V, DISABLE = low, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VCC = +5.0V, TA = +25°C.)
(Note 1)
PARAMETER
Power-Supply Current
LOS Output TTL High
CONDITIONS
TYP
MAX
MAX3761, IVCC
25
37
MAX3762, IVCC
30
46
MAX3761
MIN
2.8
UNITS
mA
V
(TA = +25°C to +85°C)
0.40
(TA = -40°C to +25°C)
0.44
LOS Output TTL Low
MAX3761
LOS Output PECL High
MAX3762 (Notes 2, 3)
-1150
-880
mV
LOS Output PECL Low
MAX3762 (Notes 2, 3)
-1830
-1555
mV
DISABLE Input Current
Logic high
100
µA
DISABLE Input High
MAX3761
DISABLE Input Low
MAX3761
DISABLE Input PECL High
MAX3762 (Note 3)
DISABLE Input PECL Low
MAX3762 (Note 3)
PECL Data Output Voltage High (VOH)
(Notes 2, 3)
PECL Data Output Voltage Low (VOL)
Disabled Differential Output
Disabled Common-Mode Output
2.65
V
0.8
-1160
V
mV
-1470
mV
-1150
-880
mV
(Notes 2, 3)
-1830
-1555
mV
DISABLE = high
-100
100
mV
DISABLE = high
VCC - 0.7
Note 1: Dice are tested at TA = +25°C.
Note 2: Outputs terminated with 50Ω to VCC - 2V.
Note 3: Voltage measurements are relative to VCC.
2
V
_______________________________________________________________________________________
VCC -1.2
V
Low-Power, 622Mbps Limiting Amplifiers
with Chatter-Free Power Detect for LANs
(VCC = +4.5V to +5.5V, PECL outputs terminated with 50Ω to VCC - 2V, input 4mV to 2Vp-p, TA = -40°C to +85°C, unless otherwise
noted. Typical values are at VCC = +5.0V, TA = +25°C.) (Note 5)
PARAMETER
MAX
UNITS
Minimum LOS Assert Input
TA = -40°C, 223 - 1 PRBS
CONDITIONS
MIN
TYP
3.2
mV
Data-Output Edge Speed
20% to 80%
250
ps
Data-Output Overshoot
(Note 6)
20
%
Pulse-Width Distortion
(Notes 6, 7)
15
80
ps
Input Resistance
Differential
3900
Ω
LOS Hysteresis
223 - 1 PRBS, VTH = 1.8V
3.5
dB
Note 5: AC parameters are guaranteed by design and characterization.
Note 6: Input signal is a 1-0 pattern, 622Mbps.
Note 7: PWD = [(width of wider pulse) - (width of narrower pulse)] / 2.
__________________________________________Typical Operating Characteristics
(MAX3761/MAX3762 EV kit, VCC = +5.0V, PECL outputs terminated with 50Ω to VCC - 2V, input is a 1-0 pattern, 622Mbps, TA = +25°C,
unless otherwise noted.)
RSSI VOLTAGE (V)
CURRENT (mA)
40
2.16
35
30
25
VCC = 5.0V
20
2.28
1.92
1.80
1-0 PATTERN
1.56
2.04
1.92
1.80
1.68
1.56
1.44
1.44
15
1.32
1.32
10
1.20
VCC = 4.5V
-40
-15
10
35
60
AMBIENT TEMPERATURE (°C)
85
10MHz
2.16
2.04
1.68
2.40
RSSI VOLTAGE (V)
VCC = 5.5V
223 - 1
PRBS PATTERN
2.28
MAX3761/62-02
45
2.40
MAX3761/62-01
50
RSSI vs.
INPUT POWER AND FREQUENCY
RSSI vs. INPUT AMPLITUDE
AND DATA PATTERN
MAX3761/62-03
MAX3762
SUPPLY CURRENT vs. TEMPERATURE
500MHz
1.20
1
10
100
INPUT SIGNAL (mVp-p)
1000
-50 -45 -40 -35 -30 -25 -20 -15 -10 -5
0
INPUT POWER (dBm)
_______________________________________________________________________________________
3
MAX3761/MAX3762
AC ELECTRICAL CHARACTERISTICS
____________________________Typical Operating Characteristics (continued)
(MAX3761/MAX3762 EV kit, VCC = +5.0V, PECL outputs terminated with 50Ω to VCC - 2V, input is a 1-0 pattern, 622Mbps, TA = +25°C,
unless otherwise noted.)
LOS HYSTERESIS vs. TEMPERATURE
(622Mbps 223 - 1 PRBS PATTERN)
VIN = 16mVp-p
1.60
1.52
1.44
3.50
3.25
3.00
VIN = 4mVp-p
1.36
2.75
1.28
-20
0
20
40
60
20
40
60
80
100
-40
-20
0
20
40
60
80
AMBIENT TEMPERATURE (°C)
DATA OUTPUT LEVELS
(REFERENCE TO VCC)
DIFFERENTIAL OUTPUT
vs. INPUT AMPLITUDE
PULSE-WIDTH DISTORTION
(622Mbps DATA RATE)
-1.4
-1.6
VOL
1160
1040
920
800
680
560
440
20
40
60
0.1m
80
AMBIENT TEMPERATURE (°C)
LOS OPERATION
WITH SQUELCHING
LOS+
5µs/div
1m
0.01
0.1
1
INPUT SIGNAL (Vp-p)
OUT+
100mV/
div
DATA IN
MAX3761/62-06
30
20
10
10
0
0.001
LOS+
0.01
0.1
1
INPUT SIGNAL (Vp-p)
INPUT = 4mVp-p
TA = +85°C
50mV/
div
DATA IN
5µs/div
10
DATA OUTPUT SINGLE-ENDED
(223 - 1 PRBS PATTERN)
LOS OPERATION
WITHOUT SQUELCHING
MAX3761/62-10
OUT+
-40°C
+85°C
200
0
40
320
-1.8
-20
50
100
MAX3761/62-09
1280
PULSE-WIDTH DISTORTION (PS)
-1.2
1400
MAX3761/62-08
MAX3761/62-07
VOH
4
3
0
AMBIENT TEMPERATURE (°C)
-1.0
100mV/
div
ASSERT LEVEL SET
TO APPROXIMATELY
30mVp-p
AMBIENT TEMPERATURE (°C)
-0.8
-40
5
4
-40 -20
80
DIFFERENTIAL OUTPUT (mV)
-40
6
ASSERT LEVEL SET
TO APPROXIMATELY 30mVp-p
2.50
1.20
ASSERT LEVEL SET
TO APPROXIMATELY
2mVp-p
7
500ps/div
_______________________________________________________________________________________
MAX3761/62-12
1.68
8
MAX3761/62-11
RSSI VOLTAGE (V)
1.76
ASSERT LEVEL SET
TO APPROXIMATELY
2mVp-p
3.75
HYSTERESIS (dB)
VIN = 50mVp-p
1.84
4.00
HYSTERESIS (dB)
1.92
MAX3761/62-04
2.00
LOS HYSTERESIS vs. TEMPERATURE
(622Mbps 1-0 PATTERN)
MAX3761/62-05
RSSI vs. TEMPERATURE
(622Mbps 223 - 1 PRBS)
VOLTAGE (V)
MAX3761/MAX3762
Low-Power, 622Mbps Limiting Amplifiers
with Chatter-Free Power Detect for LANs
Low-Power, 622Mbps Limiting Amplifiers
with Chatter-Free Power Detect for LANs
200mV/
div
50mV/
div
10
RANDOM JITTER (ps rms)
DIFFERENTIAL OUTPUT
(OUT+ - OUT-)
INPUT = 16mVp-p
TA = +27°C
1-0 PATTERN 622Mbps
MAX3761/62-14
MAX3761/62-13
INPUT = 2Vp-p
TA = +85°C
RANDOM JITTER vs.
POWER-SUPPLY NOISE FREQUENCY
RANDOM JITTER
8
DIFFERENTIAL OUTPUT RANDOM JITTER
DATA INPUT AMPLITUDE = 16mVp-p
INPUT AMPLITUDE
POWER SUPPLY = 100mVp-p
MAX3761/62-15
DATA OUTPUT SINGLE-ENDED
(223-1 PRBS PATTERN)
6
4
2
500ps/div
103
200ps/div
104
106
105
FREQUENCY ON POWER SUPPLY (Hz)
______________________________________________________________Pin Description
PIN
NAME
1
FILTER
2
RSSI
FUNCTION
Sets the integration frequency of the power detector. Impedance at this node is approximately 500Ω.
Received-Signal-Strength Indicator. An analog DC voltage representing the input power.
3
EN
Connect to VCC.
4, 17
VCC
+5V Power Supply
5
VIN+
Positive Input Data
6
VIN-
Negative Input Data
7
GND
Supply Ground
8
SUB
Substrate. Connect to ground.
9
CZP
Sets input offset correction, low-frequency cutoff.
10
CZN
Sets input offset correction, low-frequency cutoff.
11
INV
Negative Input to Op Amp. Used for programming the loss-of-signal threshold.
12
VTH
Loss-of-Signal Threshold Voltage
13
GNDO
Ground Power Supply for Output Buffers
14
OUT-
Negative PECL Data Output
15
OUT+
Positive PECL Data Output
16
VCCO
+5V Power Supply for Output Buffers
18
LOS-
Negative Loss-of-Power Flag, TTL (MAX3761) or PECL (MAX3762)
19
LOS+
Positive Loss-of-Power Flag, TTL (MAX3761) or PECL (MAX3762)
20
DISABLE
Disables the data outputs when high. TTL (MAX3761) or PECL (MAX3762).
_______________________________________________________________________________________
5
MAX3761/MAX3762
____________________________Typical Operating Characteristics (continued)
(MAX3761/MAX3762 EV kit, VCC = +5.0V, PECL outputs terminated with 50Ω to VCC - 2V, input is a 1-0 pattern, 622Mbps, TA = +25°C,
unless otherwise noted.)
MAX3761/MAX3762
Low-Power, 622Mbps Limiting Amplifiers
with Chatter-Free Power Detect for LANs
CAZ
VCC
GND
SUB
CZN
CZP
EN
VCCO
DISABLE
LIMITER
LIMITER
LIMITER
LIMITER
VIN+/VIN-
OUT+/OUT50Ω
CIN
FWD
FWD
FWD
VCC - 2V
FWD
RSSI
FILTER
LOS+/LOSCFILTER
REF
VCC
MAX3761/MAX3762
INV
FWD = FULL-WAVE DETECTOR
R1
VTH
GNDO
R2
Figure 1. Functional Diagram
_______________Detailed Description
Figure 1 shows the functional diagram for the MAX3761/
MAX3762. The input signal is applied to VIN+ and VIN-.
A chain of amplifier stages, each contributing approximately 12.5dB of gain, amplifies the input signal to
PECL output voltage swings. A 4mVp-p input signal will
cause the output to fully limit.
Received-Signal-Strength
Indicator (RSSI)
Each amplifier stage contains a full-wave logarithmic
detector (FWD). The full-wave detector outputs are
summed at the FILTER pin and used to generate the
received-signal-strength indication (RSSI). The RSSI
output voltage is linearly proportional to the input power
(in decibels), and is approximated by:
VRSSI(V) = 1.13 + 0.457log (VIN )
where VIN is the peak-to-peak input signal in millivolts.
The RSSI output is insensitive to fluctuations in temperature
and supply voltage. The power detector functions as a
broadband power meter that detects the total power of all
signals present in the passband of approximately 750MHz.
Refer to the Typical Operating Characteristics graphs showing RSSI output versus input power and signal amplitude.
6
The high-speed RSSI signal is filtered with one external
capacitor connected from FILTER to VCC. The impedance at the FILTER pin is approximately 500Ω.
The FILTER capacitor (CFILTER) must be connected
to VCC for proper operation.
Input-Offset Correction
The limiting amplifier provides approximately 60dB of
gain. An input DC offset of even 1mV reduces the
power-detection circuit’s accuracy and can cause the
output to limit. A low-frequency feedback loop is integrated into the MAX3761/MAX3762 to remove input offset. DC coupling the inputs is not recommended, as
this prevents the DC-offset-correction circuitry from
functioning properly. Input offset is typically reduced to
less than 100µV.
The capacitance between pins CZP and CZN, in parallel
with a 10pF integrated capacitance, determines the offset-correction circuit’s time constant. The input impedance between CZP and CZN is approximately 800kΩ.
The offset correction circuitry requires an average datainput duty cycle of 50%. If the input data has a different
average duty cycle, the output will have increased
pulse-width distortion.
_______________________________________________________________________________________
Low-Power, 622Mbps Limiting Amplifiers
with Chatter-Free Power Detect for LANs
Output Buffers
The DISABLE pin can be used to disable the dataoutput buffer. When DISABLE is high, the differential
output signal at OUT+ and OUT- is approximately zero.
In the disabled state, the common-mode voltage of
each output is approximately VCC - 0.8V. Connecting
__________________Design Procedure
Supply Voltage
The MAX3761/MAX3762 can be operated with a single
+5V or -5V power supply.
Programming the LOS Assert Level
First determine the receiver system’s sensitivity in dBm
either by estimating or from prototyping results.
Estimate the total gain of the preamplifier and photodiode, then use Figure 3 to select resistor R2, placing the
LOS assert 3dB to 4dB below the receiver sensitivity.
Alternatively, use the Typical Operating Characteristics
to select the VTH value needed for LOS assert, then
program VTH with the following relation:
VTH = 1.18(1 + R2 / R1)
Select R1 ≥ 100kΩ.
80
R1 = 100kΩ
45mV
45mV
VALUE OF R2 (kΩ)
25mV/dB
VDEASSERT
VTH
VASSERT
GAIN = 6000
70
RSSI
VOLTAGE
MAX3761/2-03
To ensure chatter-free LOS operation, the internal LOS
comparator contains approximately 90mV of hysteresis.
The RSSI signal output has a slope of 25mV/dB.
Therefore, the overall circuit hysteresis is approximately
3.6dB[90mV / (25mV/dB)]. The LOS assert threshold is
45mV below VTH, while the LOS deassert threshold is
45mV above VTH.
DISABLE to LOS+ implements a squelch function. When
using the squelch function, the output signal is disabled
whenever the input signal is too small to be reliably
detected (as determined by the voltage at VTH). Use of
the disable function is recommended at all times.
The data outputs (OUT+ and OUT-) are implemented
with emitter followers that have output impedance of
approximately 2Ω. The MAX3762’s PECL LOS outputs
also are implemented with emitter followers that have
output impedance of approximately 2Ω.
The MAX3761 TTL LOS output buffers are open-collector transistors with 6kΩ internal pull-up resistors.
60
GAIN = 4000
50
40
30
20
GAIN = 2000
1.2V
10
3.6dB
typical
0
-38
VASSERT (min)
VDEASSERT (max)
INPUT SIGNAL AMPLITUDE
Figure 2. Loss-of-Signal Definitions
-36 -34 -32 -30 -28 -26 -24
-22
INPUT SIGNAL (dBm)
GAIN IS PHOTODIODE RESPONSIVITY x TRANSIMPEDANCE GAIN.
EXTINCTION RATIO OF 10 IS ASSUMED.
Figure 3. Using TIA Gain and Photodiode Responsivity to
Select LOS Programming Resistor
_______________________________________________________________________________________
7
MAX3761/MAX3762
Loss-of-Signal Indicator
The MAX3761/MAX3762 includes a loss-of-signal monitor with a programmable assert threshold and a hysteresis comparator. Internally, one comparator input is
tied to the RSSI output signal and the other is tied to the
threshold-voltage (VTH) pin, which provides a threshold
for the LOS indication. An op amp referenced to an
internal bandgap voltage (1.18V) is supplied for programming a supply-independent threshold voltage.
Only two external resistors are needed to program the
LOS assert level. VTH is programmable from 1.18V to
2.4V, providing adequate coverage of the RSSI output’s
useful range. The op amp runs on very low supply current and provides an accurate, temperature-stable
threshold, but can source only 20µA of current. For
proper operation, resistor R1 (see the Typical
Operating Circuit) should have a value ≥ 100kΩ. The
input bias current at INV is < 50nA.
MAX3761/MAX3762
Low-Power, 622Mbps Limiting Amplifiers
with Chatter-Free Power Detect for LANs
Capacitor Selection
A typical MAX3761/MAX3762 implementation requires
four external capacitors. To select the capacitors, first
determine the following parameters in the receiver system (see the Applications Information section for recommendations in 622Mbps ATM and Fibre Channel
1063Mbps systems):
1) The duration of the expected longest run of consecutive bits in the data stream. For example, 72 consecutive zeros in a 622Mbps data stream have a
duration of 116ns.
2) The maximum allowable data-dependent jitter.
3) The desired power-detector integration time constant [1 / (2πfINT)].
4) The transimpedance amplifier’s maximum peak-topeak output voltage.
Step 1. Select the Input AC-Coupling Capacitors (CIN).
When using a limiting preamplifier with a highpass
frequency response, select C IN to provide a lowfrequency cutoff (f C ) one decade lower than the
preamplifier low-frequency cutoff. This causes nearly all
data-dependent jitter (DDJ) to be generated in the preamplifer circuit. For example, if the preamplifier’s lowfrequency cutoff is 150kHz, then select CIN to provide a
15kHz low-frequency cutoff.
Select CIN with the following equation:
1
CIN =
2πfC 1950Ω
For differential input signals, use a capacitor equal to
CIN on both inputs (VIN+ and VIN-). For single-ended
input signals, one capacitor should be tied to VIN+ and
another should decouple VIN- to ground.
When using a preamplifier without a highpass
response, select CIN to ensure that data-dependent jitter is acceptable. The following equation provides an
estimate for CIN:
CIN ≥
- tL

DDJ BW
1950 ln 1 −
0.5

(
)( ) 
value of CIN. The following equation estimates LOS time
delay when the maximum-amplitude signal is instantaneously removed from the input, and when the FILTER
time constant is much faster than the input time constant (CFILTER < 0.4CIN):
tLOS ASSERT = 1950CINln(VMAXp-p / VASSERTp-p)
where VMAXp-p is the maximum output of the preamplifier, and VASSERTp-p is the input amplitude that causes
LOS to assert. The equation describes the input capacitors’ discharge time, from maximum input to the LOS
threshold into the 1950Ω, single-ended input resistance.
Step 2. Select the Offset-Correction Capacitor (CAZ).
To maintain stability, it is important to keep a onedecade separation between fC and the low-frequency
cutoff associated with the DC-offset-correction circuit
(fOC).
The input impedance between CZP and CZN is
approximately 800kΩ in parallel with 10pF. As a result,
the low-frequency cutoff (fOC) associated with the DCoffset-correction loop is computed as follows:
fOC =
1
2π800kΩ C AZ + 10pF
(
where CAZ is an optional external capacitor between
CZP and CZN.
If CIN is known, then:
C AZ ≥
CIN
− 10pF
41
Step 3. Select the Power-Detect Integration Capacitor
(CFILTER). For 622Mbps ATM applications, Maxim recommends a filter frequency of 3MHz, which requires
CFILTER = 100pF. The integration frequency can be
selected lower to remove low-frequency noise, or to
prevent unusual data sequences from asserting LOS.
CFILTER = 1 / ( 2π500fINT)
where fINT is the integration frequency.

where: tL = duration of the longest run of consecutive
bits with the same value (seconds); DDJ = maximum
allowable data-dependent jitter, peak-to-peak (seconds);
BW = typical system bandwidth, normally 0.6 to 1.0
times the data rate (hertz).
Regardless of which method is used to select CIN, the
maximum LOS assert time can be estimated from the
8
)
_______________________________________________________________________________________
Low-Power, 622Mbps Limiting Amplifiers
with Chatter-Free Power Detect for LANs
Converting Average Optical Power to
Signal Amplitude
Many of the MAX3761/MAX3762’s specifications relate
to input-signal amplitude. When working with fiber optic
receivers, the input is usually expressed in terms of
average optical power and extinction ratio. The relations given in Table 1 are helpful for converting optical
power to input signal when designing with the
MAX3761/MAX3762.
OPTICAL
POWER P1
PAVE
P0
Table 1. Optical-Power Relations*
PARAMETER
SYMBOL
TIME
RELATION
Figure 4. Optical-Power Relations
PAVE = (P0 + P1) / 2
Average
Power
PAVE
Extinction
Ratio
re
re = P1 / P0
Optical Power
of a “1”
P1
P1 = 2PAVE
Optical Power
of a “0”
P0
P0 = 2PAVE / re + 1
Signal
Amplitude
PIN
PIN = P1 − P0 = 2PAVE
In an optical receiver the dB change at the MAX3761/
MAX3762 will always equal 2x the optical dB change.
The MAX3761/MAX3762’s typical voltage hysteresis is
3.6dB. This provides an optical hysteresis of 1.8dB.
re
re + 1
(
Input Sensitivity
)
(re − 1)
re + 1
* Assuming a 50% average input data duty cycle (true for SONET/ATM data).
In an optical receiver, the input voltage to the limiting
amplifier can be found by multiplying the relationship in
Table 1 with the photodiode responsivity (p) and transimpedance amplifier gain (G).
Optical Hysteresis
Power and hysteresis are often expressed in decibels.
By definition, decibels are always 10log (power). At the
inputs to the MAX3761/MAX3762 limiting amplifier, the
power is VIN2/R. If a receiver’s optical input power (x)
increases by a factor of two, and the preamplifier is linear, then the voltage input to the MAX3761/MAX3762
also increases by a factor of two.
The optical power change is 10log(2x / x) = 10log(2) =
+3dB
At the MAX3761/MAX3762, the voltage change is:
10log
(2VIN )2 / R
2
VIN / R
= 10log(22 ) = 20log(2) = + 6dB
The receiver’s gain sensitivity defines the smallest signal
input that results in fully limited PECL-compatible data
outputs. Smaller signals result in nonlimited outputs. The
MAX3761/MAX3762’s input sensitivity (SGAIN) is 4mVp-p:
SGAIN = 4mV
Optical gain sensitivity (in dBm) is:
S

r +1
10log  GAIN x e
x 1000
ρ
r
−
2G
1
e


In a receiver with G = 6kΩ, re = 10, and ρ = 0.8A/W,
gain sensitivity is 510nW, or -32.9dBm.
622Mbps ATM Component Selection
As an example, a preamplifier with a 150kHz lowfrequency cutoff and a 950mVp-p maximum output has
the best performance with the following selections:
CIN = 5.6nF, so that fC = 15kHz (one decade below the
150kHz cutoff)
C AZ = 150pF, so that f OC < 1.5kHz (one decade
below fC)
C FILTER = 100pF, so that the integration frequency
equals 3MHz.
These selections should provide data-dependent jitter
less than 110ps p-p when the input consists of PRBS
data with no more than 72 consecutive bits.
_______________________________________________________________________________________
9
MAX3761/MAX3762
__________Applications Information
MAX3761/MAX3762
Low-Power, 622Mbps Limiting Amplifiers
with Chatter-Free Power Detect for LANs
For LOS assert at -35dBm, select R1 = 100kΩ and R2 =
22kΩ, which programs the LOS assert at input ≅ 3mV.
With this selection, LOS assert time will typically be less
than 85µs.
OUT+
Fibre Channel Component Selection
In Fibre Channel applications, the desired LOS assert
time is typically 25µs maximum, and data-dependent
jitter is reduced by 8B10B coding techniques. The following are recommended in a Fibre Channel system
where preamp gain is 2000V/W, LOS assert is set for
-24dBm (13mV MAX3761/MAX3762 input), and the
maximum input to the MAX3761/MAX3762 is 1Vp-p:
CIN = 3.3nF (to provide LOS assert in 25µs)
CAZ = 82pF (to provide fOC = 1/10 fC for stability)
470Ω
50Ω
470Ω
50Ω
MAX3761
OUT-
DRIVING 50Ω TO GROUND
CFILTER = 100pF (for a 3MHz integration constant)
R1 = 100kΩ, R2 = 50kΩ (to set LOS assert at -24dBm)
PECL Terminations
The standard PECL termination (50Ω to VCC - 2V) is
recommended for best performance and output characteristics. The data outputs operate at high speed,
and should always drive transmission lines with
50Ω to 75Ω terminations. Balanced termination is recommended for all outputs.
Figure 5 shows an alternative method for terminating
the data outputs. The technique provides approximately 8mA DC bias current, with a 50Ω AC load, for the
output termination. This technique is useful for viewing
the output on an oscilloscope or changing the PECL
reference voltage.
The MAX3762’s PECL LOS outputs are relatively slow
and do not need 50Ω terminations (although they are
capable of driving them). To reduce power, the
MAX3762’s LOS outputs can be terminated with 500Ω.
Figure 6 shows a typical operating circuit for the
MAX3762.
10
Figure 5. Alternative PECL Termination
Wire Bonding
For high current density and reliable operation, the
MAX3761/MAX3762 use gold metalization. Make connections to the dice with gold wire only, and use ballbonding techniques (wedge bonding is not
recommended). Die-pad size is 4 mils square, with a
6 mil pitch. Die thickness is 12 mils (0.3mm).
Layout Techniques
The MAX3761/MAX3762 are high-frequency, highbandwidth circuits. To ensure stability, use good highfrequency layout techniques. Filter voltage supplies,
and keep ground connections short. Use multiple vias
where possible. Use controlled-impedance transmission lines to connect the MAX3761/MAX3762 data outputs to other circuits.
______________________________________________________________________________________
Low-Power, 622Mbps Limiting Amplifiers
with Chatter-Free Power Detect for LANs
+5V
CZN
DISABLE
LOS+
EN
10nF
CAZ
150pF
CZP
VCC
RSSI
VCCO
CIN
5.6nF
OUT+
GNDO
VCC - 2V
GND
FILTER
CFILTER
INV
VCC - 2V
50Ω
50Ω
MAX3762
VIN-
VCC - 2V
500Ω
OUTVIN+
100pF
500Ω
LOS-
CIN
5.6nF
100pF
VTH
SUB
+VCC
R1
R2
___________________Chip Topography
RSSI
FILTER
DISABLE
LOS+
EN
LOS-
V CC
V CC
VCCO
VIN+
VIN-
0.063"
(1.60mm)
OUT+
GND
OUTGNDO
SUB
CZP
CZN
INV
VTH
0.059"
(1.49mm)
TRANSISTOR COUNT: 961
SUBSTRATE CONNECTED TO SUB
______________________________________________________________________________________
11
MAX3761/MAX3762
_____________________________________Typical Operating Circuits (continued)
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
QSOP.EPS
MAX3761/MAX3762
Low-Power, 622Mbps Limiting Amplifiers
with Chatter-Free Power Detect for LANs
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
12 __________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600
© 2004 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.