AD ADUM6132ARWZ Isolated half-bridge gate driver with integrated isolated high-side supply Datasheet

Isolated Half-Bridge Gate Driver with
Integrated Isolated High-Side Supply
ADuM6132
FEATURES
GENERAL DESCRIPTION
isoPower integrated isolated high-side supply
275 mW isolated dc-to-dc converter
200 mA output sink current, 200 mA output source current
High common-mode transient immunity: >50 kV/μs
Wide-body 16-lead SOIC package
Safety and regulatory approvals (pending)
UL recognition
3750 V rms for 1 minute per UL 1577
CSA Component Acceptance Notice #5A
CSA/IEC 60950-1, 400 V rms
VDE certificate of conformity
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12
VIORM = 560 V peak
The ADuM61321 is an isolated half-bridge gate driver that
employs the Analog Devices, Inc., iCoupler® technology to
provide an isolated high-side driver with an integrated 275 mW
high-side supply. This supply, provided by an internal isolated
dc-to-dc converter, powers not only the ADuM6132 high-side
output but also any external buffer circuitry that is commonly
used with the ADuM6132. This functionality eliminates the
cost, space, and performance issues associated with external
supply configurations such as a bootstrap circuit.
The architecture of the ADuM6132 isolates the high-side
channel and the high-side power from the control and lowside interface circuitry. Care has been taken to ensure close
matching between the high-side and low-side driver timing
characteristics to reduce the need for a dead time margin.
APPLICATIONS
In comparison to gate drivers that employ high voltage level
translation methodologies, the ADuM6132 offers the benefit
of true, galvanic isolation. The differential voltage between
high-side and low-side channels can be as high as 800 V with
good insulation lifetime (see Table 12).
MOSFET/IGBT gate drivers
Motor drives
Solar panel inverters
Power supplies
isoPower® uses high frequency switching elements to transfer
power through its transformer. Special care must be taken
during printed circuit board (PCB) layout to meet emissions
standards. Refer to the AN-0971 Application Note for details on
board layout considerations.
VDD 1
ISOLATED
DC-TO-DC
CONVERTER
GND 2
ENCODE
VIB 5
VOB 6
DECODE AND
LEVEL-SHIFT
VIA 4
LEVELSHIFT
VDDL 3
16
VISO
15
GNDISO
14
GNDA
13
VDDA
12
VOA
11
NC
VDDB 7
10
NC
GND 8
9
ADuM6132
GNDISO
07393-001
FUNCTIONAL BLOCK DIAGRAM
Figure 1.
1
Protected by U.S. Patents 5,952,849; 6,873,065; 6,903,578; 7,075,329; and other pending patents
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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Fax: 781.461.3113
©2008 Analog Devices, Inc. All rights reserved.
ADuM6132
TABLE OF CONTENTS
Features .............................................................................................. 1
ESD Caution...................................................................................6
Applications ....................................................................................... 1
Pin Configuration and Function Descriptions..............................7
General Description ......................................................................... 1
Typical Performance Characteristics ..............................................8
Functional Block Diagram .............................................................. 1
Terminology .................................................................................... 10
Revision History ............................................................................... 2
Applications Information .............................................................. 11
Specifications..................................................................................... 3
Typical Application Usage ......................................................... 11
Electrical Characteristics ............................................................. 3
PCB Layout ................................................................................. 11
Package Characteristics ............................................................... 4
Thermal Analysis ....................................................................... 12
Regulatory Information ............................................................... 4
Undervoltage Lockout ............................................................... 12
Insulation and Safety Related Specifications ............................ 4
Propagation Delay-Related Parameters ................................... 13
DIN V VDE V 0884-10 (VDE V 0884-10) Insulation
Characteristics .............................................................................. 5
Magnetic Field Immunity.......................................................... 13
Recommended Operating Conditions ...................................... 5
Outline Dimensions ....................................................................... 15
Absolute Maximum Ratings............................................................ 6
Ordering Guide .......................................................................... 15
Insulation Lifetime ..................................................................... 14
REVISION HISTORY
7/08—Revision 0: Initial Version
Rev. 0 | Page 2 of 16
ADuM6132
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
All voltages are relative to their respective ground; 4.5 V ≤ VDD = VDDL ≤ 5.5 V; 12.5 V ≤ VDDB ≤ 17.0 V; VDDA = VISO. All minimum/maximum
specifications apply over the entire recommended operating range, unless otherwise noted. All typical specifications are at TA = 25°C,
VDD = VDDL = 5.0 V, VDDB = 15 V, VDDA = VISO.
Table 1.
Parameter
DC SPECIFICATIONS
Isolated Power Supply
Input Current, Quiescent
Input Current, Loaded
Maximum Output Current 1
Output Voltage
Logic Supply
Input Current
Output Supplies, Channel A or Channel B 2
Supply Current, Quiescent
Supply Current, fIN = 20 kHz
Supply Current, fIN = 100 kHz
Supply Current, fIN = 1000 kHz
Logic Inputs, Channel A or Channel B
Input Current
Logic High Input Voltage
Logic Low Input Voltage
Outputs, Channel A or Channel B
Channel A High Level Output Voltage
Channel B High Level Output Voltage
Low Level Output Voltages
High Level Output Current, Peak 3
Low Level Output Current, Peak3
Undervoltage Lockout, VDDA or VDDB Supply 4
Positive Going Threshold
Negative Going Threshold
Hysteresis
Undervoltage Lockout, VDDL Supply4
Positive Going Threshold
Negative Going Threshold
Hysteresis
SWITCHING SPECIFICATIONS
Minimum Pulse Width1
Maximum Switching Frequency1
Propagation Delay1
Change vs. Temperature
Pulse Width Distortion, |tPLH − tPHL|
Channel-to-Channel Matching, Rising or
Falling Matching Edge Polarity1
Channel-to-Channel Matching, Rising vs.
Falling Opposite Edge Polarity1
Symbol
Min
IDD(Q)
IDD
IISO(MAX)
VISO
Typ
Max
Unit
Test Conditions/Comments
280
350
IISO = 0 mA, dc signal inputs
IISO = IISO(MAX)
12.5 V ≤ VISO ≤ 17.0 V
0 mA ≤ IISO ≤ 22 mA
15
17
mA
mA
mA
V
IDDL
1.8
3.0
mA
IDDA(Q), IDDB(Q)
IDDA(20), IDDB(20)
IDDA(100), IDDB(100)
IDDA(1000), IDDB(1000)
1.0
1.1
1.3
4.5
2.0
2.1
2.3
5.5
mA
mA
mA
mA
+0.01
+10
μA
V
V
0 V ≤ VIA, VIB ≤ 5.5 V
V
V
V
mA
mA
IOAH = −1 mA
IOBH = −1 mA
IOAL, IOBL = 1 mA
22
12.5
IIA, IIB
VIAH, VIBH
VIAL, VIBL
−10
0.7 × VDDL
VOAH
VOBH
VOAL,VOBL
IOAH, IOBH
IOAL, IOBL
VDDA − 0.1
VDDB − 0.1
VDDAUV+, VDDBUV+
VDDAUV−, VDDBUV−
VDDAUVH, VDDBUVH
11.0
10.0
VDDLUV+
VDDLUV−
VDDLUVH
3.5
3.1
PW
fIN
tPHL, tPLH
0.3 × VDDL
0.1
200
200
11.7
10.7
1.0
12.3
11.2
V
V
V
4.2
3.8
V
V
V
50
CL = 200 pF
CL = 200 pF
CL = 200 pF
CL = 200 pF
0.5
PWD
tM2
10
20
ns
kHz
ns
ps/°C
ns
ns
tM1
20
ns
1000
40
Rev. 0 | Page 3 of 16
60
100
CL = 200 pF
CL = 200 pF
CL = 200 pF
100
CL = 200 pF
CL = 200 pF
ADuM6132
Parameter
Part-to-Part Matching1
Output Rise Time (10% to 90%)
Output Fall Time (10% to 90%)
Symbol
Min
Typ
tR
tF
Max
60
15
15
Unit
ns
ns
ns
Test Conditions/Comments
CL = 200 pF
CL = 200 pF
CL = 200 pF
1
See the Terminology section.
IDDA is supplied by the output of the integrated isolated dc-to-dc power supply. IDDB is supplied by an external power connection to the VDDB pin. See Figure 16.
Duration less than 1 second. Average output current must conform to the limit shown in the Absolute Maximum Ratings section.
4
Undervoltage lockout (UVLO) holds the outputs in a low state if the corresponding input or output power supply is below the referenced threshold. Hysteresis is built
into the detection threshold to prevent oscillations and noise sensitivity.
2
3
PACKAGE CHARACTERISTICS
Table 2.
Parameter
Resistance (Input Side to High-Side Output) 1
Capacitance (Input Side to High-Side Output)1
Input Capacitance
Junction-to-Ambient Thermal Resistance
1
Symbol
RI-O
CI-O
CI
θJA
Min
Typ
1012
2.0
4.0
45
Max
Unit
Ω
pF
pF
°C/W
Test Conditions/Comments
4-layer PCB
The device is considered a two-terminal device: Pin 1 through Pin 8 are shorted together, and Pin 9 through Pin 16 are shorted together.
REGULATORY INFORMATION
The ADuM6132 is pending approval by the organizations listed in Table 3.
Table 3.
UL (Pending)
Recognized under UL 1577
component recognition program 1
Double/reinforced insulation,
3750 V rms isolation voltage
File E214100
1
2
CSA (Pending)
Approved under CSA Component Acceptance
Notice #5A
Basic insulation per CSA 60950-1-03 and IEC 60950-1,
800 V rms (1131 V peak) maximum working voltage
Reinforced insulation per CSA 60950-1-03 and
IEC 60950-1, 400 V rms maximum working voltage
File 205078
VDE (Pending)
Certified according to DIN V VDE V 0884-10
(VDE V 0884-10):2006-12 2
Reinforced insulation, 560 V peak
File 2471900-4880-0001
In accordance with UL 1577, each ADuM6132 is proof-tested by applying an insulation test voltage ≥4500 V rms for 1 second (current leakage detection limit = 10 μA).
In accordance with DIN V VDE V 0884-10, each ADuM6132 is proof-tested by applying an insulation test voltage ≥1050 V peak for 1 second (partial discharge detection
limit = 5 pC). The asterisk (*) marking branded on the component designates DIN V VDE V 0884-10 approval.
INSULATION AND SAFETY RELATED SPECIFICATIONS
Table 4.
Parameter
Rated Dielectric Insulation Voltage
Minimum External Air Gap (Clearance)
Symbol
L(I01)
Value
3750
>8.0
Unit
V rms
mm
Minimum External Tracking (Creepage)
L(I02)
>8.0
mm
Minimum Internal Gap (Internal Clearance)
Tracking Resistance (Comparative Tracking Index)
Isolation Group
CTI
0.017 min
>175
IIIa
mm
V
Rev. 0 | Page 4 of 16
Test Conditions/Comments
1 minute duration
Measured from input terminals to output
terminals, shortest distance through air
Measured from input terminals to output
terminals, shortest distance path along body
Insulation distance through insulation
DIN IEC 112/VDE 0303 Part 1
Material Group (DIN VDE 0110, 1/89, Table 1)
ADuM6132
DIN V VDE V 0884-10 (VDE V 0884-10) INSULATION CHARACTERISTICS
The ADuM6132 is suitable for reinforced electrical isolation only within the safety limit data. Maintenance of the safety data is ensured by
protective circuits. The asterisk (*) marking on the package denotes DIN V VDE V 0884-10 approval.
Table 5.
Parameter
Installation Classification per DIN VDE 0110
For Rated Mains Voltage ≤ 150 V rms
For Rated Mains Voltage ≤ 300 V rms
For Rated Mains Voltage ≤ 400 V rms
Climatic Classification
Pollution Degree (DIN VDE 0110, Table 1)
Maximum Working Insulation Voltage
Input-to-Output Test Voltage, Method B1
Test Conditions/Comments
VIORM × 1.875 = VPR, 100% production test, tm = 1 sec,
partial discharge <5 pC
Input-to-Output Test Voltage, Method A
After Environmental Tests Subgroup 1
After Input and/or Safety Test Subgroup 2
and Subgroup 3
Highest Allowable Overvoltage
Safety-Limiting Values
Value
Unit
VIORM
VPR
I to IV
I to III
I to II
40/105/21
2
560
1050
V peak
V peak
896
672
V peak
V peak
VTR
6000
V peak
TS
IS1
RS
150
555
>109
°C
mA
Ω
VPR
VIORM × 1.6 = VPR, tm = 60 sec, partial discharge <5 pC
VIORM × 1.2 = VPR, tm = 60 sec, partial discharge <5 pC
Transient overvoltage, tTR = 10 sec
Maximum value allowed in the event of a failure
(see Figure 2)
Case Temperature
Side 1 Current
Insulation Resistance at TS
VIO = 500 V
600
RECOMMENDED OPERATING CONDITIONS
500
Table 6.
Parameter
Operating Temperature Range, TA
Input Supply Voltage, VDD and VDDL1
Channel A, Channel B Supply Voltage,
VDDA and VDDB1
Input Signal Rise and Fall Times
Common-Mode Transient Immunity,
Input to Output
Minimum Power-On Slew Rate (PSLEW),
VDD and VDDL2
400
300
200
100
0
0
50
100
150
AMBIENT TEMPERATURE (°C)
200
07393-002
SAFE OPERATING VDD CURRENT (mA)
Symbol
1
2
Figure 2. Thermal Derating Curve, Dependence of Safety-Limiting Values
with Ambient Temperature per DIN V VDE V 0884-10
Rating
−40°C to +85°C
4.5 V to 5.5 V
12.5 V to 17 V
1 ms
−50 kV/μs to +50 kV/μs
1 V/ms
All voltages are relative to their respective ground.
The ADuM6132 power supply may fail to properly initialize if VDD and VDDL are
applied too slowly. The power supply slew rate must be faster than specified
over the entire turn-on ramp. Power-on should start from a completely
discharged state.
Rev. 0 | Page 5 of 16
ADuM6132
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Table 7.
Parameter
Storage Temperature Range, TST
Ambient Operating Temperature
Range, TA
Input Supply Voltage, VDDL, VDD1
Channel A, Channel B Supply
Voltage, VDDA, VDDB1
Input Voltage, VIA, VIB1
Output Voltage, VOA1
Output Voltage, VOB1
Average DC Output Current,
IOA, IOB
Peak Output Current, IOA, IOB
Common-Mode Transients2
1
2
Rating
−55°C to +150°C
−40°C to +85°C
−0.5 V to +7.0 V
−0.5 V to +27 V
ESD CAUTION
−0.5 V to VDDL + 0.5 V
−0.5 V to VISO + 0.5 V
−0.5 V to VDDB + 0.5 V
−10 mA to +10 mA
−200 mA to +200 mA
−100 kV/μs to +100 kV/μs
All voltages are relative to their respective ground.
Refers to common-mode transients across any insulation barrier. Commonmode transients exceeding the absolute maximum ratings can cause latch-up
or permanent damage.
Rev. 0 | Page 6 of 16
ADuM6132
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
VDD 1
16 VISO
VDDL 3
VIA 4
VIB 5
15 GNDISO
ADuM6132
TOP VIEW
(Not to Scale)
14 GNDA
13 VDDA
12 VOA
VOB 6
11 NC
VDDB 7
10 NC
GND 8
9
GNDISO
NC = NO CONNECT
07393-003
GND 2
Figure 3. Pin Configuration
Table 8. Pin Function Descriptions
Pin No.
1
2, 8
3
4
5
6
7
9, 15
10, 11
12
13
14
16
Mnemonic
VDD
GND
VDDL
VIA
VIB
VOB
VDDB
GNDISO
NC
VOA
VDDA
GNDA
VISO
Description
Input Supply Voltage for Isolated Power Supply, 4.5 V to 5.5 V.
Ground Reference for Isolated Power Supply Input and Logic Inputs.
Input Supply Voltage for Logic, 4.5 V to 5.5 V.
Logic Input A.
Logic Input B.
Output B (Nonisolated).
Output B Supply Voltage Input (Nonisolated), 12.5 V to 17 V.
Ground Reference for Isolated Power Supply Output.
No Connect.
Output A (Isolated).
Output A Supply Voltage Input. Must be connected externally to VISO (Pin 16).
Output A Ground Reference. Must be connected externally to GNDISO (Pin 15).
Isolated Power Supply Voltage Output.
Table 9. Truth Table (Positive Logic) 1
VIA Input
L
L
H
H
X
VIB Input
L
H
L
H
X
VDDL State
Powered
Powered
Powered
Powered
Unpowered
VDDB State
Powered
Powered
Powered
Powered
Powered
VOA Output
L
L
H
H
L
VOB Output
L
H
L
H
L
X
X
Powered
Unpowered
L
L
1
L = low; H = high; X = high or low.
Rev. 0 | Page 7 of 16
Notes
VOA returns to input state within 1 μs of VDDL
power restoration.
ADuM6132
TYPICAL PERFORMANCE CHARACTERISTICS
All typical performance curves are based on operation at TA = 25°C, unless otherwise noted.
1.2
15.5
1.0
POWER DISSIPATION (W)
16.0
VDD = 5.5V
14.5
VDD = 4.5V
14.0
VDD = 5.0V
5
10
15
20
25
VDD = 5.5V
0.6
0.4
0
07393-024
0
IISO LOAD CURRENT (mA)
0
5
10
15
20
25
IISO LOAD CURRENT (mA)
Figure 4. Typical VISO Supply Voltage vs. IISO External Load
Figure 7. Typical Total Power Dissipation vs. IISO External Load
300
14.8
14.6
VDD = 4.5V
250
VDD = 5.5V
14.4
VDD = 5.0V
VISO AT 22mA LOAD (V)
IDD INPUT CURRENT (mA)
VDD = 4.5V
0.2
13.5
13.0
0.8
07393-027
VISO (V)
15.0
VDD = 5.0V
200
VDD = 5.5V
150
100
14.2
VDD = 5.0V
14.0
13.8
13.6
13.4
VDD = 4.5V
13.2
13.0
50
5
10
15
20
25
IISO LOAD CURRENT (mA)
12.6
–40
07393-025
0
–20
0
20
40
60
80
100
120
AMBIENT TEMPERATURE (°C)
Figure 5. Typical IDD Supply Current vs. IISO External Load
07393-028
12.8
0
Figure 8. Typical VISO Output Voltage at Maximum Combined Load
over Temperature
30
2500
VDD = 5.5V
VDD = 5.0V
15
10
5
0
5
10
15
20
IISO LOAD CURRENT (mA)
Figure 6. Typical VISO Supply Efficiency vs. IISO External Load
25
1500
VDD = 5.0V
1000
VDD = 5.5V
500
0
1
10
100
VISO LOAD IMPEDANCE (Ω)
1000
07393-029
POWER DISSIPATION (mW)
20
0
VDD = 4.5V
2000
VDD = 4.5V
07393-026
EFFICIENCY (%)
25
Figure 9. Power Dissipation vs. Load Impedance for Fault Conditions
Rev. 0 | Page 8 of 16
ADuM6132
6
4
VDDA = 17V
VOL OUTPUT VOLTAGE (V)
IDDA CURRENT (mA)
5
4
3
VDDA = 12.5V
2
VDDA = 15V
3
2
1
0
200
400
600
800
1000
VOA DATA FREQUENCY (kHz)
0
07393-030
Figure 10. Typical IDDA Supply Current, CL = 200 pF
200
250
VDDB = 17V
4
3
VDDB = 12.5V
2
VDDB = 15V
200
400
600
800
1000
VOB DATA FREQUENCY (kHz)
tPLH CHA
60
tPHL CHA
55
50
–50
07393-031
0
65
–25
0
25
50
75
100
TEMPERATURE (°C)
Figure 11. Typical IDDB Supply Current, CL = 200 pF
07393-034
VOA PROPAGATION DELAY (ns)
IDDB CURRENT (mA)
150
70
1
Figure 14. Typical Channel A Propagation Delay vs. Temperature
0
70
VOB PROPAGATION DELAY (ns)
–1
–2
–3
–4
0
50
100
150
200
250
IOH (mA)
tPLH CHB
65
tPHL CHB
60
55
50
–50
07393-032
(VOH – VDD) OUTPUT VOLTAGE DROP (V)
100
Figure 13. Typical VOL vs. IOL (VDD = VDDL = 5 V, VDDA = VDDB = 12 V to 17 V)
5
–5
50
IOL (mA)
6
0
0
–25
0
25
50
75
100
TEMPERATURE (°C)
Figure 15. Typical Channel B Propagation Delay vs. Temperature
Figure 12. Typical VOH Voltage Drop vs. IOH (VDD = VDDL = 5 V,
VDDA = VDDB = 12 V to 17 V)
Rev. 0 | Page 9 of 16
07393-035
0
07393-033
1
ADuM6132
TERMINOLOGY
Channel-to-Channel Matching
Channel-to-channel matching with rising or falling matching
edge polarity is the magnitude of the propagation delay difference between two channels of the same part when the inputs
are both rising edges or both falling edges. The loads on each
channel are equal.
Channel-to-channel matching with rising vs. falling opposite
edge polarity is the magnitude of the propagation delay difference between two channels of the same part when one input is
a rising edge and one input is a falling edge. The loads on each
channel are equal.
Maximum Output Current
The maximum output current is the maximum isolated supply
current that the ADuM6132 can provide. This current supports
external loads as well as the needs of the ADuM6132 Channel A
output circuitry. This is achieved via external connection of the
VISO pin to the VDDA pin and of the GNDISO pin to the GNDA pin
(see Figure 16). The net current available to power external loads
is the ADuM6132 output current, IISO, minus the Channel A
supply current, IDDA.
Maximum Switching Frequency
The maximum switching frequency is the maximum signal
frequency at which the specified timing parameters are guaranteed. Operation beyond the maximum switching frequency
is not recommended, because high switching rates can cause
droop in the output supply voltage.
Minimum Pulse Width
The minimum pulse width is the shortest pulse width at which
the specified pulse width distortion is guaranteed. Operation
below the minimum pulse width is not recommended.
Part-to-Part Matching
Part-to-part matching is the magnitude of the propagation
delay difference between the same channels of two different
parts. This includes rising vs. rising edges, falling vs. falling
edges, or rising vs. falling edges. The supply voltages, temperatures, and loads of each part are equal.
Propagation Delay
The propagation delay is the time that it takes a logic signal to
propagate through a component. The propagation delay to a
logic low output may differ from the propagation delay to a
logic high output.
The tPHL propagation delay is measured from the 50% level
of the falling edge of the VIA or VIB signal to the 50% level of
the falling edge of the VOA or VOB signal. The tPLH propagation
delay is measured from the 50% level of the rising edge of the
VIA or VIB signal to the 50% level of the rising edge of the VOA
or VOB signal.
Capacitive Load (CL)
The output capacitive load simulates a typical FET, IGBT, or
buffer for timing or current measurements. This load includes
all discrete and parasitic capacitive loads on the output.
Rev. 0 | Page 10 of 16
ADuM6132
APPLICATIONS INFORMATION
voltage transistor combination can be selected to suit the
requirements of the application.
TYPICAL APPLICATION USAGE
The architecture of the ADuM6132 is ideal for motor drive and
inverter applications where the low-side channels are common
to the controller. This arrangement requires only two isolation
regions in a package. All the isolated signals and the isolated
power are grouped on one side of the package to maintain full
package creepage and clearance. The low-side driver, as well as the
control signals, share a common reference and are also grouped.
PCB LAYOUT
The ADuM6132 digital isolator with integrated 275 mW
isoPower dc-to-dc converter requires no external interface
circuitry for the logic interfaces. Power supply bypassing is
required at the input and output supply pins (see Figure 17).
The power supply section of the ADuM6132 uses a very high
oscillator frequency to efficiently pass power through its chip
scale transformers. In addition, the normal operation of the
data section of the iCoupler introduces switching transients
on the power supply pins. Bypass capacitors are required for
several operating frequencies. Noise suppression requires a low
ESR, high frequency capacitor; ripple suppression and proper
regulation require a large value capacitor in parallel (see Table 10).
The total lead length between both ends of the capacitor and
the input power supply pin should not exceed 20 mm.
To maximize the effectiveness of external bypass capacitors, the
isoPower dc-to-dc converter is not internally tied to the data
channels, and should be treated as a completely independent
subsystem, except for a UVLO function (see the Undervoltage
Lockout section). This means that power must be applied to VDD
to operate the dc-to-dc converter. Power must also be applied to
VDDL and VDDB to operate the data input and the Channel B
driver output. On the secondary side, the power generated at
the VISO pin must be applied as an input power supply to the
VDDA pin. GNDISO and GNDA must also be connected.
Table 10. Recommended Bypass Capacitors
The ADuM6132 is intended for use in driving low gate
capacitance transistors (200 pF typically). Most high voltage
applications involve larger transistors than this. To accommodate these applications, users can implement a buffer
configuration with the ADuM6132, as shown in Figure 16. In
many cases, this buffer configuration is the least expensive
option to drive high capacitance devices and provides the
greatest amount of design flexibility. The precise buffer/high
Supply
VDD
VDDB
VDDL
VDDA
VISO
Pins
1, 2
7, 8
2, 3
13, 14
15, 16
Bypass Capacitors
0.1 μF, 10 μF
0.1 μF
0.1 μF
0.1 μF
0.1 μF, 10 μF
ADuM6132
VDD
10µF
0.1µF
GND
GND
1
2
ISOLATED
DC-TO-DC
CONVERTER
0.1µF
15
9
VDDL
+5V
16
VIA
3
4
13
ISOLATED
GATE
DRIVE
12
14
VDDB
+15V
0.1µF
GNDISO
IISO
GNDISO
VDDA IDDA
IAVAIL
BUFFER
0.1µF
VOA
CBUF
GNDA
+15V
7
0.1µF
VIB
RG
RBUF
5
NONISOLATED
GATE
DRIVE
CBUF
6
BUFFER
RG
VOB
RBUF
GND
8
GND
VDC–
Figure 16. Typical Application Circuit
Rev. 0 | Page 11 of 16
07393-016
+5V
VDC+
VISO
ADuM6132
VDD
GND
VDDL
VIA
VIB
VOB
VDDB
GND
VISO
GNDISO
GNDA
VDDA
VOA
NC
NC
GNDISO
07393-017
In applications involving high common-mode transients, care
should be taken to ensure that board capacitive coupling across
the isolation barrier is minimized. Furthermore, the board
layout should be designed so that any coupling that does occur
affects all pins on a given component side equally. Failure to
ensure this may cause voltage differentials between pins that
exceed the absolute maximum ratings of the device (see Table 7),
leading to latch-up or permanent damage.
Figure 17. Recommended PCB Layout
UNDERVOLTAGE LOCKOUT
The ADuM6132 has undervoltage lockout (UVLO) circuits on
the VDDL, VDDA, and VDDB supplies. For each supply, the respective
UVLO circuit monitors the supply voltage and takes a predetermined action based on whether the supply voltage is above or
below a given threshold. These thresholds are specified in Table 1.
In the recommended configuration shown in Figure 16, only
two independent supplies are controlled by the user: VDDB and
VDDL/VDD (VDDL = VDD in Figure 16). VDDA is supplied by the
internal dc-to-dc converter via the VISO = VDDA external connection. Nevertheless, the VDDA UVLO functionality is included in
Table 11 to show how the VOA output behaves when the internal
dc-to-dc converter powers on and off.
Table 11. Undervoltage Lockout Functionality1
The ADuM6132 is a power device that dissipates approximately
1 W of power when fully loaded and running at maximum speed.
Because it is not possible to apply a heat sink to an isolation
device, the device depends primarily on heat dissipation into
the PCB through the GND pins. If the device will be used at
high ambient temperatures, provide a thermal path from the
GND pins to the PCB ground plane.
The board layout in Figure 17 shows enlarged pads for Pin 8
(GND) and Pin 9 (GNDISO). Multiple vias should be implemented from the pad to the ground plane. This layout significantly
reduces the temperatures inside the chip. The dimensions of the
expanded pads are left to the discretion of the designer and the
available board space.
THERMAL ANALYSIS
The ADuM6132 consists of several internal die attached to
two lead frame paddles. For the purposes of thermal analysis,
the part is treated as a thermal unit with the highest junction
temperature determining θJA, as shown in Table 2. The value of
θJA is based on measurements taken with the part mounted on
a JEDEC standard 4-layer board with fine width traces and still
air. Under normal operating conditions, the ADuM6132 operates at full load across the full temperature range without derating
the output current. However, following the recommendations in
the PCB Layout section decreases the thermal resistance to the
PCB, allowing increased thermal margin at high ambient
temperatures.
Under VISO output short-circuit conditions, as shown in
Figure 9, the package power dissipation quickly exceeds the safe
operating limit of 1.44 W for ambient temperatures up to 85°C.
At low input voltage, the power dissipation can approach 2 W.
Because internal compensation of the PWM makes low VDD a
worst-case condition, input voltage limiting is not an effective
strategy for protecting the ADuM6132 from output load fault
conditions. Therefore, the preferred protection methods, where
required, are either limiting ambient temperature to 60°C or the
use of a fuse.
User-Provided
Supplies
VDDL
VDDB
H
H
VISO Powered
Supply
VDDA
H
H
H
L
X
L
X
L
X
X
1
Effect
Normal operation.
Internal dc-to-dc converter is
active.
VOA/VOB output logic states
match VIA/VIB input logic states.
Internal dc-to-dc converter is
active but VISO is below UVLO
threshold.
VOA output is driven low.
VOB output operates normally.
Internal dc-to-dc converter is
turned off (VISO = 0).
VOA output is driven low.
VOB output is driven low.
Internal dc-to-dc converter is
turned off (VISO = 0).
VOA output is driven low.
VOB output is driven low.
H: supply voltage > UVLO threshold; L: supply voltage < UVLO threshold;
X: supply voltage level is irrelevant.
When all three supplies are above their respective UVLO
thresholds, the ADuM6132 operates normally. The internal
dc-to-dc converter is active, and both outputs operate as
determined by their respective input logic signals. If either of
the user-provided supplies is below its UVLO threshold, the
ADuM6132 is put into a disabled mode. In this mode, the
internal dc-to-dc converter is turned off and both outputs are
driven low.
The VOB output is driven low by either the VDDL or VDDB
UVLO circuit (whichever is below its threshold). The VOA
output is driven low when the internal dc-to-dc converter is
turned off. The VISO supply voltage drops to 0 V, causing VDDA
to drop also because VISO and VDDA are externally connected.
When VDDA is below its UVLO threshold, the VDDA UVLO
circuit drives VOA low.
Rev. 0 | Page 12 of 16
ADuM6132
100
50%
tPHL
OUTPUT (VOx)
07393-018
tPLH
50%
Figure 18. Propagation Delay Parameters
MAGNETIC FIELD IMMUNITY
The ADuM6132 is extremely immune to external magnetic
fields. The limitation on the ADuM6132 magnetic field immunity
is set by the condition in which induced voltage in the receiving
coil of the transformer is sufficiently large to falsely set or reset
the decoder. The following analysis defines the conditions
under which this may occur.
The pulses at the transformer output have an amplitude greater
than 1.0 V. The decoder has a sensing threshold at approximately
0.5 V, thus establishing a 0.5 V margin in which induced voltages
can be tolerated. The voltage induced across the receiving coil is
given by
V = (−dβ/dt) Σπrn2 ; n = 1, 2, … N
where:
0.1
0.01
Pulse width distortion is the maximum difference between
these two propagation delay values and is an indication of how
accurately the timing of the input signal is preserved.
Channel-to-channel matching refers to the maximum amount
that the propagation delay differs between channels within a
single ADuM6132 component.
1
0.001
1k
10k
100k
1M
10M
MAGNETIC FIELD FREQUENCY (Hz)
100M
Figure 19. Maximum Allowable External Magnetic Flux Density
For example, at a magnetic field frequency of 1 MHz, the
maximum allowable magnetic flux density of 0.2 kgauss
induces a voltage of 0.25 V at the receiving coil. This voltage
is approximately 50% of the sensing threshold and does not
cause a faulty output transition. Similarly, if such an event
occurs during a transmitted pulse (with the worst-case polarity),
the received pulse is reduced from >1.0 V to 0.75 V—still well
above the 0.5 V sensing threshold of the decoder.
The preceding magnetic flux density values correspond to
specific current magnitudes at given distances from the
ADuM6132 transformers. Figure 20 expresses these allowable
current magnitudes as a function of frequency for selected
distances. As shown in Figure 20, the ADuM6132 is extremely
immune and can be affected only by extremely large currents
operated at high frequency and very close to the component.
For example, at a magnetic field frequency of 1 MHz, a 0.5 kA
current would need to be placed 5 mm away from the ADuM6132
to affect the operation of the component.
Given the geometry of the receiving coil in the ADuM6132 and
an imposed requirement that the induced voltage be at most
50% of the 0.5 V margin at the decoder, a maximum allowable
magnetic flux density is calculated, as shown in Figure 19.
MAXIMUM ALLOWABLE CURRENT (kA)
1000
β is the magnetic flux density (gauss).
rn is the radius of the nth turn in the receiving coil (cm).
N is the number of turns in the receiving coil.
DISTANCE = 1m
100
10
DISTANCE = 100mm
1
DISTANCE = 5mm
0.1
0.01
1k
10k
100k
1M
10M
MAGNETIC FIELD FREQUENCY (Hz)
Figure 20. Maximum Allowable Current for Various
Current-to-ADuM6132 Spacings
Rev. 0 | Page 13 of 16
100M
07393-020
INPUT (VIx)
10
07393-019
Propagation delay is a parameter that describes the time it takes
a logic signal to propagate through a component. The propagation delay to a logic low output may differ from the propagation
delay to a logic high output.
MAXIMUM ALLOWABLE MAGNETIC FLUX
DENSITY (kgauss)
PROPAGATION DELAY-RELATED PARAMETERS
ADuM6132
Analog Devices performs accelerated life testing using voltage
levels higher than the rated continuous working voltage. Acceleration factors for several operating conditions are determined.
These factors allow calculation of the time to failure at the actual
working voltage. Table 12 summarizes the recommended peak
working voltages for 50 years and 15 years of service life for
various operating conditions evaluated by Analog Devices. In
many cases, the approved working voltage is higher than the
50-year service life voltage. Operation at these high working
voltages can lead to shortened insulation life in some cases.
Any cross-insulation voltage waveform that does not conform to
Figure 22 or Figure 23 should be treated as a bipolar ac waveform,
and its peak voltage should be limited to the 50-year lifetime
voltage value listed in Table 12. Note that the voltage shown in
Figure 22 is sinusoidal for illustration purposes only. It is meant
to represent any voltage waveform varying between 0 V and
some limiting value. The limiting value can be positive or
negative, but the voltage cannot cross 0 V.
RATED PEAK VOLTAGE
07393-021
All insulation structures eventually break down when subjected
to voltage stress over a sufficiently long period. The rate of insulation degradation depends on the characteristics of the voltage
waveform applied across the insulation. In addition to the testing
performed by the regulatory agencies, Analog Devices conducts
an extensive set of evaluations to determine the lifetime of the
insulation structure within the ADuM6132.
0V
Figure 21. Bipolar AC Waveform
RATED PEAK VOLTAGE
07393-022
INSULATION LIFETIME
In the case of unipolar ac or dc voltage, the stress on the
insulation is significantly lower, which allows operation at
higher working voltages while still achieving a 50-year service
life. The working voltages listed in Table 12 can be applied while
maintaining the 50-year minimum lifetime, provided that the
voltage conforms to either the unipolar ac or dc voltage cases.
0V
The insulation lifetime of the ADuM6132 depends on the
voltage waveform type imposed across the isolation barrier.
The iCoupler insulation structure degrades at different rates
depending on whether the waveform is bipolar ac, unipolar ac,
or dc. Figure 21, Figure 22, and Figure 23 illustrate these
different isolation voltage waveforms.
Figure 22. Unipolar AC Waveform
RATED PEAK VOLTAGE
07393-023
Note that in the presence of strong magnetic fields and high
frequencies, any loops formed by PCB traces may induce
sufficiently large error voltages to trigger the threshold of
succeeding circuitry. Care should be taken in the layout of such
traces to avoid this possibility.
0V
Bipolar ac voltage is the most stringent environment. The goal
of a 50-year operating lifetime under the bipolar ac condition
determines the maximum working voltage recommended by
Analog Devices.
Figure 23. DC Waveform
Table 12. Maximum Continuous Working Voltage1
Parameter
AC Voltage, Bipolar Waveform
AC Voltage, Unipolar Waveform
Basic Insulation
Basic Insulation
DC Voltage Waveform
Basic Insulation
Basic Insulation
1
Peak Voltage
424 V peak
Lifetime
50-year minimum lifetime
800 V peak
660 V peak
15-year minimum lifetime
50-year minimum lifetime
800 V peak
660 V peak
15-year minimum lifetime
50-year minimum lifetime
Refers to continuous voltage magnitude imposed across the isolation barrier. See the Insulation Lifetime section for more details.
Rev. 0 | Page 14 of 16
ADuM6132
OUTLINE DIMENSIONS
10.50 (0.4134)
10.10 (0.3976)
9
16
7.60 (0.2992)
7.40 (0.2913)
1.27 (0.0500)
BSC
0.30 (0.0118)
0.10 (0.0039)
COPLANARITY
0.10
10.65 (0.4193)
10.00 (0.3937)
8
0.51 (0.0201)
0.31 (0.0122)
0.75 (0.0295)
0.25 (0.0098)
2.65 (0.1043)
2.35 (0.0925)
SEATING
PLANE
45°
8°
0°
1.27 (0.0500)
0.40 (0.0157)
0.33 (0.0130)
0.20 (0.0079)
COMPLIANT TO JEDEC STANDARDS MS-013- AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
032707-B
1
Figure 24. 16-Lead Standard Small Outline Package [SOIC_W]
Wide Body
(RW-16)
Dimensions shown in millimeters (inches)
ORDERING GUIDE
Model
ADuM6132ARWZ 1
ADuM6132ARWZ-RL1
1
No. of
Channels
2
2
Output Peak
Current (A)
0.2
0.2
Output
Voltage (V)
15
15
Temperature Range
−40°C to +85°C
−40°C to +85°C
Z = RoHS Compliant Part.
Rev. 0 | Page 15 of 16
Package Description
16-Lead SOIC_W
16-Lead SOIC_W, 13-inch Tape
and Reel Option (1,000 Units)
Package
Option
RW-16
RW-16
ADuM6132
NOTES
©2008 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07393-0-7/08(0)
Rev. 0 | Page 16 of 16
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