TI MAX3222ECDBRG4 3-v to 5.5-v multichannel rs-232 line driver/receiver with â±15-kv esd protection Datasheet

MAX3222E
www.ti.com.......................................................................................................................................... SLLS708A – JANUARY 2006 – REVISED SEPTEMBER 2009
3-V TO 5.5-V MULTICHANNEL RS-232 LINE DRIVER/RECEIVER
WITH ±15-kV ESD PROTECTION
Check for Samples: MAX3222E
FEATURES
1
•
•
•
•
•
•
•
•
•
ESD Protection for RS-232 Bus Pins
– ±15-kV Human-Body Model (HBM)
– ±8-kV IEC61000-4-2, Contact Discharge
– ±15-kV IEC61000-4-2, Air-Gap Discharge
Meets or Exceeds the Requirements of
TIA/EIA-232-F and ITU v.28 Standards
Operates With 3-V to 5.5-V VCC Supply
Operates up to 500 kbit/s
Two Drivers and Two Receivers
Low Standby Current . . . 1 μA Typ
External Capacitors . . . 4 × 0.1 μF
Accepts 5-V Logic Input With 3.3-V Supply
Alternative High-Speed Pin-Compatible Device
(1 Mbit/s) for SNx5C3222E
APPLICATIONS
•
•
•
•
•
•
Battery-Powered Systems
PDAs
Notebooks
Laptops
Palmtop PCs
Hand-Held Equipment
The device meets the requirements of TIA/EIA-232-F
and provides the electrical interface between an
asynchronous communication controller and the
serial-port connector. The charge pump and four
small external capacitors allow operation from a
single 3-V to 5.5-V supply. The device operates at
typical data signaling rates up to 500 kbit/s and a
maximum of 30-V/μs driver output slew rate.
DB, DW, OR PW PACKAGE
(TOP VIEW)
EN
C1+
V+
C1−
C2+
C2−
V−
DOUT2
RIN2
ROUT2
1
20
2
19
3
18
4
17
5
16
6
7
15
14
8
13
9
12
10
11
PWRDOWN
VCC
GND
DOUT1
RIN1
ROUT1
NC
DIN1
DIN2
NC
NC − No internal connection
DESCRIPTION/ORDERING INFORMATION
The MAX3222E consists of two line drivers, two line
receivers, and a dual charge-pump circuit with ±15-kV
ESD protection pin to pin (serial-port connection pins,
including GND).
The MAX3222E can be placed in the power-down mode by setting the power-down (PWRDOWN) input low,
which draws only 1 μA from the power supply. When the device is powered down, the receivers remain active
while the drivers are placed in the high-impedance state. Also, during power down, the onboard charge pump is
disabled; V+ is lowered to VCC, and V– is raised toward GND. Receiver outputs also can be placed in the
high-impedance state by setting enable (EN) high.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006–2009, Texas Instruments Incorporated
MAX3222E
SLLS708A – JANUARY 2006 – REVISED SEPTEMBER 2009.......................................................................................................................................... www.ti.com
ORDERING INFORMATION
TA
PACKAGE
SOIC – DW
0°C to 70°C
SSOP – DB
TSSOP – PW
SOIC – DW
–40°C to 85°C
SSOP – DB
TSSOP – PW
(1)
(2)
(1) (2)
ORDERABLE PART NUMBER
Tube of 25
MAX3222ECDW
Reel of 2000
MAX3222ECDWR
Tube of 70
MAX3222ECDB
Reel of 2000
MAX3222ECDBR
Tube of 70
MAX3222ECPW
Reel of 2000
MAX3222ECPWR
Tube of 25
MAX3222EIDW
Reel of 2000
MAX3222EIDWR
Tube of 70
MAX3222EIDB
Reel of 2000
MAX3222EIDBR
Tube of 70
MAX3222EIPW
Reel of 2000
MAX3222EIPWR
TOP-SIDE MARKING
MAX3222EC
MP222EC
MP222EC
MAX3222EI
MP222EI
MP222EI
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
Table 1. FUNCTION TABLES
XXX
EACH DRIVER (1)
INPUTS
DIN
(1)
PWRDOWN
OUTPUT
DOUT
X
L
Z
L
H
H
H
H
L
H = high level, L = low level, X = irrelevant, Z = high impedance
Table 2. EACH RECEIVER (1)
INPUTS
(1)
2
RIN
EN
OUTPUT
ROUT
H
L
L
H
L
L
X
H
Z
Open
L
H
H = high level, L = low level, X = irrelevant,
Z = high impedance (off),
Open = input disconnected or connected driver off
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MAX3222E
www.ti.com.......................................................................................................................................... SLLS708A – JANUARY 2006 – REVISED SEPTEMBER 2009
LOGIC DIAGRAM (POSITIVE LOGIC)
DIN1
DIN2
13
17
12
8
20
PWRDOWN
DOUT1
DOUT2
Powerdown
1
EN
15
ROUT1
16
RIN1
5 kW
10
ROUT2
9
RIN2
5 kW
Pin numbers are for the DB, DW, and PW packages.
ABSOLUTE MAXIMUM RATINGS (1)
over operating free-air temperature range (unless otherwise noted)
Supply voltage range (2)
VCC
(2)
V+
Positive-output supply voltage range
V–
Negative-output supply voltage range (2)
V+ – V–
Supply voltage difference (2)
VI
Input voltage range
VO
Output voltage range
θJA
Package thermal impedance (3)
Operating virtual junction temperature
Tstg
Storage temperature range
(1)
(2)
(3)
(4)
6
V
–0.3
7
V
0.3
–7
V
13
V
–0.3
6
Receiver
–25
25
Receiver
TJ
MAX
Driver (EN, PWRDOWN)
Driver
(4)
MIN
–0.3
–13.2
13.2
–0.3
VCC + 0.3
DB package
70
DW package
58
PW package
83
–65
UNIT
V
V
°C/W
150
°C
150
°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages are with respect to network GND.
Maximum power dissipation is a function of TJ(max), θJA, and TA. The maximum allowable power dissipation at any allowable ambient
temperature is PD = (TJ(max) – TA)/θJA. Operating at the absolute maximum TJ of 150°C can affect reliability.
The package thermal impedance is calculated in accordance with JESD 51-7.
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3
MAX3222E
SLLS708A – JANUARY 2006 – REVISED SEPTEMBER 2009.......................................................................................................................................... www.ti.com
RECOMMENDED OPERATING CONDITIONS (1)
See Figure 5
MIN NOM MAX UNIT
VCC = 3.3 V
Supply voltage
VCC = 5 V
VIH
Driver and control high-level input voltage
DIN, EN, PWRDOWN
VIL
Driver and control low-level input voltage
DIN, EN, PWRDOWN
VI
Driver and control input voltage
DIN, EN, PWRDOWN
VI
Receiver input voltage
TA
(1)
3
3.3
3.6
4.5
5
5.5
VCC = 3.3 V
VCC = 5 V
2
V
2.4
MAX3222EI
0.8
V
0
5.5
V
–25
25
V
0
70
–40
85
MAX3222EC
Operating free-air temperature
V
°C
Test conditions are C1–C4 = 0.1 μF at VCC = 3.3 V ± 0.3 V; C1 = 0.047 μF, C2–C4 = 0.33 μF at VCC = 5 V ± 0.5 V.
ELECTRICAL CHARACTERISTICS (1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 5)
PARAMETER
II
ICC
(1)
(2)
4
TEST CONDITIONS
Input leakage current (EN, PWRDOWN)
Supply current
No load, PWRDOWN at VCC
Supply current (powered off)
No load, PWRDOWN at GND
MIN
(2)
MAX
±0.01
±1
μA
0.3
1
mA
1
10
μA
TYP
UNIT
Test conditions are C1–C4 = 0.1 μF at VCC = 3.3 V ± 0.3 V; C1 = 0.047 μF, C2–C4 = 0.33 μF at VCC = 5 V ± 0.5 V.
All typical values are at VCC = 3.3 V or VCC = 5 V, and TA = 25°C.
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MAX3222E
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DRIVER SECTION
abc
Electrical Characteristics (1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 5)
PARAMETER
TEST CONDITIONS
TYP
MIN
(2)
MAX
UNIT
VOH
High-level output voltage
DOUT at RL = 3 kΩ to GND,
DIN = GND
5
5.4
V
VOL
Low-level output voltage
DOUT at RL = 3 kΩ to GND,
DIN = VCC
–5
–5.4
V
IIH
High-level input current
VI = VCC
±0.01
±1
μA
IIL
Low-level input current
VI at GND
±0.01
±1
μA
±35
±60
mA
IOS
Short-circuit output current (3)
ro
Output resistance
IOZ
(1)
(2)
(3)
VCC = 3.6 V
VO = 0 V
VCC = 5.5 V
VCC, V+, and V– = 0 V,
Output leakage current
PWRDOWN = GND
VO = ±2 V
300
Ω
10M
VCC = 3 V to 3.6 V,
VO = ±12 V
±25
VCC = 4.5 V to 5.5 V,
VO = ±10 V
±25
μA
Test conditions are C1–C4 = 0.1 μF at VCC = 3.3 V ± 0.3 V; C1 = 0.047 μF, C2–C4 = 0.33 μF at VCC = 5 V ± 0.5 V.
All typical values are at VCC = 3.3 V or VCC = 5 V, and TA = 25°C.
Short-circuit durations should be controlled to prevent exceeding the device absolute power dissipation ratings, and not more than one
output should be shorted at a time.
Switching Characteristics (1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 5)
PARAMETER
TEST CONDITIONS
Maximum data rate
CL = 1000 pF,
One DOUT switching,
RL = 3 kΩ,
See Figure 1
tsk(p)
Pulse skew (3)
CL = 150 pF to 2500 pF,
See Figure 2
RL = 3 kΩ to 7 kΩ,
SR(tr)
Slew rate,
transition region
(see Figure 1)
RL = 3 kΩ to 7 kΩ,
VCC = 3.3 V
(1)
(2)
(3)
MIN
250
TYP
(2)
MAX
UNIT
500
kbit/s
300
ns
CL = 150 pF to 1000 pF
6
30
CL = 150 pF to 2500 pF
4
30
V/μs
Test conditions are C1–C4 = 0.1 μF at VCC = 3.3 V ± 0.3 V; C1 = 0.047 μF, C2–C4 = 0.33 μF at VCC = 5 V ± 0.5 V.
All typical values are at VCC = 3.3 V or VCC = 5 V, and TA = 25°C.
Pulse skew is defined as |tPLH – tPHL| of each channel of the same device.
ESD Protection
TYP
Driver outputs (DOUTx)
Human-Body Model (HBM)
±15
IEC61000-4-2, Air-Gap Discharge
±15
IEC61000-4-2, Contact Discharge
±8
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UNIT
kV
5
MAX3222E
SLLS708A – JANUARY 2006 – REVISED SEPTEMBER 2009.......................................................................................................................................... www.ti.com
RECEIVER SECTION
abc
Electrical Characteristics (1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 5)
PARAMETER
TEST CONDITIONS
VOH
High-level output voltage
IOH = –1 mA
VOL
Low-level output voltage
IOL = 1.6 mA
VCC – 0.6
TYP
(2)
MAX
VCC – 0.1
1.5
2.4
VCC = 5 V
1.8
2.4
Positive-going input threshold voltage
VIT–
Negative-going input threshold voltage
Vhys
Input hysteresis (VIT+ – VIT–)
IOZ
Output leakage current
EN = 1
ri
Input resistance
VI = ±3 V to ±25 V
VCC = 3.3 V
0.6
1.2
VCC = 5 V
0.8
1.5
UNIT
V
0.4
VCC = 3.3 V
VIT+
(1)
(2)
MIN
V
V
V
0.3
V
±0.05
±10
μA
5
7
kΩ
(2)
UNIT
3
Test conditions are C1–C4 = 0.1 μF at VCC = 3.3 V ± 0.3 V; C1 = 0.047 μF, C2–C4 = 0.33 μF at VCC = 5 V ± 0.5 V.
All typical values are at VCC = 3.3 V or VCC = 5 V, and TA = 25°C.
Switching Characteristics (1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TYP
tPLH
Propagation delay time, low- to high-level output
CL = 150 pF, See Figure 3
300
ns
tPHL
Propagation delay time, high- to low-level output
CL = 150 pF, See Figure 3
300
ns
ten
Output enable time
CL = 150 pF, RL = 3 kΩ, See Figure 4
200
ns
tdis
Output disable time
CL = 150 pF, RL = 3 kΩ, See Figure 4
200
ns
tsk(p)
Pulse skew (3)
See Figure 3
300
ns
TYP
UNIT
(1)
(2)
(3)
Test conditions are C1–C4 = 0.1 μF at VCC = 3.3 V ± 0.3 V; C1 = 0.047 μF, C2–C4 = 0.33 μF at VCC = 5 V ± 0.5 V.
All typical values are at VCC = 3.3 V or VCC = 5 V, and TA = 25°C.
Pulse skew is defined as |tPLH – tPHL| of each channel of the same device.
ESD Protection
Receiver inputs (RINx)
6
Human-Body Model (HBM)
±15
IEC61000-4-2, Air-Gap Discharge
±15
IEC61000-4-2, Contact Discharge
±8
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kV
Copyright © 2006–2009, Texas Instruments Incorporated
Product Folder Link(s): MAX3222E
MAX3222E
www.ti.com.......................................................................................................................................... SLLS708A – JANUARY 2006 – REVISED SEPTEMBER 2009
PARAMETER MEASUREMENT INFORMATION
3V
Input
Generator
(see Note B)
1.5 V
RS-232
Output
50 Ω
RL
1.5 V
0V
CL
(see Note A)
tTHL
3V
PWRDOWN
tTLH
VOH
3V
3V
Output
−3 V
−3 V
VOL
TEST CIRCUIT
VOLTAGE WAVEFORMS
SR(tr) +
t
THL
6V
or t
TLH
A.
CL includes probe and jig capacitance.
B.
The pulse generator has the following characteristics: PRR = 250 kbit/s, ZO = 50 Ω, 50% duty cycle, tr ≤ 10 ns,
tf ≤ 10 ns.
Figure 1. Driver Slew Rate
3V
Generator
(see Note B)
RS-232
Output
50 Ω
RL
Input
1.5 V
1.5 V
0V
CL
(see Note A)
tPLH
tPHL
VOH
3V
PWRDOWN
50%
50%
Output
VOL
TEST CIRCUIT
VOLTAGE WAVEFORMS
A.
CL includes probe and jig capacitance.
B.
The pulse generator has the following characteristics: PRR = 250 kbit/s, ZO = 50 Ω, 50% duty cycle, tr ≤ 10 ns,
tf ≤ 10 ns.
Figure 2. Driver Pulse Skew
EN
0V
3V
Input
1.5 V
1.5 V
−3 V
Output
Generator
(see Note B)
50 Ω
tPHL
CL
(see Note A)
tPLH
VOH
50%
Output
50%
VOL
TEST CIRCUIT
VOLTAGE WAVEFORMS
A.
CL includes probe and jig capacitance.
B.
The pulse generator has the following characteristics: ZO = 50 Ω, 50% duty cycle, tr ≤ 10 ns, tf ≤ 10 ns.
Figure 3. Receiver Propagation Delay Times
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MAX3222E
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PARAMETER MEASUREMENT INFORMATION (continued)
VCC
GND
S1
3V
Input
RL
3 V or 0 V
0V
tPZH
(S1 at GND)
CL
(see Note A)
S1 at GND)
VOH
Output
50%
0.3 V
Generator
(see Note B)
1.5 V
tPHZ
Output
EN
1.5 V
50 Ω
tPLZ
(S1 at VCC)
0.3 V
Output
50%
VOL
tPZL
(S1 at VCC)
TEST CIRCUIT
VOLTAGE WAVEFORMS
A.
CL includes probe and jig capacitance.
B.
The pulse generator has the following characteristics: ZO = 50 Ω, 50% duty cycle, tr ≤ 10 ns, tf ≤ 10 ns.
Figure 4. Receiver Enable and Disable Times
8
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MAX3222E
www.ti.com.......................................................................................................................................... SLLS708A – JANUARY 2006 – REVISED SEPTEMBER 2009
APPLICATION INFORMATION
1
EN
2
+
C1
−
3
C3†
+
20
Powerdown
VCC
C1+
V+
GND
19
18
17
C1−
16
5
C2+
−
6
7
−
RIN1
15
C2−
14
V−
ROUT1
NC
+
13
8
DOUT2
9
RIN2
12
5 kW
ROUT2
DOUT1
5 kW
+
C4
+ C
BYPASS
− = 0.1 µF
−
4
C2
PWRDOWN
11
10
DIN1
DIN2
NC
† C3 can be connected to V
CC or GND.
NOTES: A. Resistor values shown are nominal.
B. NC − No internal connection
C. Nonpolarized ceramic capacitors are acceptable. If polarized tantalum or electrolytic capacitors are used, they should be
connected as shown.
VCC vs CAPACITOR VALUES
VCC
3.3 V " 0.3 V
C1
0.1 µF
C2, C3, and C4
0.1 µF
5 V " 0.5 V
0.047 µF
0.33 µF
3 V to 5.5 V
0.1 µF
0.47 µF
Figure 5. Typical Operating Circuit and Capacitor Values
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PACKAGE OPTION ADDENDUM
www.ti.com
16-Jun-2009
PACKAGING INFORMATION
(1)
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
MAX3222ECDB
ACTIVE
SSOP
DB
20
70
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
MAX3222ECDBG4
ACTIVE
SSOP
DB
20
70
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
MAX3222ECDBR
ACTIVE
SSOP
DB
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
MAX3222ECDBRG4
ACTIVE
SSOP
DB
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
MAX3222ECDW
ACTIVE
SOIC
DW
20
25
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
MAX3222ECDWG4
ACTIVE
SOIC
DW
20
25
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
MAX3222ECDWR
ACTIVE
SOIC
DW
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
MAX3222ECDWRG4
ACTIVE
SOIC
DW
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
MAX3222ECPW
ACTIVE
TSSOP
PW
20
70
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
MAX3222ECPWG4
ACTIVE
TSSOP
PW
20
70
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
MAX3222ECPWR
ACTIVE
TSSOP
PW
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
MAX3222ECPWRG4
ACTIVE
TSSOP
PW
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
MAX3222EIDB
ACTIVE
SSOP
DB
20
70
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
MAX3222EIDBG4
ACTIVE
SSOP
DB
20
70
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
MAX3222EIDBR
ACTIVE
SSOP
DB
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
MAX3222EIDBRG4
ACTIVE
SSOP
DB
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
MAX3222EIDW
ACTIVE
SOIC
DW
20
25
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
MAX3222EIDWG4
ACTIVE
SOIC
DW
20
25
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
MAX3222EIDWR
ACTIVE
SOIC
DW
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
MAX3222EIDWRG4
ACTIVE
SOIC
DW
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
MAX3222EIPW
ACTIVE
TSSOP
PW
20
70
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
MAX3222EIPWG4
ACTIVE
TSSOP
PW
20
70
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
MAX3222EIPWR
ACTIVE
TSSOP
PW
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
MAX3222EIPWRG4
ACTIVE
TSSOP
PW
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
The marketing status values are defined as follows:
Addendum-Page 1
Lead/Ball Finish
MSL Peak Temp (3)
PACKAGE OPTION ADDENDUM
www.ti.com
16-Jun-2009
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
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information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Apr-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
MAX3222ECDBR
Package Package Pins
Type Drawing
SPQ
Reel
Reel
Diameter Width
(mm) W1 (mm)
A0 (mm)
B0 (mm)
K0 (mm)
P1
(mm)
W
Pin1
(mm) Quadrant
SSOP
DB
20
2000
330.0
16.4
8.2
7.5
2.5
12.0
16.0
Q1
MAX3222ECDWR
SOIC
DW
20
2000
330.0
24.4
10.8
13.0
2.7
12.0
24.0
Q1
MAX3222ECPWR
TSSOP
PW
20
2000
330.0
16.4
6.95
7.1
1.6
8.0
16.0
Q1
MAX3222EIDBR
SSOP
DB
20
2000
330.0
16.4
8.2
7.5
2.5
12.0
16.0
Q1
MAX3222EIDWR
SOIC
DW
20
2000
330.0
24.4
10.8
13.0
2.7
12.0
24.0
Q1
MAX3222EIPWR
TSSOP
PW
20
2000
330.0
16.4
6.95
7.1
1.6
8.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Apr-2008
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
MAX3222ECDBR
SSOP
DB
20
2000
346.0
346.0
33.0
MAX3222ECDWR
SOIC
DW
20
2000
346.0
346.0
41.0
MAX3222ECPWR
TSSOP
PW
20
2000
346.0
346.0
33.0
MAX3222EIDBR
SSOP
DB
20
2000
346.0
346.0
33.0
MAX3222EIDWR
SOIC
DW
20
2000
346.0
346.0
41.0
MAX3222EIPWR
TSSOP
PW
20
2000
346.0
346.0
33.0
Pack Materials-Page 2
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
0,15 M
15
0,25
0,09
8,20
7,40
5,60
5,00
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
2,00 MAX
0,10
0,05 MIN
PINS **
14
16
20
24
28
30
38
A MAX
6,50
6,50
7,50
8,50
10,50
10,50
12,90
A MIN
5,90
5,90
6,90
7,90
9,90
9,90
12,30
DIM
4040065 /E 12/01
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-150
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
0,65
14
0,10 M
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
8
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064/F 01/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-153
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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