Feb 28, 2011 IR1155S PROGRAMMABLE FREQUENCY, ONE CYCLE CONTROL PFC IC Features • PFC IC with IR proprietary “One Cycle Control” • Continuous conduction mode boost type PFC • Programmable switching frequency (48k-200kHz) • Average current mode control • Output overvoltage protection • Open loop protection • Cycle by cycle peak current limit • VCC under voltage lockout • Programmable soft start • Micropower startup • User initiated micropower “Sleep Mode” • OVP/EN pin internal filtering for higher noise immunity • 1.5A peak gate drive • Latch immunity and ESD protection Description Package The μPFC IR1155 power factor correction IC, based on IR proprietary "One Cycle Control" (OCC) technique, provides for high PF, low THD and excellent DC Bus regulation while enabling drastic reduction in component count, PCB area and design time as compared to traditional solutions. The IC is designed to operate in continuous conduction mode Boost PFC converters with average current mode control over 85-264VAC input line voltage range. Switching frequency can be programmed to anywhere between 48kHz to 200kHz based on the specific application requirement. In addition, IR1155 offers several advanced system-enabling and protective features such as dedicated pin for over voltage protection, cycle by cycle peak current limitation, open loop protection, VCC UVLO, soft-start and micropower startup/sleep-mode with IC current consumption less than 200µA. The sleep mode, invoked by pulling the OVP/EN pin low, enables compliance with standby power requirements mandated by regulations such as Energy Star, Green Power, Blue Angel etc. IR1155 Application Diagram AC LINE VOUT - + AC NEUTRAL 1 2 3 4 COM GATE FREQ VCC ISNS VFB OVP COMP 8 7 VCC 6 5 IR1155S RTN www.irf.com © 2011 International Rectifier IR1155S Qualification Information Qualification Level Moisture Sensitivity Level Machine Model ESD Human Body Model IC Latch-Up Test RoHS Compliant Industrial Comments: This family of ICs has passed JEDEC’s Industrial qualification. IR’s Consumer qualification level is granted by extension of the higher Industrial level. MSL2 260°C (per IPC/JEDEC J-STD-020) Class A (per JEDEC standard JESD22-A115) Class 1B (passes 500V) (per EIA/JEDEC standard EIA/JESD22-A114) Class I, Level A (per JESD78) Yes Absolute Maximum Ratings Parameter Symbol Min. Max. Units VCC Voltage VCC -0.3 20 V FREQ Voltage VFREQ -0.3 6.5 V ISNS Voltage VISNS -10 0.3 V VFB, VOVP -0.3 6.5 V COMP Voltage VCOMP -0.3 6.5 V GATE Voltage VGATE -0.3 18 V ISNS Current IISNS -2 2 mA Junction Temperature TJ -40 150 °C Storage Temperature TS -55 150 °C RθJA 128 °C/W PD 976 mW VFB, OVP Voltage Thermal Resistance Junction to Ambient Package Power Dissipation Remarks TAMB = 25°C Recommended Operating Conditions Recommended operating conditions for reliable operation with margin Parameter Symbol Min. VCC Junction Temperature Switching Frequency Supply Voltage www.irf.com Typ. Max. Units 12 19 V TJ -25 125 °C FSW 48 200 kHz 2 Remarks © 2011 International Rectifier IR1155S Electrical Characteristics The electrical characteristics involve the spread of values guaranteed within the specified supply voltage and junction temperature range TJ from –25 °C to 125°C. Typical values represent the median values, which are related to 25°C. If not otherwise stated, a supply voltage of VCC =15V is assumed for test condition. Supply Section Parameter Symbol Min. Typ. Max. Units VCC ON 10.65 11.3 11.95 V VCC Turn Off Threshold (Under Voltage Lock Out) VCC UVLO 9.2 9.8 10.4 V VCC Turn On/Off Hysteresis VCC HYST 1.5 Operating Current ICC 10 VCC Turn On Threshold V 13 6 Startup Current Sleep Current ICCSTART ISLEEP Remarks mA Cload=1nF, FSW=181kHz 8 mA Standby Mode (Inactive Gate, Inactive Internal Oscillator) VFB<VOLP See State Transition Diagram 175 uA VCC=VCC ON - 0.1V 125 200 uA Sleep Mode (Inactive Gate, Inactive Oscillator) - VOVP<VSLEEP,OFF See State Transition Diagram Sleep Mode Threshold (Enable) VSLEEP,ON 0.80 0.90 1.00 V IC Enable threshold, Bias on OVP pin Sleep Mode Threshold (Disable) VSLEEP,OFF 0.53 0.60 0.67 V IC Disable threshold, Bias on OVP pin www.irf.com 3 © 2011 International Rectifier IR1155S Oscillator Section Parameter Switching Frequency Symbol Min. FSW 48 Typ. Max. Units 200 kHz Oscillator Charge Current IOSC(CHG) 200 µA Oscillator Discharge Current IOSC(DCHG) 6.6 mA Oscillator Peak VOSC PK 4 V Oscillator Valley VOSC VAL 2 V Initial Accuracy FSW ACC Remarks 200khz:C=430pF approx. 48kHz: C=2nF approx. 5 % C=2nF, TA = 25°C 8 % C=500pF, TA = 25°C 1 % 14V < VCC < 19V Voltage Stability VSTAB 0.2 Temperature Stability TSTAB 2 % -25°C ≤ TJ ≤ 125°C FVT 10 % Line & Temperature Total Variation Maximum Duty Cycle DMAX Minimum Duty Cycle DMIN 94 99 % 0 % Pulse Skipping Protection Section Parameter Symbol Min. Typ. Max. Units Open Loop Protection (OLP) VFB Threshold V OLP 17 19 21 % VREF Bias on VFB pin Output Over Voltage Protection (OVP) V OVP 104.5 106.5 108.5 % VREF Bias on OVP/EN pin VOVP(RST) 100.2 102.2 104.2 % VREF Bias on OVP/EN pin V ISNS -0.85 -0.77 -0.69 V -0.2 µA Output Over Voltage Protection (OVP) Reset Peak Current Limit Protection (IPK LMT) ISNS Voltage Threshold OVP Input Bias Current www.irf.com IOVP(Bias) 4 Remarks Bias on ISNS pin © 2011 International Rectifier IR1155S Internal Voltage Reference Section Parameter Symbol Min. Typ. Max. Reference Voltage VREF 4.9 5 5.1 V Line Regulation RREG 10 20 mV Temp Stability TSTAB 0.4 Total Variation ΔVTOT 4.85 Units Remarks TA = 25°C 14 V < VCC < 19V % -25°C ≤ TAMB ≤ 125°C 5.1 V Line & Temperature Voltage Error Amplifier Section Parameter Transconductance Source Current Sink Current Symbol Min. Typ. Max. Units gm 35 50 65 µS IOVEA(SRC) 30 44 58 µA 20 44 90 -57 -43 -30 -90 -43 -20 IOVEA(SNK) µA 35 VCOMP Voltage (Fault) VCOMP FLT 1 1.4 V Effective VCOMP Voltage VCOMP EFF 4.9 5.2 V VFB Input Bias Current IIB(Bias) -0.2 µA Output Low Voltage VOL 0.25 V Output High Voltage VOH 5 5.4 V VCOMP Start Voltage VCOMP START 240 460 mV www.irf.com 5 TAMB = 25°C -25°C ≤TAMB≤ 125°C tSS 340 TAMB = 25°C -25°C ≤TAMB≤ 125°C Soft Start Delay Time 4.6 Remarks msec RGAIN = 1kΩ, CZERO = 0.33uF, CPOLE = 0.01uF @ 100µA steady state current VFB=4.9V © 2011 International Rectifier IR1155S Current Amplifier Section Parameter DC Gain Corner Frequency Input Offset Voltage ISNS Bias Current Blanking Time Symbol Min. Typ. Max. Units Remarks gDC 3.1 V/V fC 5 kHz - Average current mode, Note 1 VIO 4 16 mV Note 1 -13 µA ns IISNS(Bias) -57 TBLANK 220 370 520 Symbol Min. Typ. Max. Units 0.8 V IGATE=200mA 14 V Internal Gate clamp V VCC = 11.5V Gate Driver Section Parameter Gate Low Voltage VGLO Gate High Voltage VGTH 12 13 10 Remarks Rise Time tr 20 ns CLOAD = 1nF Fall Time tf 20 ns CLOAD = 1nF A CLOAD = 10nF, Note 1 V IGATE = 20mA Output Peak Current IOPK Gate Voltage @ Fault VG fault 1.5 0.08 Note 1 – Guaranteed by design, but Not tested in production www.irf.com 6 © 2011 International Rectifier IR1155S Lead Assignments & Definitions Lead Assignment 1 www.irf.com Pin# Symbol Description 1 COM Ground 2 FREQ Frequency Set 3 ISNS Current Sense 4 OVP Output Over Voltage Detect / Enable 5 COMP Voltage Loop Compensation 6 VFB Output Voltage Sense 7 VCC IC Supply Voltage 8 GATE Gate Drive Output 8 2 7 3 6 4 5 7 © 2011 International Rectifier IR1155S Block Diagram FREQ ISNS OSC VBIAS OVP OVP Peak Overcurrent Comparator VOVP Overvoltage Comparator V BIAS V BIAS OSCILLATOR OCP VBIAS SET RESET VISNS(PK) GATE OFF V BIAS SLEEP VSLEEP Enable Comparator (SLEEP MODE) BLANK - MAX DUTY CYCLE LIMIT + OVP V BIAS GATE OFF V BIAS VREF Blanking Pulse at Ton MAX DUTY V BIAS V BIAS Vm VCC VSUMMER VFB RAMP S PWM OFF GATE R1 VCOMP COMP Q 0 RESET UVLO VCC OK VCOMP Discharge VOVP = 106% VREF VREF V BIAS VCC Internal Rail & Precision Reference STNDBY VOLP S1 Q UVLO/SLEEP Open Loop Comparator (Stand-By Mode) R 80% VREF Q VOUV = 50% VREF VOLP = 19%VREF 250mV VCOMP Discharge Threshold Comparator VSLEEP 250mV www.irf.com SLEEP (POWER OFF) 8 COM © 2011 International Rectifier IR1155S State & Transition Diagrams Note: Soft-Start & Normal modes are essentially the same (differentiation above is for purpose of clarity only) www.irf.com 9 © 2011 International Rectifier IR1155S Timing Diagrams 106.5% VREF 102.2% V REF 100% VREF 19% VREF STAND_BY (OLP) SOFT START OVP NORMAL STAND-BY (OLP) Voltage on VCC pin Output Protection VCC(ON) VCC(UVLO) UVLO NORMAL UVLO VCC Undervoltage Lockout www.irf.com 10 © 2011 International Rectifier IR1155S IR1155 General Description The μPFC IR1155 IC is intended for power factor correction in continuous conduction mode Boost PFC converters operating at fixed switching frequency with average current mode control. The switching frequency is programmable any where from 48kHz to 200khz. The IC operates according to IR's proprietary "One Cycle Control" (OCC) PFC algorithm, which is based on the resettable integrator principle. When operating a AC-DC Boost converter, power factor correction can be achieved using this algorithm without AC input line sensing. Feature set The IR1155 offers a host of advanced features and system protections functions, which makes it the most feature-intensive IC in PFC market in a compact 8-pin package. User-Programmable Switching Frequency IR1155 IC operates under fixed switching frequency. The switching frequency is userprogrammed by inserting a capacitor between FREQ & COM pins. A pair of current sources inside the IC source/sink current in/out of the capacitor alternately thus generating a constant-slope sawtooth ramp signal between a pre-determined peak & valley voltage pair (typically between 2V to 4V). This saw-tooth signal is the oscillator signal of the IC. The frequency of operation of the IC can be programmed anywhere between 48kHz and 200kHz by suitably sizing the capacitor. The oscillator signal is a key control signal and is used by the resettable integrator block of the IC to generate the internal PWM ramp every switching cycle. Theory of Operation The OCC algorithm works using two loops - a slow outer voltage loop and a fast inner current loop. The outer voltage loop monitors the VFB pin to maintain regulation of boost converter output voltage and generates a constant error signal. The inner current loop exploits the embedded input voltage information in the boost converter duty cycle to generate a current reference for power factor correction. The combination of the two control elements forces the amplitude and shape of the input current to be proportional to and in phase with the input voltage while maintaining output voltage regulation. This is true so long as operation in continuous conduction mode is maintained. Average current mode operation is envisaged by filtering the switching frequency ripple from the current sense signal in the current loop using an on-chip filter. IC Supply Circuit & Low start-up current The IR1155 UVLO circuit maintains the IC in UVLO mode during start-up if VCC pin voltage is less than the VCC turn-on threshold, VCC,ON and current consumption is less than ICC,START. Should VCC pin voltage should drop below UVLO threshold VCC, UVLO anytime after start-up, the IC is pushed back into UVLO mode (VCOMP pin is discharged) and VCC pin has to exceed VCC,ON again to re-start operation. It is noted that there is no internal clamping of the VCC pin. The IC determines the boost converter instantaneous duty cycle using the voltage feedback loop error signal Vm and the current sense signal VISNS, which is the voltage at the current sense pin of the IC. The PWM ramp is generated using a resettable integrator that tracks Vm every switching cycle. The current sense signal is amplified by the current amplifier averaged to remove the ripple component and fed into the summing node where it is subtracted from the voltage error signal, Vm. The resulting voltage (Vm - gDC.VISNS) is compared with the PWM ramp signal by the PWM comparator to determine the gate drive duty cycle. The instantaneous duty cycle is mathematically given by: D = (Vm - gDC.VISNS) /Vm A more detailed description of IR1155 theory of operation is available in Application Note. www.irf.com User initiated Micropower Sleep mode The IC can be actively pushed into a micropower sleep mode where current consumption is less than ICC,SLEEP by pulling OVP/EN pin below the Sleep threshold, VSLEEP(OFF), even while VCC is above VCC,ON. This allows the user to disable PFC during application stand-by situations in order to meet regulations (Blue Angel, Green Power etc). When OVP/EN pin is pulled low, the VCOMP pin of the IC is actively discharged as the IC is relegated to the Sleep mode. This enables the IC to go through softstart when the IC is re-enabled. Since VSLEEP(OFF) is less than 1V, even logic level signals can be employed to disable and enable the IC. 11 © 2011 International Rectifier IR1155S IR1155 General Description - Soft-current limit is an output voltage fold-back type protection feature that is encountered when the RMS current in the PFC converter exceeds a certain magnitude that causes the internal error signal of the voltage feedback, Vm to saturate at its highest value. Amplitude of Vm signal is directly proportional to the RMS input current admitted into the PFC converter. In effect, once Vm saturates, the maximum RMS current admissible into the PFC converter has been encountered. Any attempt to increase the RMS current beyond this limit causes the IC to limit the duty cycle delivered to the PFC converter, which then has the effect of causing the DC bus voltage to droop i.e. output voltage folds-back. The current level at which Vm saturates is closely related to the value of the current sense resistor selected for the PFC converter. In one way, this feature can be perceived to offer an overpower limitation of sorts at the conditions at which current sense design is performed (minimum VAC & maximum output power). For details, please refer to IR1155 Application Note. Programmable Soft Start The soft start process controls the rate of rise of the voltage feedback loop error signal thus providing a linear control on RMS input current that the PFC converter will admit. The soft start time is essentially controlled by voltage error amplifier compensation components selected and is therefore user programmable to some degree based on desired loop crossover frequency. Gate Drive Capability The gate drive output stage of the IC is a totem pole driver with 1.5A peak current drive capability. The gate drive is internally clamped at 13V (Typ). Gate drive buffer circuits can be easily driven with the GATE pin of the IC to suit any system power level. System Protection Features IR1155 protection features include DC bus Overvoltage protection (OVP) via a dedicated pin, Open-loop protection (OLP), Cycle-by-cycle peak current limit (IPK LIMIT), Soft-current limit and VCC under voltage lock-out (UVLO). - Cycle-by-cycle peak current limit protection instantaneously turns-off the gate output whenever the ISNS pin voltage exceeds VISNS(PK) threshold in magnitude. The gate drive output is re-enabled only after the magnitude of the ISNS pin voltage drops below the VISNS(PK) threshold. It is clarified that even though the IC operates based on average current mode control, since the averaging circuit is decoupled from the peak current limit comparator input, the IC is still able to provide instantaneous response to a system overcurrent condition. This protection feature incorporates a leading edge blanking circuit following the comparator to improve noise immunity. - Overvoltage voltage protection (OVP) feature in IR1155 is achieved using a dedicated pin called the OVP/EN pin. The input of OVP comparator is connected the OVP pin. When the OVP pin voltage exceeds VOVP, an overvoltage situation is detected and the gate drive is immediately terminated. The gate drive is re-enabled only after OVP pin voltage drops below VOVP(RST). The use of a dedicated OVP/EN pin ensures that the system is protected from catastrophic overvoltages, even if the feed-back loop (connected to the VFB pin) encounters any failure. This ensures the best possible system overvoltage protection against extremes of situations. - VCC Under Voltage Lockout protection maintains the IC in a low current consumption, UVLO mode during start-up if VCC pin voltage is less than the VCC turn-on threshold, VCC,ON. In UVLO mode the current consumption is less than ICC,START which is typically about 200uA. Should VCC pin voltage should drop below UVLO threshold VCC, UVLO anytime after start-up, the IC is pushed back into UVLO mode (VCOMP pin is discharged) and VCC pin has to exceed VCC,ON again to re-start operation. - Open Loop Protection (OLP) is activated whenever the VFB pin voltage falls below VOLP threshold. The gate drive is then immediately disabled, VCOMP is actively discharged and the IC is pushed into Stand-by mode. The IC will restart (with soft-start) once the VFB pin voltage exceeds VOLP again. There is no voltage hysteresis associated with this feature. During start-up the IC is held in Stand-by until this pin exceeds VOLP. www.irf.com 12 © 2011 International Rectifier IR1155S IR1155 Pin Description The FREQ-COM loop represents yet another very important control loop to the IC and hence a dedicated PCB trace loop is recommended in layout (star-connection to GND potential) for noise free, stable operation. Pin COM: This is ground potential pin of the IC. All internal devices are referenced to this point. A star-connection point, very close to this pin, is recommended in PCB lay-out in order to reference the return traces of the various control loops to the COM potential of the IC. Pin OVP/EN: The OVP/EN pin is connected to the input of the overvoltage comparator and is used to detect output overvoltage situations. The output voltage information is communicated to the OVP pin using a resistive divider. This pin also serves the second purpose of an ENABLE pin. The OVP/EN pin can be used to activate the IC into “micropower sleep” mode by pulling the voltage on this pin below the VSLEEP threshold. Pin COMP: External circuitry from this pin to ground compensates the system voltage loop and programs the soft start time. The COMP pin is essentially the output of the voltage error amplifier. VCOMP is actively discharged using an internal switch & resistance inside the IC whenever the IC is pushed into Stand-by mode (Open Loop Condition) or UVLO/Sleep mode. The IC is designed not to start-up (from UVLO, Sleep or Stand-by modes) when there is a pre-bias on VCOMP pin that is greater than VCOMP,START. The VCOMP-COM loop represents a very important control loop to the IC and hence a dedicated PCB trace loop is recommended for layout (starconnection to GND potential) for noise free, stable operation. Pin VFB: The converter output voltage is sensed via a resistive divider and fed into this pin. VFB pin is the inverting input of the output voltage error amplifier. The non-inverting input of this amplifier is connected to an internal 5V reference. The impedance of the divider string must be low enough that it does not introduce substantial error due to the input bias currents of the amplifier, yet high enough to minimize power dissipation. Typical value of external divider impedance will be 1MΩ. VFB pin is also the inverting input to the Open Loop comparator. The IC is held in Stand-by Mode whenever VFB pin voltage is below VOLP threshold. Pin ISNS: ISNS pin is the inverting input to the current sense amplifier of the IC. The voltage at this pin is the negative voltage drop sensed across the system current sense resistor and thus represents the inductor current sense signal to the IC for determining gate drive duty cycle. ISNS pin is also the inverting input to the cycle-by-cycle peak current limit comparator. Whenever this pin voltage exceeds VISNS(PK) threshold in magnitude, the gate drive is instantaneously disabled. Any external filtering of the ISNS pin must be performed carefully in order to ensure that the integrity of the current sense signal is maintained for cycle-by-cycle protection. Pin VCC: This is the supply voltage pin of the IC and sense node for the under-voltage lock out circuit. It is possible to turn off the IC by pulling this pin below the minimum turn off threshold voltage, VCC,UVLO without damage to the IC. This pin is not internally clamped. Pin GATE: This is the gate drive output of the IC. This drive voltage is internally clamped to 13V(Typ) and provides a drive current of ±1.5A peak with matched rise and fall times. Pin FREQ: This is the user-programmable frequency pin. The switching frequency is programmed by inserting a capacitor between FREQ & COM pins. A pair of current sources inside the IC source/sink current in/out of the capacitor alternately thus generating a constantslope saw-tooth ramp signal between a predetermined peak & valley voltage pair (typically between 2V to 4V). This saw-tooth signal is the oscillator signal of the IC. The frequency of operation of the IC can be programmed anywhere between 48kHz and 200kHz by suitably sizing the capacitor. www.irf.com 13 © 2011 International Rectifier IR1155S IR1155 Modes of operation (refer to States & Transitions Diagram) UVLO/Sleep Mode: The IC is in the UVLO/Sleep mode when either the VCC pin voltage is below VCC,UVLO and/or the OVP/EN pin voltage is below VSLEEP. The UVLO/Sleep mode is accessible from any other state of operation. This mode can be actively invoked by pulling the OVP/EN pin below the Sleep threshold VSLEEP even if VCC pin voltage is above VCC,ON. In the UVLO/Sleep state, the gate drive circuit is inactive, most of the internal circuitry is unbiased and the IC draws a quiescent current of ISLEEP which is typically 200uA or less. Also, the internal logic of the IC ensures that whenever the UVLO/Sleep mode is actively invoked, the COMP pin is actively discharged below VCOMP,START prior to entering the sleep mode, in order to facilitate soft-start upon resumption of operation. For all practical purposes, the Soft-start mode of the IC is the same as the Normal mode (only difference being that the DC bus voltage is approaching the regulation point). All protection functions of the IC are active during soft-start mode. Normal Mode: The IC enters the normal operating mode seamlessly following conclusion of soft-start. At this point the DC bus is well regulated and all protection functions of the IC are active. If, from the normal mode, the IC is pushed into either a Stand-by mode or Sleep mode then COMP pin is actively discharged below VCOMP,START and system will go through soft-start upon resumption of operation. OVP Mode: The IC enters OVP fault mode whenever an overvoltage condition is detected. A system overvoltage condition is recognized when OVP/EN pin voltage exceeds VOVP threshold. When this happens the IC immediately disables the gate drive. The gate drive is re-enabled only when OVP/EN pin voltage is less than VOVP(RST) threshold. This state is accessible from both the soft start and normal modes of operation. Stand-by Mode: The IC is placed in Stand-by mode whenever an Open-loop situation is detected. An open-loop situation is sensed anytime VFB pin voltage is less than VOLP. All internal circuitry is biased in the Stand-by Mode, but the gate is inactive and the IC draws a few mA of current. This state is accessible from any other state of operation of the IC. COMP pin is actively discharged to below VCOMP,START whenever this state is entered from normal operation in order to facilitate soft-start upon resumption of operation. IPK LIMIT Mode: The IC enters IPK LIMIT fault mode whenever the magnitude of ISNS pin voltage exceeds the VISNS(PK) threshold triggering cycle-bycycle peak over current protection. When this happens, the IC immediately disables the gate drive. Gate drive is re-enabled when magnitude of ISNS pin voltage drops below VISNS(PK) threshold. This state is accessible from both the soft start and normal modes of operation. Soft Start Mode: During system start-up, the softstart mode is activated once the VCC voltage has exceeded VCC,ON, the VFB pin voltage has exceeded VOLP and OVP pin voltage has exceeded VSLEEP(ON). The soft start time is the time required for the VCOMP voltage to charge through its entire dynamic range i.e. through VCOMP,EFF. As a result, the soft-start time is dependent upon the component values selected for compensation of the voltage loop on the COMP pin. As VCOMP voltage raises gradually, the IC allows a higher and higher RMS current into the PFC converter. This controlled increase of the input current amplitude contributes to reducing system component stress during startup. It is clarified that, during soft-start, the IC is capable of full duty cycle modulation (from 0% to MAX DUTY), based on the instantaneous ISNS signal from system current sensing. . www.irf.com 14 © 2011 International Rectifier IR1155S 12.0 V 10 VCC UVLO Thresholds 11.5 V ISUPPLY (mA) 1 0.1 11.0 V VCC UV+ 10.5 V VCC UV- 10.0 V 9.5 V 0.01 7.0 V 9.0 V 11.0 V 13.0 V 15.0 V 9.0 V -50 °C 17.0 V Supply voltage Figure 1: Supply Current vs. Supply Voltage 50 °C 100 °C Temperature 150 °C Figure 2: Undervoltage Lockout vs. Temperature Icc @ CLOAD=1nF ICCSTART and ISLEEP 9.7 170.0 9.6 ISLEEP 150.0 9.5 9.4 Current (uA) ICC Supply Current (mA) 0 °C 9.3 9.2 9.1 ICCSTART 130.0 110.0 90.0 9.0 70.0 8.9 8.8 8.7 -50 °C 50.0 -50 °C 0 °C 50 °C 100 °C Temperature 150 °C Figure 3: Icc Current vs. Temperature (@181kHz frequency) www.irf.com 0 °C 50 °C 100 °C 150 °C Temperature Figure 4: Startup Current and Sleep Current vs. Temperature 15 © 2011 International Rectifier IR1155S 5.05 180.0 160.0 140.0 CT=500pF Reference Voltage (V) Switching Frequency (KHz) 200.0 CT=2nF 120.0 100.0 80.0 60.0 5.03 5.01 4.99 4.97 40.0 20.0 -50 °C 0 °C 50 °C 100 °C 4.95 -50 °C 150 °C 0 °C Temperature Error Amplifier Source/Sink Current (uA) EA Transconductance gm (uS) 52.0 50.0 48.0 46.0 44.0 42.0 50 °C 100 °C 150 °C 80.0 70.0 Source |Sink| 60.0 50.0 40.0 30.0 20.0 10.0 -50 °C 0 °C 50 °C 100 °C 150 °C Temperature Temperature Figure 8: Voltage Error Amplifier Source & Sink Current vs. Temperature Figure 7: Voltage Error Amplifier Transconductance vs. Temperature www.irf.com 150 °C Figure 6: Reference Voltage vs. Temperature 54.0 0 °C 100 °C Temperature Figure 5: Switching Frequency vs. Temperature 40.0 -50 °C 50 °C 16 © 2011 International Rectifier 3.30 -0.5 Peak Current Limit Threshold (V) Current Sense Amplifier DC Gain gDC (V/V) IR1155S 3.25 3.20 3.15 3.10 3.05 3.00 -50 °C 0 °C 50 °C 100 °C -0.6 -0.7 -0.8 -0.9 -1.0 -50 °C 150 °C 0 °C Temperature Figure 9: Current Amplifier DC Gain vs. Temperature 150 °C Frequency vs. CT VOVP 200.00 VOVP(RST) 180.00 Frequency (KHz) OVP Threshold (%Vref) 100 °C Figure 10: Peak Current Limit Threshold VISNS(PK) vs. Temperature 1.10 1.08 50 °C Temperature 1.06 1.04 1.02 160.00 140.00 120.00 100.00 80.00 60.00 40.00 1.00 -50 °C 400 0 °C 50 °C 100 °C 150 °C 650 900 1150 1400 1650 1900 CT (pF) Temperature Figure 12: Oscillator Frequency vs. Programming Capacitor Figure 11: Over Voltage Protection Thresholds vs. Temperature www.irf.com 17 © 2011 International Rectifier IR1155S Package Details: SOIC8N www.irf.com 18 © 2011 International Rectifier IR1155S Tape and Reel Details: SOIC8N LOADED TAPE FEED DIRECTION A B H D F C NOTE : CONTROLLING DIM ENSION IN M M E G CARRIER TAPE DIMENSION FOR Metric Code Min Max A 7.90 8.10 B 3.90 4.10 C 11.70 12.30 D 5.45 5.55 E 6.30 6.50 F 5.10 5.30 G 1.50 n/a H 1.50 1.60 8SOICN Imperial Min Max 0.311 0.318 0.153 0.161 0.46 0.484 0.214 0.218 0.248 0.255 0.200 0.208 0.059 n/a 0.059 0.062 F D C B A E G H REEL DIMENSIONS FOR 8SOICN Metric Code Min Max A 329.60 330.25 B 20.95 21.45 C 12.80 13.20 D 1.95 2.45 E 98.00 102.00 F n/a 18.40 G 14.50 17.10 H 12.40 14.40 www.irf.com 19 Imperial Min Max 12.976 13.001 0.824 0.844 0.503 0.519 0.767 0.096 3.858 4.015 n/a 0.724 0.570 0.673 0.488 0.566 © 2011 International Rectifier IR1155S Part Marking Information www.irf.com 20 © 2011 International Rectifier IR1155S Ordering Information Base Part Number Package Type IR1155S SOIC8N Standard Pack Complete Part Number Form Quantity Tube/Bulk 95 IR1155SPBF Tape and Reel 2500 IR1155STRPBF The information provided in this document is believed to be accurate and reliable. However, International Rectifier assumes no responsibility for the consequences of the use of this information. International Rectifier assumes no responsibility for any infringement of patents or of other rights of third parties which may result from the use of this information. No license is granted by implication or otherwise under any patent or patent rights of International Rectifier. The specifications mentioned in this document are subject to change without notice. This document supersedes and replaces all information previously supplied. For technical support, please contact IR’s Technical Assistance Center http://www.irf.com/technical-info/ WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245 Tel: (310) 252-7105 www.irf.com 21 © 2011 International Rectifier