Vishay DG405DY Low-power, high-speed cmos analog switch Datasheet

DG401, DG403, DG405
Vishay Siliconix
Low-Power, High-Speed CMOS Analog Switches
DESCRIPTION
FEATURES
The DG401, DG403, DG405 monolithic analog switches
were designed to provide precision, high performance
switching of analog signals. Combining low power (0.35 µW,
typ.) with high speed (tON: 75 ns, typ.), the DG401 series is
ideally suited for portable and battery powered industrial and
military applications.
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Built on the Vishay Siliconix proprietary high-voltage
silicon-gate process to achieve high voltage rating and
superior switch on/off performance, break-before-make is
guaranteed for the SPDT configurations. An epitaxial layer
prevents latchup.
44 V supply max. rating
± 15 V analog signal range
On-resistance - RDS(on): 30 Ω
Low leakage - ID(on): 40 pA
Fast switching - tON: 75 ns
Ultra low power requirements - PD: 0.35 µW
TTL, CMOS compatible
Single supply capability
Compliant to RoHS directive 2002/95/EC
BENEFITS
• Wide dynamic range
• Break-before-make switching action
• Simple interfacing
Each switch conducts equally well in both directions when
on, and blocks up to 30 V peak-to-peak when off. Onresistance is very flat over the full ± 15 V analog range,
rivaling JFET performance without the inherent dynamic
range limitations.
APPLICATIONS
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The three devices in this series are differentiated by the type
of switch action as shown in the functional block diagrams.
Audio and video switching
Sample-and-hold circuits
Battery operation
Test equipment
Communications systems
PBX, PABX
FUNCTIONAL BLOCK DIAGRAM AND PIN CONFIGURATION
DG401
DG401
LCC
Dual-In-Line and SOIC
NC
D1
NC
NC
NC
NC
NC
NC
D2
1
16
S1
2
15
IN1
3
14
4
13
5
12
6
11
7
8
Key
3
2
NC
1
S1
20
IN1
19
NC
4
18
V-
GND
NC
5
17
GND
VL
NC
6
16
NC
V-
V+
NC
7
NC
8
10
IN2
9
S2
15
14
9
NC
Top View
D1
10
11
D2
NC
12
S2
13
VL
V+
Two SPST Switches per Package
TRUTH TABLE
Logic
Switch
0
OFF
1
ON
Logic "0" ≤ 0.8 V
Logic "1" ≥ 2.4 V
IN2
Top View
* Pb containing terminations are not RoHS compliant, exemptions may apply
Document Number: 70049
S09-2561-Rev. I, 30-Nov-09
www.vishay.com
1
DG401, DG403, DG405
Vishay Siliconix
FUNCTIONAL BLOCK DIAGRAM AND PIN CONFIGURATION
DG403
DG403
LCC
Dual-In-Line and SOIC
D1
NC
D3
S3
S4
D4
NC
D2
NC D1 NC
16 S1
1
2
15
3
14
4
13
5
12
IN1
Key
V+
11
7
10
IN2
8
9
S2
1
20
18
V-
S3
5
17
GND
NC
6
16
NC
S4
D4
7
15
VL
8
14
V+
9
10
11
12
NC D2 NC
Top View
DG405
DG405
16 S1
2
15
D3
3
14
S3
4
13
S4
5
12
D4
NC
D2
6
11
NC D1 NC
Key
3
IN1
Logic
SW1, SW2
0
OFF
SW3, SW4
ON
1
ON
OFF
Logic "0" ≤ 0.8 V
Logic "1" ≥ 2.4 V
13
IN2
2
1
S1
20
IN1
19
Two DPST Switches per Package
D3
4
18
V-
GND
S3
5
17
GND
16
Switch
NC
6
Logic
VL
NC
0
OFF
V+
S4
7
15
VL
1
ON
8
14
10
IN2
8
9
S2
D4
9
10
11
NC D2 NC
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2
TRUTH TABLE
V-
7
Top View
Two SPDT Switches per Package
LCC
1
NC
S2
Top View
Dual-In-Line and SOIC
D1
19
4
VL
6
2
IN1
D3
VGND
3
S1
12
S2
V+
TRUTH TABLE
Logic "0" ≤ 0.8 V
Logic "1" ≥ 2.4 V
13
IN2
Top View
Document Number: 70049
S09-2561-Rev. I, 30-Nov-09
DG401, DG403, DG405
Vishay Siliconix
ORDERING INFORMATION
Temp. Range
Package
Part Number
16-Pin Plastic DIP
DG401DJ
DG401DJ-E3
16-Pin Narrow SOIC
DG401DY
DG401DY-T1
DG401DY-E3
DG401DY-T1-E3
16-Pin Plastic DIP
DG403DJ
DG403DJ-E3
16-Pin Narrow SOIC
DG403DY
DG403DY-E3
DG403DY-T1
DG403DY-T1-E3
16-Pin Plastic DIP
DG405DJ
DG405DJ-E3
16-Pin Narrow SOIC
DG405DY
DG405DY-E3
DG405DY-T1
DG405DY-T1-E3
DG401
- 40 °C to 85 °C
DG403
- 40 °C to 85 °C
DG405
- 40 °C to 85 °C
ABSOLUTE MAXIMUM RATINGS
Parameter
Limit
V+ to VGND to V-
25
(GND - 0.3) to (V+) + 0.3
VL
Current (Any Terminal) Continuous
30
Current, S or D (Pulsed 1 ms, 10 % Duty)
100
Power Dissipation (Package)b
V
(V-) - 2 to (V+) + 2
or 30 mA, whichever occurs first
Digital Inputsa, VS, VD
Storage Temperature
Unit
44
(DJ, DY Suffix)
- 65 to 125
16-Pin Plastic DIPc
450
16-Pin SOICd
600
mA
°C
mW
Notes:
a. Signals on SX, DX, or INX exceeding V+ or V- will be clamped by internal diodes. Limit forward diode current to maximum current ratings.
b. All leads welded or soldered to PC board.
c. Derate 6 mW/°C above 75 °C.
d. Derate 7.6 mW/°C above 75 °C.
Document Number: 70049
S09-2561-Rev. I, 30-Nov-09
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DG401, DG403, DG405
Vishay Siliconix
SPECIFICATIONSa
D Suffix
- 40 °C to 85 °C
Test Conditions
Unless Specified
V+ = 15 V, V- = - 15 V
Parameter
Analog Switch
Symbol
Analog Signal Rangee
VANALOG
Drain-Source
On-Resistance
RDS(on)
Δ Drain-Source
On-Resistance
ΔRDS(on)
IS(off)
Switch Off Leakage Current
ID(off)
Channel On Leakage Current
ID(on)
VL = 5 V, VIN = 2.4 V, 0.8 Vf
Temp.b
IS = - 10 mA, VD = ± 10 V
V+ = 13.5 V, V- = - 13.5 V
IS = - 10 mA, VD = ± 5 V, 0 V
V+ = 16.5 V, V- = - 16.5 V
Room
Full
30
45
55
Room
Full
3
3
5
Room
Hot
Room
Hot
- 0.01
V+ = 16.5 V, V- = - 16.5 V
VD = ± 15.5 V, VS = ± 15.5 V
V+ = 16.5 V, V- = - 16.5 V
VS = VD = ± 15.5 V
Room
Hot
Typ.c
Full
Min.d
- 15
Max.d
Unit
15
V
- 0.5
-5
- 0.5
-5
0.5
5
0.5
5
- 0.04
-1
- 10
1
10
Full
0.005
-1
1
Full
0.005
-1
1
- 0.01
Ω
nA
Digital Control
Input Current VIN Low
IIL
Input Current VIN High
IIH
VIN under test = 0.8 V
All Other = 2.4 V
VIN under test = 2.4 V
All Other = 0.8 V
µA
Dynamic Characteristics
Turn-On Time
tON
75
150
Turn-Off Time
Break-Before-Make
Time Delay (DG403)
RL = 300 Ω, CL = 35 pF
See Figure 2
Room
tOFF
Room
30
100
tD
RL = 300 Ω, CL = 35 pF
Room
35
Q
CL = 10 nF
Vgen = 0 V, Rgen = 0 Ω
Room
60
OIRR
XTALK
RL = 100 Ω, CL = 5 pF
f = 1 MHz
Charge Injection
Off Isolation Reject Ratio
Channel-to-Channel Crosstalk
Source Off Capacitance
CS(off)
Drain Off Capacitance
CD(off)
Channel On Capacitance
f = 1 MHz, VS = 0 V
CD, CS(on)
Room
72
Room
90
Room
12
Room
12
Room
39
Room
Full
Room
Full
Room
Full
Room
Full
0.01
ns
5
pC
dB
pF
Power Supplies
Positive Supply Current
I+
Negative Supply Current
I-
Logic Supply Current
IL
Ground Current
IGND
V+ = 16.5 V, V- = - 16.5 V
VIN = 0 or 5 V
- 0.01
1
5
-1
-5
0.01
- 0.01
1
5
µA
-1
-5
Notes:
a. Refer to PROCESS OPTION FLOWCHART.
b. Room = 25 °C, Full = as determined by the operating temperature suffix.
c. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
d. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this datasheet.
e. Guaranteed by design, not subject to production test.
f. VIN = input voltage to perform proper function.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
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Document Number: 70049
S09-2561-Rev. I, 30-Nov-09
DG401, DG403, DG405
Vishay Siliconix
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
3.5
7
V+ = 15 V
V- = -15 V
6
3
SW1, 2
5
2.5
V T (V)
V TH (V)
VL = 7 V
4
SW3, 4
3
2
1.5
2
1
1
0.5
0
VL = 5 V
0
0
2
4
6
8
10
12
14
16
18
5
10
15
20
VL - Logic Supply (V)
35
Input Switching Threshold vs. Supply Voltages
60
50
V+ = 15 V, V- = - 15 V
VL = 5 V
45
R DS(on) - Drain-Source On-Resistance (Ω)
R DS(on) - Drain-Source On-Resistance (Ω)
30
(V+)
Input Switching Threshold vs. Logic Supply Voltage
40
35
85 °C
30
25 °C
25
0 °C
20
15
- 40 °C
10
5
0
- 15
TA = 25 °C
50
±6V
± 10 V
± 12 V
± 15 V
± 20 V
40
30
± 22 V
20
10
- 10
-5
0
5
10
15
- 25
- 15
VD - Drain Voltage (V)
-5
5
15
26
VD - Drain Voltage (V)
RDS(on) vs. VD and Temperature
RDS(on) vs. VD and Power Supply Voltage
100
50
TA = 25 °C
CL = 10 nF
90
40
7.5 V
80
30
70
12 V
50
15 V
40
1 nF
20
10 V
60
Q (pC)
R DS(on) - Drain-Source On-Resistance (Ω)
25
10
0
20 V
100 pF
22 V
30
- 10
20
- 20
10
0
5
10
15
20
25
VD - Drain Voltage (V)
RDS(on) vs. VD and Power Supply Voltage (V- = 0 V)
Document Number: 70049
S09-2561-Rev. I, 30-Nov-09
- 30
- 15
- 10
-5
0
5
10
15
VS - Source Voltage (V)
Charge Injection vs. Analog Voltage
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DG401, DG403, DG405
Vishay Siliconix
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
1000p
40
V+ = 15 V
V- = -15 V
VL = 5 V
VD = ± 14 V
ID (off)
20
ID (on)
IS (off)
I S, I D (pA)
100p
I D (off)
IS (off)
0
ID (on)
- 20
- 40
10p
- 60
ID (off)
- 80
1p
- 40
- 20
0
20
40
60
- 100
- 15
80
Temperature (°C)
- 10
-5
0
5
10
15
VD or V S - Drain or Source Voltage (V)
Leakage Current vs. Temperature
100 nA
Leakage Current vs. Analog Voltage
120
I-
V+ = 15 V
V- = - 15 V
VL = 5 V
I+
V+ = 15 V
V- = - 15 V
VL = 5 V
100
tON
1 nA
t ON , t OFF (ns)
I+, I-, IL (A)
IL
100 pA
80
VS = 10 V
VS = - 10 V
60
tOFF
VS = 10 V
40
10 pA
20
VS = - 10 V
1 pA
0
- 40
- 20
0
20
40
60
- 40
100
80
- 20
0
20
40
60
80
TA - Temperature (°C)
TA - Temperature (°C)
Supply Current vs. Temperature
Switching Time vs. Temperature*
180
100
300
VS = 5 V
160
270
0V
VS = 5 V
240
140
VS = - 5 V
210
100
80
tON
60
180
-5V
150
- 15 V
120
90
VS = 5 V
40
t ON, t OFF (ns)
t ON , t OFF (ns)
120
tOFF
20
-5V
30
VS = - 5 V
0
tON
- 15 V
60
tOFF
0V
0
0
±5
± 10
± 15
± 20
± 25
V+, V- Positive and Negative Supplies (V)
Switching Time vs. Power Supply Voltage*
0
5
10
15
20
25
V+ - Positive Supply (V)
Switching Time vs. Positive Supply Voltage*
* Refer to Figure 2 for test conditions.
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Document Number: 70049
S09-2561-Rev. I, 30-Nov-09
DG401, DG403, DG405
Vishay Siliconix
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
100 mA
10 mA
Supply Current (A)
1 mA
100 µA
10 µA
1 µA
100 nA
10 nA
10
100
1K
10K
100K
1M
10M
Frequency (Hz)
Supply Current vs. Switching Frequency
SCHEMATIC DIAGRAM Typical Channel
V+
S
VL
V–
VIN
Level
Shift/
Drive
V+
GND
D
V–
Figure 1.
Document Number: 70049
S09-2561-Rev. I, 30-Nov-09
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DG401, DG403, DG405
Vishay Siliconix
TEST CIRCUITS
VO is the steady state output with the switch on. Feedthrough via switch capacitance may result in spikes at the leading and
trailing edge of the output waveform.
+5V
Logic
Input
+ 15 V
VL
V+
S
± 10 V
D
IN
RL
1 kΩ
V-
GND
tOFF
VS
VO
90 %
CL
35 pF
0V
Switch
Output
Switch
Input*
- 15 V
CL (includes fixture and stray capacitance)
tON
90 %
VO
-V S
* VS = 10 V for t ON, V S = - 10 V for tOFF
RL
VO = V S
0V
Switch
Input*
VO
tf < 20 ns
tf < 20 ns
50 %
Note: Logic input waveform is inverted for switches that
have the opposite logic sense control
RL + rDS(on)
Figure 2. Switching Time
+5V
+ 15 V
VL
VS1
VS2
3V
Logic
Input
50 %
V+
S1
D1
S2
D2
0V
VS1
VO1
VO1
Switch
Output
IN
RL1
V-
GND
90 %
VO2
RL2
L2
0V
VS2
VO2
CL1
CL2
90 %
0V
Switch
Output
tD
tD
- 15 V
CL (includes fixture and stray capacitance)
Figure 3. Break-Before-Make
Rg
+5V
+ 15 V
VL
V+
S
IN
Vg
VO
CL
10 nF
3V
GND
ΔVO
D
VO
IN
On
Off
On
VQ = ΔVO x CL
- 15 V
Figure 4. Charge Injection
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Document Number: 70049
S09-2561-Rev. I, 30-Nov-09
DG401, DG403, DG405
Vishay Siliconix
TEST CIRCUITS
C
+5V
C
V+
Rg = 50 Ω
50 Ω
RL
V-
D
S2
RL
100 Ω
IN
GND
V+
IN
0.8 V
C
GND
Off Isolation = 20 log
- 15 V
VS
XTALK Isolation = 20 log
VO
C = RF bypass
C = RF bypass
+5V
+ 15 V
+ 15 V
C
C
C
C
VL
V+
S
VS
VS
VO
Figure 7. Crosstalk
Figure 5. Off Isolation
VL
C
V-
- 15 V
+5V
C
Rg = 50 Ω
VO
0 V, 2.4 V
VL
S1
VS
VO
D
S
VS
+ 15 V
+ 15 V
C
VL
+5V
V+
S
VO
D
Meter
Rg = 50 Ω
RL
100 Ω
IN
0 V, 2.4 V
GND
V-
IN
HP4192A
Impedance
Analyzer
or Equivalent
0 V, 2.4 V
D
C
GND
V-
C
f = 1 MHz
- 15 V
C = RF bypass
Figure 6. Insertion Loss
Document Number: 70049
S09-2561-Rev. I, 30-Nov-09
- 15 V
Figure 8. Capacitances
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DG401, DG403, DG405
Vishay Siliconix
APPLICATIONS
+5V
+ 15 V
VL
Left
Source 1
Right
Left
D1
ein
S3
D3
Left
IN1
D2
V+
D1
S3
D3
+
-
eout
S4
D4
C1
Integrate/
Reset
Right
TTL
IN2
Channel
Select
VL
S1
IN1
S2
TTL
+ 15 V
V+
S1
Source 2
Right
+5V
S2
D2
S4
D4
C2
IN2
DG403
GND
DG403
Slope
Select
V-
GND
V-
- 15 V
- 15 V
Figure 9. Stereo Source Selector
Figure 10. Dual Slope Integrator
Dual Slope Integrators:
The DG403 is well suited to configure a selectable slope
integrator. One control signal selects the timing capacitor C1
or C2. Another one selects ein or discharges the capacitor in
preparation for the next integration cycle.
Band-Pass Switched Capacitor Filter:
+5V
+ 15 V
VL
V+
S1
D1
S3
D3
IN1
Single-pole double-throw switches are a common element
for switched capacitor networks and filters. The fast
switching times and low leakage of the DG403 allow for
higher clock rates and consequently higher filter operating
frequencies.
ein
S2
D2
S4
D4
IN2
DG403
Clock
GND
V-
- 15 V
+
-
eout
Figure 11. Band-Pass Switched Capacitor Filter
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Document Number: 70049
S09-2561-Rev. I, 30-Nov-09
DG401, DG403, DG405
Vishay Siliconix
APPLICATIONS
Peak Detector:
A3 acting as a comparator provides the logic drive for
operating SW1. The output of A2 is fed back to A3 and
compared to the analog input ein. If ein > eout the output of A3
is high keeping SW1 closed. This allows C1 to charge up to
the analog input voltage. When ein goes below eout A3 goes
negative, turning SW1 off. The system will therefore store the
most positive analog input experienced.
Reset
SW2
ein
–
A1
+
+
A3
–
SW1
R1
+
A2
–
DG401
eout
C1
Figure 12. Positive Peak Detector
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?70049.
Document Number: 70049
S09-2561-Rev. I, 30-Nov-09
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Package Information
Vishay Siliconix
SOIC (NARROW):
16ĆLEAD
JEDEC Part Number: MS-012
MILLIMETERS
16
15
14
13
12
11
10
Dim
A
A1
B
C
D
E
e
H
L
Ĭ
9
E
1
2
3
4
5
6
7
8
INCHES
Min
Max
Min
Max
1.35
1.75
0.053
0.069
0.10
0.20
0.004
0.008
0.38
0.51
0.015
0.020
0.18
0.23
0.007
0.009
9.80
10.00
0.385
0.393
3.80
4.00
0.149
0.157
1.27 BSC
0.050 BSC
5.80
6.20
0.228
0.244
0.50
0.93
0.020
0.037
0_
8_
0_
8_
ECN: S-03946—Rev. F, 09-Jul-01
DWG: 5300
H
D
C
All Leads
e
Document Number: 71194
02-Jul-01
B
A1
L
Ĭ
0.101 mm
0.004 IN
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Package Information
Vishay Siliconix
PDIP: 16ĆLEAD
16
15
14
13
12
11
10
9
E
E1
1
2
3
4
5
6
7
8
D
S
Q1
A
A1
L
15°
MAX
C
B1
e1
Dim
A
A1
B
B1
C
D
E
E1
e1
eA
L
Q1
S
B
eA
MILLIMETERS
Min
Max
INCHES
Min
Max
3.81
5.08
0.150
0.200
0.38
1.27
0.015
0.050
0.38
0.51
0.015
0.020
0.89
1.65
0.035
0.065
0.20
0.30
0.008
0.012
18.93
21.33
0.745
0.840
7.62
8.26
0.300
0.325
5.59
7.11
0.220
0.280
2.29
2.79
0.090
0.110
7.37
7.87
0.290
0.310
2.79
3.81
0.110
0.150
1.27
2.03
0.050
0.080
0.38
1.52
.015
0.060
ECN: S-03946—Rev. D, 09-Jul-01
DWG: 5482
Document Number: 71261
06-Jul-01
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Package Information
Vishay Siliconix
CERDIP: 16ĆLEAD
16
15
14
13
12
11
10
9
E1 E
1
2
3
4
5
6
7
8
D
S
Q1
A
A1
L1
L
e1
C
B
B1
MILLIMETERS
Dim
A
A1
B
B1
C
D
E
E1
e1
eA
L
L1
Q1
S
∝
eA
INCHES
Min
Max
Min
Max
4.06
5.08
0.160
0.200
0.51
1.14
0.020
0.045
0.38
0.51
0.015
0.020
1.14
1.65
0.045
0.065
0.20
0.30
0.008
0.012
19.05
19.56
0.750
0.770
7.62
8.26
0.300
0.325
6.60
7.62
0.260
0.300
2.54 BSC
∝
0.100 BSC
7.62 BSC
0.300 BSC
3.18
3.81
0.125
0.150
3.81
5.08
0.150
0.200
1.27
2.16
0.050
0.085
0.38
1.14
0.015
0.045
0°
15°
0°
15°
ECN: S-03946—Rev. G, 09-Jul-01
DWG: 5403
Document Number: 71282
03-Jul-01
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1
Packaging Information
Vishay Siliconix
20ĆLEAD LCC
A1
D
L1
A
Dim
28
e
1
2
E
A
A1
B
D
E
e
L
L1
MILLIMETERS
Min
Max
INCHES
Min
Max
1.37
2.24
0.054
0.088
1.63
2.54
0.064
0.100
0.56
0.71
0.022
0.028
8.69
9.09
0.342
0.358
8.69
9.09
0.442
0.358
1.27 BSC
0.050 BSC
1.14
1.40
0.045
0.055
1.96
2.36
0.077
0.093
ECN: S-03946—Rev. B, 09-Jul-01
DWG: 5321
L
Document Number: 71290
02-Jul-01
B
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Application Note 826
Vishay Siliconix
RECOMMENDED MINIMUM PADS FOR SO-16
RECOMMENDED MINIMUM PADS FOR SO-16
0.372
(9.449)
0.152
0.022
0.050
0.028
(0.559)
(1.270)
(0.711)
(3.861)
0.246
(6.248)
0.047
(1.194)
Recommended Minimum Pads
Dimensions in Inches/(mm)
Return to Index
APPLICATION NOTE
Return to Index
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24
Document Number: 72608
Revision: 21-Jan-08
Legal Disclaimer Notice
Vishay
Disclaimer
ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE
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“Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other
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Document Number: 91000
Revision: 11-Mar-11
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