EL5120, EL5220, EL5420 ® Data Sheet March 4, 2009 12MHz Rail-to-Rail Input-Output Op Amps Features The EL5120, EL5220, and EL5420 are low power, high voltage, rail-to-rail input-output amplifiers. The EL5120 contains a single amplifier, the EL5220 contains two amplifiers, and the EL5420 contains four amplifiers. Operating on supplies ranging from 5V to 15V, while consuming only 500µA per amplifier, the EL5120, EL5220, and EL5420 have a bandwidth of 12MHz (-3dB). They also provide common mode input ability beyond the supply rails, as well as rail-to-rail output capability. This enables these amplifiers to offer maximum dynamic range at any supply voltage. • 12MHz -3dB Bandwidth The EL5120, EL5220, and EL5420 also feature fast slewing and settling times, as well as a high output drive capability of 30mA (sink and source). These features make these amplifiers ideal for use as voltage reference buffers in Thin Film Transistor Liquid Crystal Displays (TFT-LCD). Other applications include battery power, portable devices, and anywhere low power consumption is important. • Pb-Free Available (RoHS Compliant) The EL5420 is available in the space-saving 14 Ld TSSOP package, the industry-standard 14 Ld SOIC package, as well as the 16 Ld QFN package. The EL5220 is available in the 8 Ld MSOP package and the 8Ld DFN package. The EL5120 is available in the 5 Ld TSOT package. All feature a standard operational amplifier pin out. These amplifiers are specified for operation over the full -40°C to +85°C temperature range. • Touch-Screen Displays FN7186.6 • Supply Voltage = 4.5V to 16.5V • Low Supply Current (per Amplifier) = 500µA • High Slew Rate = 10V/µs • Unity-Gain Stable • Beyond the Rails Input Capability • Rail-to-Rail Output Swing • Ultra-Small Package Applications • TFT-LCD Drive Circuits • Electronics Notebooks • Electronics Games • Personal Communication Devices • Personal Digital Assistants (PDA) • Portable Instrumentation • Sampling ADC Amplifiers • Wireless LANs • Office Automation • Active Filters • ADC/DAC Buffer 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2004, 2005, 2007, 2008, 2009. All Rights Reserved All other trademarks mentioned are the property of their respective owners. EL5120, EL5220, EL5420 Ordering Information PART MARKING PART NUMBER EL5120IWT-T7* K EL5120IWT-T7A* EL5120IWTZ-T7* (Note) TEMP. RANGE (°C) PACKAGE PKG. DWG. # -40 to +85 5 Ld TSOT Tape and Reel MDP0049 K -40 to +85 5 Ld TSOT Tape and Reel MDP0049 BKAA -40 to +85 5 Ld TSOT Tape and Reel (Pb-Free) MDP0049 EL5120IWTZ-T7A* (Note) BKAA -40 to +85 5 Ld TSOT Tape and Reel (Pb-Free) MDP0049 EL5220ILZ-T13 *(Note) 20Z -40 to +85 8 Ld DFN Tape and Reel (Pb-Free) L8.2x3 EL5220CY D -40 to +85 8 Ld MSOP MDP0043 EL5220CY-T7 D -40 to +85 8 Ld MSOP Tape and Reel MDP0043 EL5220CY-13 D -40 to +85 8 Ld MSOP Tape and Reel MDP0043 EL5220CYZ (Note) BBAAA -40 to +85 8 Ld MSOP (Pb-Free) MDP0043 EL5220CYZ-T7* (Note) BBAAA -40 to +85 8 Ld MSOP Tape and Reel (Pb-Free) MDP0043 EL5220CYZ-T13* (Note) BBAAA -40 to +85 8 Ld MSOP Tape and Reel (Pb-Free) MDP0043 EL5420CL 5420CL -40 to +85 16 Ld QFN MDP0046 EL5420CL-T7 5420CL -40 to +85 16 Ld QFN Tape and Reel MDP0046 EL5420CL-T13 5420CL -40 to +85 16 Ld QFN Tape and Reel MDP0046 EL5420CLZ (Note) 5420CLZ -40 to +85 16 Ld QFN (Pb-Free) MDP0046 EL5420CLZ-T7* (Note) 5420CLZ -40 to +85 16 Ld QFN Tape and Reel (Pb-Free) MDP0046 EL5420CLZ-T13* (Note) 5420CLZ -40 to +85 16 Ld QFN Tape and Reel (Pb-Free) MDP0046 EL5420CS 5420CS -40 to +85 14 Ld SOIC MDP0027 EL5420CS-T7 5420CS -40 to +85 14 Ld SOIC Tape and Reel MDP0027 EL5420CS-T13 5420CS -40 to +85 14 Ld SOIC Tape and Reel MDP0027 EL5420CSZ (Note) 5420CSZ -40 to +85 14 Ld SOIC (Pb-Free) MDP0027 EL5420CSZ-T7* (Note) 5420CSZ -40 to +85 14 Ld SOIC Tape and Reel (Pb-Free) MDP0027 EL5420CSZ-T13* (Note) 5420CSZ -40 to +85 14 Ld SOIC Tape and Reel (Pb-Free) MDP0027 EL5420CR 5420CR -40 to +85 14 Ld TSSOP MDP0044 EL5420CR-T7* 5420CR -40 to +85 14 Ld TSSOP Tape and Reel MDP0044 EL5420CR-T13* 5420CR -40 to +85 14 Ld TSSOP Tape and Reel MDP0044 EL5420CRZ (Note) 5420CRZ -40 to +85 14 Ld TSSOP (Pb-Free) M14.173 EL5420CRZ-T7* (Note) 5420CRZ -40 to +85 14 Ld TSSOP Tape and Reel (Pb-Free) M14.173 EL5420CRZ-T13* (Note) 5420CRZ -40 to +85 14 Ld TSSOP Tape and Reel (Pb-Free) M14.173 * Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 2 FN7186.6 March 4, 2009 EL5120, EL5220, EL5420 Pinouts EL5220 (8 LD DFN) TOP VIEW EL5220 (8 LD MSOP) TOP VIEW VOUTA 1 8 VS+ VOUTA 1 VINA- 2 7 VOUTB + VINA+ 3 VS- 4 + 8 VS+ VINA- 2 6 VINB- VINA+ 3 5 VINB+ VS- 4 7 VOUTB THERMAL PAD 6 VINB5 VINB+ THERMAL PAD CONNECTS TO VS- VINA+ 3 VS+ 4 VINB+ 5 VINB- 6 VOUTB 7 - + + - 12 VIND+ VINA- 1 11 VS- VINA+ 2 10 VINC+ VS+ 3 9 VINC- VINB+ 4 8 VOUTC 13 NC 13 VIND- 14 VOUTD + - 12 VIND11 VIND+ THERMAL PAD 10 VS9 VINC+ VINC- 8 4 VIN- - + 15 VOUTA VINA- 2 + - 14 VOUTD VOUTC 7 VIN+ 3 VOUTA 1 VOUTB 6 VS- 2 5 VS+ EL5420 (16 LD QFN) TOP VIEW 16 NC VOUT 1 EL5420 (14 LD TSSOP, SOIC) TOP VIEW VINB- 5 EL5120 (5 LD TSOT) TOP VIEW THERMAL PAD CONNECTS TO VS- 3 FN7186.6 March 4, 2009 EL5120, EL5220, EL5420 Absolute Maximum Ratings (TA = +25°C) Thermal Information Supply Voltage between VS+ and VS- . . . . . . . . . . . . . . . . . . . .+18V Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . VS- - 0.5V, VS +0.5V Maximum Continuous Output Current . . . . . . . . . . . . . . . . . . . 30mA Maximum Die Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . +125°C Thermal Resistance (Typical) θJA (°C/W) 5 Ld TSOT (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . 214 8 Ld DFN (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . 55 8 Ld MSOP (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . 115 16 Ld QFN (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . 44 14 Ld SOIC (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . 82 14 Ld TSSOP (Note 1) . . . . . . . . . . . . . . . . . . . . . . . 93 Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Ambient Operating Temperature . . . . . . . . . . . . . . . .-40°C to +85°C Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 1. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 2. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA Electrical Specifications PARAMETER VS+ = +5V, VS- = -5V, RL = 10kΩ and CL = 10pF to 0V, TA = +25°C, unless otherwise specified. DESCRIPTION CONDITIONS MIN TYP MAX UNIT 12 mV INPUT CHARACTERISTICS VOS Input Offset Voltage VCM = 0V 2 TCVOS Average Offset Voltage Drift (Note 3) 5 IB Input Bias Current VCM = 0V 2 RIN Input Impedance 1 GΩ CIN Input Capacitance 1.35 pF CMIR Common-Mode Input Range CMRR Common-Mode Rejection Ratio for VIN from -5.5V to +5.5V 50 70 dB AVOL Open Loop Gain -4.5V ≤ VOUT ≤ +4.5V 75 95 dB -5.5 µV/°C 50 +5.5 nA V OUTPUT CHARACTERISTICS VOL Output Swing Low IL = -5mA VOH Output Swing High IL = 5mA ISC IOUT -4.92 4.85 -4.85 V 4.92 V Short Circuit Current ±120 mA Output Current ±30 mA 80 dB POWER SUPPLY PERFORMANCE PSRR Power Supply Rejection Ratio VS is moved from ±2.25V to ±7.75V IS Supply Current (Per Amplifier) No load 500 60 750 µA DYNAMIC PERFORMANCE SR Slew Rate (Note 4) -4.0V ≤ VOUT ≤ +4.0V, 20% to 80% 10 V/µs tS Settling to +0.1% (AV = +1) (AV = +1), VO = 2V step 500 ns BW -3dB Bandwidth RL = 10kΩ, CL = 10pF 12 MHz GBWP Gain-Bandwidth Product RL = 10kΩ, CL = 10pF 8 MHz 4 FN7186.6 March 4, 2009 EL5120, EL5220, EL5420 Electrical Specifications PARAMETER VS+ = +5V, VS- = -5V, RL = 10kΩ and CL = 10pF to 0V, TA = +25°C, unless otherwise specified. DESCRIPTION CONDITIONS MIN TYP MAX UNIT PM Phase Margin RL = 10kΩ, CL = 10pF 50 ° CS Channel Separation f = 5MHz (EL5220 and EL5420 only) 75 dB NOTES: 3. Measured over operating temperature range. 4. Slew rate is measured on rising and falling edges. Electrical Specifications PARAMETER VS+ = +5V, VS- = 0V, RL = 10kΩ and CL = 10pF to 2.5V, TA = +25°C, unless otherwise specified. DESCRIPTION CONDITIONS MIN TYP MAX UNIT 10 mV INPUT CHARACTERISTICS VOS Input Offset Voltage VCM = 2.5V 2 TCVOS Average Offset Voltage Drift (Note 5) 5 IB Input Bias Current VCM = 2.5V 2 RIN Input Impedance 1 GΩ CIN Input Capacitance 1.35 pF CMIR Common-Mode Input Range CMRR Common-Mode Rejection Ratio for VIN from -0.5V to +5.5V 45 66 dB AVOL Open Loop Gain 0.5V ≤ VOUT ≤+ 4.5V 75 95 dB -0.5 µV/°C 50 +5.5 nA V OUTPUT CHARACTERISTICS VOL Output Swing Low IL = -5mA VOH Output Swing High IL = +5mA ISC IOUT 80 4.85 150 mV 4.92 V Short Circuit Current ±120 mA Output Current ±30 mA 80 dB POWER SUPPLY PERFORMANCE PSRR Power Supply Rejection Ratio VS is moved from 4.5V to 15.5V IS Supply Current (Per Amplifier) No load 500 60 750 µA DYNAMIC PERFORMANCE SR Slew Rate (Note 6) 1V ≤ VOUT ≤ 4V, 20% to 80% 10 V/µs tS Settling to +0.1% (AV = +1) (AV = +1), VO = 2V step 500 ns BW -3dB Bandwidth RL = 10kΩ, CL = 10pF 12 MHz GBWP Gain-Bandwidth Product RL = 10kΩ, CL = 10pF 8 MHz PM Phase Margin RL = 10kΩ, CL = 10pF 50 ° CS Channel Separation f = 5MHz (EL5220 and EL5420 only) 75 dB NOTES: 5. Measured over operating temperature range. 6. Slew rate is measured on rising and falling edges. 5 FN7186.6 March 4, 2009 EL5120, EL5220, EL5420 Electrical Specifications PARAMETER VS+ = +15V, VS- = 0V, RL = 10kΩ and CL = 10pF to 7.5V, TA = +25°C, unless otherwise specified. DESCRIPTION CONDITIONS MIN TYP MAX UNIT 14 mV INPUT CHARACTERISTICS VOS Input Offset Voltage VCM = 7.5V 2 TCVOS Average Offset Voltage Drift (Note 7) 5 IB Input Bias Current VCM = 7.5V 2 RIN Input Impedance 1 GΩ CIN Input Capacitance 1.35 pF CMIR Common-Mode Input Range CMRR Common-Mode Rejection Ratio for VIN from -0.5V to +15.5V 53 72 dB AVOL Open Loop Gain 0.5V ≤ VOUT ≤ 14.5V 75 95 dB -0.5 µV/°C 50 +15.5 nA V OUTPUT CHARACTERISTICS VOL Output Swing Low IL = -5mA VOH Output Swing High IL = +5mA ISC IOUT 80 14.85 150 mV 14.92 V Short Circuit Current ±120 mA Output Current ±30 mA 80 dB POWER SUPPLY PERFORMANCE PSRR Power Supply Rejection Ratio VS is moved from 4.5V to 15.5V IS Supply Current (Per Amplifier) No load 500 60 750 µA DYNAMIC PERFORMANCE SR Slew Rate (Note 8) 1V ≤ VOUT ≤ 14V, 20% to 80% 10 V/µs tS Settling to +0.1% (AV = +1) (AV = +1), VO = 2V step 500 ns BW -3dB Bandwidth RL = 10kΩ, CL = 10pF 12 MHz GBWP Gain-Bandwidth Product RL = 10kΩ, CL = 10pF 8 MHz PM Phase Margin RL = 10kΩ, CL = 10pF 50 ° CS Channel Separation f = 5MHz (EL5220 and EL5420 only) 75 dB NOTES: 7. Measured over operating temperature range 8. Slew rate is measured on rising and falling edges 6 FN7186.6 March 4, 2009 EL5120, EL5220, EL5420 Typical Performance Curves 70 VS = ±5V TA = +25°C 1600 TYPICAL PRODUCTION DISTRIBUTION 1400 1200 1000 800 600 400 QUANTITY (AMPLIFIERS) 200 50 40 30 20 10 INPUT BIAS CURRENT (nA) INPUT OFFSET VOLTAGE (mV) 5 0 -5 50 100 2.0 50 100 21 19 150 FIGURE 4. INPUT BIAS CURRENT vs TEMPERATURE 4.95 4.94 4.93 150 TEMPERATURE (°C) FIGURE 5. OUTPUT HIGH VOLTAGE vs TEMPERATURE -4.91 OUTPUT LOW VOLTAGE (V) OUTPUT HIGH VOLTAGE (V) 4.96 7 0 TEMPERATURE (°C) VS = ±5V IOUT = 5mA 100 17 -2.0 -50 4.97 50 15 0.0 150 FIGURE 3. INPUT OFFSET VOLTAGE vs TEMPERATURE 0 13 VS = ±5V TEMPERATURE (°C) -50 11 FIGURE 2. EL5420 INPUT OFFSET VOLTAGE DRIFT VS = ±5V 0 9 INPUT OFFSET VOLTAGE DRIFT, TCVOS (µV/°C) FIGURE 1. EL5420 INPUT OFFSET VOLTAGE DISTRIBUTION -50 7 1 12 8 10 6 4 2 -0 -2 -4 -6 -8 -10 -12 INPUT OFFSET VOLTAGE (mV) 5 0 0 10 TYPICAL PRODUCTION DISTRIBUTION VS = ±5V 60 3 QUANTITY (AMPLIFIERS) 1800 -4.92 VS = ±5V IOUT = -5mA -4.93 -4.94 -4.95 -4.96 -4.97 -50 0 50 100 150 TEMPERATURE (°C) FIGURE 6. OUTPUT LOW VOLTAGE vs TEMPERATURE FN7186.6 March 4, 2009 EL5120, EL5220, EL5420 Typical Performance Curves VS = ±5V RL = 10kΩ 10.40 SLEW RATE (V/µs) 100 OPEN LOOP GAIN (dB) (Continued) 90 80 VS = ±5V 10.35 10.30 10.25 -50 0 50 100 -50 150 100 150 TEMPERATURE (°C) TEMPERATURE (°C) FIGURE 8. SLEW RATE vs TEMPERATURE FIGURE 7. OPEN LOOP GAIN vs TEMPERATURE 700 VS = ±5V TA = +25°C 0.55 SUPPLY CURRENT (µA) SUPPLY CURRENT (mA) 50 0 0.5 600 500 400 0.45 -50 0 50 100 300 150 5 0 TEMPERATURE (°C) FIGURE 9. EL5420 SUPPLY CURRENT PER AMPLIFIER vs TEMPERATURE 200 -30 -80 50 -50 10 -130 100 1k 10k PHASE (°) GAIN (dB) 100 -180 GAIN -230 100k 1M 10M 100M FREQUENCY (Hz) FIGURE 11. OPEN LOOP GAIN AND PHASE vs FREQUENCY 8 MAGNITUDE (NORMALIZED) (dB) 5 PHASE VS = ±5V, TA = +25°C RL = 10kΩ to GND CL = 12pF to GND 20 15 FIGURE 10. EL5420 SUPPLY CURRENT PER AMPLIFIER vs SUPPLY VOLTAGE 20 150 0 10 SUPPLY VOLTAGE (V) 10kΩ 0 1kΩ 560Ω -5 -10 150Ω CL = 10pF AV = 1 VS = ±5V -15 100k 1M 10M 100M FREQUENCY (Hz) FIGURE 12. FREQUENCY RESPONSE FOR VARIOUS RL FN7186.6 March 4, 2009 EL5120, EL5220, EL5420 Typical Performance Curves (Continued) 200 RL = 10kΩ AV = 1 10 VS = ±5V OUTPUT IMPEDANCE (Ω) MAGNITUDE (NORMALIZED) (dB) 20 12pF 0 50pF -10 100pF 1000pF -20 -30 100k 1M 160 120 80 40 0 10k 100M 10M AV = 1 VS = ±5V TA = +25°C FIGURE 13. FREQUENCY RESPONSE FOR VARIOUS CL FIGURE 14. CLOSED LOOP OUTPUT IMPEDANCE vs FREQUENCY 80 12 10 60 8 CMRR (dB) MAXIMUM OUTPUT SWING (VP-P) 10M FREQUENCY (Hz) FREQUENCY (Hz) 6 VS = ±5V TA = +25°C AV = 1 RL = 10kΩ CL = 12pF Distortion <1% 4 2 0 10k 40 20 VS = ±5V TA = +25°C 100k 1M 0 100 10M 1k FIGURE 15. MAXIMUM OUTPUT SWING vs FREQUENCY 100k 1M 10M FIGURE 16. CMRR vs FREQUENCY 600 PSRR+ VOLTAGE NOISE (nV/√Hz) 80 10k FREQUENCY (Hz) FREQUENCY (Hz) PSRR- 60 PSRR (dB) 1M 100k 40 20 VS = ±5V TA = +25°C 0 100 1k 10k 100k 1M FREQUENCY (Hz) FIGURE 17. PSRR vs FREQUENCY 9 10M 100 10 1 100 1k 10k 100k 1M 10M 100M FREQUENCY (Hz) FIGURE 18. INPUT VOLTAGE NOISE SPECTRAL DENSITY vs FREQUENCY FN7186.6 March 4, 2009 EL5120, EL5220, EL5420 Typical Performance Curves (Continued) -60 0.010 DUAL MEASURED CHANNEL A TO B QUAD MEASURED CHANNEL A TO D OR B TO C OTHER COMBINATIONS YIELD IMPROVED REJECTION 0.009 0.008 -80 X-TALK (dB) THD+ N (%) 0.007 0.006 0.005 0.004 VS = ±5V 0.003 RL = 10kΩ AV = 1 0.002 V = 1V IN RMS -100 VS = ±5V RL = 10kΩ AV = 1 VIN = 220mVRMS -120 -140 0.001 1k 10k 1k 100k 10k FIGURE 19. TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY 1M 6M V = ±5V 90 AS = 1 V RL = 10kΩ VIN = ±50mV 70 T = +25°C A FIGURE 20. CHANNEL SEPARATION vs FREQUENCY RESPONSE VS = ±5V AV = 1 RL = 10kΩ CL = 12pF TA = +25°C 4 3 STEP SIZE (V) OVERSHOOT (%) 100k FREQUENCY (Hz) FREQUENCY (Hz) 50 30 2 0.1% 1 0 -1 -2 0.1% -3 10 -4 10 100 1k LOAD CAPACITANCE (pF) FIGURE 21. SMALL SIGNAL OVERSHOOT vs LOAD CAPACITANCE 1V 1µs VS = ±5V TA = +25°C AV = 1 RL = 10kΩ CL = 12pF FIGURE 23. LARGE SIGNAL TRANSIENT RESPONSE 10 0 200 400 600 800 SETTLING TIME (ns) FIGURE 22. SETTLING TIME vs STEP SIZE 50mV 200ns VS = ±5V TA = +25°C AV = 1 RL = 10kΩ CL = 12pF FIGURE 24. SMALL SIGNAL TRANSIENT RESPONSE FN7186.6 March 4, 2009 EL5120, EL5220, EL5420 Pin Descriptions EL5120 EL5220 5 LD TSOT 8 LD MSOP, 8 LD DFN EL5420 16 LD QFN PIN NAME 13, 16 NC No Connect IN+ Amplifier Non-Inverting Input (Reference Circuit 1) IN- Amplifier Inverting Input (Reference Circuit 1) OUT Amplifier Output (Reference Circuit 2) 3 VIN+ Amplifier Non-Inverting Input (Reference Circuit 1) 4 VIN- Amplifier Inverting Input (Reference Circuit 1) 1 VOUT Amplifier Output (Reference Circuit 2) Amplifier A Output (Reference Circuit 2) 5 2 14 LD TSSOP, 14 LD SOIC PIN FUNCTION EQUIVALENT CIRCUIT 1 1 15 VOUTA 2 2 1 VINA- Amplifier A Inverting Input (Reference Circuit 1) 3 3 2 VINA+ Amplifier A Non-Inverting Input (Reference Circuit 1) 8 4 3 VS+ 5 5 4 VINB+ Amplifier B Non-Inverting Input (Reference Circuit 1) 6 6 5 VINB- Amplifier B Inverting Input (Reference Circuit 1) 7 7 6 VOUTB Amplifier B Output (Reference Circuit 2) 8 7 VOUTC Amplifier C Output (Reference Circuit 2) 9 8 VINC- Amplifier C Inverting Input (Reference Circuit 1) 10 9 VINC+ Amplifier C Non-Inverting Input (Reference Circuit 1) 11 10 VS- 12 11 VIND+ Amplifier D Non-Inverting Input (Reference Circuit 1) 13 12 VIND- Amplifier D Inverting Input (Reference Circuit 1) 14 14 VOUTD Amplifier D Output (Reference Circuit 2) 4 Positive Power Supply Negative Power Supply VS+ VS+ VSVSCIRCUIT 1 11 GND CIRCUIT 2 FN7186.6 March 4, 2009 EL5120, EL5220, EL5420 Applications Information Product Description The EL5120, EL5220, and EL5420 voltage feedback amplifiers are fabricated using a high voltage CMOS process. They exhibit rail-to-rail input and output capability, they are unity gain stable, and have low power consumption (500µA per amplifier). These features make the EL5120, EL5220, and EL5420 ideal for a wide range of generalpurpose applications. Connected in voltage follower mode and driving a load of 10kΩ and 12pF, the EL5120, EL5220, and EL5420 have a -3dB bandwidth of 12MHz while maintaining a 10V/µs slew rate. The EL5120 is a single amplifier, the EL5220 is a dual amplifier, and the EL5420 is a quad amplifier. Operating Voltage, Input, and Output indefinitely, the power dissipation could easily increase such that the device may be damaged. Maximum reliability is maintained if the output continuous current never exceeds ±30mA. This limit is set by the design of the internal metal interconnects. Output Phase Reversal The EL5120, EL5220, and EL5420 are immune to phase reversal as long as the input voltage is limited from (VS-) -0.5V to (VS+) +0.5V. Figure 26 shows a photo of the output of the device with the input voltage driven beyond the supply rails. Although the device's output will not change phase, the input's overvoltage should be avoided. If an input voltage exceeds supply voltage by more than 0.6V, electrostatic protection diodes placed in the input stage of the device begin to conduct and overvoltage damage could occur. The EL5120, EL5220, and EL5420 are specified with a single nominal supply voltage from 5V to 15V or a split supply with its total range from 5V to 15V. Correct operation is guaranteed for a supply range of 4.5V to 16.5V. Most EL5120, EL5220, and EL5420 specifications are stable over both the full supply range and operating temperatures of -40°C to +85°C. Parameter variations with operating voltage and/or temperature are shown in the typical performance curves. The input common-mode voltage range of the EL5120, EL5220, and EL5420 extends 500mV beyond the supply rails. The output swings of the EL5120, EL5220, and EL5420 typically extend to within 80mV of positive and negative supply rails with load currents of 5mA. Decreasing load currents will extend the output voltage range even closer to the supply rails. Figure 25 shows the input and output waveforms for the device in the unity-gain configuration. Operation is from ±5V supply with a 10kΩ load connected to GND. The input is a 10VP-P sinusoid. The output voltage is approximately 9.985VP-P. 1V 1V 100µs VS = ±2.5V TA = +25°C AV = 1 VIN = 6VP-P FIGURE 26. OPERATION WITH BEYOND-THE-RAILS INPUT Power Dissipation With the high-output drive capability of the EL5120, EL5220, and EL5420 amplifiers, it is possible to exceed the +125°C “absolute-maximum junction temperature” under certain load current conditions. Therefore, it is important to calculate the maximum junction temperature for the application to determine if load conditions need to be modified for the amplifier to remain in the safe operating area. The maximum power dissipation allowed in a package is determined according to Equation 1: OUTPUT INPUT VS = ±5V TA = +25°C AV = 1 VIN = 10VP-P FIGURE 25. OPERATION WITH RAIL-TO-RAIL INPUT AND OUTPUT Short Circuit Current Limit T JMAX – T AMAX P DMAX = --------------------------------------------Θ JA (EQ. 1) where: • TJMAX = Maximum junction temperature • TAMAX = Maximum ambient temperature • θJA = Thermal resistance of the package • PDMAX = Maximum power dissipation in the package The maximum power dissipation actually produced by an IC is the total quiescent supply current times the total power The EL5120, EL5220, and EL5420 will limit the short circuit current to ±120mA if the output is directly shorted to the positive or the negative supply. If an output is shorted 12 FN7186.6 March 4, 2009 EL5120, EL5220, EL5420 supply voltage, plus the power in the IC due to the loads as shown in Equation 2: P DMAX = Σi × [ V S × I SMAX + ( V S + – V OUT i ) × I LOAD i ] (EQ. 2) when sourcing, and: P DMAX = Σi × [ V S × I SMAX + ( V OUT i – V S - ) × I LOAD i ] (EQ. 3) when sinking. where: parallel with 10kΩ with just 1.5dB of peaking, and 100pF with 6.4dB of peaking. If less peaking is desired in these applications, a small series resistor (usually between 5Ω and 50Ω) can be placed in series with the output. However, this will obviously reduce the gain slightly. Another method of reducing peaking is to add a “snubber” circuit at the output. A snubber is a shunt load consisting of a resistor in series with a capacitor. Values of 150Ω and 10nF are typical. The advantage of a snubber is that it does not draw any DC load current or reduce the gain Power Supply Bypassing and Printed Circuit Board Layout • i = 1 to 2 for dual and 1 to 4 for quad • VS = Total supply voltage • ISMAX = Maximum supply current per amplifier • VOUTi = Maximum output voltage of the application • ILOADi = Load current If we set the two PDMAX equations equal to each other, we can solve for RLOADi to avoid device overheat. Figure 27 provide a convenient way to see if the device will overheat. The maximum safe power dissipation can be found graphically, based on the package type and the ambient temperature. By using the previous equation, it is a simple matter to see if PDMAX exceeds the device's power derating curves. To ensure proper operation, it is important to observe the recommended derating curves in Figure 27. The EL5120, EL5220, and EL5420 can provide gain at high frequency. As with any high-frequency device, good printed circuit board layout is necessary for optimum performance. Ground plane construction is highly recommended, lead lengths should be as short as possible and the power supply pins must be well bypassed to reduce the risk of oscillation. For normal single supply operation, where the VS- pin is connected to ground, a 0.1µF ceramic capacitor should be placed from VS+ to pin to VS- pin. A 4.7µF tantalum capacitor should then be connected in parallel, placed in the region of the amplifier. One 4.7µF capacitor may be used for multiple devices. This same capacitor combination should be placed at each supply pin to ground if split supplies are to be used. JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD POWER DISSIPATION (W) 3.0 2.5 QFN16 θJA = 44°C/W 2.27W 2.0 1.800W 1.5 DFN8 θJA = 55°C/W 1.08W TSSOP14 θJA = 93°C/W 1.22W SOIC14 θJA = 82°C/W 1.0 870mW 0.5 MSOP8 θJA = 115°C/W 0 0 25 50 75 85 100 125 150 AMBIENT TEMPERATURE (°C) FIGURE 27. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE Unused Amplifiers It is recommended that any unused amplifiers in a dual and a quad package be configured as a unity gain follower. The inverting input should be directly connected to the output and the non-inverting input tied to the ground plane. Driving Capacitive Loads The EL5120, EL5220, and EL5420 can drive a wide range of capacitive loads. As load capacitance increases, however, the -3dB bandwidth of the device will decrease and the peaking will increase. The amplifiers drive 10pF loads in 13 FN7186.6 March 4, 2009 EL5120, EL5220, EL5420 Dual Flat No-Lead Plastic Package (DFN) L8.2x3 2X 0.15 C A A D 8 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE 2X MILLIMETERS 0.15 C B SYMBOL E MIN A 0.80 A1 - 6 A3 INDEX AREA b TOP VIEW D2 0.20 0.10 SIDE VIEW C SEATING PLANE D2 (DATUM B) 0.08 C A3 7 0.90 1.00 - - 0.05 - 0.25 0.32 1.50 1.65 1.75 1 7,8 3.00 BSC - 8 1.65 e 1.80 1.90 7,8 0.50 BSC - k 0.20 - - - L 0.30 0.40 0.50 8 N 8 Nd 4 D2/2 6 INDEX AREA 5,8 C E2 A NOTES 2.00 BSC E // MAX 0.20 REF D B NOMINAL 2 3 Rev. 0 6/04 2 NX k NOTES: 1. Dimensioning and tolerancing conform to ASME Y14.5-1994. 2. N is the number of terminals. 3. Nd refers to the number of terminals on D. (DATUM A) E2 4. All dimensions are in millimeters. Angles are in degrees. E2/2 5. Dimension b applies to the metallized terminal and is measured between 0.25mm and 0.30mm from the terminal tip. NX L 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. N N-1 NX b e 8 5 0.10 (Nd-1)Xe REF. M C A B 7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. 8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389. BOTTOM VIEW CL (A1) NX (b) L 5 SECTION "C-C" C C TERMINAL TIP e FOR EVEN TERMINAL/SIDE 14 FN7186.6 March 4, 2009 EL5120, EL5220, EL5420 Small Outline Package Family (SO) A D h X 45¬ (N/2)+1 N A PIN #1 I.D. MARK E1 E c SEE DETAIL ‚Äö 1 (N/2) B L1 0.010 M C A B e H C A2 GAUGE PLANE SEATING PLANE A1 0.004 C 0.010 M C A B L b 0.010 4¬¨¬®Ð DETAIL X MDP0027 SMALL OUTLINE PACKAGE FAMILY (SO) INCHES SYMBOL SO-14 SO16 (0.300”) (SOL-16) SO20 (SOL-20) SO24 (SOL-24) SO28 (SOL-28) TOLERANCE NOTES A 0.068 0.068 0.068 0.104 0.104 0.104 0.104 MAX - A1 0.006 0.006 0.006 0.007 0.007 0.007 0.007 ±0.003 - A2 0.057 0.057 0.057 0.092 0.092 0.092 0.092 ±0.002 - b 0.017 0.017 0.017 0.017 0.017 0.017 0.017 ±0.003 - c 0.009 0.009 0.009 0.011 0.011 0.011 0.011 ±0.001 - D 0.193 0.341 0.390 0.406 0.504 0.606 0.704 ±0.004 1, 3 E 0.236 0.236 0.236 0.406 0.406 0.406 0.406 ±0.008 - E1 0.154 0.154 0.154 0.295 0.295 0.295 0.295 ±0.004 2, 3 e 0.050 0.050 0.050 0.050 0.050 0.050 0.050 Basic - L 0.025 0.025 0.025 0.030 0.030 0.030 0.030 ±0.009 - L1 0.041 0.041 0.041 0.056 0.056 0.056 0.056 Basic - h 0.013 0.013 0.013 0.020 0.020 0.020 0.020 Reference - 16 20 24 28 Reference - N SO-8 SO16 (0.150”) 8 14 16 Rev. M 2/07 NOTES: 1. Plastic or metal protrusions of 0.006” maximum per side are not included. 2. Plastic interlead protrusions of 0.010” maximum per side are not included. 3. Dimensions “D” and “E1” are measured at Datum Plane “H”. 4. Dimensioning and tolerancing per ASME Y14.5M-1994 15 FN7186.6 March 4, 2009 EL5120, EL5220, EL5420 Mini SO Package Family (MSOP) 0.25 M C A B D MINI SO PACKAGE FAMILY (N/2)+1 N E MDP0043 A E1 MILLIMETERS PIN #1 I.D. 1 B (N/2) e H C SEATING PLANE 0.10 C N LEADS SYMBOL MSOP8 MSOP10 TOLERANCE NOTES A 1.10 1.10 Max. - A1 0.10 0.10 ±0.05 - A2 0.86 0.86 ±0.09 - b 0.33 0.23 +0.07/-0.08 - c 0.18 0.18 ±0.05 - D 3.00 3.00 ±0.10 1, 3 E 4.90 4.90 ±0.15 - E1 3.00 3.00 ±0.10 2, 3 e 0.65 0.50 Basic - L 0.55 0.55 ±0.15 - L1 0.95 0.95 Basic - N 8 10 Reference - 0.08 M C A B b Rev. D 2/07 NOTES: 1. Plastic or metal protrusions of 0.15mm maximum per side are not included. L1 2. Plastic interlead protrusions of 0.25mm maximum per side are not included. A 3. Dimensions “D” and “E1” are measured at Datum Plane “H”. 4. Dimensioning and tolerancing per ASME Y14.5M-1994. c SEE DETAIL "X" A2 GAUGE PLANE L A1 0.25 3¬¨¬®Ð DETAIL X 16 FN7186.6 March 4, 2009 EL5120, EL5220, EL5420 Thin Shrink Small Outline Package Family (TSSOP) 0.25 M C A B D MDP0044 A THIN SHRINK SMALL OUTLINE PACKAGE FAMILY (N/2)+1 N MILLIMETERS SYMBOL 14 LD 16 LD 20 LD 24 LD 28 LD TOLERANCE PIN #1 I.D. E E1 0.20 C B A 1 (N/2) B 2X N/2 LEAD TIPS TOP VIEW 0.05 e C SEATING PLANE 0.10 M C A B b 0.10 C N LEADS H A 1.20 1.20 1.20 1.20 1.20 Max A1 0.10 0.10 0.10 0.10 0.10 ±0.05 A2 0.90 0.90 0.90 0.90 0.90 ±0.05 b 0.25 0.25 0.25 0.25 0.25 +0.05/-0.06 c 0.15 0.15 0.15 0.15 0.15 +0.05/-0.06 D 5.00 5.00 6.50 7.80 9.70 ±0.10 E 6.40 6.40 6.40 6.40 6.40 Basic E1 4.40 4.40 4.40 4.40 4.40 ±0.10 e 0.65 0.65 0.65 0.65 0.65 Basic L 0.60 0.60 0.60 0.60 0.60 ±0.15 L1 1.00 1.00 1.00 1.00 1.00 Reference Rev. F 2/07 NOTES: 1. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed 0.15mm per side. SIDE VIEW 2. Dimension “E1” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm per side. SEE DETAIL ‚Äö 3. Dimensions “D” and “E1” are measured at dAtum Plane H. 4. Dimensioning and tolerancing per ASME Y14.5M-1994. c END VIEW L1 A A2 GAUGE PLANE 0.25 L A1 0¬¨¬®Ðê DETAIL X 17 FN7186.6 March 4, 2009 EL5120, EL5220, EL5420 QFN (Quad Flat No-Lead) Package Family MDP0046 QFN (QUAD FLAT NO-LEAD) PACKAGE FAMILY (COMPLIANT TO JEDEC MO-220) A MILLIMETERS D N (N-1) (N-2) B 1 2 3 PIN #1 I.D. MARK E (N/2) 2X 0.075 C 2X 0.075 C N LEADS TOP VIEW 0.10 M C A B (N-2) (N-1) N b L SYMBOL QFN44 QFN3 TOLERANCE NOTES A 0.90 0.90 0.90 0.90 ±0.10 - A1 0.02 0.02 0.02 0.02 +0.03/-0.02 - b 0.25 0.25 0.23 0.22 ±0.02 - c 0.20 0.20 0.20 0.20 Reference - D 7.00 5.00 8.00 5.00 Basic - Reference 8 Basic - Reference 8 Basic - D2 5.10 3.80 5.80 3.60/2.48 E 7.00 7.00 8.00 1 2 3 6.00 E2 5.10 5.80 5.80 4.60/3.40 e 0.50 0.50 0.80 0.50 L 0.55 0.40 0.53 0.50 ±0.05 - N 44 38 32 32 Reference 4 ND 11 7 8 7 Reference 6 NE 11 12 8 9 Reference 5 MILLIMETERS PIN #1 I.D. 3 QFN32 SYMBOL QFN28 QFN2 QFN20 QFN16 A 0.90 0.90 0.90 0.90 0.90 ±0.10 - A1 0.02 0.02 0.02 0.02 0.02 +0.03/ -0.02 - b 0.25 0.25 0.30 0.25 0.33 ±0.02 - c 0.20 0.20 0.20 0.20 0.20 Reference - D 4.00 4.00 5.00 4.00 4.00 Basic - D2 2.65 2.80 3.70 2.70 2.40 Reference - (E2) (N/2) NE 5 7 (D2) BOTTOM VIEW 0.10 C e C SEATING PLANE TOLERANCE NOTES E 5.00 5.00 5.00 4.00 4.00 Basic - E2 3.65 3.80 3.70 2.70 2.40 Reference - e 0.50 0.50 0.65 0.50 0.65 Basic - L 0.40 0.40 0.40 0.40 0.60 ±0.05 - N 28 24 20 20 16 Reference 4 ND 6 5 5 5 4 Reference 6 NE 8 7 5 5 4 Reference 5 Rev 11 2/07 0.08 C N LEADS & EXPOSED PAD SEE DETAIL "X" NOTES: 1. Dimensioning and tolerancing per ASME Y14.5M-1994. 2. Tiebar view shown is a non-functional feature. SIDE VIEW 3. Bottom-side pin #1 I.D. is a diepad chamfer as shown. 4. N is the total number of terminals on the device. (c) C 5. NE is the number of terminals on the “E” side of the package (or Y-direction). 2 A (L) A1 N LEADS DETAIL X 6. ND is the number of terminals on the “D” side of the package (or X-direction). ND = (N/2)-NE. 7. Inward end of terminal may be square or circular in shape with radius (b/2) as shown. 8. If two values are listed, multiple exposed pad options are available. Refer to device-specific datasheet. 18 FN7186.6 March 4, 2009 EL5120, EL5220, EL5420 TSOT Package Family MDP0049 e1 D TSOT PACKAGE FAMILY A MILLIMETERS 6 N SYMBOL 4 E1 2 E 3 0.15 C D 2X 1 5 2 (N/2) 0.25 C 2X N/2 TIPS e ddd M B C A-B D b NX 0.15 C A-B 1 3 D 2X TSOT5 TSOT6 TSOT8 TOLERANCE A 1.00 1.00 1.00 Max A1 0.05 0.05 0.05 ±0.05 A2 0.87 0.87 0.87 ±0.03 b 0.38 0.38 0.29 ±0.07 c 0.127 0.127 0.127 +0.07/-0.007 D 2.90 2.90 2.90 Basic E 2.80 2.80 2.80 Basic E1 1.60 1.60 1.60 Basic e 0.95 0.95 0.65 Basic e1 1.90 1.90 1.95 Basic L 0.40 0.40 0.40 ±0.10 L1 0.60 0.60 0.60 Reference ddd 0.20 0.20 0.13 - N 5 6 8 Reference Rev. B 2/07 C A2 SEATING PLANE 1. Plastic or metal protrusions of 0.15mm maximum per side are not included. 2. Plastic interlead protrusions of 0.15mm maximum per side are not included. A1 0.10 C NOTES: NX 3. This dimension is measured at Datum Plane “H”. 4. Dimensioning and tolerancing per ASME Y14.5M-1994. (L1) 5. Index area - Pin #1 I.D. will be located within the indicated zone (TSOT6 AND TSOT8 only). H A GAUGE PLANE c L 19 6. TSOT5 version has no center lead (shown as a dashed line). 0.25 4¬¨¬®Ð FN7186.6 March 4, 2009 EL5120, EL5220, EL5420 Thin Shrink Small Outline Plastic Packages (TSSOP) N INDEX AREA E 0.25(0.010) M 2 14 LEAD THIN SHRINK SMALL OUTLINE PLASTIC PACKAGE E1 GAUGE PLANE -B1 M14.173 B M INCHES SYMBOL 3 L 0.05(0.002) -A- 0.25 0.010 SEATING PLANE A D -C- α e A2 A1 b c 0.10(0.004) 0.10(0.004) M C A M B S NOTES: 1. These package dimensions are within allowable dimensions of JEDEC MO-153-AC, Issue E. MIN MAX MILLIMETERS MIN MAX NOTES A - 0.047 - 1.20 - A1 0.002 0.006 0.05 0.15 - A2 0.031 0.041 0.80 1.05 - b 0.0075 0.0118 0.19 0.30 9 c 0.0035 0.0079 0.09 0.20 - D 0.195 0.199 4.95 5.05 3 E1 0.169 0.177 4.30 4.50 4 e 0.026 BSC 0.65 BSC - E 0.246 0.256 6.25 6.50 - L 0.0177 0.0295 0.45 0.75 6 8o 0o N α 14 0o 14 7 8o 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. Rev. 2 4/06 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E1” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. (Angles in degrees) All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 20 FN7186.6 March 4, 2009