ICST ICS9148F-11 Frequency generator & integrated buffers for pentiumtm Datasheet

Integrated
Circuit
Systems, Inc.
ICS9148-11
Frequency Generator & Integrated Buffers for PENTIUMTM
General Description
Features
The ICS9148-11 generates all clocks required for high speed RISC
or CISC microprocessor systems such as Intel PentiumPro. An
output enable pin is provided for testability. MODE allows power
management functions: CPU_STOP#, PCI_STOP# &
PWR_DWN#.
•
High drive BCLK outputs typically provide greater than 1V/ns slew
rate into 30 pF loads. PCLK outputs typically provide better than 1V/
ns slew rate into 20 pF loads while maintaining 50± 5% duty cycle.
The REF clock outputs typically provide better than 0.5V/ns slew
rates.
•
•
•
•
•
•
•
•
•
Generates four processor, six bus, one 14.31818MHz and 12
SDRAM clocks.
Synchronous clocks skew matched to 250ps window on
CPU, SDRAM and 500ps window on BUS clocks.
CPUCLKs to BUS clocks skew 1-4 ns (CPU early)
Test clock mode eases system design
Custom configurations available
VDD(1:3) - 3.3V ±10%
(inputs 5V tolerant w/series R )
VDDL(1:2) - 2.5V or 3.3V ±5%
PC serial configuration interface
Power Management Control Input pins
48-pin SSOP package
Block Diagram
Pin Configuration
48-Pin SSOP
Functionality
OE
0
1
CPUCLK,
SDRAM
(MHz)
High-Z
66.6
X1, REF
(MHz)
PCICLK
(MHz)
High-Z
14.318
High-Z
33.3
Pentium is a trademark of Intel Corporation
I2C is a trademark of Philips Corporation
9148-11 RevB 12/09/97P
ICS reserves the right to make changes in the device data identified in this
publication without further notice. ICS advises its customers to obtain the latest
version of all device data to verify that any information being relied upon by the
customer is current and accurate.
ICS9148-11
Pin Descriptions
PIN NUMBER
2
3, 9, 16, 22, 27,
33, 39, 45
4
5
25
7
8, 10, 11, 12
13, 15
26
23
24
1, 6, 14,
19, 30, 36,
17, 18, 20, 21,
32, 34, 35, 37, 38
42, 48
40, 41, 43, 44
46, 47
28
29
31
PIN NAME
TYPE
DESCRIPTION
REF0
OUT
14.318 MHz reference clock outputs.
GND
PWR
Ground.
X1
IN
X2
MODE
PCLK_F
OUT
IN
OUT
PCICLK (0:5)
OUT
OE
SDATA
SCLK
VDD1, VDD2,
VDD3
SDRAM
(0:4) (8:11)
IN
IN
IN
XTAL_IN 14.318MHz Crystal input, has internal 33pF load cap and feed
back resistor from X2
XTAL_OUT Crystal output, has internal load cap 33pF
Mode select pin for enabling power management features.
Free running BUS clock during PCI_STOP# = 0.
BUS clock outputs.
Logic input for output enable, tristates all outputs when low.
Serial data in for serial config port.
Clock input for serial config port.
PWR
Nominal 3.3V power supply, see power groups for function.
OUT
SDRAM clocks 66.6MHz.
VDDL2, VDDL1
PWR
CPUCLK (0:3)
IOAPIC (0:1)
SDRAM7
PCI_STOP#
SDRAM6
CPU_STOP#
SDRAM5
PWR_DWN#
OUT
OUT
OUT
IN
OUT
IN
OUT
IN
CPU and IOAPIC clock power supply, either
2.5 or 3.3V nominal
CPU output clocks, powered by VDDL2 (66.6 MHz)
IOAPIC clock output, (14.318 MHz) powered by VDDL1
SDRAM clock 66.6 MHz selected
Halts PCICLK (0:5) at logic "0" level when low
SDRAM clock 66.6 MHz selected
Halts CPUCLK clocks at logic "0" level when low
SDRAM clock 66.6 MHz selected
Powers down chip, active low
Power Groups
VDD1 = REF0, X1, X2
VDD2 = PCICLK_F, PCICLK (0:5)
VDD3 = SDRAM (0:4) (8:11) SDRAM5/PWR_DWN#,
SDRAM6/CPU_STOP#, SDRAM7/PCI_STOP#, supply for PLL Core.
VDDL1 = IOAPIC (0:1)
VDDL2 = CPUCLK (0:3)
2
ICS9148-11
Power-On Conditions
MODE
1
0
PIN #
44, 43, 41, 40
38, 37, 35, 34,
32, 31, 21, 20,
18, 17, 29, 28
8, 10, 11,
12, 14, 15, 7
DESCRIPTION
CPUCLKs
28
PCI_STOP#
29
CPU_STOP#
31
SDRAM/PWR
_DWN#
7
PCICLK_F
44, 43, 41, 40
CPUCLKs
38, 37, 35,
34, 32, 21,
20, 18, 17
8, 10, 11,
12, 14, 15
FUNCTION
66.6 MHz - w/serial config enable/disable
SDRAM
66.6 MHz - All SDRAM outputs
PCICLKs
33.3 MHz - w/serial config enable/disable
Power Management, PCI (0:5) Clocks Stopped
when low
Power Management, CPU (0:3) Clocks Stopped
when low
Used as PWR_DWN# when low
33.3 MHz - 33.3 MHz - PCI Clock Free running for
Power Management
66.6 MHz - CPU Clocks w/external Stop Control and
serial config individual enable/disable.
SDRAM
66.6 MHz - SDRAM Clocks w/serial config individual
enable/disable.
PCICLKs
33.3 MHz - PCI Clocks w/external Stop control and
serial config individual enable/disable.
Example:
a) if MODE = 1, pins 28, 29 and 31 are configured as SDRAM7, SDRAM6 and SDRAM5 respectively.
b) if MODE = 0, pins 28, 29 and 31 are configured as PCI_STOP#, CPU_STOP# and PWR_DWN# respectively.
Power-On Default Conditions
At power-up and before device programming, all clocks will default to an enabled and “on” condition. The frequencies that are then
produced are on the FS and MODE pin as shown in the table below.
CLOCK
REF 0
IOAPIC (0:1)
DEFAULT CONDITION AT POWER-UP
14.31818 MHz
14.31818 MHz
3
ICS9148-11
Technical Pin Function Descriptions
VDD(1,2,3)
This is the power supply to the internal core logic of the device as well
as the clock output buffers for REF(0:1), PCICLK, 48/24MHzA/B
and SDRAM(0:7).
REF0
The REF Output is a fixed frequency Clock that runs at the same
frequency as the Input Reference Clock X1 or the Crystal (typically
14.31818MHz) attached across X1 and X2.
This pin operates at 3.3V volts. Clocks from the listed buffers that it
supplies will have a voltage swing from Ground to this level. For the
actual guaranteed high and low voltage levels for the Clocks, please
consult the DC parameter table in this data sheet.
PCICLK_F
This Output is equal to PCICLK(0:5) and is FREE RUNNING, and
will not be stopped by PCI_STP#.
PCICLK (0:5)
These Output Clocks generate all the PCI timing requirements for a
Pentium/Pro based system. They conform to the current PCI
specification. They run at 1/2 CPU frequency.
VDDL1,2
This is the power supplies for the CPUCLK and IOAPCI output
buffers. The voltage level for these outputs may be 2.5 or 3.3volts.
Clocks from the buffers that each supplies will have a voltage swing
from Ground to this level. For the actual Guaranteed high and low
voltage levels of these Clocks, please consult the DC parameter
table in this Data Sheet.
MODE
This Input pin is used to select the Input function of the I/O pins. An
active Low will place the I/O pins in the Input mode and enable those
stop clock functions.
GND
This is the power supply ground (common or negative) return pin for
the internal core logic and all the output buffers.
PWR_DWN#
This is an asynchronous active Low Input pin used to Power Down
the device into a Low Power state by not removing the power supply.
The internal Clocks are disabled and the VCO and Crystal are
stopped. Powered Down will also place all the Outputs in a low state
at the end of their current cycle. The latency of Power Down will not
be greater than 3ms. The I2C inputs will beTri-Stated and the device
will retain all programming information. This input pin only valid when
MODE=0 (Power Management Mode)
X1
This input pin serves one of two functions. When the device is used
with a Crystal, X1 acts as the input pin for the reference signal that
comes from the discrete crystal. When the device is driven by an
external clock signal, X1 is the device input pin for that reference
clock. This pin also implements an internal Crystal loading capacitor
that is connected to ground. With a nominal value fo 33pF no
external load cap is needed for a CL =17 to 18pF crystal.
CPU_STOP#
This is a synchronous active Low Input pin used to stop the
CPUCLK clocks in an active low state. All other Clocks including
SDRAM clocks will continue to run while this function is enabled.
The CPUCLK’s will have a turn ON latency of at least 3 CPU
clocks. This input pin only valid when MODE=0 (Power Management
Mode)
X2
This Output pin is used only when the device uses a Crystal as the
reference frequency source. In this mode of operation, X2 is an
output signal that drives (or excites) the discrete Crystal. The X2 pin
will also implement an internal Crystal loading capacitor nominally
33pF.
PCI_STOP#
This is a synchronous active Low Input pin used to stop the PCICLK
clocks in an active low state. It will not effect PCICLK_F nor any
other outputs. This input pin only valid when MODE=0 (Power
Management Mode)
CPUCLK (0:3)
These Output pins are the Clock Outputs that drive processor and
other CPU related circuitry that requires clocks which are in tight
skew tolerance with the CPU clock. The voltage swing of these
Clocks are controlled by theVoltage level applied to theVDDL2 pin
of the device. See the Functionality Table for a list of the specific
frequencies that are available for these Clocks and the selection
codes to produce them.
I2C
The SDATA and SCLOCK Inputs are use to program the device.
The clock generator is a slave-receiver device in the I2C protocol.
It will allow read-back of the registers. See configuration map for
register functions. The I2C specification in Philips I2C Peripherals
Data Handbook (1996) should be followed.
SDRAM(0:11)
These Output Clocks are use to drive Dynamic RAM’s and are low
skew copies of the CPU Clocks. The voltage swing of the
SDRAM’s output is controlled by the supply voltage that is applied
to VDD3 of the device, operates at 3.3 volts.
OE
Output Enable tristates the outputs when held low. This pin will
override the I2C Byte 0 function, so that the outputs will be tristated
when the OE is low regardless of the I2C defined function. When OE
is high, the I2 C function is in active control.
IOAPIC (0:1)
This Output is a fixed frequency Output Clock that runs at the
Reference Input (typically 14.31818MHz) . Its voltage level swing
is controlled by VDDL1 and may operate at 2.5 or 3.3volts.
4
ICS9148-11
General I2C serial interface information
For the clock generator to be addressed by an I2C controller, the following address must be sent as a start sequence,
with an acknowledge bit between each byte.
A.
Clock Generator
Address (7 bits)
A(6:0) & R/W#
D2(H)
ACK
+ 8 bits dummy
command code
ACK
+ 8 bits dummy
Byte count
ACK
Then Byte 0, 1, 2, etc in
sequence until STOP.
The clock generator is a slave/receiver I2C component. It can "read back "(in Philips I2C protocol) the data stored in the
latches for verification. (set R/W# to 1 above). There is no BYTE count supported, so it does not meet the Intel SMB
PIIX4 protocol.
B.
Clock Generator
Address (7 bits)
A(6:0) & R/W#
D3(H)
ACK
Byte 0
ACK
Byte 1
ACK
Byte 0, 1, 2, etc in sequence until STOP.
C.
The data transfer rate supported by this clock generator is 100K bits/sec (standard mode)
D.
The input is operating at 3.3V logic levels.
E.
The data byte format is 8 bit bytes.
F.
To simplify the clock generator I2C interface, the protocol is set to use only block writes from the controller. The bytes
must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has
been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two
bytes. The data is loaded until a Stop sequence is issued.
G.
In the power down mode (PWR_DWN# Low), the SDATA and SCLK pins are tristated and the internal data latches
maintain all prior programming information.
H.
At power-on, all registers are set to a default condition. See Byte 0 detail for default condition, Bytes 1 through 5 default
to a 1 (Enabled output state)
Serial Configuration Command Bitmaps
Byte 0: Functional and Frequency Select Clock Register (Default=0)
BIT
Bit 7
Bit 6
PIN#
-
Bit 5
Bit 4
Bit
Bit
Bit
Bit
3
2
1
0
-
DESCRIPTION
Reserved
Must be 0 for normal operation
Must be 0 for normal operation
In Spread Spectrum, Controls type
(0=centered, 1=down spread)
Must be 0 for normal operation
In Spread Spectrum, Controls Spreading
(0=1.8%, 1=0.6%)
Reserved
Reserved
Bit1
Bit0
1
1 - Tri-State
1
0 - Spread Spectrum Enable
0
1 - Testmode
0
0 - Normal operation
5
PWD
0
0
0
0
0
0
0
0
0
0
Note: PWD = Power-Up Default
ICS9148-11
Select Functions
OUTPUTS
FUNCTION
DESCRIPTION
CPU
Tri - State
Test Mode
Hi-Z
TCLK/21
PCI,
PCI_F
Hi-Z
TCLK/41
SDRAM
REF
IOAPIC
Hi-Z
TCLK/21
Hi-Z
TCLK1
Hi-Z
TCLK1
Notes:
1. REF is a test clock on the X1 inputs during test mode.
Byte 1: CPU Clock Register
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN#
40
41
43
44
PWD
1
1
1
1
1
1
1
1
Byte 2: PCICLK Clock Register
BIT PIN# PWD
DESCRIPTION
Bit 7
1
Reserved
Bit 6
7
1
PCICLK_F (Act/Inact)
Bit 5 15
1
PCICLK5 (Act/Inact)
Bit 4 13
1
PCICLK4 (Act/Inact)
Bit 3 12
1
PCICLK3 (Act/Inact)
Bit 2 11
1
PCICLK2 (Act/Inact)
Bit 1 10
1
PCICLK1 (Act/Inact)
Bit 0
8
1
PCICLK0 (Act/Inact)
DESCRIPTION
Reserved
Reserved
Reserved
Reserved
CPUCLK3 (Act/Inact)
CPUCLK2 (Act/Inact)
CPUCLK1 (Act/Inact)
CPUCLK0 (Act/Inact)
Notes: 1 = Enabled; 0 = Disabled, outputs held low
Notes: 1 = Enabled; 0 = Disabled, outputs held low
Byte 3: SDRAM Clock Register
Byte 4: SDRAM Clock Register
BIT
PIN#
PWD
Bit 7
28
1
Bit 6
29
1
Bit 5
31
1
Bit
Bit
Bit
Bit
Bit
32
34
35
37
38
1
1
1
1
1
4
3
2
1
0
BIT PIN# PWD
DESCRIPTION
Bit 7
1
Reserved
Bit 6
1
Reserved
Bit 5
1
Reserved
Bit 4
1
Reserved
Bit 3 17
1
SDRAM11 (Act/Inact)
Bit 2 18
1
SDRAM10 (Act/Inact)
Bit 1 20
1
SDRAM9 (Act/Inact)
Bit 0 21
1
SDRAM8 (Act/Inact)
DESCRIPTION
SDRAM7 (Act/Inact)
Desktop only
SDRAM6 (Act/Inact)
Desktop only
SDRAM5 (Act/Inact)
Desktop only
SDRAM4 (Act/Inact)
SDRAM3 (Act/Inact)
SDRAM2 (Act/Inact)
SDRAM1 (Act/Inact)
SDRAM0 (Act/Inact)
Notes: 1 = Enabled; 0 = Disabled, outputs held low
Notes: 1 = Enabled; 0 = Disabled, outputs held low
Note: PWD = Power-Up Default
6
ICS9148-11
Byte 6: Optional Register for Future
Byte 5: Peripheral Clock Register
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN# PWD
DESCRIPTION
1
Reserved
1
Reserved
46
1
IOAPIC1 (Act/Inact)
47
1
IOAPIC0 (Act/Inact)
1
Reserved
1
Reserved
1
Reserved
2
1
REF0(Act/Inact)
PIN# PWD
DESCRIPTION
1
Reserved
1
Reserved
1
Reserved
1
Reserved
1
Reserved
1
Reserved
1
Reserved
1
Reserved
Notes:
1. Byte 6 is reserved by Integrated Circuit Systems for
future applications.
Notes: 1 = Enabled; 0 = Disabled, outputs held low
Note: PWD = Power-Up Default
Power Management
Clock Enable Configuration
CPU_STOP#
PCI_STOP#
PWR_DWN#
CPUCLK
PCICLK
X
0
0
1
1
X
0
1
0
1
0
1
1
1
1
Low
Low
Low
66.6 MHz
66.6 MHz
Low
Low
33.3 MHz
Low
33.3 MHz
Other Clocks,
SDRAM,
REF,
IOAPICs
Stopped
Running
Running
Running
Running
Crystal
VCOs
Off
Running
Running
Running
Running
Off
Running
Running
Running
Running
Full clock cycle timing is guaranteed at all times after the system has initially powered up except where noted. The first clock pulse coming out
of a stopped clock condition may be slightly distorted due to clock network charging circuitry. Board routing and signal loading may have a
large impact on the initial clock distortion also.
ICS9148-11 Power Management Requirements
SIGNAL
SIGNAL STATE
CPU_ STOP#
0 (Disabled) 2
1 (Enabled) 1
0 (Disabled) 2
1 (Enabled) 1
1 (Normal Operation) 3
0 (Power Down) 4
PCI_STOP#
PWR_DWN#
Latency
No. of rising edges of free
running PCICLK
1
1
1
1
3mS
2max
Notes.
1. Clock on latency is defined from when the clock enable goes active to when the first valid clock comes out of the device.
2. Clock off latency is defined from when the clock enable goes inactive to when the last clock is driven low out of the device.
3. Power up latency is when PD# goes inactive (high) to when the first valid clocks are output by the device.
4. Power down has controlled clock counts applicable to CPUCLK, SDRAM, PCICLK only.
The REF and IOAPIC will be stopped independant of these.
7
ICS9148-11
CPU_STOP# Timing Diagram
CPUSTOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPUCLKs for low power operation. CPU_STOP#
is synchronized by theICS9148-11. The minimum that the CPUCLK is enabled (CPU_STOP# high pulse) is 100 CPUCLKs.All other clocks
will continue to run while the CPUCLKs are disabled. The CPUCLKs will always be stopped in a low state and start in such a manner that
guarantees the high pulse width is a full pulse. CPUCLK on latency is less than 4 CPUCLKs and CPUCLK off latency is less than 4 CPUCLKs.
Notes:
1. All timing is referenced to the internal CPUCLK.
2. CPU_STOP# is an asynchronous input and metastable conditions may exist. This signal is synchronized to the CPUCLKs inside
the ICS9148-11.
3. All other clocks continue to run undisturbed.
4. PD# and PCI_STOP# are shown in a high (true) state.
PCI_STOP# Timing Diagram
PCI_STOP# is an asynchronous input to the ICS9148-11. It is used to turn off the PCICLK (0:5) clocks for low power operation.
PCI_STOP# is synchronized by the ICS9148-11 internally. The minimum that the PCICLK (0:5) clocks are enabled (PCI_STOP# high pulse)
is at least 10 PCICLK (0:5) clocks. PCICLK (0:5) clocks are stopped in a low state and started with a full high pulse width guaranteed.
PCICLK (0:5) clock on latency cycles are only one rising PCICLK clock off latency is one PCICLK clock.
(Drawing shown on next page.)
8
ICS9148-11
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9148 device.)
2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized
inside the ICS9148.
3. All other clocks continue to run undisturbed.
4. PD# and CPU_STOP# are shown in a high (true) state.
PD# Timing Diagram
The power down selection is used to put the part into a very low power state without turning off the power to the part. PD# is an asynchronous
active low input. This signal is synchronized internal by theICS9148-11 prior to its control action of powering down the clock synthesizer.
Internal clocks will not be running after the device is put in power down state. When PD# is active (low) all clocks are driven to a low state
and held prior to turning off the VCOs and the Crystal oscillator. The power on latency is guaranteed to be less than 3mS. The power down
latency is less than three CPUCLK cycles. PCI_STOP# and CPU_STOP# are don’t care signals during the power down operations.
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9148 device).
2. PD# is an asynchronous input and metastable conditions may exist. This signal is synchronized inside the ICS9148.
3. The shaded sections on the VCO and the Crystal signals indicate an active clock is being generated.
9
ICS9148-11
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress
specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = VDDL = 3.3 V +/-5% (unless otherwise stated)
PARAMETER
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Input Low Current
Operating
Supply Current
Outputs Disabled
Supply Current
Input Capacitance
Transition Time
Settling Time
1
1
Clk Stabilization
1
1
SYMBOL
VIH
VIL
IIH
IIL1
IIL2
IDD3.3OP
IDD3.3OE
Skew
VIN = VDD
VIN = 0 V; Inputs with no pull-up resistors
VIN = 0 V; Inputs with pull-up resistors
CL = 0 pF; Select @ 66M
MIN
2
VSS-0.3
-5
-200
CL = 0 pF; With input address to Vdd or GND
CIN
CINX
Logic Inputs
X1 & X2 pins
Ttrans
To 1st crossing of target Freq.
27
TYP
0.1
2.0
-100
75
MAX UNITS
VDD +0.3
V
0.8
V
µA
5
µA
µA
95
mA
18
25
mA
36
5
45
pF
pF
3
ms
Ts
From 1st crossing to 1% target Freq.
5
TSTAB
From VDD = 3.3 V to 1% target Freq.
VT = 1.5 V
5
200
3
500
ms
ps
2
900
4
ns
ps
TCP U-SDRAM2
1
CONDITIONS
TCP U-P CI2 VT = 1.5 V
TREF-IOAP IC VT = 1.5 V
1
10
ms
ICS9148-11
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5% (unless otherwise stated)
PARAMETER
Operating
Supply Current
SYMBOL
IDD2.5OP
CONDITIONS
CL = 0 pF; Select @ 66M
MIN
6
TYP
8
MAX
9.5
UNITS
mA
250
500
ps
2
860
4
ns
ps
TCP U-SDRAM2 VT = 1.5 V; VTL = 1.25 V; SDRAM Leads
1
Skew
1
TCP U-P CI2 VT = 1.5 V; VTL = 1.25 V; CPU Leads
TREF-IOAP IC VT = 1.5 V; VTL = 1.25 V; CPU Leads
1
Guarenteed by design, not 100% tested in production.
Electrical Characteristics - CPU
TA = 0 - 70C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 10 - 20 pF (unless otherwise stated)
PARAMETER
SYMBOL
Output Impedance
1
RDSP 2B
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
1
RDSN2B
VOH2B
VOL2B
IOH2B
IOL2B
tr2B
1
1
Fall Time
tf2B
Duty Cycle
1
d t2B
Skew
t sk2B
1
1
t jcyc-cyc2B
Jitter
tj1s2B
1
1
tjabs2B
1
CONDITIONS
MIN
TYP
MAX UNITS
VO = VDD *(0.5)
15
45
Ω
VO = VDD *(0.5)
IOH = -12.0 mA
IOL = 12 mA
VOH = 1.7 V
VOL = 0.7 V
15
2
45
Ω
V
V
mA
mA
2.6
0.3
-25
26
0.4
-16
VOL = 0.4 V, VOH = 2.0 V
1.7
2
ns
VOH = 2.0 V, VOL = 0.4 V
1.5
2
ns
50
55
%
VT = 1.25 V
60
250
ps
VT = 1.25 V
150
250
ps
VT = 1.25 V
30
150
ps
80
+250
ps
19
VT = 1.25 V
45
VT = 1.25 V
-250
Guarenteed by design, not 100% tested in production.
11
ICS9148-11
Electrical Characteristics - IOAPIC
TA = 0 - 70C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 10 - 20 pF (unless otherwise stated)
PARAMETER
SYMBOL
Output Impedance
1
RDSP 4B
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
1
RDSN4B
VOH4\B
VOL4B
IOH4B
IOL4B
t r4B
1
1
MIN
VO = VDD *(0.5)
10
VO = VDD *(0.5)
IOH = -18 mA
IOL = 18 mA
VOH = 1.7 V
VOL = 0.7 V
10
2
TYP
MAX UNITS
30
Ω
30
Ω
V
V
mA
mA
2.4
0.45
-25
26
0.5
-16
VOL = 0.4 V, VOH = 2.0 V
1.4
1.6
ns
VOH = 2.0 V, VOL = 0.4 V
1.2
1.6
ns
54
60
%
19
Fall Time
tf4B
Duty Cycle
1
d t4B
VT = 1.25 V
1
t jcyc-cyc4B
VT = 1.25 V
1400
VT = 1.25 V
300
400
ps
-1000
800
1000
ps
MIN
10
10
2.6
TYP
MAX UNITS
24
Ω
24
Ω
V
0.4
V
-54
mA
mA
Jitter
tj1s4B
1
1
tjabs4B
1
CONDITIONS
40
VT = 1.25 V
ps
Guarenteed by design, not 100% tested in production.
Electrical Characteristics - REF0
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 20 - 45 pF (unless otherwise stated)
PARAMETER
Output Impedance
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
Fall Time
Duty Cycle
SYMBOL
RDSP 7
RDSN7
VOH7
VOL7
IOH7
IOL7
Tr7
Tf7
1
1
Dt7
1
tj1s7B
1
1
tjabs7B
1
42
2.75
0.3
-62
50
VOL = 0.4 V, VOH = 2.4 V
0.9
2
ns
VOH = 2.4 V, VOL = 0.4 V
0.9
2
ns
54
60
%
VT = 1.5 V
1
tjcyc-cyc7B
Jitter
CONDITIONS
VO = VDD *(0.5)
VO = VDD *(0.5)
IOH = -30 mA
IOL = 23 mA
VOH = 2.0 V
VOL = 0.8 V
40
VT = 1.25 V
1400
ps
VT = 1.25 V
350
ps
VT = 1.25 V
-1000
Guarenteed by design, not 100% tested in production.
12
900
1000
ps
ICS9148-11
Electrical Characteristics - PCI
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 30 pF (unless otherwise stated)
PARAMETER
Output Impedance
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
Fall Time
Duty Cycle
Skew
Jitter
SYMBOL
RDSP 1
RDSN1
VOH1
VOL1
IOH1
IOL1
t r1
tf1
1
1
1
dt1
1
t sk1
tj1s1
CONDITIONS
1
1
MIN
VO = VDD *(0.5)
12
VO = VDD *(0.5)
IOH = -11 mA
IOL = 9.4 mA
VOH = 2.0 V
VOL = 0.8 V
12
2.6
TYP
MAX UNITS
55
Ω
55
Ω
V
V
mA
mA
3.1
0.15
-65
54
0.4
-54
VOL = 0.4 V, VOH = 2.4 V
1.5
2
ns
VOH = 2.4 V, VOL = 0.4 V
1.4
2
ns
50
55
%
VT = 1.5 V
200
500
ps
VT = 1.5 V
10
150
ps
-250
65
250
ps
MIN
TYP
40
VT = 1.5 V
1
tjabs1
1
1
45
VT = 1.5 V
Guarenteed by design, not 100% tested in production.
Electrical Characteristics - SDRAM
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 20 - 30 pF (unless otherwise stated)
PARAMETER
Output Impedance
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
Fall Time
Duty Cycle
Skew
Jitter
SYMBOL
RDSP 3
RDSN3
VOH3
VOL3
IOH3
IOL3
Tr3
Tf3
1
1
1
Dt3
1
Tsk3
Tj1s3
CONDITIONS
1
1
MAX UNITS
VO = VDD *(0.5)
10
24
Ω
VO = VDD *(0.5)
IOH = -30 mA
IOL = 23 mA
VOH = 2.0 V
VOL = 0.8 V
10
2.6
24
Ω
V
V
mA
mA
2.8
0.3
-67
55
0.4
-54
VOL = 0.4 V, VOH = 2.4 V
1.5
2
ns
VOH = 2.4 V, VOL = 0.4 V
1.4
2
ns
50
55
%
VT = 1.5 V
200
500
ps
VT = 1.5 V
50
150
ps
100
250
ps
40
VT = 1.5 V
1
Tjabs3
1
1
45
VT = 1.5 V
-250
Guarenteed by design, not 100% tested in production.
13
ICS9148-11
SSOP Package
SYMBOL
A
A1
A2
B
C
D
E
e
H
h
L
N
∝
X
COMMON DIMENSIONS
MIN.
NOM.
MAX.
.095
.101
.110
.008
.012
.016
.088
.090
.092
.008
.010
.0135
.005
.010
See Variations
.292
.296
.299
0.025 BSC
.400
.406
.410
.010
.013
.016
.024
.032
.040
See Variations
0°
5°
8°
.085
.093
.100
VARIATIONS
AC
MIN.
.620
D
NOM.
.625
N
MAX.
.630
48
Ordering Information
ICS9148F-11
Example:
ICS XXXX F - PPP
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
F=SSOP
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
14
ICS reserves the right to make changes in the device data identified in this
publication without further notice. ICS advises its customers to obtain the latest
version of all device data to verify that any information being relied upon by the
customer is current and accurate.
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