CXA3086Q
6-bit 140MSPS Flash A/D Converter
Description
The CXA3086Q is an 6-bit high-speed flash A/D
converter capable of digitizing analog signals at the
maximum rate of 140MSPS. ECL, PECL or TTL can
be selected as the digital input level in accordance
with the application. The TTL digital output level
allows 1: 2 demultiplexed output.
48 pin QFP (Plastic)
Features
• Differential linearity error: ±0.2LSB or less
• Integral linearity error: ±0.2LSB or less
• High-speed operation with a maximum conversion
rate of 140MSPS
• Low input capacitance: 7pF
• Wide analog input bandwidth: 200MHz
• Low power consumption: 358mW
• Low error rate
• Excellent temperature characteristics
• 1: 2 demultiplexed output
• 1/2 frequency divided clock output
(with reset function)
• Compatible with ECL, PECL and TTL digital input levels
• Single +5V power supply operation available
• Surface mounting package
P2D3
5
DGND2
P2D4
6
P2D0 (LSB)
P2D5 (MSB)
7
P2D2
DGND2
8
P2D1
DVCC2
9
RESET/E
RESETN/T
Applications
• Magnetic recording (PRML)
• Communications (QPSK, QAM)
• LCDs
• Digital oscilloscopes
12 11 10
RESETN/E
Pin Configuration (Top View)
Structure
Bipolar silicon monolithic IC
4
3
2
1
DVEE3 13
48 DVCC2
47 DVCC1
AGND 14
46 DGND1
VRBS 15
VRB 16
45 N.C.
44 PS
AVCC 17
43 CLKOUT
N.C. 18
42 INV
VIN 19
41 SELECT
AVCC 20
40 N.C.
VRT 21
39 DGND1
VRTS 22
38 DVCC1
AGND 23
DGND3 24
37 DVCC2
DGND2
P1D5 (MSB)
P1D4
P1D3
P1D2
P1D1
DGND2
P1D0 (LSB)
DVCC2
CLK/T
CLKN/E
CLK/E
25 26 27 28 29 30 31 32 33 34 35 36
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E95619C77
CXA3086Q
Absolute Maximum Ratings (Ta = 25°C)
• Supply voltage
AVCC, DVCC1, DVCC2
DGND3
DVEE3
DGND3 – DVEE3
Unit
V
V
V
V
–0.5 to +7.0
–0.5 to +7.0
–7.0 to +0.5
–0.5 to +7.0
• Analog input voltage
• Reference input voltage
VIN
VRT – 2.7 to AVCC
V
VRT
2.7 to AVCC
V
VRB
VIN – 2.7 to AVCC
V
|VRT – VRB|
2.5
V
• Digital input voltage
ECL (∗∗∗/E∗1)
DVEE3 to +0.5
V
PECL (∗∗∗/E)
–0.5 to DGND3
V
TTL (∗∗∗/T, INV, PS)
–0.5 to DVCC1
V
other (SELECT)
–0.5 to DVCC1
V
VID∗2 (|∗∗∗/E – ∗∗∗N/E|)
2.7
V
• Storage temperature
Tstg
–65 to +150
°C
• Allowable power dissipationPD
1.2
W
(when mounted on a glass fabric base epoxy board with 76mm x 114mm, 1.6mm thick)
Recommended Operating Conditions
•
•
•
•
•
•
With a single power supply With dual power supplies Unit
Min.
Typ.
Max.
Min.
Typ.
Max.
Supply voltage
DVCC1, DVCC2, AVCC
+4.75
+5.0
+5.25 +4.75
+5.0
+5.25
V
DGND1, DGND2, AGND –0.05
0
+0.05 –0.05
0
+0.05
V
DGND3
+4.75
+5.0
+5.25 –0.05
0
+0.05
V
–0.05
0
+0.05
–5.5
–5.0
–4.75
V
DVEE3
Analog input voltage
VIN
VRB
VRT
VRB
VRT
V
Reference input voltage VRT
+2.9
+4.1
+2.9
+4.1
V
VRB
+1.4
+2.6
+1.4
+2.6
V
|VRT – VRB|
1.5
2.1
1.5
2.1
V
Digital input voltage
ECL (∗∗∗/E)
: VIH
DGND3 – 1.05
DGND3 – 0.5 V
: VIL
DGND3 – 3.2
DGND3 – 1.4 V
PECL (∗∗∗/E)
: VIH DGND3 – 1.05 DGND3 – 0.5
V
: VIL DGND3 – 3.2
DGND3 – 1.4
V
TTL (∗∗∗/T, INV, PS): VIH 2.0
2.0
V
: VIL
0.8
0.8
V
other (SELECT) : VIH
DVCC1
DVCC1
V
: VIL
DGND1
DGND1
V
∗
2
VID (|∗∗∗/E – ∗∗∗N/E|)
0.4
0.8
0.4
0.8
V
Maximum conversion rate Fc
(Straight mode)
100
100
MSPS
(DMUX mode)
140
140
MSPS
Ambient temperature
Ta
–20
+75
–20
+75
°C
∗1 ∗∗∗/E and ∗∗∗/T indicate CLK/E and CLK/T, etc. for the pin name.
∗2 VID: Input Voltage Differential
ECL and PECL switching level
DGND3
VIH (max.)
VIL
VTH (DGND3 – 1.2V)
VID
VIH
VIL (min.)
–2–
CXA3086Q
Block Diagram
AVCC
DVCC1
INV
17 20
DVCC2
38 47
42
9
DGND3
28 37 48
24
VRTS 22
r1
VRT 21
(MSB)
r
35 P1D5
1
34 P1D4
LATCHA
2
r
•
•
•
33 P1D3
32 P1D2
6bit
31 P1D1
30 P1D0
30
(LSB)
31
r
32
r
ENCODER
VIN 19
6bit
6bit LATCH
r
TTLOUT
r
6bit
(MSB)
33
r2
r
6 P2D4
62
6bit
TTLOUT
r
•
•
•
LATCHB
r
7 P2D5
5 P2D3
4 P2D2
3 P2D1
63
VRB 16
2 P2D0
VRBS 15
(LSB)
18
CLK/T 27
40
Delay
CLK/E 25
N.C.
45
CLKN/E 26
D
Q
Q
RESETN/T 10
Select
43 CLKOUT
RESETN/E 12
RESET/E 11
14 23
AGND
44
41
PS
SELECT
–3–
39 46
DGND1
1
8 29 36
DGND2
13
DVEE3
CXA3086Q
Pin Description and I/O Pin Equivalent Circuit
Pin
No.
Symbol
I/O
Standard
voltage level
Equivalent circuit
Description
14, 23
AGND
GND
Analog ground.
Separated from the digital ground.
17, 20
AVCC
+5V
(typ.)
Analog power supply.
Separated from the digital power
supply.
1, 8,
DGND1
29, 36,
DGND2
39, 46
GND
Digital ground.
9, 28,
DVCC1
37, 38,
DVCC2
47, 48
+5V
(typ.)
Digital power supply.
24
+5V (typ.)
(With a
single
power
supply)
DGND3
Digital power supply.
Ground for ECL input.
+5V for PECL and TTL input.
GND
(With dual
power
supplies)
13
GND
(With a
single
power
supply)
DVEE3
Digital power supply.
–5V for ECL input.
Ground for PECL and TTL input.
–5V (typ.)
(With dual
power
supplies)
No connected pin.
Not connected with the internal
circuits.
18, 40,
N.C.
45
25
CLK/E
I
Clock input.
I
CLK/E complementary input.
When left open, this pin goes to the
threshold potential.
Only CLK/E can be used for
operation, but complementary input
is recommended to attain fast and
stable operation.
DGND3
26
CLKN/E
r
r
12 25
ECL/
PECL
RESETN/E
I
1.2V
12
11 26
DVEE3
11
RESET/E
r
r
Reset input.
When the input is set to low level,
the built-in CLK frequency divider
circuit can be reset.
RESETN/E complementary input.
When left open, this pin goes to the
threshold voltage. Only RESETN/E
can be used for operation.
I
–4–
CXA3086Q
Pin
No.
Symbol
I/O
Standard
voltage level
Equivalent circuit
Description
DVCC1
27
CLK/T
r/2
I
TTL
10 27
1.5V
r
10
RESETN/T
I
DGND1
DVEE3
42
INV
TTL
44
PS
Reset input.
When left open, this input goes to
high level. When the input is set to
low level, the built-in CLK frequency
divider circuit can be reset.
Data output polarity inversion input.
When left open, this input goes to
high level.
(See Table 1. I/O Correspondence
Table.)
DVCC1
I
Clock input.
Power saving input.
When the input is set to low level,
the power saving mode is set.
In this time the all TTL outputs go
into the high-impedance state.
Normally, set to high level or left
open.
42 44
I
DGND1
DVEE3
DVCC1
41
Vcc
or
GND
SELECT
Data output mode selection.
(See Table 2. Operating Mode
Table.)
41
DGND1
DVEE3
22
VRTS
O
+4.0V
(typ.)
Reference voltage sense.
By-pass to AGND with a 0.1µF chip
capacitor.
22
21
r1
r
Comparator 1
r
21
16
VRT
VRB
I
I
VRTS
+r1 x Iref
Comparator 2
Top reference voltage.
By-pass to AGND with a 1µF tantal
capacitor and a 0.1µF chip
capacitor.
Comparator 62
Bottom reference voltage.
By-pass to AGND with a 1µF tantal
capacitor and a 0.1µF chip
capacitor.
r
r
r
VRBS
–r2 x Iref
r
r
Comparator 63
r2
15
VRBS
O
+2.0V
(typ.)
r
Reference voltage sense.
By-pass to AGND with a 0.1µF chip
capacitor.
16
15
–5–
CXA3086Q
Pin
No.
Symbol
I/O
Standard
voltage level
Equivalent circuit
AVCC
Description
Comparator
AVCC
19
VIN
I
VRT
to
VRB
Analog input.
DVEE3
30
to
35
P1D0
to
P1D5
O
2
to
7
P2D0
to
P2D5
O
Vref
19
AGND
Port 1 side data output.
DVCC1
DVCC2
2
TTL
100k
DGND1
43
CLKOUT
to
7
30 to 35
Port 2 side data output.
43
DGND2
DVEE3
Clock output.
(See Table 2. Operating Mode Table.)
O
–6–
CXA3086Q
Electrical Characteristics
(DVCC1, 2, AVCC, DGND3 = +5V, DGND1, 2, AGND, DVEE3 = 0V, VRT = 4V, VRB = 2V, Ta = 25°C)
Item
Symbol
Conditions
Min.
Resolution
EIL
EDL
Analog input
Analog input capacitance
Analog input resistance
Analog input current
CIN
RIN
IIN
Reference input
Reference resistance
Reference current
Residual resistance r1
r2
Rref∗3
Iref∗4
r1
r2
Digital input (ECL, PECL)
Digital input voltage: High
: Low
Threshold voltage
Digital input current : High
: Low
Digital input capacitance
VIH
VIL
VTH
IIH
IIL
Digital input (TTL)
Digital input voltage: High
: Low
Threshold voltage
Digital input current : High
: Low
Digital input capacitance
VIH
VIL
VTH
IIH
IIL
Digital output (TTL)
Digital output voltage : High VOH
: Low
VOL
Leak current during output off IOZ
Output rise time
Output fall time
Max.
6
DC characteristics
Integral linearity error
Differential linearity error
Switching characteristics
Maximum conversion rate
Aperture jitter
Sampling delay
Clock high pulse width
Clock low pulse width
RESET Signal setup time
RESET Signal hold time
CLKOUT output delay
Data output delay
Typ.
Fc
Taj
Tds
Tpw1
Tpw0
T_rs
T_rh
Td_clk
Tdo1
Tdo2
Tr
Tf
VIN = 2Vp-p, Fc = 5MSPS
VIN = +3.0V + 0.07Vrms
bits
±0.2
±0.2
LSB
LSB
150
125
pF
kΩ
µA
308
12.5
5.7
5.7
Ω
mA
Ω
Ω
DGND3 – 0.5
DGND3 – 1.4
V
V
V
µA
µA
pF
7
16
0
160
6.5
3.0
3.0
225
9.0
4.2
4.2
DGND3 – 1.05
DGND3 – 3.2
DGND3 – 1.2
VIH = DGND3 – 0.8V
VIL = DGND3 – 1.6V
–50
–75
+50
0
5
0
0
5
V
V
V
µA
µA
pF
0.5
70
V
V
µA
2.0
0.8
1.5
VIH = 3.5V
VIL = 0.2V
–50
–500
IOH = –2mA
IOL = 1mA
Power saving mode
–15
DMUX mode
140
CLK
CLK
RESETN – CLK
RESETN – CLK
DMUX mode
0.8 to 2.0V
0.8 to 2.0V
(CL = 5pF)
(CL = 5pF)
(CL = 5pF)
(CL = 5pF)
(CL = 5pF)
∗ These characteristics are for PECL input, unless otherwise specified.
–7–
2.4
3
2.9
2.9
3.5
0
4.5
T∗5
6.5
10
4.5
7
T+1
8
2
2
Unit
6
8
T+2
10
MSPS
ps
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CXA3086Q
Item
Symbol
Conditions
Dynamic characteristics
Input bandwidth
S/N ratio
Min.
VIN = 2Vp-p, –3dB
Fc = 140MSPS,
fin = 1kHz Fs
DMUX mode
Fc = 140MSPS,
fin = 34.999MHz Fs
DMUX mode
Fc = 140MSPS,
fin = 1kHz Fs
DMUX mode
Error > 4LSB
Fc = 140MSPS,
fin = 34.999MHz Fs
DMUX mode
Error > 4LSB
Fc = 100MSPS,
fin = 24.999MHz Fs
straight mode
Error > 4LSB
ICC
IEE
Pd∗7
ICC + IEE
Pd
54.0
0.4
290
2.0
28
Power saving mode
Power saving mode
Unit
37.0
MHz
dB
34.5
dB
{
{
{
Power supply
Supply current
Supply current
Power consumption
Supply current
Power consumption
Max.
200
{
{
Error rate
Typ.
67.5
0.6
360
10–12
TPS∗6
10–9
TPS
10–9
TSP
90
0.8
470
8.0
58
mA
mA
mW
mA
mW
∗3 Rref: Resistance value between VRT and VRB
∗4 Iref = VRT – VRB
Rref
1
∗5 T =
Fc
∗6 TPS: Times Per Sample
∗7 Pd = (ICC + IEE) · VCC +
(VRT – VRB) 2
Rref
INV
Step
1
D5
VRTS
VRBS
63
62
:
32
31
:
1
0
1 1 1 1 1
1 1 1 1 1
:
1 0 0 0 0
0 1 1 1 1
:
0 0 0 0 0
0 0 0 0 0
0
D0 D5
1 0 0 0 0
0 0 0 0 0
:
0 0 1 1 1
1 1 0 0 0
:
1 1 1 1 1
0 1 1 1 1
Table 1. I/O Correspondence Table
D0
0 0
0 1
1 1
0 0
1 0
1 1
Step
VIN
63
62
61
60
59
58
·
·
·
·
·
·
·
5
4
3
2
1
0
1LSB
r1 × Iref
r2 × Iref
VRT VRTS
VRBS VRB
VIN
–8–
CXA3086Q
Electrical Characteristics Measurement Circuit
Sampling Delay Measurement Circuit
Aperture Jitter Measurement Circuit
Current Consumption Measurement Circuit
5V
5V
A Icc
A IEE
100MHz
4V
AVCC
DVCC1
DVCC2
VRT
1.95V
OSC1
φ: Variable
DGND3
VIN
6
fr
VIN
Logic
Analizer
CXA3086Q
5MHz PECL
CLK/E
CLK
1024
samples
OSC2
DGND2
DGND1
AGND
VRB
2V
Amp
ECL
Buffer
DVEE3
100MHz
Integral Linearity Error Measurement Circuit
Differential Linearity Error Measurement Circuit
Aperture Jitter Measurement Method
+V
VRT
VIN
S2
VRB
S1: ON when A < B
S2: ON when A > B
S1
CLK
A<B A>B
Comparator
VIN
CXA3086Q
6
A6
to
A1
B6
to
B1
A0
B0
VIN
6
Buffer
CLK
“0”
00···0
to
11···0
Controller
Where σ (LSB) is the deviation of the output codes when
the largest slew rate point is sampled at the clock which
has exactly the same frequency as the analog input
signal, the aperture jitter Taj is:
Taj = σ/
Error Rate Measurement Circuit
VIN
FC – 1kHz
4
2Vp-p Sin Wave
CXA3086Q
6
CLK
+
4LSB
Signal
Source
∆υ
∆t
= σ/ ( 64
2
× 2πf )
A
Latch
B
CLK
σ (LSB)
Sampling timing fluctuation
(= aperture jitter)
“1”
DVM
Signal
Source
33
32
31
30
29
∆υ
∆t
–V
1/8
FC
–9–
Latch
Comparator
A>B
Pulse
Counter
CXA3086Q
Description of Operating Modes
The CXA3086Q has two types of operating modes which are selected with Pin 41 (SELECT).
Operating
mode
SELECT
Maximum
conversion rate
Data output
Clock output
DMUX mode
VCC
140MSPS
Demultiplexed output
70Mbps
The input clock is 1/2 frequency divided
and output.
70MHz
Straight mode
GND
100MSPS
Straight output
100Mbps
The input clock is inverted and output.
100MHz
Table 2. Operating Mode Table
1. DMUX mode (See Application Circuits (1), (2) and (3).)
Set the SELECT pin to Vcc for this mode. In this mode, the clock frequency is divided by 2 in the IC, and the
data is output after being demultiplexed by this 1/2 frequency divided clock. The 1/2 frequency divided clock,
which has adequate setup time and hold time for the output data, is output from the CLKOUT pin.
When resetting this 1/2 frequency divided clock, the low level of the RESET signal should be input to the
RESETN pin (Pin 10 or 12). The RESET signal requires the setup time (T_rs ≥ 3.5ns) and hold time (T_rh ≥
0ns) to the clock rising edge because it is synchronized with and taken in the clock. Therefore, set the RESET
signal to low for T_rs (min.) + T_rh (min.) = 3.5ns or longer to the clock rising edge.
The reset period can be extended by making the low level period of the RESET signal longer because the
clock output pin is fixed to low (reset) during the low level period at the clock rising edge. If the reset start
timing is regarded as not important, the timing where the RESET signal is set from high to low is not so
consequence. However, when the reset is released this timing must become significant because the timing is
used to commence the 1/2 frequency divided clock. In this case, the setup time (T_rs) is also necessary.
See the timing chart for detail. (This chart shows the example of reset for 2T.)
The A/D converter can operate at FC (min.) = 140MSPS in this mode.
– 10 –
CXA3086Q
When the RESET signal is not used.
AAAA
AAAA
AAAA
AAAA
AAAA
CLK
CXA3086Q
CLK
CLK
A A
CLKOUT
6bit
DATA
RESETN
CXA3086Q
CLK
B B
CLKOUT
6bit
DATA
RESETN
When the RESET signal is used.
AAA
AAA
AAA
AAA
AAA
CLK
RESET signal
CXA3086Q
CLK
A
CLK
CLKOUT
DATA
RESETN
CXA3086Q
B
CLK
RESET signal
RESETN
(Reset period)
6bit
CLKOUT
(Reset period)
6bit
DATA
2. Straight mode (See Application Circuits (4), (5) and (6).)
Set the SELECT pin to GND for this mode. In this mode, data output can be obtained in accordance with the
clock frequency applied to the A/D converter for applications which use the clock applied to the A/D converter
as the system clock.
The A/D converter can operate at Fc (min.) = 100MSPS in this mode.
Digital input level and supply voltage settings
The logic input level for the CXA3086Q supports ECL, PECL and TTL levels.
The power supplies (DVEE3, DGND3) for the logic input block must be set to match the logic input (CLK and
RESET signals) level.
Digital input level
DVEE3
DGND3
ECL
PECL
TTL
–5V
0V
0V
0V
+5V
+5V
Supply voltage Application circuits
±5V
+5V
+5V
Table 3. Logic Input Level and Power Supply Settings
– 11 –
(1) (4)
(2) (5)
(3) (6)
CXA3086Q
Application Circuit 1
(1) DMUX ECL input
+5V (D)
DG
P2D0 to P2D5
6 bit Digital
Data
DG
ECL RESET Signal
12 11 10 9
8
7
6
5
4
3
2
1
–5V (D)
13
48
AG
14
47
15
46
AG
16
45
+5V (A)
17
44
2V
AG
+5V (A)
18
43
19
42
20
41
AG
21
40
22
39
AG
23
38
DG
24
4V
6 bit Digital Data
Latch
37
+5V (D)
DG
+5V (D)
DG
+5V (D)
25 26 27 28 29 30 31 32 33 34 35 36
ECL-CLK
P1D0 to P1D5
6 bit Digital
Data
DG
DG
+5V (D)
6 bit Digital Data
Latch
(2) DMUX PECL input
+5V (D)
DG
DG
PECL RESET Signal
12 11 10 9
8
7
6
5
4
3
2
13
48
AG
14
47
15
46
AG
16
45
+5V (A)
17
44
AG
+5V (A)
4V
AG
6 bit Digital Data
Latch
1
DG
2V
P2D0 to P2D5
6 bit Digital
Data
18
43
19
42
20
41
21
40
22
39
AG
23
38
+5V (D)
24
37
+5V (D)
DG
+5V (D)
DG
+5V (D)
25 26 27 28 29 30 31 32 33 34 35 36
PECL-CLK
P1D0 to P1D5
6 bit Digital
Data
DG
DG
+5V (D)
6 bit Digital Data
Latch
(3) DMUX TTL input
+5V (D)
DG
DG
TTL RESET Signal
12 11 10 9
8
7
6
5
4
3
2
13
48
AG
14
47
15
46
AG
16
45
+5V (A)
17
44
AG
+5V (A)
18
43
19
42
20
41
AG
21
40
22
39
AG
23
38
+5V (D)
24
4V
6 bit Digital Data
Latch
1
DG
2V
P2D0 to P2D5
6 bit Digital
Data
37
+5V (D)
DG
+5V (D)
DG
+5V (D)
25 26 27 28 29 30 31 32 33 34 35 36
TTL-CLK
DG
DG
+5V (D)
– 12 –
P1D0 to P1D5
6 bit Digital
Data
6 bit Digital Data
Latch
CXA3086Q
(4) Straight ECL input
+5V (D)
DG
12 11 10 9
8
DG
6
7
5
4
1
2
3
–5V (D)
13
48
AG
14
47
15
46
AG
16
45
+5V (A)
17
44
2V
AG
+5V (A)
4V
AG
18
43
19
42
20
41
21
40
22
39
AG
23
38
DG
24
37
+5V (D)
DG
+5V (D)
DG
DG
+5V (D)
25 26 27 28 29 30 31 32 33 34 35 36
ECL-CLK
P1D0 to P1D5
6 bit Digital
Data
DG
DG
+5V (D)
ECL
6 bit Digital Data
Latch
TTL
(5) Straight PECL input
+5V (D)
DG
12 11 10 9
8
DG
7
6
5
4
3
2
1
DG
13
48
AG
14
47
15
46
16
45
17
44
2V
AG
+5V (A)
+5V (D)
DG
18
43
19
42
+5V (D)
20
41
DG
AG
21
40
22
39
AG
23
38
+5V (D)
24
AG
+5V (A)
4V
37
DG
+5V (D)
25 26 27 28 29 30 31 32 33 34 35 36
PECL-CLK
P1D0 to P1D5
6 bit Digital
Data
DG
DG
+5V (D)
PECL
6 bit Digital Data
Latch
TTL
(6) Straight TTL input
+5V (D)
DG
12 11 10 9
8
DG
7
6
5
4
3
2
1
DG
13
48
AG
14
47
15
46
AG
16
45
+5V (A)
17
44
2V
+5V (D)
DG
18
43
19
42
+5V (D)
20
41
DG
AG
21
40
22
39
AG
23
38
+5V (D)
24
AG
+5V (A)
4V
37
DG
+5V (D)
25 26 27 28 29 30 31 32 33 34 35 36
TTL-CLK
DG
+5V (D)
DG
– 13 –
P1D0 to P1D5
6 bit Digital
Data
6 bit Digital Data
Latch
CXA3086Q
Application Circuit 2
Straight Mode TTL I/O (When a single power supply is used)
AG
Analog
input
1µF
4V
+5V
(A)
AG
AG AG
AG
1µF
10µF
VRTS
2V
short
VRBS
short
23
22
21
20
19
18
17
16
15
14
AGND
VRTS
VRT
AVCC
VIN
N.C.
AVCC
VRB
VRBS
AGND
RESETN/E 12
25 CLK/E
26 CLKN/E
TTL CLK
13
DVEE3
24
DGND3
DG
RESET/E 11
27 CLK/T
RESETN/T 10
28 DVCC2
DVCC2 9
29 DGND2
DGND2 8
(LSB) P1D0
30 P1D0
P2D5 7
P2D5 (MSB)
P1D1
31 P1D1
P2D4 6
P2D4
P1D2
32 P1D2
P2D3 5
P2D3
P1D3
33 P1D3
P2D2 4
P2D2
P1D4
34 P1D4
P2D1 3
P2D1
(MSB) P1D5
35 P1D5
P2D0 2
P2D0 (LSB)
DVCC1
DGND1
N.C.
SELECT
INV
CLKOUT
PS
N.C.
DGND1
DVCC1
DVCC2
DGND2 1
DVCC2
36 DGND2
37
38
39
40
41
42
43
44
45
46
47
48
CLKOUT
10µF
DG
+5V
(D)
Short the analog system and digital system at one point immediately under the A/D converter.
See the Notes on Operation.
is the chip capacitor of 0.1µF.
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
– 14 –
CXA3086Q
DMUX Mode Timing Chart (Select = VCC)
Tds
N–1
N+6
4.5ns (typ.)
N+5
N+7
VIN
N+3
N
T
N+4
N+2
N+1
CLK
Tpw1 Tpw0
Tdo2;
8ns (typ.)
6.5ns (min.)
10ns (max.)
P1D0 to D5
N+1
P2D0 to D5
N
Td_clk;
AA
AA
AA
AAAAAA
7ns (typ.)
Tdo1
T + 1ns (typ.)
8ns (max.)
4.5ns (min.)
CLK OUT
(Reset period)
2.0V
2.0V
2.0V
0.8V
0.8V
0.8V
4.5ns (min.)
8ns (max.)
T_rh
T_rs
T_rh
T_rs
Td_clk
RESET signal
– 15 –
2.0V
0.8V
2.0V
0.8V
≈T
N+3
N+2
≈T
CXA3086Q
Straight Mode Timing Chart (Select = GND)
N+2
N–1
N+1
VIN
N+3
Tds
4.5ns (typ.)
N
T
CLK
Tpw1
Tpw0
Tdo2; 8ns (typ.)
6.5ns (min.)
10ns (max.)
P1D0 to D5
N–4
2.0V
N–3
N–2
N–1
N
N–4
N–3
N–2
N–1
0.8V
P2D0 to D5
N–5
2.0V
0.8V
Td_clk; 7ns (typ.)
4.5ns (min.)
8ns (max.)
CLK OUT
(CLK is inverted and output.)
2.0V
0.8V
RESET signal
– 16 –
CXA3086Q
Timing of A/D Converter and Peripheral Circuit
In the maximum clock rate of the DEMUX Mode, the timing of 3 channels of ADC CLK OUT in same phase is
described in detail as below.
For example, the CLK OUT from one of the ADC is used as the data latch clock. The clock delay and data
delay are showed in the following specification, i.e.
Td_clk
4.5ns (min.) to 8.0ns (max.)
Tdo2
6.5ns (min.) to 10ns (max.)
These values are considered in all the temperature change and power supply variation. When the maximum
clock rate 140MSPS is used, the set-up time (ts) is seemed to be very small from above specifications. But the
3 channels of ADC are in the same circuit board, so that the DATA OUT delay and CLK OUT delay will be
changed in same trend at the same condition of the temperature change and power supply variation. As a
result, 0.5ns of the delay will be faster, when the highest temperature and highest power supply is used. Also,
0.5ns of the delay will be later, when the lowest temperature and lowest power supply is used. These delay
can be omitted in this case.
When Ta = 25°C, VCC = +5V, the clock delay and data delay are
Td_clk
5.0ns (min.) to 7.5ns (max.)
Tdo2
7.0ns (min.) to 9.5ns (max.)
The timing of the DATA OUT and CLK OUT with above delay variation is showed in below. Consequently, the
set-up time for the data latching can be obtained as ts (min.) = 2.5ns. The output delay change of the DATA OUT
and CLK OUT due to the temperature change and the power supply variation should have the same trend of
the delay change, the minimum ts = 2.5ns can be guaranteed at any temperature change and power supply
variation.
Analog input R
Analog input G
Analog input B
CLK
RESET
CXA3086Q
Vin
P1D/out
CLK
P2D/out
RESET CLK OUT
Gate Array
6bit
6bit
CXA3086Q
Vin
P1D/out
CLK
P2D/out
RESET CLK OUT
Latch
6bit
6bit
CXA3086Q
Vin
P1D/out
CLK
P2D/out
RESET CLK OUT
6bit
6bit
7ns
( = 1/140MSPS)
CLK
th-reset
RESET signal
Td_clk (min.)
5.0ns
<4.5ns>
CLK OUT
Td_clk (max.)
7.5ns
<8.0ns>
Tdo2 (min.)
7.0ns
<6.5ns>
Tdo2 (min.)
9.5ns
<10ns>
ts (min.)
2.5ns
th (min.)
6.5ns
P1D/out
P2D/out
14ns
Note: In the timing chart, the values in the brackets < > are included all the temperature change and the
power supply variation.
– 17 –
CXA3086Q
Notes on Operation
• The CXA3086Q is a high-speed A/D converter which is capable of TTL, ECL and PECL level clock input.
Characteristic impedance should be properly matched to ensure optimum performance during high-speed
operation.
• The power supply and grounding have a profound influence on converter performance. The power supply
and grounding method are particularly important during high-speed operation. General points for caution are
as follows.
— The ground pattern should be as large as possible. It is recommended to make the power supply and
ground patterns wider at an inner layer using a multi-layer board.
— To prevent interference between AGND and DGND and between AVcc and DVcc, make sure the
respective patterns are separated. To prevent a DC offset in the power supply pattern, connect the AVcc
and DVcc lines at one point each via a ferrite-bead filter Shorting the AGND and DGND patterns in one
place immediately under the A/D converter improves A/D converter performance.
— Ground the power supply pins (AVcc, DVcc1, DVcc2, DVEE3) as close to each pin as possible with a
0.1µF or larger ceramic chip capacitor.
(Connect the AVcc pin to the AGND pattern and the DVcc1, DVcc2 and DVEE3 pins to the DGND pattern.)
— The digital output wiring should be as short as possible. If the digital output wiring is long, the wiring
capacitance will increase, deteriorating the output slew rate and resulting in reflection to the output
waveform since the original output slew rate is quite fast.
• The analog input pin VIN has an input capacitance of approximately 7pF. To drive the A/D converter with
proper frequency response, it is necessary to prevent performance deterioration due to parasitic capacitance
or parasitic inductance by using a large capacity drive circuit. keeping wiring as short as possible, and using
chip parts for resistors and capacitors, etc.
• The VRT and VRB pins must have adequate by-pass to protect them from high-frequency noise. By-pass them
to AGND with an approximately 1µF tantal capacitor and 0.1µF chip capacitor as short as possible.
• The offset for residual resistance is generated each for the reference voltage pins VRT and VRB.
When the offset voltage has no influence on the IC operation, the voltage should be applied to the VRT and
VRB pins directly, keeping the VRBS pin open. When the reference voltage is to be supplied to these pins
precisely, form the feedback loop circuit with VRT and VRB as a force pin and adjust the offset voltage to be
0V. See the “Application Circuit 2” for details.
• If the CLKN/E pin is not used, by-pass this pin to DGND with an approximately 0.1µF capacitor. At this time,
approximately DGND3 – 1.2V voltage is generated. However, this is not recommended for use as threshold
voltage VBB as it is too weak.
• When the digital input level is ECL or PECL level, ∗∗∗/E pins should be used and ∗∗∗/T pins left open. When
the digital input level is TTL, ∗∗∗/T pins should be used and ∗∗∗/E pins left open.
– 18 –
CXA3086Q
Example of Representative Characteristics
Current consumption vs.
Ambient temperature characteristics
Current consumption vs.
Conversion rate characteristics
90
Current consumption [mA]
Current consumption [mA]
70
65
60
55
50
80
fin = fCLK – 1kHz
4
DMUX mode
CL = 5pF
70
60
50
–25
25
Ta – Ambient temperature [°C]
75
0
Analog input current vs.
Analog input voltage characteristics
70
Fc – Conversion rate [MSPS]
140
Reference current vs.
Ambient temperature characteristics
11
Reference current [mA]
Analog input current [µA]
100
VRT = 4V
VRB = 2V
50
10
9
8
7
0
2
3
Analog input voltage [V]
4
–25
– 19 –
25
Ta – Ambient temperature [°C]
75
CXA3086Q
SNR vs. Input frequency response
Error rate vs. Conversion rate characteristics
40
10–6
Fc = 140MSPS
Error rate [TPS]
SNR [dB]
10–7
35
fin = fCLK – 1kHz
4
Error > 4LSB
10–8
10–9
30
10–10
1
3
5
10
30
Input frequency [MHz]
50
100
Fc – Maximum conversion rate [MSPS]
Maximum conversion rate vs.
Ambient temperature characteristics
180
170
fCLK
– 1kHz
4
Error > 4LSB
Error rate: 10–9TPS
fin =
160
150
140
–25
25
Ta – Ambient temperature [°C]
75
– 20 –
140
160
180
Fc – Conversion rate [MSPS]
200
CXA3086Q
CXA3086Q Evaluation Board
Description
The CXA3086Q Evaluation Board is a special board designed to maximize and facilitate the evaluation
performance of the CXA3086Q. After latching the CXA3086Q output data with a frequency divided clock, the
analog signal can be regenerated by a 10-bit high-speed D/A converter. The latched data can also be
extracted externally via a 24-pin cable connector.
Features
• Resolution:
• Maximum conversion rate:
• Supply voltage:
• Dual analog input pins:
6 bits
140MSPS (min.)
±5.0V
DIR.IN: AC coupling input pin
AMP.IN: Operational amplifier input pin
• Clock frequency division: 1/1 to 1/16
Absolute Maximum Ratings
• Supply voltage VCC
VEE
–0.5 to +7.0
–7.0 to +0.5
Recommended Operating Conditions
• Supply voltage VCC
GND
VEE
• Analog input
AMP. IN
DIR. IN
• Clock input
CLK. IN
V
V
Min.
+4.75
–5.25
–0.75
1.5
0.8
– 21 –
Typ.
+5.0
0
–5.0
0
2.0
1.0
Max.
+5.25
–4.75
+1.05
2.2
1.2
V
V
V
V
Vp-p
Vp-p
CLK IN
AMP IN
DIR IN
DGND
CON3
AGND
CON1
AGND
CON2
VEE
DGND
51Ω
AGND
82Ω
AGND
51Ω
CON6
GND
0.1µF
1kΩ
VBB
× (–2)
1kΩ
390Ω
AGND
VCC
130Ω
270Ω
Vrt
Vrb
Vrb
Vrt
B
S1
A
(PECL)
4
(PECL)
OFFSET
OFFSET. R3
SW1
P2D0 to D5
INV
SW2
VRB
(TTL)
4
CLK
S2
CLKOUT
P1D0 to D5
VIN CXA3086Q
VRT
Straight
SW4
CON8
(TTL)
(TTL)
6
(TTL)
6
INV
P1 side DATA
PS
SW3
A/D
D/A
INV
INV
SELECT
PS
DMUX
NORM
NORM
NORM
LATCH
LATCH
VRT. R2
Counter
P2 side DATA
CON7
(TTL)
6
(TTL)
6
TTL/ECL
TTL/ECL
VRB. R1
PECL/TTL
– 22 –
TTL/ECL
(ECL)
(ECL)
6
(ECL)
6
AGND
CON5
AGND
CON4
D/A OUT
(–1.0V)
P1 side OUT
P2 side OUT
D/A OUT
(–1.0V)
FULL SCALE. R4 FULL SCALE. R5
DAC
DAC
Block Diagram
CXA3086Q
CXA3086Q
Pin Description and I/O Level
Pin No.
Symbol
I/O
Standard
I/O level
Current
Description
CON1
AMP. IN
I
0.95Vp-p
Doubles the analog input signal amplitude using the
operational amplifier. The input impedance is 50Ω.
CON2
DIR. IN
I
2.0Vp-p
AC coupling input. Suitable for sine waves and other
repeating waveforms. The input impedance is 50Ω.
CON3
CLK. IN
I
1.0Vp-p
The CXA3086Q operates at the PECL level clock
using the sine wave-to-PECL conversion circuit.
The input impedance is 50Ω.
CON4
P2 side OUT
O
0 to –1V
Allows the D/A converted waveform of the
CXA3086Q port 2 side data to be observed.
The output impedance is 50Ω.
CON5
P1 side OUT
O
0 to –1V
Allows the D/A converted waveform of the
CXA3086Q port 1 side data to be observed.
The output impedance is 50Ω.
VCC
I
+5.0V
GND
I
0V
VEE
I
–5.0V
CON7
P2 side DATA
O
TTL
The CXA3086Q port 2 side data output is latched at
the frequency divided clock and then output.
CON8
P1 side DATA
O
TTL
The CXA3086Q port 1 side data output is latched at
the frequency divided clock and then output.
CON6
0.8A
The inside of the board is divided into analog and
digital systems.
–0.6A
Board Adjustments and Settings
1. VRB.R1:
CXA3086Q VRB voltage adjusting volume.
2.
3.
VRT.R2:
OFFSET.R3:
4.
5.
6.
FULL SCALE.R4:
FULL SCALE.R5:
S1:
CXA3086Q VRT voltage adjusting volume.
Adjusting volume for matching the AMP.IN input and DIR.IN input signal ranges to the
CXA3086Q input range.
Full-scale adjusting volume for the port 2 D/A output. (–1V: Typ.)
Full-scale adjusting volume for the port 1 D/A output. (–1V: Typ.)
Switching junction for the dual analog input pins.
Set as follows according to the input pins used.
Junction
A
B
AMP.IN
OPEN
SHORT
DIR.IN
0.1µF
10kΩ
Symbol
7.
S2:
8.
9.
10.
11.
SW1 SELECT:
SW2 A/D INV:
SW3 PS:
SW4 D/A INV:
Setting junction for the clock frequency division ratio. The operating speed after
latching is determined by the frequency division ratio set here.
When set to CLK OUT, it operates according to the CXA3086Q clock output.
CXA3086Q output mode selector switch.
CXA3086Q output polarity inversion switch.
CXA3086Q PS switch.
D/A converter output polarity inversion switch.
– 23 –
CXA3086Q
Notes on Board Operation
1.
The factory settings for the CXA3086Q Evaluation Board are as follows.
VRB.R1 = 1.5V
VRT.R2 = 3.0V
OFFSET.R3 = 2.25V
FULL SCALE.R4 = –1V
FULL SCALE.R5 = –1V
S1
S2
A : OPEN, B : SHORT
8 : SHORT (1/8 frequency division)
When using the board in this condition, the input signals should be input at the amplitudes shown below.
(The frequency is set as desired.)
Analog input signal: CON1 (AMP.IN)
0V center, 800mVp-p or less
Clock input signal: CON3 (CLK.IN)
0V center, 1.0Vp-p
2.
When the analog signal is input from the CON1 (AMP.IN) pin, IC2:CLC404 limits the input dynamic range
of the A/D converter's analog input signal.
3.
When the analog input signal is a sine wave or other repeating waveform, the signal can be input from the
CON2 (DIR.IN) pin with AC coupling. In these cases, the input dynamic range is not limited, but the VRT
level may be limited by IC3: NJM3403A.
4.
In the evaluation board of the CXA3086Q, CLC404 (Comlinear) is employed for IC2 to drive the analog
input signal. Though, CLC505 (Comlinear) can also be used instead of CLC404, there should be a little
change in the peripheral circuit in this case.
– 24 –
CXA3086Q
CXA3086Q Evaluation Board Timing Chart
N
N+3
N+1
CON2
DIR IN
2Vp-p
0V
N+2
CON3
CLK IN
CXA3086Q
CLK
1Vp-p
0V
(PECL)
CXA3086Q
P1 side DATA
N–4
N–3
N–2
N–1
(TTL)
Approximately 6.0ns
CON8
P1 side DATA
CLK
CON8
P1 side DATA
DATA
(TTL)
Approximately 9.0ns
N–6
N–4
N–2
(TTL)
N–6
CON5
P1 side OUT
N–4
N–2
(Analog regeneration waveform)
0 to –1V
Operating Conditions
CXA3086Q operating mode : Straight mode
Analog input
: DIR IN pin input
S2 setting
: 1/2 frequency divided clock
– 25 –
CXA3086Q
Circuit Diagram
CON6
VEE
L1
GND
L2
L3
VCC
L4
L5
L6
DGND
C1
33µF
C2
33µF
C3
33µF
DAINV
C4
33µF
SW4
D/A INV
PS
AVEE
DVEE
AGND
DGND
AVCC
SW3
PS
DVCC
ADINV
SW2
A/D INV
DVCC
SELECT
SW1
SELECT
C24
0.1µF
DVCC
AGND
C5
1µF
AVEE
C14
0.1µF
AGND
C6
1µF
DGND
P2D5
AVEE
P2D4
P2D3
C15
0.1µF
P2D2
P2D1
AGND
P2D0
AGND
4
R18
51
CON2
DIR IN
C19
0.1µF
3
AVCC
DVCC2
P2D5
P2D4
P2D3
P2D2
P2D1
13 DVEE3
DVCC2 48
14 AGND
DVCC1 47
17 AVCC
C20
0.1µF
22 VRTS
C16
0.1µF
C8
1µF
DGND1 39
23 AGND
AGND
DVCC
DVCC2 37
DGND
C17
0.1µF
DGND2
24 DGND3
C27
0.1µF
AGND
C27
0.1µF
DGND
AVCC
AGND
DVCC
25 26 27 28 29 30 31 32 33 34 35 36
DGND
AGND
DGND
DVCC1 38
P1D5
IC3C
NJM3403A
10
8
9
C7
1µF
C21
0.1µF
P1D4
AGND
N.C. 40 C26
0.1µF
21 VRT
C10
1µF
IC2
7 CLC404
DGND2
AGND
2
3
R14
130
ADINV
SELECT
SELECT 41
DVCC2
R13
82
CLKOUT
INV 42
20 AVCC
CLK/T
CON1
AMP IN
AVCC
PS
PS 44
CLKOUT 43
IC1
CXA3086Q
DVCC
DGND
C25
N.C. 45 0.1µF
19 VIN
S1
DGND
C28
0.1µF
DGND1 46
18 N.C.
B
R17
43
1
15 VRBS
AVCC
R16
4 270
6
2
P2D0
4
DGND2
5
16 VRB
A
AGND
C18
0.1µF
6
P1D3
R15
270
C9
1µF
7
P1D2
R6
51
AGND
8
P1D1
IC3A
NJM3403A
AGND
RESET/E
1
9
P1D0
R10
22k
11
2
3
R11
200k
RESETN/T
R3
10k
IC3B
NJM3403A
6
7
5
CLK/E
R8
510
R2
1k
DGND
R12
390k
CLKN/E
D1
TL431CP
R9
7.5k
RESETN/E
12 11 10
R7
510
R1
2k
DGND2
DGND
AVCC
P1D5
P1D4
DVCC
P1D3
P1D2
CON3
CLK IN
DGND
IC4B
10H116 (PECL)
7
10
9
6
C13
0.1µF
R19
51
DGND
R20
1k
R21
390
R22
1k
R23
82
IC4A
10H116 (PECL)
3
5
4
2
IC4C
10H116 (PECL)
15
13
12
14
P1D1
DVCC
P1D0
DGND
C23
0.1µF
R24
130
11
IC4D
10H116 (PECL)
13 CLK
Cout 4
DGND
9 S1
7 S2
R25 130
R28 82
R26 130
R29 82
R27 130
R30 82
DGND
DVCC
IC5
10H136 (PECL)
12 D0
Q3 3
11 D1
Q2 2
6 D2
Q1 15
5 D3
Q0 14
1/16
1/8
1/4
1/2
CLK
CLKN
– 26 –
CXA3086Q
DGND DVcc
1
2
C42
0.1µF
IC15
74ALS541
P2D5
3
17
P2D4
4
16
P2D3
5
15
P2D2
6
14
P2D1
7
13
P2D0
8
12
CON7
P2 side DATA
IC14
74ALS541
9
11
25
DGND
26
DGND
C47
0.1µF
DVCC
R47
620
Q5 14
DGND
11 CLK
DVEE
Q4 12
1 MSB
AGND 28
9
2 D2
VREF 27
NQ3 10
3 D3
AVEE 26
Q0 24
4 D4
NC 25
NC 24
NQ4 11
2 1D
1Q 19
3 2D
P2D5
P2D3
P2D2
P2D1
P2D0
Q3
2Q 18
IC6
74AS574
4 3D
P2D4
3Q 17
5 4D
4Q 16
6 5D
5Q 15
7 6D
6Q 14
8 7D
7Q 13
9 8D
8Q 12
P2D5
IC9
100324
15 5D
P2D4
NQ0
1
5 D5
17 3D
Q1
2
6 D6
21 0D
NQ1
3
7 D7
22 1D
Q2
5
8 D8
23 2D
NQ2
4
9 D9
16 4D
P2D3
P2D2
P2D1
P2D0
AGND
NQ5 13
19 E
1 OC
IC12
CX20201-1
R48
620
C44
0.1µF
R37
82
C45
0.1µF
NQ5 13
19 E
Q4 12
DGND
1 OC
P1D4
Q3
3 2D
P1D3
P1D1
P1D0
P1D5
P1D3
3Q 17
P1D2
11 NC
AGND 18
DGND 17
13 CLKN
Q0 24
DVEE
AGND
1 MSB
AGND 28
VREF 27
AVEE 26
16 4D
NQ0
1
3 D3
Q1
2
4 D4
NC 25
21 0D
NQ1
3
5 D5
NC 24
22 1D
Q2
5
6 D6
23 2D
NQ2
4
7 D7
5Q 15
7 6D
6Q 14
8 7D
7Q 13
8 D8
9 8D
8Q 12
9 D9
R50
620
C46
0.1µF
DGND
19 OE
C54
0.1µF
R44
1k
R5
2k
C55
0.1µF
NC 23
IC13
CX20201-1
D3
TL431CP
C12
1µF AVEE
NC 21
AGND CON5
P1 side OUT
NC 19
11 NC
AGND 18
12 NC
DGND 17
13 CLKN
AGND
DGND
C56
0.1µF
INV 16
14 CLK
DVEE
DVEE 15
17 VBB
R51
620
6 B
CLKOUT
DGND
24 D0
Q0
2
1 D0N
1/16
23 D1
21 D2
20 D2N
1/4
16 D3
IC8
100390
14 D4
CLK
12 D5
11 D5N
R31 82
R34 130
R32 82
R35 130
R33 82
R36 130
DGND
R46
620
3
DGND
Y3 12
10 A3
1/4
R41
620
Y4 14
Y4 13
11 A4
1/2
C50
0.1µF
DVEE
Y3 15
Q3 8
DVEE
Q4 9
13 D4N
CLKN
DVCC
Y2
Q2 4
15 D3N
1/2
Y2 1
IC11
10H124
7 A2
1/8
2
Y1 4
Q1 3
22 D1N
1/8
Y1
5 A1
1/16
1/1
DVCC
Q5 10
1
2
S2
C43
0.1µF
IC14
74ALS541
P1D5
3
17
P1D4
4
16
P1D3
5
15
P1D2
6
14
P1D1
7
13
P1D0
8
12
CON8
P1 side DATA
25
26
DGND
– 27 –
R45
270
NC 22
OUT 20
10 LSB
DVEE
DGND
DGND
C53
0.1µF
DVEE 15
17 3D
DAINV
CLKOUT
C31
0.1µF
AGND
INV 16
2 D2
6 5D
DGND
AGND CON4
P2 side OUT
R39
130
4Q 16
P1D0
NC 21
12 NC
5 4D
P1D1
C11
1µF AVEE
R40
130 DVEE
DVEE
9
NQ3 10
IC10
100324
15 5D
P1D4
2Q 18
IC7
74AS574
4 3D
P1D2
R38
82
R49
620
NQ4 11
11 CLK
1Q 19
C52
NC 23 0.1µF
NC 22
D2
TL431CP
NC 19
14 CLK
Q5 14
2 1D
R4
2k
R43
270
DGND
DVCC
P1D5
R42
1k
OUT 20
10 LSB
DVEE
C51
0.1µF
CXA3086Q
Component List
No.
Product name
IC1
CXA3086Q
IC2
CLC404AJE
IC3
NJM3403AM
IC4
MC10H116L
IC5
MC10H136L
IC6, 7
74AS574N
IC8
100390
IC9, 10
100324PC
IC11
MC10H124L
IC12, 13
CXA20201A-1
IC14, 15
74ALS541N
D1 to 3
TL431CP
SW1 to 4
ATE1D-2F3-10
S1, 2
JX-1
CON1 to 5
01K0315
CON6
TJ-563
CON7, 8
(FAP-2601-1202)
L1 to 6
ZBF503D-00
C1 to 4
Tantal capacitor
C5 to 12
Tantal capacitor
C13
Ceramic capacitor
All parts other than those listed above
Chip capacitor
Function
6-bit A/D converter
OP-AMP
OP-AMP
ECL Buffer
ECL Countor
TTL Latch
PECL→TTL conversion
TTL→ECL conversion
TTL→ECL conversion
10-bit D/A converter
TTL Buffer
Shunt regulator
Toggle switch
Short pin
BNC connector
Power supply connector
Flat cable connector
Ferrite-bead filter
33µF
1µF
0.1µF
No.
R2
R1, 4, 5
R3
R47 to 51
Product name
RJ-5W-1K
RJ-5W-2K
RJ-5W-10K
RGLD4X621J
Function
1kΩ volume resistor
2kΩ volume resistor
10kΩ volume resistor
620Ω network resistor
R6, 18, 19
R7.8
R9
R10
R11
R12
R13, 23, 28 to 33, 37, 38
R14, 24 to 27, 34 to 36, 39, 40
R15, 16, 43, 45
R17
R20, 22, 42, 44
R21
R41, 46
FRD-25SR (0.25W)
FRD-25SR (0.25W)
FRD-25SR (0.25W)
FRD-25SR (0.25W)
FRD-25SR (0.25W)
FRD-25SR (0.25W)
FRD-25SR (0.25W)
FRD-25SR (0.25W)
FRD-25SR (0.25W)
FRD-25SR (0.25W)
FRD-25SR (0.25W)
FRD-25SR (0.25W)
FRD-25SR (0.25W)
51Ω
510Ω
7.5kΩ
22kΩ
200kΩ
390kΩ
82Ω
130Ω
270Ω
43Ω
1kΩ
390Ω
620Ω
0.1µF
∗ CON7 and 8 are not mounted when boards are shipped. (Manufacturer: YAMAICHI Electronics Co., Ltd.)
Component side silk diagram
– 28 –
CXA3086Q
Component side pattern diagram
Solder side pattern diagram
– 29 –
CXA3086Q
Package Outline
Unit: mm
48PIN QFP (PLASTIC)
15.3 ± 0.4
+ 0.1
0.15 – 0.05
+ 0.4
12.0 – 0.1
36
25
0.15
24
48
13
13.5
37
12
0.8
+ 0.15
0.3 – 0.1
± 0.12 M
0.9 ± 0.2
1
+ 0.2
0.1 – 0.1
+ 0.35
2.2 – 0.15
PACKAGE STRUCTURE
SONY CODE
QFP-48P-L04
EIAJ CODE
∗QFP048-P-1212-B
JEDEC CODE
PACKAGE MATERIAL
EPOXY RESIN
LEAD TREATMENT
SOLDER / PALLADIUM
PLATING
LEAD MATERIAL
COPPER / 42 ALLOY
PACKAGE WEIGHT
0.7g
NOTE : PALLADIUM PLATING
This product uses S-PdPPF (Sony Spec.-Palladium Pre-Plated Lead Frame).
– 30 –