Cypress CY7C9235-270JC Smpte-259m/dvb-asi scrambler/controller Datasheet

PRELIMINARY
CY7C9235
SMPTE-259M/DVB-ASI
Scrambler/Controller
a CY7B9234 HOTLink transmitter, which then converts the
bit-parallel characters into a SMPTE-259M compatible
high-speed serial data stream.
1CY7C9235
Features
This device performs both TRS (sync) detection and filtering,
data scrambling with the SMPTE-259M X9 + X4 + 1 algorithm,
and NRZ-to-NRZI encoding. These functions operate at any
character rate from 16- to 40 MHz. For those systems operating with non-SMPTE-259M compliant video streams (or for diagnostic purposes), the scrambler and NRZI encoding functions can be disabled.
• Fully compatible with SMPTE-259M
— SMPTE-125M compliant for 4:2:2 component video
•
•
•
•
•
•
— SMPTE-244M compliant for 4fsc composite video
Fully compatible with DVB-ASI
Operates from a single +5V or –5V supply
44-pin PLCC package
Encodes both 8- and 10-bit parallel digital streams for
any rate from 16–40 M characters/sec (160–400
Mbits/sec serial)
Operates with CY7B9234 SMPTE HOTLink™ serializer/transmitter
X9 + X4 + 1 scrambler and NRZI encoder may be bypassed for raw data output
DVB-ASI Operation
The CY7C9235 also contains the necessary multiplexers, control inputs, and outputs, to sequence out a DVB-ASI compliant
video stream. DVB-ASI operation is enabled through activation of a single input signal. This allows a single serial output
port to support both SMPTE and DVB data streams under software or hardware control.
In DVB-ASI mode the CY7C9235 operates with two enable
signals (ENA and ENN) to allow data to be presented from
either synchronous (clocked) or asynchronous FIFOs. When
data is not available, the CY7C9235 ensures that the proper
fill character (K28.5) is generated by the attached CY7B9234
serializer.
Functional Description
SMPTE-259M Operation
The CY7C9235 is a CMOS integrated circuit designed to encode SMPTE-125M and SMPTE-244M bit-parallel digital characters (or other data formats) using the SMPTE-259M encoding rules. Following encoding, the characters are output as
bit-parallel characters ready for serialization. The encoded
outputs of the CY7C9235 are designed to be directly mated to
The CY7C9235 operates from a single +5V or −5V supply. It
is available in a 44-pin PLCC space saving package.
Logic Block Diagram
PD9(SVS)
TRS_DET
PD2
PD1
PD0(SC/D)
TRS_FILT
INPUT REGISTER
PD3
10
10
10
Q7
10
SC/D_EN
OUTPUT REGISTER
10
PD4
Q8
MODE MULTIPLEXOR
PD5
Q9(SVS)
NRZI ENCODER
PD6
SMPTE SCRAMBLER
PD7
TRS FILTER / DETECTOR
PD8
Q6
Q5
Q4
Q3
Q2
Q1
Q0(SC/D)
SVS_EN
BYPASS
DVB_EN
ENA
ENA_OUT
ENN
CKW
OE
Cypress Semiconductor Corporation
Document #: 38-02012 Rev. *A
•
3901 North First Street
•
San Jose
•
CA 95134 • 408-943-2600
Revised December 27, 2002
PRELIMINARY
CY7C9235
HOTLink is a trademark of Cypress Semiconductor Corporation.
Q9(SVS)
Q8
Q7
Q6
Q5
VSS
VCC
Q4
Q3
Q2
Q1
Pin Configuration
6
5
4
3
2
1
44
43
42
41
40
39
Q0(SC/D)
38
ENA_OUT
9
37
ENN
OE
10
36
ENA
VSS
11
35
CKW
VSS
12
34
VSS
VSS
13
33
VSS
BYPASS
14
32
VSS
DVB_EN
15
31
SC/D_EN
NC
16
30
NC
PD9(SVS)
17
29
NC
23
24
25
26
27
28
PD0(SC/D)
22
PD1
21
PD2
20
PD3
19
PD4
18
VSS
PLCC
Top View
VCC
SVS_EN
NC
PD5
8
PD6
TRS_FILT
PD7
7
PD8
TRS_DET
Maximum Ratings[1]
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ..................................... −40°C to +125°C
DC Input Current .............................................................± 20 mA
Latch-Up Current............................................................>200 mA
Supply Voltage to Ground Potential .................−0.5V to +7.0V
DC Voltage Applied to Outputs
in High-Z State.....................................................−0.5V to +7.0V
Operating Range
Output Current into Outputs.........................................16 mA
Range
DC Input Voltage .................................................−0.5V to +7.0V
Commercial
Static Discharge Voltage.............................................. > 2001 V
(per MIL-STD-883, Method 3015)
Industrial
Document #: 38-02012 Rev. *A
Ambient
Temperature
VCC
0°C to +70°C
5V ± 5%
−40°C to +85°C
5V ± 10%
Page 2 of 8
PRELIMINARY
CY7C9235
Pin Descriptions
CY7C9235 SMPTE-259M Encoder
Name
I/O
Description
ENA
Input
Enable Parallel Data. If ENA is LOW at the rising edge of CKW, the data present on the PD0−9
inputs is latched, and routed to the Q0–9 outputs. This pin is only interpreted when DVB_EN is
active (LOW). If the CY7C9235 is only used in SMPTE-259M mode this signal should be tied
to VSS.
ENN
Input
Enable Next Parallel Data. If ENN is LOW at the rising edge of CKW, the data present on the
PD0–9 inputs at the next rising edge of TXCLK is latched, and routed to the Q0–9 outputs. This
pin is only interpreted when DVB_EN is active (LOW). If the CY7C9235 is only used in
SMPTE-259M mode this signal should be tied to VSS.
BYPASS
Input
Bypass SMPTE Encoding. BYPASS is ignored if DVB_EN is active (LOW). If BYPASS is HIGH
at the rising edge of CKW (and DVB_EN is HIGH), the data latched into the input register is
routed around both the SMPTE scrambler and the NRZI encoder and presented to the output
register. If BYPASS is LOW at the rising edge of the CKW clock (and DVB_EN is HIGH), the
data present in the input register is routed through the SMPTE scrambler and NRZI encoder.
TRS_DET
Output
TRS Character Detected. This output indicates when a character used in the TRS sequence is
detected in the input register. If the data contains any of the reserved characters of 000–003 or
3FC–3FF in 10-bit hex, the output will be LOW for one clock period. If the character in the input
register is any other pattern (or DVB_EN is LOW) this output will remain HIGH.
TRS_FILT
Input
TRS Character Filter. This signal controls an internal filter that converts the low-order two bits
of all TRS characters to same state as the upper eight bits. This allows a proper 30-bit TRS ID
to be generated when the CY7C9235 is operated with 8-bit or non-standard video streams.
When this signal is LOW, all characters from 000–003 are converted to 000, and all characters
from 3FC–3FF are converted to 3FF. When TRS_FILT is disabled (HIGH), all characters are
passed to the scrambler without modification. This signal has no effect when DVB_EN is active
(LOW).
SVS_EN
Input
Send Violation Symbol Enable. This input is only valid when DVB_EN is active (LOW). If
SVS_EN is HIGH and a HIGH input is present on PD9, Q9 will also be high on a following clock
cycle, forcing the CY7B9234 serializer to generate an invalid 8B/10B character. If SVS_EN is
LOW, the level present on PD9 is ignored and Q9 is forced to a LOW state.
SC/D_EN
Input
Special Character/Data Select Enable. This input is only valid when DVB_EN is active (LOW).
If SC/D_EN is HIGH and a HIGH input is present on PD0, Q0 will also be high on a following
clock cycle, forcing the CY7B9234 serializer to generate an 8B/10B control character as selected by the character present on the PD8–1 inputs. If SC/D_EN is LOW, the level present on PD0
is ignored and Q0 is forced to a LOW (data only) state.
PD9(SVS)
Input
Parallel Data 9 or Send Violation Symbol. This is the MSB of the input data field. It is latched
in the input register at the rising edge of CKW. When DVB_EN is active (LOW) and SVS_EN
is HIGH, this latched input is routed to the output register bit Q9 (SVS). When DVB_EN is active
(LOW) and SVS_EN is LOW, output register bit Q9 (SVS) is forced to a LOW (zero) level. When
DVB_EN is inactive (HIGH), this latched input is routed to the scrambler and NRZI encoder.
PD8–1
Input
Parallel Data 8 through 1. The signals present at the PD8–1 inputs are latched in the input
register at the rising edge of CKW. When DVB_EN is HIGH, these signals are the middle eight
bits of the SMPTE 10-bit data field, and are then routed to the scrambler and NRZI encoder.
When DVB_EN is active (LOW), these signals are full DVB-ASI data bus, and are then routed
to the Q8−1 outputs.
PD0(SC/D)
Input
Parallel Data 0 or Special Code/Data Select. This is the LSB of the input data field. It is latched
in the input register at the rising edge of CKW. When DVB_EN is active (LOW) and SC/D_EN
is HIGH, this input is routed to output register bit Q0 (SVS). When DVB_EN is active (LOW) and
SC/D_EN is LOW, output register bit Q0 (SC/D) is forced to a LOW (zero) level. When DVB_EN
is inactive (HIGH), this input data bit is routed through the input register and the scrambler and
NRZI encoder.
Q9(SVS)
Output
Output Bit 9. This is the MSB of the output register. It should be connected directly to the
CY7B9234 serializer input signal SVS(Dj).
Q8–1
Output
Output Bits 8 through 1. These signals should be connected directly to the CY7B9234 serializer
input signals D7−0 respectively.
Document #: 38-02012 Rev. *A
Page 3 of 8
PRELIMINARY
CY7C9235
Pin Descriptions (continued)
CY7C9235 SMPTE-259M Encoder
Name
I/O
Description
Q0(SC/D)
Output
Output Bit 0. This is the LSB of the output register. It should be connected directly to the
CY7B9234 serializer input signal SC/D(Da).
DVB_EN
Input
DVB Mode Enable. This signal is sampled by the rising edge of the CKW clock. If DVB_EN is
active (LOW), the data present on the PD0−9, ENA, and ENN inputs are latched and routed to
the Q0−9 and ENA_OUT outputs.
CKW
Input
Clock Write. This clock controls all synchronous operations of the CY7C9235. It operates at the
character rate which is equivalent to one tenth the serialized bit-rate. This clock also connects
directly to the CKW input of the CY7B9234 serializer.
ENA_OUT
Output
Enable Parallel Data Out. This output attached directly to the CY7B9234 ENA input, and identifies when valid data is available at the CY7C9235 outputs. If used only for SMPTE-259M data
streams, this output may be left open, with the ENA input to the CY7B9234 directly connected
to VSS.
OE
Input
Output Enable. When this signal is HIGH all outputs are driven to their normal logic levels. When
LOW, all outputs are placed in a High-Z state.
VCC
Power.
VSS
Ground.
CY7C9235 Description
Input Register
NRZI Encoder
The input register is clocked by the rising edge of CKW. This
register captures the data present at the PD0−9 inputs on every
clock cycle. In addition to the data inputs, all control inputs
except OE are also captured at each rising edge of CKW. This
includes BYPASS, DVB_EN, SVS_EN, SC/D_EN, TRS_DET,
TRS_FILT, ENN, and ENA.
The scrambled data is also fed through an NRZ-to-NRZI encoder. This also increases the transition density of the serial
data stream, decreases the DC-content of the transmitted serial bit stream, and makes the serial stream insensitive to polarity inversions.
TRS Filter
The CY7C9235 is designed to operate in both SMPTE-259M
and DVB-ASI environments. When operated in SMPTE-only
environments, the DVB control inputs may be tied to either
VCC or VSS as needed to place them in a known state. When
not used for DVB operation, the ENA, ENN, SVS_EN, and
SC/D_EN inputs many be tied to either VCC or VSS. DVB_EN
must be tied or driven HIGH.
The TRS Filter is used to convert all 8-bit TRS characters
(000–003 and 3FC–3FF in 10-bit hex) to their full 10-bit value.
If TRS_FILT is active (LOW) and any of these values are detected in the input register, the lower two bits are forced to
either zeros or ones respectively. This allows the encoder to
be used with both 8- and 10-bit SMPTE character streams.
If TRS_FILT is HIGH, the filter function is disabled and all characters are passed from the input register to the SMPTE scrambler unmodified.
TRS Detector
When operated in SMPTE mode (DVB_EN is HIGH), the TRS
detector looks for the most significant eight bits of the input
register to be either all ones or all zeros. If either of these
values are detected, the TRS_DET output will go LOW following the rising edge of CKW, and remain LOW until a character
is detected in the input register that is not all zeros or ones, or
DVB_EN is latched LOW.
SMPTE Scrambler
The SMPTE scrambler implements a parallel encoded version
of a linear-feedback shift register. It encodes the data present
in the input register using the X9 + X4 + 1 polynomial to increase the transition density of the serial data stream and to
decrease the DC-content of the transmitted serial bit stream.
Document #: 38-02012 Rev. *A
DVB-ASI Operation
DVB-ASI operation is enabled by asserting DVB_EN LOW.
This signal is latched by the rising edge of the CKW clock.
When the CY7C9235 is placed in DVB mode, the SMPTE and
NRZI encoders are bypassed, and the data latched into the
input register is routed directly to the output register.
Error Propagation
For those DVB-ASI implementations that do not require propagation of detected errors, the Q9 output may be forced to a
zero by setting SVS_EN LOW. When SVS_EN is HIGH (and
the encoder is in DVB mode) the PD9 data latched into the
input register is routed to the output register and to the
CY7B9234 SVS input.
Command Code Generation
The DVB-ASI interface does not normally transmit any command characters other than the K28.5 code that is used both
for synchronization and as a fill character when data is not
being transmitted. These K28.5 characters may be generated
by two methods; by controlling when the CY7C9235 is enabled
Page 4 of 8
PRELIMINARY
CY7C9235
using the ENA and ENN inputs, or by placing a C5.0 character
on the PD9–0 inputs when one of the two enables is active.
data bit is not routed to the output register by forcing the Q0
output to always be LOW.
If the generation of K28.5 fill characters is to be controlled
using the ENA or ENN inputs, the SC/D_EN input should be
driven LOW or connected to VSS. This will insure that the PD0
If the generation of a K28.5 characters is controlled by transmission of a C5.0 character, the SC/D_EN input must be HIGH
to allow the PD0 input to be propagated to the Q0 output.
Electrical Characteristics Over the Operating Range
Parameter
Description
Test Conditions
VOH
Output HIGH Voltage
VCC=Min., IOH = −3.2 mA
VOL
Output LOW Voltage
VCC=Min., IOL = 16.0 mA
VIH
Input HIGH Voltage
Guaranteed Input Logical HIGH
Voltage for all Inputs[2]
VIL
Input LOW Voltage
IIX
Input Load Current
IOZ
Output Leakage Current
[3,4]
Min.
Max.
Unit
2.4
V
0.5
V
2.0
7.0
V
Guaranteed Input Logical HIGH
Voltage for all Inputs[2]
–0.5
0.8
V
VI = VCC or VSS
−10
+10
µA
VO = VCC or VSS
−50
+50
µA
−10
−80
mA
IOS
Output Short Circuit Current
VCC = Max., VOUT = 0.5V
ICC
Power Supply Current
VIN, VI/O = VCC or VSS
mA
Capacitance[4]
Max.
Unit
CIN
Parameter
Input Capacitance
Description
VIN = 5.0V at f = 1 MHz
Test Conditions
10
pF
COUT
Output Capacitance
VOUT = 5.0V at f = 1 MHz
12
pF
Notes:
1. Single Power Supply: The voltage on any input or I/O pin cannot exceed the power pin during power-up.
2. These are absolute values with respect to device ground. All overshoots due to system or tester noise are included.
3. Not more than one output should be tested at a time. Duration of the short circuit should not exceed 1 second. VOUT = 0.5V has been chosen to avoid test
problems caused by tester ground degradation.
4. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-02012 Rev. *A
Page 5 of 8
PRELIMINARY
CY7C9235
AC Test Loads and Waveforms
TTL OUTPUTS
ALL INPUT PULSES
238Ω
238Ω
3.0V
5V
5V
90%
OUTPUT
OUTPUT
170Ω
35 pF
INCLUDING
JIG AND
SCOPE
170
5 pF
GND
10%
< 2 ns
INCLUDING
JIG AND
(b)
SCOPE
Equivalent to: THÉVENIN
99 Ω
OUTPUT
(a)
90%
10%
< 2 ns
7C9335–9
EQUIVALENT
2.08V
Switching Characteristics Over the Operating Range[5]
Parameter
Description
CY7C9235-27
CY7C9235-40
Min.
Min.
Max.
Max.
Unit
tSD
Data Set-Up Time
10
8
ns
tHD
Data Hold Time
0
0
ns
tCPWH
CKW Pulse Width HIGH
6.5
6.5
ns
tCPWL
CPW Pulse Width LOW
6.5
6.5
ns
tCKW
Write Clock Period
30
tA
Access Time
tH
Data Output Hold Time From CKW Rise
tEA
Input to Output Enable
62.5
25
10
4
[6]
Input to Output Disable
tER
Notes:
5. All AC parameters are with all outputs switching.
6. Test load (b) used for this parameter. Test load (a) used for all other AC parameters.
62.5
ns
8
ns
3
ns
23
20
ns
23
20
ns
Switching Waveform
tCKW
tSD
PD0−9, ENA, ENN,
BYPASS, TRS_FILT,
SVS_EN, SC/D_EN,
DVB_EN
tHD
CKW
tCPWL
tCPWH
tA
Q0–9, TRS_DET,
ENA_OUT
tER
tEA
tH
OE
Document #: 38-02012 Rev. *A
Page 6 of 8
PRELIMINARY
CY7C9235
v
Ordering Information
Ordering Code
Package
Name
Package Type
Operating
Range
CY7C9235-270JC
J67
44-pin Plastic Leaded Chip Carrier
Commercial
CY7C9235-400JC
J67
44-pin Plastic Leaded Chip Carrier
Commercial
Package Diagram
44-Lead Plastic Leaded Chip Carrier J67
51-85003-A
Document #: 38-02012 Rev. *A
Page 7 of 8
© Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
PRELIMINARY
CY7C9235
Document Title: CY7C9235 SMPTE-259M/DVB-ASI Scrambler/Controller
Document Number: 38-02012
REV.
ECN NO.
Issue Date
Orig. of
Change
**
105850
03/22/01
SZV
Change from Spec number: 38-00571 to 38-02012
*A
122203
12/27/02
RBI
Add power up requirements to maximum ratings information.
Document #: 38-02012 Rev. *A
Description of Change
Page 8 of 8
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