Lattice ISPGDX2-128/E High performance interfacing and switching Datasheet

ispGDX2™ Family
Includes
High,
Performance
t
os
-C
w
Lo
“E-Series”
September 2005
Features
Data Sheet
■ Two Options Available
• High-performance sysHSI (standard part number)
• Low-cost, no sysHSI (“E-Series”)
■ High Performance Bus Switching
• High bandwidth
– Up to 12.8 Gbps (SERDES)
– Up to 38 Gbps (without SERDES)
• Up to 16 (15x10) FIFOs for data buffering
• High speed performance
– fMAX = 360MHz
– tPD = 3.0ns
– tCO = 2.9ns
– tS = 2.0ns
• Built-in programmable control logic capability
• I/O intensive: 64 to 256 I/Os
• Expanded MUX capability up to 188:1 MUX
■ sysHSI Blocks Provide up to 16 High-speed
Channels
•
•
•
•
•
Serializer/de-serializer (SERDES) included
Clock Data Recovery (CDR) built in
800 Mbps per channel
LVDS differential support
10B/12B support
– Encoding / decoding
– Bit alignment
– Symbol alignment
• 8B/10B support
– Bit alignment
– Symbol alignment
• Source Synchronous support
■ sysCLOCK™ PLL
•
•
•
•
High Performance Interfacing and Switching
Frequency synthesis and skew management
Clock multiply and divide capability
Clock shifting up to +/-2.35ns in 335ps steps
Up to four PLLs
■ Flexible Programming and Testing
• IEEE 1532 compliant In-System Programmability (ISP™)
• Boundary scan test through IEEE 1149.1
interface
• 3.3V, 2.5V or 1.8V power supplies
• 5V tolerant I/O for LVCMOS 3.3 and LVTTL
interfaces
■ sysIO™ Interfacing
• LVCMOS 1.8, 2.5, 3.3 and LVTTL support for
standard board interfaces
• SSTL 2/3 Class I and II support
• HSTL Class I, III and IV support
• GTL+, PCI-X for bus interfaces
• LVPECL, LVDS and Bus LVDS differential support
• Hot socketing
• Programmable drive strength
Table 1. ispGDX2 Family Selection Guide
ispGDX2-64/E
ispGDX2-128/E
ispGDX2-256/E
I/Os
64
128
256
GDX Blocks
4
8
16
tPD
3.0ns
3.2ns
3.5ns
tS
2.0ns
2.0ns
2.0ns
2.9ns
3.1ns
3.2ns
360MHz
330MHz
300MHz
SERDES1, 2
3.2Gbps
6.4Gbps
12.8Gbps
Without SERDES3
11Gbps
21Gbps
38Gbps
tCO
fMAX (Toggle)
Max Bandwidth
2
sysHSI Channels
4
8
16
LVDS/Bus LVDS (Pairs)
32
64
128
PLLs
Package
2
2
4
100-ball fpBGA
208-ball fpBGA
484-ball fpBGA
1. Max number of SERDES channels per device * 800Mbps
2. “E-Series” does not support sysHSI.
3. fMAX (Toggle) * maximum I/Os divided by 2.
© 2005 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com
1
gdx2fam_13
Lattice Semiconductor
ispGDX2 Family Data Sheet
Figure 1. ispGDX2 Block Diagram (256-I/O Device)
sysIO Bank
sysCLOCK
PLL
sysHSI
Block
SERDES
SERDES
SERDES
FIFO
FIFO
FIFO
FIFO
GDX Block
GDX Block
GDX Block
GDX Block
sysHSI
Block
SERDES
SERDES
SERDES
sysIO Bank
SERDES
sysIO Bank
sysHSI
Block
sysIO Bank
FIFO
sysIO Bank
FIFO
SERDES sysHSI
Block
FIFO
SERDES
FIFO
SERDES
GDX Block
SERDES
GDX Block
FIFO
sysHSI
Block
GDX Block
FIFO
GDX Block
GDX Block
GDX Block
FIFO
GDX Block
FIFO
SERDES
GDX Block
FIFO
GDX Block
SERDES
Global Routing Pool
(GRP)
sysCLOCK
PLL
FIFO
GDX Block
FIFO
GDX Block
FIFO
SERDES
GDX Block
SERDES
sysIO Bank
sysHSI
Block
SERDES
sysHSI
Block
sysHSI
Block
sysIO Bank
sysCLOCK
PLL
sysIO Bank
sysCLOCK
PLL
ISP & Boundary Scan
Test Port
Introduction
The ispGDX2™ family is Lattice’s second generation in-system programmable generic digital crosspoint switch for
high speed bus switching and interface applications.
The ispGDX2 family is available in two options. The standard device supports sysHSI capability for ultra fast serial
communications while the lower-cost “E-series” supports the same high-performance FPGA fabric without the
sysHSI Block.
This family of switches combines a flexible switching architecture with advanced sysIO interfaces including high
performance sysHSI Blocks, and sysCLOCK PLLs to meet the needs of the today’s high-speed systems. Through
a muliplexer-intensive architecture, the ispGDX2 facilitates a variety of common switching functions.
The availability of on-chip control logic further enhances the power of these devices. A high-performance solution,
the family supports bandwidth up to 38Gbps.
Every device in the family has a number of PLLs to provide the system designer with the ability to generate multiple
clocks and manage clock skews in their systems.
2
Lattice Semiconductor
ispGDX2 Family Data Sheet
The sysIO interfaces provide system-level performance and integration. These I/Os support various modes of
LVCMOS/LVTTL and support popular high-speed standard interfaces such as GTL+, PCI-X, HSTL, SSTL, LVDS
and Bus-LVDS. The sysHSI Blocks further extend this capability by providing high speed serial data transfer capability.
Devices in the family can operate at 3.3V, 2.5V or 1.8V core voltages and can be programmed in-system via an
IEEE 1149.1 interface that is compliant with the IEEE 1532 standard. Voltages required for the I/O buffers are independent of the core voltage supply. This further enhances the flexibility of this family in system designs.
Typical applications for the ispGDX2 include multi-port multi-processor interfaces, wide data and address bus multiplexing, programmable control signal routing and programmable bus interfaces. Table 1 shows the members of
the ispGDX2 family and their key features.
Architecture
The ispGDX2 devices consist of GDX Blocks interconnected by a Global Routing Pool (GRP). Signals interface
with the external system via sysIO banks. In addition, each GDX Block is associated with a FIFO and a sysHSI
Block to facilitate the transfer of data on- and off-chip. Figure 1 shows the ispGDX2 block diagram. Each GDX
Block can be individually configured in one of four modes:
• Basic (No FIFO or SERDES)
• FIFO Only
• SERDES Only
• SERDES and FIFO
Each sysIO bank has its own I/O power supply and reference voltage. Designers can use any output standard
within a bank that is compatible with the power supply. Any input standard may be used, providing it is compatible
with the reference voltage. The banks are independent.
Global Routing Pool (GRP)
The ispGDX2 architecture is organized into GDX Blocks, which are connected via a Global Routing Pool. The innovative GRP is optimized for routability, flexibility and speed. All the signals enter via the GDX Block. The block supplies these either directly or in registered form to the GRP. The GRP routes the signals to different blocks, and
provides separate data and control routing. The data path is optimized to achieve faster speed and routing flexibility
for nibble oriented signals. The control routing is optimized to provide high-speed bit oriented routing of control signals.
There are some restrictions on the allocation of pins for optimal bus routing. These restrictions are considered by
the software in the allocation of pins.
GDX Block
The blocks are organized in a “block” (nibble) manner, with each GDX Block providing data flow and control logic
for 16 I/O buffers. The data flow is organized as four nibbles, each nibble containing four Multiplexer Register
Blocks (MRBs). Data for the MRBs is provided from 64 lines from the GRP. Figure 2 illustrates the groups of signals
going into and out of a GDX Block.
Control signals for the MRBs are provided from the Control Array. The Control Array receives the 32 signals from
the GRP and generates 16 control signals: eight MUX Select, four Clock/Clock Enable, two Set/Reset and two Output Enable. Each nibble is controlled via two MUX select signals. The remaining control signals go to all the MRBs.
Besides the control signals from the Control Array, the following global signals are available to the MRBs in each
GDX Block: four Clock/Clock Enable, one reset/preset, one power-on reset, two of four MUX select (two of two in
64 I/O), four Output Enable (two in 64 I/O) and Test Out Enable (TOE).
3
Lattice Semiconductor
ispGDX2 Family Data Sheet
MUX and Register Block (MRB)
Every MRB Block has a 4:1 MUX (I/O MUX) and a set of three registers which are connected to the I/O buffers,
FIFO and sysHSI Blocks. Multiple MRBs can be combined to form large multiplexers as described below. Figure 3
shows the structure of the MRB.
Each of the three registers in the MRB can be configured as edge-triggered D-type flip-flop or as a level sensitive
latch. One register operates on the input data, the other output data and the last register synchronizes the output
enable function. The input and output data signals can bypass each of their registers. The polarity of the data out
and output enable signals can be selected.
The Output and OE register share the same clock and clock enable signals. The Input register has a separate clock
and clock enable. The initialization signals of each register can be independently configured as Set or Reset. These
registers have programmable polarity control for Clock, Clock Enable and Set/Reset. The output enable register
input can be set either by one of the two output enables generated locally from the Control Array or from one of the
four (two in 64 I/O) Global OE enable pins. In addition to the local clock and clock enable signals, each MRB has
access to Global Clock, Clock Enable, Reset and TOE nets.
4
Lattice Semiconductor
ispGDX2 Family Data Sheet
Figure 2. GDX Block
GRP
GDX Block
32 bits
MUX
Control Select
sysIO Bank
Control Array
8
Nibble 0
8
OE
8
MUX and Register
Block (MRB)
0
2
4 bits
8
IN
OUT
OE
MUX and Register
Block (MRB)
1
2
4 bits
IN
OUT
8
MUX and Register
Block (MRB)
2
2
4 bits
OE
IN
OUT
8
OE
MUX and Register
Block (MRB)
3
2
4 bits
8
IN
OUT
2
Nibble 1
MRBs 4-7
OE
IN
OUT
2
Nibble 2
MRBs 8-11
OE
IN
OUT
2
Nibble 3
MRBs 12-15
OE
IN
OUT
16 bits
4
8
16 bits
4
8
16 bits
4
The output register of the MRB has a built-in bi-directional shift register capability. Each output register corresponding to MRB “n”, receives data output from its two adjacent MRBs, MRB (n-1) and MRB (n+1), to provide shift register capability. Like the output register, each input register of the MRB has built-in shift register capability. Each input
register can receive data from its two adjacent MRB input registers, to provide bi-directional shift register capability.
The chaining crosses GDX Block boundaries. The chain of input registers and the chain of output registers can be
combined as one shift register via the GRP.
5
Lattice Semiconductor
ispGDX2 Family Data Sheet
The four data inputs to the 4:1 MUX come from the GRP. The output of this MUX connects to the output register. A
fast feedback path from the MUX to the GRP allows wider MUXes to be built. Table 2 summarizes the various MUX
sizes and delay levels.
Table 2. MUX Size Versus Internal Delay
MUX Sizes
Levels of Internal GRP Delays
4:1
One Level
Up to 16:1
Two Levels
Up to 64:1
Three Levels
Up to 188:1 (with ispGDX2-256)
Four Levels
Figure 3. ispGDX2 Family MRB
4
2-4
OE
MUX
Select
Global
Signals
Global
Signals
CK/CE
MUX Select
Control Array Signals
GDX
Control Array
2
4
2
D/L
OE
Q
ClK
OE
Reg/Latch
CK
CE
CE
Set
Reset
OE
CK/CE
From GRP
Set/Reset
VCC
from
Out_Reg(n-1)
from
Out_Reg(n+1)
D/L
TOE
Flags*
(FIFO, SERDES
or PLL)
Q
to Out_Reg(n-1)
Out
Reg/Latch
ClK
to Out_Reg(n+1)
CE
Set
Reset
VCC
S/R
Global Resetb
To GRP
Delay
FIFO Out*
from IN_Reg(n-1)
from IN_Reg(n+1)
D/L
Q
to IN_Reg(n-1)
to IN_Reg(n+1)
Input
Reg/Latch
ClK
CK
CE
CE
Set
Reset
S/R
Global Resetb
*Selected MRBs see Logic Signal Connection Table for details
Control Array
The control array generates control signals for the 16 MRBs within a GDX Block. The true and complement forms
of 32 inputs from the GRP are available in the control array. The 20 NAND terms can use any or all of these inputs
to form the control array outputs. Two AND terms are combined with a NOR term to form Set/Reset and OE signals. Figure 4 illustrates the control array.
6
Lattice Semiconductor
ispGDX2 Family Data Sheet
Figure 4. ispGDX2 Family Control Array
32 Inputs from Control GRP
Each connection
is programmable.
MUX Select
to Nibble 0
MUX Select
to Nibble 1
MUX Select
to Nibble 2
MUX Select
to Nibble 3
To MRB Clock/
Clock Enable
On selected blocks,
this signal can reset
the M Divider of the
PLL.
To MRB
Set/Reset
To MRB
Output Enable
sysIO Banks
The inputs and outputs of ispGDX2 devices are divided into eight sysIO banks, where each bank is capable of supporting different I/O standards. The number of I/Os per bank is 32, 16 and 8 for the 256-, 128- and 64-I/O devices
respectively. Each sysIO bank has its own I/O supply voltage (VCCO) and reference voltage (VREF), allowing each
bank complete independence from the other banks. Each I/O within a bank can be individually configured to any
standard consistent with the VCCO and VREF settings. Figure 5 shows the I/O banks for the ispGDX2-256 device.
The I/O of the ispGDX2 devices contain a programmable strength and slew rate tri-state output buffer, a programmable input buffer, a programmable pull-up resistor, a programmable pull-down resistor and a programmable buskeeper latch. These programmable capabilities allow the support of a wide range of I/O standards.
7
Lattice Semiconductor
ispGDX2 Family Data Sheet
Figure 5. ispGDX2-256 sysIO Banks
VCCO3
VREF3
GND
VCCO4
VREF4
GND
sysIO Bank 4
sysIO Bank 3
VCCO5
VREF5
VCCO2
sysIO Bank 5
sysIO Bank 2
VREF2
GND
GND
VCCO6
VCCO1
VREF6
sysIO Bank 6
sysIO Bank 1
GND
VREF1
GND
sysIO Bank 7
sysIO Bank 0
VCCO0
VREF0
GND
VCCO7
VREF7
GND
There are three classes of I/O interface standards implemented in the ispGDX2 devices. The first is the non-terminated, single-ended interface; it includes the 3.3V LVTTL standard along with the 1.8V, 2.5V and 3.3V LVCMOS
interface standards. The slew rate and strength of these output buffers can be controlled individually. Additionally,
PCI 3.3, PCI-X and AGP-1X are all subsets of this interface type. The second interface class implemented is the
terminated, single-ended interface standard. This group of interfaces includes different versions of SSTL and HSTL
interfaces along with CTT and GTL+. Use of these I/O interfaces requires an additional VREF signal. At the system
level, a termination voltage, VTT, is also required. Typically, an output will be terminated to VTT at the receiving end
of the transmission line it is driving. The final types of interfaces implemented are the differential standards
LVPECL, LVDS and Bus LVDS. Table 3 shows the I/O standards supported by the ispGDX2 devices along with
nominal VCCO, VREF and VTT.
The ispGDX2 family also features 5V tolerant I/O. I/O banks with VCCO = 3.3V may have inputs driven to a maximum of 5.5V for easy interfacing with legacy systems. Up to 64 I/O pins per device may be driven by 5V inputs.
8
Lattice Semiconductor
ispGDX2 Family Data Sheet
Table 3. ispGDX2 Supported I/O Standards
sysIO Standard
Nominal VCCO
Nominal VREF
Nominal VTT
LVCMOS 3.3
3.3V
—
—
LVCMOS 2.5
2.5V
—
—
LVCMOS 1.8
1.8V
—
—
LVTTL
3.3V
—
—
PCI 3.3
3.3V
—
—
PCI -X
3.3V
—
—
AGP-1X
3.3V
—
—
SSTL3 class I & II
3.3V
1.5V
1.5V
SSTL2 class I & II
2.5V
1.25V
1.25V
CTT 3.3
3.3V
1.5V
1.5V
CTT 2.5
2.5V
1.25V
1.25V
HSTL class I
1.5V
0.75V
0.75V
HSTL class III
1.5V
0.9V
0.75V
HSTL class IV
1.5V
0.9V
1.5V
1.8/2.5/3.3V
1.0V
1.5V
3.3V
—
—
LVDS
2.5/3.3V
—
—
Bus-LVDS
2.5/3.3V
—
—
GTL+
LVPECL1, 2, 3
1. LVPECL drivers require three resistor pack (see Figure 17).
2. Depending on the driving LVPECL output specification, GDX2 LVPECL input driver may require terminating resistors.
3. For additional information on LVPECL refer to Lattice technical note number TN1000, sysIO Design and Usage Guidelines.
The dedicated inputs support a subset of the sysIO standards indicated in Table 4. These inputs are associated
with a bank consistent with their location.
Table 4. I/O Standards Supported by Dedicated Inputs
LVCMOS
LVDS
All other ASIC I/Os
Global OE Pins
Yes
No
Yes2
Global MUX Select Pins
Yes
No
Yes2
Resetb
Yes
No
Yes2
Global Clock/Clock Enables
Yes
Yes
Yes2
ispJTAG™ Port
Yes1
No
No
TOE
Yes
No
No
1. LVCMOS as defined by the VCCJ pin voltage.
2. No PCI clamp.
For more information on the sysIO capability, please refer to Lattice technical note number TN1000, sysIO Design
and Usage Guidelines.
sysCLOCK PLL
The sysCLOCK PLL circuitry consists of Phase-Lock Loops (PLLs) along the various dividers and reset and feedback signals associated with the PLLs. This feature gives the user the ability to synthesize clock frequencies and
generate multiple clock signals for routing within the device. Furthermore, it can generate clock signals that are
deskewed either at the board level or the device level. Figure 6 shows the ispGDX2 PLL block diagram.
Each PLL has a set of PLL_RST, PLL_FBK and PLL_LOCK signals. In order to facilitate the multiply and divide
capabilities of the PLL, each PLL has associated dividers. The M divider is used to divide the clock signal, while the
9
Lattice Semiconductor
ispGDX2 Family Data Sheet
N divider is used to multiply the clock signal. The K divider is used to provide a divided clock frequency of the adjacent PLL. This output can be routed to the global clock net. The V divider is used to provide lower frequency output
clocks, while maintaining a stable, high frequency output from the PLL’s VCO circuit. The PLL also has a delay feature that allows the output clock to be advanced or delayed to improve set-up and clock-to-out times for better performance. For more information on the PLL, please refer to Lattice technical note number TN1003, sysCLOCK PLL
Design and Usage Guidelines.
Figure 6. sysCLOCK PLL
PLL_LOCK
CLK_OUT
CLK_IN
Input Clock
(M) Divider
1 to 32
Programmable
+Delay
--------------------
Post-scalar
(V) Divider
PLL (n)
Clock Net
1, 2, 4, 8,
16, 32
Programmable
-Delay
PLL_RST
Clock (K)
Divider
2, 4, 8,
16, 32
To Adjacent_PLL
From
Adjacent_PLL
Feedback
Divider (N)
X 1 to 32
PLL_FBK
There are four global clock networks routed to each MRB block. These global clocks, CLK0-3, can either be generated by the PLL circuits or supplied externally. External clock pins can be configured as single-ended or differential
(LVDS) input. Figure 7 illustrates how the sysCLOCK PLL inputs and outputs can be routed to the I/O pins or general routing. Figure 10 shows the clock network for the ispGDX2-256 and Figure 8 shows the clock networks for
ispGDX2-128 and ispGDX2-64. The Reset (0) pin from the Control Array of selected GDX Blocks can be programmed to reset the M Divider of the PLLs. This provides a means for generating the reset signal internally.
Table 5 details which GDX Block provides reset to the PLLs.
Table 5. Internal Reset Input of the PLL (M Divider)
ispGDX2-256
PLL0
PLL1
PLL2
PLL3
GDX Block 5A
GDX Block 7B
GDX Block 1A
GDX Block 3B
ispGDX2-128
GDX Block 2A
—
GDX Block 0A
—
ispGDX2-64
GDX Block 0A
—
GDX Block 1B
—
10
Lattice Semiconductor
ispGDX2 Family Data Sheet
Figure 7. I/O Pin Connection to the sysCLOCK PLL1
PLL_LOCK
CLK_OUT
GCLK_IN
Input Clock
(M) Divider
÷ 1 to 32
Output
Reg/
Latch
Programmable
+ Delay
--------------------
PLL (n)
Programmable
- Delay
Post-scalar
(V) Divider
÷
1, 2, 4, 8,
16, 32
Clock
(K) Divider
÷
2, 4, 8,
16, 32
Clock Net
To Adjacent_PLL
Input
Reg/
Latch
From Adjacent_PLL
Feedback
Divider (N)
x 1 to 32
GRP
GDX Block
PLL_FBK
PLL_RST
Resetb (0)
Control Array
(from selected blocks)
GCLK_IN
1. Some pins are shared. See Logic Signal Connections Table for details.
11
Delay
Lattice Semiconductor
ispGDX2 Family Data Sheet
Figure 8. ispGDX2-64 CLOCK Network
sysIO Interface
sysCLOCK
Clock Net
MRB
Clock Net
Reg/
Latch
Clock Net
Reg/
Latch
Clock Net
Reg/
Latch
Clock Net
Reg/
Latch
CLK0
K(0)
GCLK/CE0
VREF0
+
-
PLL
(0)
CLK_OUT0
GCLK/CE1
VREF1
+
-
CLK_OUT2
CLK2
K(2)
GCLK/CE2
VREF2
GCLK/CE3
VREF3
+
-
PLL
(2)
+
-
Figure 9. ispGDX2-128 CLOCK Network
sysIO Interface
sysCLOCK
Clock Net
MRB
Clock Net
Reg/
Latch
Clock Net
Reg/
Latch
Clock Net
Reg/
Latch
Clock Net
Reg/
Latch
CLK0
K(0)
GCLK/CE0
VREF0
+
-
PLL
(0)
CLK_OUT0
GCLK/CE1
VREF1
+
-
CLK_OUT2
CLK2
K(2)
GCLK/CE2
VREF2
GCLK/CE3
VREF3
+
-
PLL
(2)
+
-
12
Lattice Semiconductor
ispGDX2 Family Data Sheet
Figure 10. ispGDX2-256 CLOCK Network
sysIO Interface
sysCLOCK
Clock Net
MRB
Clock Net
Reg/
Latch
Clock Net
Reg/
Latch
Clock Net
Reg/
Latch
Clock Net
Reg/
Latch
CLK0
K(0)
GCLK/CE0
VREF0
+
-
PLL
(0)
CLK_OUT0
CLK1
K(1)
GCLK/CE1
VREF1
+
-
PLL
(1)
CLK_OUT1
CLK2
K(2)
GCLK/CE2
VREF2
+
-
PLL
(2)
CLK_OUT2
CLK3
K(3)
GCLK/CE3
VREF3
+
-
PLL
(3)
CLK_OUT3
13
Lattice Semiconductor
ispGDX2 Family Data Sheet
Operating Modes
All the GDX Blocks in the ispGDX2 family can be programmed in four modes: Basic, FIFO only, SERDES only, and
FIFO with SERDES mode. In basic mode, the SERDES and FIFO are disabled and the MUX output of the MRB
connects to the output register. Inputs are connected to the GRP via the MRB.
Figure 11 shows the four different operating modes. Precise detail of the FIFO and SERDES connections is provided in their respective sections.
Figure 11. Four Operating Modes of ispGDX2 Devices
Basic
Mode
GRP
FIFO
Mode
GRP
SERDES
Mode
(FIFO in
Flow-through
Mode)
GRP
SERDES
and
FIFO Mode GRP
GDX
Block
FIFO
GDX
Block
FIFO
SERDES
SERDES
FIFO*
GDX
Block
SERDES
FIFO
GDX
Block
SERDES
sysIO
Bank
sysIO
Bank
sysIO
Bank
sysIO
Bank
*FIFO held in RESET for SERDES-only mode.
FIFO Operations
Each GDX Block is associated with a 10-bit wide and 15-word deep (10x15) RAM. This RAM, combined with two
address counters and two comparators, is used to implement a FIFO as a “circular queue”. The FIFO has separate
clocks, the Read Clock (RCLK) and Write Clock (WCLK), for asynchronous operation. The FIFO has three additional control signals Write Enable, Read Enable and FIFO Reset. Three flags show the status of the FIFO: Empty,
Full and Start Read. Each FIFO receives the global Power-on Reset and Reset signals. Figure 12 shows the connections to the FIFO.
14
Lattice Semiconductor
ispGDX2 Family Data Sheet
Figure 12. ispGDX2 FIFO Signals
10
10
Data Out (DOUT)
Data In (DIN)
Write Clock (WCLK)
Write Enable (WE)
Read Clock (RCLK)
Read Enable (RE)
FIFO
10x15
Full (FULL)
Empty (EMPTY)
Global Reset (RESETb)
Start Read (STRDb)
Power-on Reset (PORb)
FIFO Reset (FIFORSTb)
Read Clock and Read Enable are the same as the Clock and Clock Enable signals of the input registers of the
associated MRB. These registers are used to register the FIFO outputs, and in modes that utilize the FIFO are configured to use the same clock and clock enable signals. The Write Clock is selected from one of the GCLK/CE signals or the RECCLK (Recovered Clock) signal from the associated SERDES. The Write Enable is selected from
one of the local MRB product term CLK/CE signals. All FIFO operations occur on the rising edge of the clock
although clock polarity of these signals can be programmed.
The flags from the FIFO, FULL, EMPTY and STRDb (Start Read) are each fed via a MUX in the MRB to an I/O
buffer. The STRDb (half full) signal is used in conjunction with SERDES. STRDb is an active low signal, the signal
is inactive (high) on FIFO RESET. After the FIFO reset when the FIFO contains data in five memory locations, at
the following write clock transition the STRDb becomes active (low). Note, if the Read Clocks arrive before writing
the sixth location, it may take longer than five write clocks before the STRDb becomes active. When the FIFO has
data in the first six locations, at the next write clock transition the STRDb becomes inactive (high). Again, if the
Read Clocks arrive before writing the seventh location, the STRDb may stay active for longer than one write clock
period, even if the FIFO contains data in less than five locations. After this event, the STRDb stays inactive until the
FIFO is RESET again. STRDb does not become active again even if less than six memory locations are occupied
in the FIFO. It is the user’s responsibility to monitor the FULL and EMPTY signals to avoid data underflow/overflow
and to take appropriate actions.
Figure 13 shows how the FIFO is connected between the I/O banks and the GDX Blocks in FIFO mode. For more
information on the FIFO, please refer to Lattice technical note number TN1020, sysHSI Usage Guidelines.
15
Lattice Semiconductor
ispGDX2 Family Data Sheet
Figure 13. Operation in FIFO Mode2
GRP
GDX Block 1
Input
Reg/
Latch
SERDES
FIFO
Delay
Pre-Assigned Pins
10
10
DOUT
DIN
RCLK
RXD
Parallel
Data
Serial
Data In
(SIN)
TXD
Parallel
Data
Serial
Data Out
(SOUT)
RE
10
Output
Reg/
Latch
PT-CLK/CE(0:3)
WE
GCLK/CE(0:3)
RECCLK
Input
Reg/
Latch
WCLK
Input
Reg/
Latch
SYDT
Output
Reg/
Latch
FULL
EMPTY
Output
Reg/
Latch
CDRRSTb
FIFORSTb
Notes:
1. For clarity, only a portion of the GDX Block is shown.
2. Some signals share pins. See Logic Signal Connections tables for details.
16
POR
RESETb
CAL
Lattice Semiconductor
ispGDX2 Family Data Sheet
High Speed Serial Interface Block (sysHSI Block)1
The High Speed Serial Interface (sysHSI) allows high speed serial data transfer over a pair of LVDS I/O. The
ispGDX2 devices have multiple sysHSI Blocks.
Each sysHSI Block has two SERDES blocks which contain two main sub-blocks, Transmitter (with a serializer) and
Receiver (with a deserializer) including Clock/Data Recovery Circuit (CDR). Each SERDES can be used as a full
duplex channel. The two SERDES in a given sysHSI Block share a common clock and must operate at the same
nominal frequency. Figure 14 shows the sysHSI Block.
Device features support two data coding modes: 10B/12B and 8B/10B (for use with other encoding schemes, see
Lattice’s sysHSI application notes). The encoding and decoding of the 10B/12B standard are performed within the
device in dedicated logic. For the 8B/10B standard, the symbol boundaries are aligned internally but the encoding
and decoding are performed outside the device.
Each SERDES block receives a single high speed serial data input stream (with embedded clock) from an input,
and provide a low speed 10-bit wide data stream and a recovered clock to the device. For transmitting, the SERDES converts a 10-bit wide low-speed data stream to a single high-speed data stream with embedded clock for
output.
Additionally, multiple sysHSI Blocks can be grouped together to form a source synchronous interface of between 18 channels.
Figure 15 shows the connections of the SERDES block with the FIFO, sysIO block and the MRB. Table 6 provides
the descriptions of the SERDES.
For more information on the SERDES/CDR, refer to Lattice technical note number TN1020, sysHSI Usage Guidelines.
Table 6. SERDES Signal Descriptions
Signal
I/O
Description
CDRRSTb
I
Resets the CDR circuit of sysHSI block
SYDT
O
Symbol alignment detect for sysHSI block
CAL
I
Initiates source synchronous calibration sequence
RXD
Internal
Parallel data in for sysHSI block
TXD
Internal
Parallel data out for sysHSI block
REFCLK
Internal
Reference clock received from the clock tree
SIN
I
Serial data input for sysHSI block (LVDS input)
SOUT
O
Serial data output for sysHSI block (LVDS output)
SS_CLKIN
I
Clock input for source synchronous group
SS_CLKOUT
O
Clock output for source synchronous group
RECCLK
Internal
Recovered clock from encoded data by CDR of sysHSI block
CSLOCK
Internal
Lock output of the PLL associated with sysHSI block
1. “E-Series” does not support sysHSI.
17
Lattice Semiconductor
ispGDX2 Family Data Sheet
Figure 14. sysHSI Block with SERDES and FIFO
sysHSI Block
Core Logic
SERDES
SOUT
SIN
Serializer
De-serializer
including CDR
TXD
10
RXD
10
FIFO
RECCLK
GDX
Block
CSLOCK
SS_CLKOUT
CSLOCK
CSPLL
SS_CLKIN
GRP
CAL
Shared Source Synchronous
pins drive multiple sysHSI
blocks
SERDES
SOUT
SIN
Serializer
De-serializer
including CDR
TXD
10
RXD
10
RECCLK
REFCLK (0:3)
Reference clocks
from CLK (0:3)
Note: Some pins are shared. See Logic Signal Connections table for details
18
FIFO
GDX
Block
Lattice Semiconductor
ispGDX2 Family Data Sheet
Figure 15. Operation in SERDES Only Mode1, 2
GRP
GDX Block
Input
Reg/
Latch
SERDES
FIFO
Pre-Assigned Pins
10
Delay
DOUT
DIN
RCLK
RXD
Parallel
Data
Serial
Data In
(SIN)
TXD
Parallel
Data
Serial
Data Out
(SOUT)
RE
10
Output
Reg/
Latch
PT-CLK/CE(0:3)
WE
GCLK/CE(0:3)
RECCLK
Input
Reg/
Latch
WCLK
Input
Reg/
Latch
SYDT
Output
Reg/
Latch
FULL
EMPTY
Output
Reg/
Latch
CDRRSTb
FIFORSTb
Notes:
1. Some pins shared. See Logic Signal
Connections table for details.
2. For SERDES only mode programmable bit
holds FIFO in reset. Input registers used for
DOUT, and RECCLK configured as
latches and held in pass through.
POR
RESETb
19
CAL
Lattice Semiconductor
ispGDX2 Family Data Sheet
Figure 16. Operation in SERDES with FIFO Mode
GRP
GDX Block
Input
Reg/
Latch
SERDES
FIFO
Pre-Assigned Pins
10
Delay
DOUT
DIN
RCLK
RXD
Parallel
Data
Serial
Data In
(SIN)
TXD
Parallel
Data
Serial
Data Out
(SOUT)
RE
10
Output
Reg/
Latch
PT-CLK/CE(0:3)
WE
GCLK/CE(0:3)
RECCLK
Input
Reg/
Latch
WCLK
Input
Reg/
Latch
SYDT
Output
Reg/
Latch
FULL
EMPTY
Output
Reg/
Latch
CDRRSTb
FIFORSTb
POR
RESETb
20
CAL
Lattice Semiconductor
ispGDX2 Family Data Sheet
IEEE 1149.1-Compliant Boundary Scan Testability
All ispGDX2 devices have boundary scan cells and are compliant to the IEEE 1149.1 standard. This allows functional testing of the circuit board on which the device is mounted through a serial scan path that can access all critical logic notes. Internal registers are linked internally, allowing test data to be shifted in and loaded directly onto
test nodes, or test node data to be captured and shifted out for verification. In addition, these devices can be linked
into a board-level serial scan path for more board-level testing. The test access port has its own supply voltage that
can operate with LVCMOS3.3, 2.5 and 1.8 standards.
sysIO Quick Configuration
To facilitate the most efficient board test, the physical nature of the I/O cells must be set before running any continuity tests. As these tests are fast, by nature, the overhead and time that is required for configuration of the I/Os'
physical nature should be minimal so that board test time is minimized. The ispGDX2 family of devices allows this
by offering the user the ability to quickly configure the physical nature of the sysIO cells. This quick configuration
takes milliseconds to complete, whereas it takes seconds for the entire device to be programmed. Lattice's
ispVM™ System programming software can either perform the quick configuration through the PC parallel port, or
can generate the ATE or test vectors necessary for a third-party test system.
IEEE 1532-Compliant In-System Programming
In-system programming of devices provides a number of significant benefits including rapid prototyping, lower
inventory levels, higher quality and the ability to make in-field modifications. All ispGDX2 devices provide In-System
Programming (ISP) capability through their Boundary Scan Test Access Port. This capability has been implemented in a manner that ensures that the port remains compliant to the IEEE 1532 standard. By using IEEE 1532
as the communication interface through which ISP is achieved, designers get the benefit of a standard, well defined
interface.
The ispGDX2 devices can be programmed across the commercial temperature and voltage range. The PC-based
Lattice software facilitates in-system programming of ispGDX2 devices. The software takes the JEDEC file output
produced by the design implementation software, along with information about the scan chain, and creates a set of
vectors used to drive the scan chain. The software can use these vectors to drive a scan chain via the parallel port
of a PC. Alternatively, the software can output files in formats understood by common automated test equipment.
This equipment can then be used to program ispGDX2 devices during the testing of a circuit board.
Security Scheme
A programmable security scheme is provided on the ispGDX2 devices as a deterrent to unauthorized copying of
the array configuration patterns. Once programmed, this scheme prevents readback of the programmed pattern by
a device programmer, securing proprietary designs from competitors. The security scheme also prevents programming and verification. The entire device must be erased in order to reset the security scheme.
Hot Socketing
The ispGDX2 devices are well suited for those applications that require hot socketing capability. Hot socketing a
device requires that the device, when powered down, can tolerate active signals on the I/Os and inputs without
being damaged. Additionally, it requires that the effects of the powered-down device be minimal on active signals.
21
Lattice Semiconductor
ispGDX2 Family Data Sheet
Absolute Maximum Ratings 1, 2, 3
ispGDX2C (1.8V)
ispGDX2B/V (2.5/3.3V)
Supply Voltage VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 2.5V . . . . . . . . . . . . . . . . -0.5 to 5.5V
PLL Supply Voltage VCCP . . . . . . . . . . . . . . . . . . . . -0.5 to 2.5V . . . . . . . . . . . . . . . . -0.5 to 5.5V
Output Supply Voltage VCCO . . . . . . . . . . . . . . . . . -0.5 to 4.5V . . . . . . . . . . . . . . . . -0.5 to 4.5V
JTAG Supply Voltage (VCCJ) . . . . . . . . . . . . . . . . . -0.5 to 4.5V . . . . . . . . . . . . . . . . -0.5 to 4.5V
Input or I/O Tristate Voltage Applied 4, 5 . . . . . . . . . -0.5 to 5.5V . . . . . . . . . . . . . . . . -0.5 to 5.5V
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . -65 to 150°C . . . . . . . . . . . . . . . -65 to 150°C
Junction Temp. (TJ) with Power Applied . . . . . . . . -55 to 150°C . . . . . . . . . . . . . . . -55 to 150°C
1. Stress above those listed under the Absolute Maximum Ratings may cause permanent damage to the device. Functional operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied (while programming, following the programming specifications).
2. Compliance with the Lattice Thermal Management document is required.
3. All voltages referenced to GND.
4. Overshoot and undershoot of -2V to (VIH (MAX)+2) volts is permitted for a duration of <20ns.
5. A maximum of 64 I/Os per device with VIN > 3.6V is allowed.
Recommended Operating Conditions
Symbol
VCC
VCCP
Min.
Max.
Units
Supply Voltage for 1.8V Devices1
Parameter
1.65
1.95
V
Supply Voltage for 2.5V Devices
2.3
2.7
V
Supply Voltage for 3.3V Devices
3
3.6
V
Supply Voltage for PLL and sysHSI Blocks, 1.8V Devices1
1.65
1.95
V
Supply Voltage for PLL and sysHSI Blocks, 2.5V Devices
2.3
2.7
V
Supply Voltage for PLL and sysHSI Blocks, 3.3V Devices
VCCJ
3
3.6
V
Power Supply Voltage for JTAG Programming 1.8V Operation
1.65
1.95
V
Power Supply Voltage for JTAG Programming 2.5V Operation
2.3
2.7
V
Power Supply Voltage for JTAG Programming 3.3V Operation
3
3.6
V
0
90
-40
105
°C
°C
TJ (COM)
Junction Commercial Operation
TJ (IND)
Junction Industrial Operation
1. sysHSI specification is valid for VCC and VCCP = 1.7V to 1.9V.
Erase Reprogram Specifications
Parameter
Erase/Reprogram Cycle
Min
Max
Units
1,000
—
Cycles
Note: Valid over commercial temperature range.
Hot Socketing Specifications1, 2, 3
Symbol
IDK
1.
2.
3.
4.
4
Parameter
Input or Tristated I/O Leakage Current
Condition
0 ≤ VIN ≤ 3.0V
Min
Typ
Max
Units
—
+/-50
+/-800
μA
Insensitive to sequence of VCC and VCCO. However, assumes monotonic rise/fall rates for VCC and VCCO, provided (VIN - VCCO) ≤ 3.6V.
LVTTL, LVCMOS only.
0 < VCC ≤ VCC (MAX), 0 < VCCO ≤ VCCO (MAX).
IDK is additive to IPU, IPD or IBH. Device defaults to pull-up until fuse circuitry is active.
22
Lattice Semiconductor
ispGDX2 Family Data Sheet
DC Electrical Characteristics
Over Recommended Operating Conditions
Symbol
IIL, IIH1
Parameter
Input or I/O Low Leakage
Min.
Typ.
Max.
Units
0 ≤ VIN ≤ (VCCO - 0.2V)
Condition
—
—
10
μA
(VCCO - 0.2V) < VIN ≤ 3.6V
—
—
30
μA
Input High Leakage Current
3.6V < VIN ≤ 5.5V and
3.0V ≤ VCCO ≤ 3.6V
—
—
3
mA
IPU
I/O Active Pull-up Current
0 ≤ VIN ≤ 0.7 VCCO
-30
—
-150
μA
IPD
I/O Active Pull-down Current
VIL (MAX) ≤ VIN ≤ VIH (MAX)
30
—
150
μA
IBHLS
Bus Hold Low Sustaining Current VIN = VIL (MAX)
30
—
—
μA
IIH
3
IBHHS
Bus Hold High Sustaining Current VIN = 0.7 VCCO
-30
—
—
μA
IBHLO
Bus Hold Low Overdrive Current
—
—
150
μA
IBHLH
Bus Hold High Overdrive Current 0 ≤ VIN ≤ VIH (MAX)
VBHT
Bus Hold Trip Points
C1
I/O Capacitance2
C2
Clock Capacitance2
C3
Global Input Capacitance2
0 ≤ VIN ≤ VIH (MAX)
—
—
-150
μA
VCCO * 0.35
—
VCCO * 0.65
V
VCCO = 3.3V, 2.5V, 1.8V
—
VCC = 1.8V, VIO = 0 to VIH (MAX)
—
VCCO = 3.3V, 2.5V, 1.8V
—
VCC = 1.8V, VIO = 0 to VIH (MAX)
—
VCCO = 3.3V, 2.5V, 1.8V
—
VCC = 1.8V, VIO = 0 to VIH (MAX)
—
—
8
—
—
6
—
—
6
—
pf
pf
pf
1. Input or I/O leakage current is measured with the pin configured as an input or as an I/O with the output driver tri-stated. It is not
measured with the output driver active. Bus maintenance circuits are disabled.
2. TA = 25°C, f = 1.0MHz.
3. 5V tolerant inputs and I/Os should be placed in banks where 3.0V ≤ VCCO ≤ 3.6V. The JTAG ports are not included for the 5V tolerant interface.
Supply Current
Over Recommended Operating Conditions (ispGDX2-256)4
Symbol
Description
Power Pins
Core Logic Power Supply Current
ICC1,2
VCC
GPLL/sysHSI Logic Power Supply
Current
ICCP2
ICCO3
ICCJ
1.
2.
3.
4.
GPLL/sysHSI CSPLL Power
Supply Current
Bank Power Supply Current
JTAG Programming Current
VCCP
VCCO
VCCJ
Vcc (V)
Min.
Typ.
Max.
Units
3.3
—
59.6
—
mA
2.5
—
58.7
—
mA
1.8
—
60.0
—
mA
3.3
—
118.7
—
mA
2.5
—
118.7
—
mA
1.8
—
117.5
—
mA
3.3
—
14.7
—
mA
2.5
—
14.7
—
mA
1.8
—
17.4
—
mA
3.3
—
35
—
mA
2.5
—
35
—
mA
1.8
—
25
—
mA
3.3
—
1.5
—
mA
2.5
—
1.0
—
mA
1.8
—
800
—
µA
64-input switching frequency at 20 MHz, with one GRP fanout.
One GPLL with fVCO = 400 MHz and one sysHSI Block (two receivers and two transmitters) at 622 MHz data rate.
All 8-bank reference circuit currents, all I/Os in tristate, inputs held at valid logic levels, and bus maintenance circuits disabled.
TA = 25°C
23
Lattice Semiconductor
ispGDX2 Family Data Sheet
sysIO Recommended Operating Conditions
VCCO (V)1
Standard
VREF (V)
Min.
Typ.
Max.
Min.
Typ.
Max.
LVCMOS 3.3
3.0
3.3
3.6
-
-
-
LVCMOS 2.5
2.3
2.5
2.7
-
-
-
LVCMOS 1.8
1.65
1.8
1.95
-
-
-
LVTTL
3.0
3.3
3.6
-
-
-
2
PCI 3.3
3.0
3.3
3.6
-
-
-
PCI-X
3.0
3.3
3.6
-
-
-
AGP-1X
3.15
3.3
3.45
-
-
-
SSTL 2
2.3
2.5
2.7
1.15
1.25
1.35
SSTL 3
3.0
3.3
3.6
1.3
1.5
1.7
CTT 3.3
3.0
3.3
3.6
1.35
1.5
1.65
CTT 2.5
2.3
2.5
2.7
1.35
1.5
1.65
HSTL Class I
1.4
1.5
1.6
0.68
0.75
0.9
HSTL Class III
1.4
1.5
1.6
-
0.9
-
HSTL Class IV
1.4
1.5
1.6
-
0.9
-
GTL+
1.4
-
3.6
0.882
1.0
1.122
LVPECL
3.0
3.3
3.6
-
-
-
LVDS
2.3
2.5/3.3
3.6
-
-
-
BLVDS
2.3
2.5/3.3
3.6
-
-
-
1. Inputs are independent of VCCO setting. However, VCCO must be set within the valid operating range for one of the supported standards.
2. Software default setting.
24
Lattice Semiconductor
ispGDX2 Family Data Sheet
sysIO Single Ended DC Electrical Characteristics
Over Recommended Operating Conditions
Input/Output
Standard
LVCMOS 3.3
LVTTL
-0.3
-0.3
LVCMOS 2.5
1, 3
LVCMOS 1.8
VIH
VIL
Min (V)
-0.3
-0.3
Max (V)
0.8
0.8
0.7
0.68
Min (V)
2.0
2.0
1.7
1.07
Max (V)
5.5
5.5
3.6
3.6
IOL2
(mA)
IOH2
(mA)
VOL
Max (V)
VOH
Min (V)
0.4
2.4
0.2
VCCO - 0.2
0.1
-0.1
0.4
2.4
4
-4
0.2
VCCO - 0.2
0.1
-0.1
0.4
VCCO - 0.4
16, 12, 8,
5.33, 4
-16, -12, -8,
-5.33, -4
0.2
VCCO - 0.2
0.1
-0.1
8
-8
0.4
VCCO - 0.4
0.4
VCCO -0.4
20, 16, 12, -20, -16, -12,
8, 5.33, 4 -8, -5.33, -4
12, 5.33, 4 -12, -5.33, -4
LVCMOS 1.83
-0.3
0.68
1.07
3.6
0.2
VCCO - 0.2
0.1
-0.1
PCI 3.34
-0.3
1.08
1.5
3.6
0.1 VCCO
0.9 VCCO
1.5
-0.5
PCI -X5
-0.3
1.26
1.5
3.6
0.1 VCCO
0.9 VCCO
1.5
-0.5
AGP-1X4
-0.3
1.08
1.5
3.6
0.1 VCCO
0.9 VCCO
1.5
-0.5
SSTL3 class I
-0.3
VREF - 0.2
VREF + 0.2
3.6
0.7
VCCO - 1.1
8
-8
SSTL3 class II
-0.3
VREF - 0.2
VREF + 0.2
3.6
0.5
VCCO - 0.9
16
-16
SSTL2 class I
-0.3
VREF - 0.18 VREF + 0.18
3.6
0.54
VCCO - 0.62
7.6
-7.6
SSTL2 class II
-0.3
VREF - 0.18 VREF + 0.18
3.6
0.35
VCCO - 0.43
15.2
-15.2
CTT 3.3
-0.3
VREF - 0.2
VREF + 0.2
3.6
VREF - 0.4
VREF + 0.4
8
-8
CTT 2.5
-0.3
VREF - 0.3
VREF + 0.2
3.6
VREF - 0.4
VREF + 0.4
8
-8
HSTL class I
-0.3
VREF - 0.1
VREF + 0.1
3.6
0.4
VCCO - 0.4
8
-8
HSTL class III
-0.3
VREF - 0.2
VREF + 0.1
3.6
0.4
VCCO - 0.4
24
-8
HSTL class IV
-0.3
VREF - 0.3
VREF + 0.1
3.6
0.4
VCCO - 0.4
48
-8
GTL+
-0.3
VREF - 0.2
VREF + 0.2
3.6
0.6
n/a
36
n/a
1. Software default setting.
2. The average DC current drawn by I/Os between adjacent bank GND connections, or between the last GND in an I/O bank and the end of
the I/O bank, as shown in the logic signals connection table, shall not exceed n*8mA. Where n is the number of I/Os between bank GND
connections or between the last GND in a bank and the end of a bank.
3. For 1.8V devices (ispGDX2C) these specifications are VIL = 0.35 VCC and VIH = 0.65VCC
4. For 1.8V power supply devices these specifications are VIL = 0.3 * VCC * 3.3/1.8, VIH = 0.5 * VCC * 3.3/1.8
5. For 1.8V power supply devices these specifications are VIL = 0.35 * VCC * 3.3/1.8 and VIH = 0.5 * VCC * 3.3/1.8
25
Lattice Semiconductor
ispGDX2 Family Data Sheet
sysIO Differential DC Electrical Characteristics
Over Recommended Operating Conditions
Parameter
Symbol
Parameter Description
Test Conditions
Min.
Typ.
Max.
Units
0
—
2.4
V
+/-100
—
—
mV
—
—
+/-10
µA
LVDS
VINP VINM
Input Voltage
VTHD
—
Differential Input Threshold
0.2V ≤ VCM ≤ 1.8V
IIN
Input Current
Power On
VOH
Output High Voltage for VOP or VOM
RT = 100Ω
—
1.38
1.60
V
VOL
Output Low Voltage for VOP or VOM
RT = 100Ω
0.9
1.03
—
V
VOD
Output Voltage Differential
(VOP - VOM), RT = 100Ω
250
350
450
mV
ΔVOD
Change in VOD Between High and Low —
—
—
50
mV
VOS
Output Voltage Offset
(VOP - VOM)/2, RT = 100Ω
1.125
1.25
1.375
V
ΔVOS
Change in VOS Between H and L
—
—
—
50
mV
IOSD
Output Short Circuit Current
VOD = 0V. Driver Outputs
Shorted.
—
—
24
mA
VOH
Output High Voltage for VOP or VOM
RT = 27Ω
—
1.4
1.80
V
Bus LVDS1
VOL
Output Low Voltage for VOP or VOM
RT = 27Ω
0.95
1.1
—
V
VOD
Output Voltage Differential
|VOP - VOM|, RT = 27Ω
240
300
460
mV
—
—
27
mV
|VOP - VOM| /2, RT = 27Ω
1.1
1.3
1.5
V
—
—
27
mV
—
36
65
mA
Max.
Units
ΔVOD
Change in VOD Between H and L
VOS
Output Voltage Offset
ΔVOS
Change in VOS Between H and L
IOSD
Output Short Circuit Current
VOD = 0. Driver Outputs
Shorted.
1. VOP and VOM are the two outputs of the LVDS output buffer.
1
LVPECL
DC Parameter
Parameter Description
Min.
Max.
Min.
Min.
Output Supply Voltage
VIH
Input Voltage High
1.49
2.72
1.49
2.72
1.49
2.72
V
VIL
Input Voltage Low
0.86
2.125
0.86
2.125
0.86
2.125
V
VOH
Output Voltage High
1.7
2.11
1.92
2.28
2.03
2.41
V
VOL
Output Voltage Low
0.96
1.27
1.06
1.43
1.25
1.57
V
Differential Input voltage
0.3
VDIFF
2
3.0
Max.
VCCO
3.3
3.6
0.3
0.3
V
V
1. These values are valid at the output of the source termination pack as shown above with 100-ohm differential load only (see Figure 17).
The VOH levels are 200mV below the standard LVPECL levels and are compatible with devices tolerant of the lower common mode ranges.
2. Valid for 0.2V ≤ VCM ≤ 1.8V.
Figure 17. LVPECL Driver with Three Resistor Pack
1/4 of Bourns P/N
CAT 16-PC4F12
A
Zo
RT=100
Rs
RD
ispGDX2
LVPECL Buffer
Rs
Zo
26
to LVPECL
differential
receiver
Lattice Semiconductor
ispGDX2 Family Data Sheet
ispGDX2V/B/C, ispGDX2EV/EB/EC External Switching Characteristics
Over Recommended Operating Conditions
-3
Parameter
Description
-32
-35
-5
Min.
Max.
Min.
Max.
Min.
Max.
Min.
—
3.0
—
3.2
—
3.5
—
Max. Units
Output Paths
tPD
Data From Input Pin to Output Pin
5.0
ns
tPD_SEL
Data From Global Select Pin to Output Pin
—
2.8
—
3.0
—
3.3
—
4.7
ns
tCO
Global Clock to Output
—
2.9
—
3.1
—
3.2
—
5.4
ns
tOPS
Set-up Time Before Global Clock
2.0
—
2.0
—
2.0
—
3.0
—
ns
tOPH
Hold Time After Global Clock
0.0
—
0.0
—
0.0
—
0.0
—
ns
tOPCES
PT Clock Enable Setup Time Before
Global Clock
3.0
—
3.0
—
4.1
—
6.9
—
ns
tOPCEH
PT Clock Enable Hold Time After
Global Clock
0.0
—
0.0
—
0.0
—
0.0
—
ns
tOPRSTO
External Reset Pin to Output Delay
—
5.3
—
6.0
—
6.0
—
10.0
ns
tIPS
Set-up Time Before Global Clock
0.5
—
0.5
—
0.5
—
0.9
—
ns
tIPSZ
Set-up Time Before Global Clock
(Zero Hold Time)
2.0
—
2.0
—
2.0
—
3.0
—
ns
tIPH
Hold Time After Global Clock
1.0
—
1.0
—
1.0
—
1.7
—
ns
tIPHZ
Hold Time After Global Clock
(Zero Hold Time)
0.0
—
0.0
—
0.0
—
0.0
—
ns
tIPCES
PT Clock Enable Setup Time Before
Global Clock
3.1
—
3.1
—
3.1
—
5.1
—
ns
tIPCEH
PT Clock Enable Hold Time After Global
Clock
0.0
—
0.0
—
0.0
—
0.0
—
ns
tIPRSTO
External Reset Pin to Output Delay
—
5.6
—
6.5
—
7.5
—
12.5
ns
Input Paths
Output Enable Paths
tOECO
Global Clock to Output Enabled Pin
—
4.2
—
4.5
—
5.5
—
9.1
ns
tOES
Output Enable Register Set-up Time
Before Global Clock
1.6
—
1.6
—
2.0
—
3.4
—
ns
tOEH
Hold Time After Global Clock
0.0
—
0.0
—
0.0
—
0.0
—
ns
tOECES
PT Clock Enable Setup Time Before
Global Clock
3.5
—
3.5
—
4.1
—
6.9
—
ns
tOECEH
PT Clock Enable Hold Time After Global
Clock
0.0
—
0.0
—
0.0
—
0.0
—
ns
tGOE/DIS
Global OE Input to Output Enable/Disable
—
3.5
—
3.8
—
4.5
—
7.5
ns
tTOE/DIS
Test OE Input to Output Enable/Disable
—
5.2
—
5.5
—
6.2
—
10.3
ns
tEN/DIS
Input to Output Enable/Disable
—
5.2
—
5.5
—
6.2
—
10.3
ns
Clock and Reset Paths
tRW
Width of Reset Pulse
2.5
—
2.5
—
2.5
—
4.1
—
ns
tCW
Clock Width
1.3
—
1.5
—
1.6
—
2.7
—
ns
tGW
Clock Width
1.5
—
1.6
—
1.6
—
2.7
—
ns
fMAX (Ext)
Clock Frequency with External
Feedback 1/(tOPS + tCO)
—
204
—
196
—
192
—
119
MHz
fMAX (Tog,
No PLL)
Clock Frequency Maximum Toggle
(No PLL)
—
360
—
330
—
300
—
180
MHz
27
Lattice Semiconductor
ispGDX2 Family Data Sheet
ispGDX2V/B/C, ispGDX2EV/EB/EC External Switching Characteristics
Over Recommended Operating Conditions
-3
Parameter
Description
fMAX
Clock Frequency Maximum Toggle
(Tog, PLL) (With PLL)
-32
-35
-5
Min.
Max.
Min.
Max.
Min.
Max.
Min.
—
360
—
330
—
300
—
Max. Units
180
MHz
Timing v.2.2
28
Lattice Semiconductor
ispGDX2 Family Data Sheet
Timing Model
The task of determining the timing through the ispGDX2 family is relatively simple. The timing model provided in
Figure 18 shows the specific delay paths. Once the implementation of a given function is determined either conceptually or from the software report file, the delay path of the function can easily be determined from the timing
model. The Lattice design tools report the timing delays based on the same timing model for a particular design.
Note that the internal timing parameters are given for reference only, and are not tested. The external timing parameters are tested and guaranteed for every device.
Figure 18. ispGDX2 Timing Model Diagram (I/O Cell)
TOE/
GOE
t TOE_IN
t GOE_IN
t IOI
TOE path
GOE path
t PTOE
from GRP
to FIFO
(WE)
to sysHSI
(REFCLK)
GCLK/
GCLKEN
t GCLK
tCLK_IN
tCLKEN_IN
t IOI
t PTCLKEN
t OEBYPASS
from GRP
tPLL_DELAY
tPLL_SEC_DELAY
t PTCLK
OE Reg.
D
GSR
Q
to FIFO
(WCLK)
to sysHSI/FIFO
(Global Reset)
CE
t SR_IN
t IOI
from sysHSI
(SOUT)
S/R
from GRP
GSEL
t PTSR
t SEL_IN
t IOI
from GRP
from Adjacent
Cells (Output)
tPTSEL
t OPBYPASS
Output Reg.
t OPAC
D
t MUXPD
t MUXSEL
from GRP
t HSISOUT
from sysHSI/FIFO
(Flags)
t HSIFIFOFLAG
from sysHSI
(SSCLKOUT)
t HSISSCLKOUT
Output
Delays
t BUF
t EN
t DIS
t IOO
Q
CE
from Adjacent Cells
(Input)
IN
t FIFODATAOUT
from sysHSI
(RECCLK, SYDT)
t HSIOUT
from PLL
(PLL Output)
t PLLOUT
to sysHSI
(TXD)
S/R
t IPAC
from FIFO
(DOUT)
OUT
to Adjacent Cells
(Output)
Input Reg.
S/R
CE
t IN
t IOI
Q
D
t ROUTEGRP
to GRP
t INDIO
tIPBYPASS
to sysHSI/FIFO
to Adjacent Cells
(Input)
(SIN, Control, DIN, I/O Reset, SSCLKIN)
Italicized parameters are optional.
Model Version 1.6.7
to FIFO
(REN)
to FIFO
(RCLK)
29
Lattice Semiconductor
ispGDX2 Family Data Sheet
Figure 19. ispGDX2 Timing Model Diagram (with sysHSI and FIFO Receive Mode)
to I/O Cell
(RECCLK)
from I/O Cell
(SIN)
Serial Data
In
tHSISIN
sysHSI
(RXD)
FIFO
Data Out
(RXD)
tFIFODATAIN
Data In
Recovered
Clock
tFIFOWCLK
Write CLK
HSI Controls
Data Out
to I/O Cell
(DOUT)
HSI Flags
from I/O Cell
(Control)
from I/O Cell
(SSCLKIN)
from I/O Cell
(REFCLK)
CAL
tHSICTRLCAL
CSLOCK
to I/O Cell
(Output Path Flag)
SYDT
to I/O Cell
(SYDT and Output
Path Flags)
FIFO Flags
FULL, EMPTY
Source
Synchronous Clock
tHSISSCLKIN
from I/O Cell
(RCLK)
tFIFORCLK
Read
Clock
from I/O Cell
(RE)
tFIFOREN
Read
Enable
Reference Clock
tHSIREFCLK
RESET
RESET
from I/O Cell
(Global RESET)
from I/O Cell
(I/O RESET)
tHSIFIFORST
Figure 20. ispGDX2 Timing Model Diagram (with sysHSI Transmit Mode)
sysHSI
(TXD)
from I/O Cell
(TXD)
from I/O Cell
(REFCLK)
Serial
Data Out
tHSITXDATA
Data In
tHSIREFCLK
Reference Clock
Source
Synchronous Clock
30
to I/O Cell
(SOUT)
to I/O Cell
(SSCLKOUT)
to I/O Cell
(Output Path Flags)
Lattice Semiconductor
ispGDX2 Family Data Sheet
Figure 21. ispGDX2 Timing Model Diagram (in FIFO Only Mode)
from I/O Cell
(DIN)
tFIFODATAIN
Data In
from I/O Cell
(WCLK)
tFIFOWCLK
Write
Clock
from I/O Cell
(WE)
tFIFOWEN
Write
Enable
FIFO
Data Out
to I/O Cell
(DOUT)
FIFO Flags
FULL, EMPTY
from I/O Cell
(RCLK)
tFIFORCLK
Read
Clock
from I/O Cell
(RE)
tFIFOREN
Read
Enable
RESET
from I/O Cell
(Global RESET)
from I/O Cell
(I/O RESET)
tHSIFIFORST
31
to I/O Cell
(Output Path Flags)
Lattice Semiconductor
ispGDX2 Family Data Sheet
Sample External Timing Calculations
The following equations illustrate the task of determining the timing through the ispGDX2 family. These are only a
sample of equations to calculate the timing through the ispGDX2.
Figure 18 shows the specific delay paths and the Internal Timing Parameters table provides the parameter values.
Note that the internal timing parameters are given for reference only and are not tested. The external timing parameters are tested and guaranteed for every device.
Data from global select pin to output pin:
tPD_SEL = tSEL_IN + tMUXSEL + tOPBYPASS + tBUF
Global clock to output:
tCO = tCLK_IN + tGCLK + tOPCOi + tBUF
Input register or latch set-up time before global clock:
tIPS = tIN + tIPS - (tCLK + tGCLK)
Input register or latch hold time after global clock:
tIPH = (tCLK_IN + tGCLK) + tIPHi - tIN
Data from product term select to output pin:
tPD_PTSEL = tIN + tIPBYPASS + tROUTEGRP + tPTSEL + tMUXSEL + tOPBYPASS + tBUF
Product term clock to output:
tCO_PT = tIN + tIPBYPASS + tROUTEGRP + tPTCLK + tOPCOi + tBUF
Input register or latch set-up time before product term clock:
tIPS_PT = tIN + tIPSi_PT - (tIN + tIPBYPASS + tROUTEGRP + tPTCLK)
Input register or latch hold time after product term clock:
tIPH_PT = (tIN + tIPBYPASS + tROUTEGRP + tPTCLK) + tIPHi - tIN
Global OE input to output enable/disable:
tGOE/DIS = tGOE_IN + tOEBYPASS + tEN
External reset pin to output delay:
tOPRSTO = tSR_IN + tOPASROi + tBUF
32
Lattice Semiconductor
ispGDX2 Family Data Sheet
ispGDX2V/B/C, ispGDX2EV/EB/EC Internal Timing Parameters1
Over Recommended Operating Conditions
-3
Parameter
Description
-32
-35
-5
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max. Units
Input/Output Delays
tBUF
Output Buffer Delay
—
0.80
—
0.80
—
0.80
—
1.14
ns
tCLK_IN
Global Clock Input Delay
—
1.00
—
1.00
—
1.00
—
1.67
ns
tCLKEN_IN
Global Clock Enable Input Delay
—
1.80
—
1.80
—
1.80
—
3.00
ns
tDIS
Output Disable Delay
—
1.80
—
1.80
—
2.50
—
4.17
ns
tEN
Output Enable Delay
—
1.50
—
1.80
—
2.50
—
4.17
ns
tGOE_IN
Global Output Enable Path Delay
—
2.00
—
2.00
—
2.00
—
3.33
ns
tIN
Input Pin Delay
—
0.40
—
0.40
—
0.40
—
0.57
ns
tSEL_IN
Global MUX Select Input Delay
—
1.60
—
1.60
—
1.60
—
2.29
ns
tSR_IN
Global Set/Reset Path Delay
—
2.00
—
2.70
—
2.70
—
4.50
ns
tTOE_IN
Test Output Enable Path Delay
—
3.70
—
3.70
—
3.70
—
6.17
ns
Shift Register and MUX Delays
tIPAC
Input Path Adjacent I/O Cell Delay
(Shift Register)
—
0.80
—
0.80
—
0.80
—
1.33
ns
tOPAC
Output Path Adjacent I/O Cell Delay
(Shift Register)
—
1.30
—
1.30
—
1.30
—
2.17
ns
tMUXPD
MUX Data Path Delay
—
0.90
—
0.90
—
0.90
—
1.29
ns
tMUXSEL
MUX Select Path Delay
—
0.40
—
0.40
—
0.40
—
0.57
ns
AND Arrays and Routing Delays
tFIFODATAOUT
FIFO Output to I/O Block Delay
—
0.00
—
0.00
—
0.00
—
0.00
ns
tGCLK
Clock Tree Delay
—
0.40
—
0.40
—
0.40
—
0.67
ns
tHSIFIFOFLAG
HSI/FIFO Flag to I/O Block Delay
—
0.00
—
0.00
—
0.00
—
0.00
ns
tHSIOUT
HSI Output to I/O Cell Block Delay
—
0.00
—
0.00
—
0.00
—
0.00
ns
tHSISSCLKOUT
HSI Source Synchronous Clock to I/O Cell
Block Delay
—
0.00
—
0.00
—
0.00
—
0.00
ns
tPLL_DELAY
PLL Delay Increment
—
0.33
—
0.33
—
0.33
—
0.33
ns
tPTCLK
Clock AND Array Delay
—
2.20
—
2.20
—
2.20
—
3.67
ns
tPTCLKEN
Clock Enable AND Array Delay
—
2.10
—
2.10
—
2.10
—
3.50
ns
tPTOE
OE AND Array Delay
—
2.40
—
2.40
—
2.40
—
4.00
ns
tPTSEL
Select AND Array Delay
—
1.70
—
1.70
—
1.70
—
2.83
ns
tPTSR
Set/Reset AND Array Delay
—
1.40
—
1.40
—
2.70
—
4.50
ns
tROUTEGRP
Global Routing Pool Delay
—
0.90
—
0.90
—
0.90
—
1.29
ns
—
2.50
—
2.50
—
2.50
—
4.17
ns
Register/Latch Delays, Output Paths
tOPASROi
Asynchronous Set/Reset to Output
tOPASRRi
Asynchronous Set/Reset Recovery
—
2.50
—
2.50
—
2.50
—
4.17
ns
tOPBYPASS
Register/Latch Bypass Delay
—
0.00
—
0.20
—
0.50
—
0.71
ns
tOPCEHi
Register Clock Enable Hold Time
1.30
—
1.30
—
1.30
—
2.17
—
ns
tOPCESi
Register Clock Enable Setup Time
(Global Clock Enable)
1.10
—
1.10
—
1.10
—
1.83
—
ns
tOPCESi_PT
Register Clock Enable Setup Time
(Product Term Clock Enable)
1.00
—
1.00
—
2.10
—
3.50
—
ns
tOPCOi
Register Clock to Output Delay
—
0.70
—
0.90
—
1.00
—
1.67
ns
tOPHi
Register Hold Time
0.80
—
0.80
—
0.80
—
1.33
—
ns
33
Lattice Semiconductor
ispGDX2 Family Data Sheet
ispGDX2V/B/C, ispGDX2EV/EB/EC Internal Timing Parameters1 (Continued)
Over Recommended Operating Conditions
-3
Parameter
Description
-32
-35
-5
Min.
Max.
Min.
Max.
Min.
Max.
Min.
—
1.00
—
1.00
—
1.00
—
Max. Units
1.67
ns
0.80
—
0.80
—
0.80
—
1.33
—
ns
—
0.30
—
0.30
—
0.30
—
0.50
ns
1.20
—
1.20
—
1.20
—
2.00
—
ns
tOPLGOi
Latch Gate to Output Delay
tOPLHi
Latch Hold Time
tOPLPDi
Latch Propagation Delay (Transparent
Mode)
tOPLSi
Latch Setup Time (Global Gate)
tOPLSi_PT
Latch Setup Time (Product Term Gate)
1.00
—
1.00
—
1.00
—
1.67
—
ns
tOPSi
Register Setup Time (Global Clock)
1.20
—
1.20
—
1.20
—
2.00
—
ns
tOPSi_PT
Register Setup Time (Product Term Clock)
1.00
—
1.00
—
1.00
—
1.67
—
ns
tOPSRPWi
Asynchronous Set/Reset Pulse Width
—
2.50
—
2.50
—
2.50
—
4.17
ns
—
1.00
—
1.00
—
1.70
—
2.83
ns
Register/Latch Delays, Input Paths
tIPASROi
Asynchronous Set/Reset to Output
tIPASRRi
Asynchronous Set/Reset Recovery
—
2.50
—
2.50
—
2.50
—
4.17
ns
tIPBYPASS
Register/Latch Bypass Delay
—
0.00
—
0.00
—
0.00
—
0.00
ns
tIPCEHi
Register Clock Enable Hold Time
1.30
—
1.30
—
1.30
—
2.17
—
ns
tIPCESi
Register Clock Enable Setup Time
(Global Clock Enable)
1.10
—
1.10
—
1.10
—
1.83
—
ns
tIPCESi_PT
Register Clock Enable Setup Time
(Product Term Clock Enable)
1.10
—
1.10
—
1.10
—
1.83
—
ns
tIPCOi
Register Clock to Output Delay
—
0.80
—
1.00
—
1.00
—
1.67
ns
tIPHi
Register Hold Time
0.00
—
0.00
—
0.00
—
0.00
—
ns
tIPLGOi
Latch Gate to Output Delay
—
1.00
—
1.00
—
1.00
—
1.67
ns
tIPLHi
Latch Hold Time
0.00
—
0.00
—
0.00
—
0.00
—
ns
tIPLPDi
Latch Propagation Delay (Transparent
Mode)
—
0.30
—
0.30
—
0.30
—
0.50
ns
tIPLSi
Latch Setup Time (Global Term)
1.50
—
1.50
—
1.50
—
2.50
—
ns
tIPLSi_PT
Latch Setup Time (Product Term Gate)
1.50
—
1.50
—
1.50
—
2.50
—
ns
tIPSi
Register Setup Time (Global Clock)
1.50
—
1.50
—
1.50
—
2.50
—
ns
tIPSi_PT
Register Setup Time (Product Term Clock)
1.50
—
1.50
—
1.50
—
2.50
—
ns
tIPSRPWi
Asynchronous Set/Reset Pulse Width
—
2.50
—
2.50
—
2.50
—
4.17
ns
tOEASROi
Asynchronous Set/Reset to Output
—
2.50
—
2.50
—
2.50
—
4.17
ns
tOEASRRi
Asynchronous Set/Reset Recovery
—
2.50
—
2.50
—
2.50
—
4.17
ns
tOEBYPASS
Register/Latch Bypass Delay
—
0.00
—
0.00
—
0.00
—
0.00
ns
tOECEHi
Register Clock Enable Hold Time
1.30
—
1.30
—
0.80
—
1.33
—
ns
tOECESi
Register Clock Enable Setup Time (Global
Clock Enable)
1.20
—
1.20
—
1.20
—
2.00
—
ns
tOECESi_PT
Register Clock Enable Setup Time
(Product Term Clock Enable)
1.50
—
1.50
—
2.10
—
3.50
—
ns
tOECOi
Register Clock to Output Delay
—
1.30
—
1.30
—
1.60
—
2.67
ns
tOEHi
Register Hold Time
0.40
—
0.40
—
0.40
—
0.67
—
ns
tOELGOi
Latch Gate to Output Delay
—
1.60
—
1.60
—
1.60
—
2.67
ns
tOELHi
Latch Hold Time
0.40
—
0.40
—
0.40
—
0.67
—
ns
tOELPDi
Latch Propagation Delay (Transparent
Mode)
—
0.30
—
0.30
—
0.30
—
0.50
ns
OE Paths
34
Lattice Semiconductor
ispGDX2 Family Data Sheet
ispGDX2V/B/C, ispGDX2EV/EB/EC Internal Timing Parameters1 (Continued)
Over Recommended Operating Conditions
-3
Parameter
Description
-32
-35
-5
Min.
Max.
Min.
Max.
Min.
Max.
Min.
1.40
—
1.40
—
1.40
—
2.33
Max. Units
tOELSi
Latch Setup Time (Global Gate)
—
ns
tOELSi_PT
Latch Setup Time (Product Term Gate)
1.00
—
1.00
—
1.00
—
1.67
—
ns
tOESi
Register Setup Time (Global Clock)
1.00
—
1.00
—
1.40
—
2.33
—
ns
tOESi_PT
Register Setup Time (Product Term Clock)
1.00
—
1.00
—
1.00
—
1.67
—
ns
tOESRPWi
Asynchronous Set/Reset Pulse Width
—
2.50
—
2.50
—
2.50
—
4.17
ns
Timing v.2.2
1. Internal parameters are not tested and are for reference only. Refer to the timing model in this data sheet for details.
2. tPLL_DELAY is the unit of increment by which the clock signal can be incremented. The PLL can adjust the clock signal by up to t RANGE (as
given in the sysCLOCK PLL Timing section) in either direction in steps of size tPLL_DELAY.
35
Lattice Semiconductor
ispGDX2 Family Data Sheet
ispGDX2V/B/C, ispGDX2EV/EB/EC Timing Adjusters
-3
Parameter
Description
-32
-35
-5
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Units
Optional Adders
tINDIO
Input Delay
—
1.50
—
1.50
—
1.50
—
2.50
ns
tPLL_SEC_DELAY
Secondary PLL Output
Delay
—
1.30
—
1.30
—
1.30
—
1.30
ns
Slow Slew
Using Slow Slew (LVTTL and
LVCMOS Outputs Only)
—
0.90
—
0.90
—
0.90
—
0.90
ns
LVTTL_out
Using 3.3V TTL Drive
—
1.20
—
1.20
—
1.20
—
1.20
ns
LVCMOS_18_4mA_out
Using 1.8V CMOS Standard,
4mA Drive
—
0.30
—
0.30
—
0.30
—
0.30
ns
LVCMOS_18_5.33mA_out
Using 1.8V CMOS Standard,
5.33mA Drive
—
0.30
—
0.30
—
0.30
—
0.30
ns
LVCMOS_18_8mA_out
Using 1.8V CMOS Standard,
8mA Drive
—
0.00
—
0.00
—
0.00
—
0.00
ns
LVCMOS_18_12mA_out
Using 1.8V CMOS Standard,
12mA Drive
—
0.00
—
0.00
—
0.00
—
0.00
ns
LVCMOS_25_4mA_out
Using 2.5V CMOS Standard,
4mA Drive
—
1.20
—
1.20
—
1.20
—
1.20
ns
LVCMOS_25_5.33mA_out
Using 2.5V CMOS Standard,
5.33mA Drive
—
1.00
—
1.00
—
1.00
—
1.00
ns
LVCMOS_25_8mA_out
Using 2.5V CMOS Standard,
8mA Drive
—
0.40
—
0.40
—
0.40
—
0.40
ns
LVCMOS_25_12mA_out
Using 2.5V CMOS Standard,
12mA Drive
—
0.40
—
0.40
—
0.40
—
0.40
ns
LVCMOS_25_16mA_out
Using 2.5V CMOS Standard,
16mA Drive
—
0.40
—
0.40
—
0.40
—
0.40
ns
LVCMOS_33_4mA_out
Using 3.3V CMOS Standard,
4mA Drive
—
1.20
—
1.20
—
1.20
—
1.20
ns
LVCMOS_33_5.33mA_out
Using 3.3V CMOS Standard,
5.33mA Drive
—
1.20
—
1.20
—
1.20
—
1.20
ns
LVCMOS_33_8mA_out
Using 3.3V CMOS Standard,
8mA Drive
—
0.80
—
0.80
—
0.80
—
0.80
ns
LVCMOS_33_12mA_out
Using 3.3V CMOS Standard,
12mA Drive
—
0.60
—
0.60
—
0.60
—
0.60
ns
LVCMOS_33_16mA_out
Using 3.3V CMOS Standard,
16mA Drive
—
0.60
—
0.60
—
0.60
—
0.60
ns
LVCMOS_33_20mA_out
Using 3.3V CMOS Standard,
20mA Drive
—
0.30
—
0.30
—
0.30
—
0.30
ns
AGP_1X_out
Using AGP 1x Standard
—
0.60
—
0.60
—
0.60
—
0.60
ns
BLVDS_out
Using Bus Low Voltage Differential Signaling (BLVDS)
—
1.00
—
1.00
—
1.00
—
1.00
ns
CTT25_out
Using CTT 2.5v
—
0.30
—
0.30
—
0.30
—
0.30
ns
tIOO Output Adjusters
CTT33_out
Using CTT 3.3v
—
0.20
—
0.20
—
0.20
—
0.20
ns
GTL+_out
Using GTL+
—
0.50
—
0.50
—
0.50
—
0.50
ns
HSTL_I_out
Using HSTL 2.5V, Class I
—
0.50
—
0.50
—
0.50
—
0.50
ns
HSTL_III_out
Using HSTL 2.5V, Class III
—
0.60
—
0.60
—
0.60
—
0.60
ns
HSTL_IV_out
Using HSTL 2.5V, Class IV
—
0.60
—
0.60
—
0.60
—
0.60
ns
36
Lattice Semiconductor
ispGDX2 Family Data Sheet
ispGDX2V/B/C, ispGDX2EV/EB/EC Timing Adjusters (Continued)
-3
Parameter
Description
-32
-35
-5
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Units
LVPECL_out
Using LVPECL Differential
Signaling
—
0.30
—
0.30
—
0.30
—
0.30
ns
LVDS_out
Using Low Voltage Differential Signaling (LVDS)
—
0.80
—
0.80
—
0.80
—
0.80
ns
PCI_out
Using PCI Standard
—
0.60
—
0.60
—
0.60
—
0.60
ns
PCI_X_out
Using PCI-X Standard
—
0.60
—
0.60
—
0.60
—
0.60
ns
SSTL2_I_out
Using SSTL 2.5V, Class I
—
0.30
—
0.30
—
0.30
—
0.30
ns
SSTL2_II_out
Using SSTL 2.5V, Class II
—
0.50
—
0.50
—
0.50
—
0.50
ns
SSTL3_I_out
Using SSTL 3.3V, Class I
—
0.20
—
0.20
—
0.20
—
0.20
ns
SSTL3_II_out
Using SSTL 3.3V, Class II
—
0.40
—
0.40
—
0.40
—
0.40
ns
LVTTL_in
Using 3.3V TTL
—
0.00
—
0.00
—
0.00
—
0.00
ns
LVCMOS_18_in
Using 1.8V CMOS
—
0.00
—
0.00
—
0.00
—
0.00
ns
LVCMOS_25_in
Using 2.5V CMOS
—
0.00
—
0.00
—
0.00
—
0.00
ns
tIOI Input Adjusters
LVCMOS_33_in
Using 3.3V CMOS
—
0.00
—
0.00
—
0.00
—
0.00
ns
AGP_1X_in
Using AGP 1x
—
1.00
—
1.00
—
1.00
—
1.00
ns
BLVDS_in
Using Bus Low Voltage Differential Signaling (BLVDS)
—
0.50
—
0.50
—
0.50
—
0.50
ns
CTT25_in
Using CTT 2.5V
—
1.00
—
1.00
—
1.00
—
1.00
ns
CTT33_in
Using CTT 3.3V
—
1.00
—
1.00
—
1.00
—
1.00
ns
GTL+_in
Using GTL+
—
0.50
—
0.50
—
0.50
—
0.50
ns
HSTL_I_in
Using HSTL 2.5V, Class I
—
0.50
—
0.50
—
0.50
—
0.50
ns
HSTL_III_in
Using HSTL 2.5V, Class III
—
0.60
—
0.60
—
0.60
—
0.60
ns
HSTL_IV_in
Using HSTL 2.5V, Class IV
—
0.60
—
0.60
—
0.60
—
0.60
ns
LVPECL_in
Using Differential Signaling
(LVPECL)
—
0.00
—
0.00
—
0.00
—
0.00
ns
LVDS_in
Using Low Voltage Differential Signaling (LVDS)
—
0.50
—
0.50
—
0.50
—
0.50
ns
PCI_in
Using PCI
—
1.00
—
1.00
—
1.00
—
1.00
ns
PCI_X_in
Using PCI-X
—
1.00
—
1.00
—
1.00
—
1.00
ns
SSTL2_I_in
Using SSTL 2.5V, Class I
—
0.50
—
0.50
—
0.50
—
0.50
ns
SSTL2_II_in
Using SSTL 2.5V, Class II
—
0.50
—
0.50
—
0.50
—
0.50
ns
SSTL3_I_in
Using SSTL 3.3V, Class I
—
0.60
—
0.60
—
0.60
—
0.60
ns
SSTL3_II_in
Using SSTL 3.3V, Class II
—
0.60
—
0.60
—
0.60
—
0.60
ns
Timing v.2.2
37
Lattice Semiconductor
ispGDX2 Family Data Sheet
ispGDX2V/B/C, ispGDX2EV/EB/EC FIFO Internal Timing
Parameter
Description
-3
-32
-35
-5
Min. Max.
Min. Max.
Min. Max.
Min. Max.
Units
Routing Delays
tFIFODATAIN
FIFO Input Delay
tFIFODATAOUT FIFO Output to I/O Core Delay
—
0.00
—
0.00
—
0.00
—
0.00
ns
—
0.00
—
0.00
—
0.00
—
0.00
ns
tFIFORCLK
Read Clock Input Delay
—
0.00
—
0.00
—
0.00
—
0.00
ns
tFIFOREN
Read Clock Enable Input Delay
—
0.00
—
0.00
—
0.00
—
0.00
ns
tFIFOWCLK
Write Clock Input Delay
—
0.00
—
0.00
—
0.00
—
0.00
ns
tFIFOWEN
Write Clock Enable Input Delay
—
0.00
—
0.00
—
0.00
—
0.00
ns
—
2.00
—
2.00
—
2.00
—
3.33
ns
Core Delays
tFIFOCLKSKEW Global Read Clock to Write Clock Skew
tFIFOEMPTY
Read Clock to Empty Flag Delay
—
1.30
—
1.80
—
1.80
—
3.00
ns
tFIFOFULL
Write Clock to Full Flag Delay
—
1.30
—
1.80
—
1.80
—
3.00
ns
tFIFORCEH
Read Clock Hold after Read Clock Enable
Time
—
0.00
—
0.00
—
0.00
—
0.00
ns
tFIFORCES
Read Clock Setup before Read Clock
Enable Time
—
1.50
—
1.50
—
1.50
—
2.50
ns
tFIFORCLKO
Read Clock to FIFO Out Delay
—
0.50
—
0.50
—
0.50
—
0.83
ns
tFIFORSTO
Reset to Output Delay
—
0.70
—
0.70
—
0.70
—
1.17
ns
tFIFORSTPW
Reset Pulse Width
—
2.00
—
2.00
—
2.00
—
3.33
ns
tFIFORSTR
Reset Recovery Time
—
1.20
—
1.50
—
2.00
—
3.33
ns
tFIFOSTRD
Write Clock to Start Read Flag Delay
—
0.00
—
0.00
—
0.00
—
0.00
ns
tFIFOTHRU
Flow Through Delay
—
0.00
—
0.00
—
0.00
—
0.00
ns
tFIFOWCEH
Write Clock hold after Write Clock Enable
Time
—
2.00
—
2.00
—
2.00
—
3.33
ns
tFIFOWCES
Write Clock Setup before Write Clock Enable
Time
—
0.00
—
0.00
—
0.00
—
0.00
ns
tFIFOWCLKH
Write Data Hold after Write Clock Time
—
0.50
—
0.50
—
0.70
—
1.17
ns
tFIFOWCLKS
Write Data Setup before Write Clock Time
—
1.00
—
1.00
—
1.00
—
1.67
ns
Timing v.2.2
38
Lattice Semiconductor
ispGDX2 Family Data Sheet
sysHSI Block Timing
Figure 22 provides a graphical representation of the SERDES receiver input requirements. It provides guidance on
a number of input parameters, including signal amplitude and rise time limits, noise and jitter limits, and P and N
input skew tolerance.
Figure 22. Receive Data Eye Diagram Template (Differential)
Bit Time
V THD
200 mV Differential
+/- 100 mV Single Ended
jt TH
eo SIN
jtTH
jtTH : Optimum Threshold Crossing Jitter
The data pattern eye opening at the receive end of a link is considered the ultimate measure of received signal
quality. Almost all detrimental characteristics of a transmit signal and the interconnection link design result in eye
closure. This combined with the eye-opening limitations of the line receiver can provide a good indication of a link’s
ability to transfer error-free data.
Signal jitter is of special interest to system designers. It is often the primary limiting characteristic of long digital
links and of systems with high noise level environments. An interesting characteristic of the clock and data recovery
(CDR) portion of the ispGDX2 SERDES receiver is its ability to filter incoming signal jitter that is below the clock
recovery PLL bandwidth. For signals with high levels of low frequency jitter, the receiver can detect incoming data
error free, with eye openings significantly less than that shown in Figure 22.
sysHSI Block AC Specifications
Operating Frequency Ranges
Symbol
fCLK
Description
Mode
Reference Clock Frequency
Test Condition
Min.
Max.
Units
SS:CAL
50
200
MHz
10B12B
33
67
MHz
8B10B
fSIN2
fSOUT2
Serial Input
Serial Out
40
80
MHz
SS:CAL
with eoSIN
400
8001
Mbps
10B12B
with eoSIN
400
8001
Mbps
8B10B
with eoSIN
400
8001
Mbps
LVDS
CL = 5 pF, RL = 100 Ohms,
fCLK with no jitter
400
8001
Mbps
1. fSIN (8B/10B and 10B/12B) 800Mbps limit applicable only to the fastest speed grade. Limit is 700Mbps for the lower speed grade.
2. fSIN and fSOUT speeds are supported at VCC and VCCP at 1.7V to 1.9V for ispGDX2C devices.
39
Lattice Semiconductor
ispGDX2 Family Data Sheet
LOCKIN Time
Symbol
tSCLOCK
Description
Mode
Max.
Units
25
μS
With SS mode sync pattern
1024
tRCP1
10B12B
With 10B12B sync pattern
1024
tRCP
8B10B
With 8B10B idle pattern
CSPLL Lock Time
Condition
All
After input is stabilized
SS
Min.
tCDRLOCK
CDRPLL Lock-in Time
tSYNC
SyncPat Length
SS
1200
tRCP
tCAL
CAL Duration
SS
1100
tRCP
tSUSYNC
SyncPat Set-up Time to CAL
SS
50
tRCP
tHDSYNC
SyncPat Hold Time from CAL
SS
50
tRCP
960
tRCP
1. REFCLK clock period.
REFCLK and SS_CLKIN Timing
Symbol
Description
Mode
tDREFCLK
Frequency Deviation Between TX REFCLK and
CDRX REFCLK on One Link
8B10B/
10B12B
tJPPREFCLK
REFCLK, SS_CLKIN Peak-to-Peak Period Jitter
All
tPWREFCLK
REFCLK, SS_CLKIN Pulse Width, (80% to 80% or
20% to 20%).
All
tRFREFCLK
REFCLK, SS_CLKIN Rise/Fall Time (20% to 80% or
80% to 20%)
All
Condition
Min.
Max.
Units
-100
100
ppm
0.01
UIPP
Random Jitter
1
ns
2
ns
Serializer Timing2
Symbol
tJPPSOUT
tJPP8B10B
tRFSOUT
Description
SOUT Peak-to-Peak Output Data Jitter
Mode
All
Condition
Min.
Max.
Units
fCLK with no jitter
0.25
UIPP
SOUT Peak-to-Peak Random Jitter
8B10B
800 Mbps w/K28.7-
130
ps
SOUT Peak-to-Peak Deterministic Jitter
8B10B
800 Mbps w/K28.5+
SOUT Output Data Rise/Fall Time (20%,
80%)
LVDS
BLVDS
160
ps
700
ps
900
ps
SS/8B10B
2Bt1 + 2
2Bt1 +10
ns
10B12B
1Bt1 + 2
1Bt1 +10
ns
250
ps
tCOSOUT
REFCLK to SOUT Delay
tSKTX
Skew of SOUT with Respect to
SS_CLKOUT
SS
tCKOSOUT
SS_CLKOUT to bit0 of SOUT
SS
2Bt1 - tSKTX 2Bt1 + tSKTX
tHSITXDDATAS TXD Data Setup Time
All
Note 3
tHSITXDDATAH TXD Data Hold Time
All
Note 3
1.5
ns
ns
1.0
ns
1. Bt: Bit Time Period. High Speed Serial Bit Time.
2. The SIN and SOUT jitter specifications listed above are under the condition that the clock tree that drives the REFCLK to sysHSI Block is in
sysCLOCK PLL BYPASS mode.
3. Internal timing for reference only.
40
Lattice Semiconductor
ispGDX2 Family Data Sheet
Deserializer Timing
Symbol
Description
Mode
fDSIN
SIN Frequency Deviation from REFCLK
eoSIN
SIN Eye Opening Tolerance
Conditions
8B10B/
10B12B
All
Notes 1, 2
Min.
Max.
Units
-100
100
ppm
0.45
UIPP
-12
ber
Bit Error Rate
All
tHSIOUTVALIDPRE
RXD, SYDT Valid Time Before RECCLK Falling Edge
10
All
Note 3
tRCP/2 - 0.7
ns
tHSIOUTVALIDPOST
RXD, SYDT Valid Time
After RECCLK Falling Edge
All
Note 3
tRCP/2 - 0.7
ns
tDSIN
Bit 0 of SIN Delay to RXD Valid at RECCLK
Falling edge
All
1.5 tRCP +
4.5Bt + 2
1. Eye opening based on jitter frequency of 100KHz.
2. Lower frequency operation assumes maximum eye closure of 800ps.
3. Internal timing for reference only.
Lock-in Timing
CDRX_SS LOCK-IN (DE-SKEW) TIMING
SIN
CAL
MIN. 1200 SYNCPAT
DATA (SERIAL)
MIN. 1100 LS CYCLE
tHDSYNC
tSUSYNC
SYDT
RXD(0:7)
SYNCPAT
TRAINING SEQUENCE
DATA (PARALLEL)
SS MODE DATA TRANSFER
CDR_10B12B LOCK-IN TIMING
SIN
1024 SYNCPAT
DATA (SERIAL)
SYDT
RXD(0:9)
SYNCPAT
41
DATA (PARALLEL)
1.5 tRCP +
4.5Bt + 10
Bits
ns
Lattice Semiconductor
ispGDX2 Family Data Sheet
Lock-in Timing (Continued)
CDR_8B10B LOCK-IN TIMING
SIN
240 Idle Pattern(960 TRCP)
DATA (SERIAL)
SYDT
RXD(0:9)
Idle Pattern
DATA (PARALLEL)
SYDT Timing
SYDT TIMING FOR CDRX_10B12B
RECCLK
SYDT
RXD(0:9)
Data0 Data1 Data2 Data3 Data4
SYNC PATTERN
Parallel Data
SYDT TIMING FOR CDRX_8B10B
RECCLK
SYDT
RXD(0:9)
K28.5 D21.4 D21.5 D21.5 K28.5 D21.4 D21.5 D21.5
IDLE PATTERN
IDLE PATTERN
42
D0
D1
D2
Data
Lattice Semiconductor
ispGDX2 Family Data Sheet
Serializer Timing
8B/10B SERIALIZER DELAY TIMING
SYMBOL N
TXD
SYMBOL N+1
tCOSOUT
REFCLK
SOUT
b4 b5 b6 b7 b8 b9 b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 b0 b1 b2
SYMBOL N
SYMBOL N-1
SYMBOL N+1
10B/12B SERIALIZER DELAY TIMING
SYMBOL N
TXD
SYMBOL N+1
t COSOUT
REFCLK
SOUT
b4 b5 b6 b7 b8 b9 "0" "1" b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 "0" "1"
SYMBOL N
SYMBOL N-1
SS Mode SERIALIZER DELAY TIMING
SYMBOL N
TXD
SYMBOL N+1
t COSOUT
REFCLK
SS_CLKOUT
t CKOSOUT
SOUT
b4
b5
b6
b7
t SKTX
b0
b2
b1
b3
SYMBOL N
SYMBOL N-1
INTERNAL TIMING FOR sysHSI BLOCK
t PWREFCLK
REFCLK
tHSITXDDATAS
tHSITXDDATAH
TXD
43
b4
b5
b6
b7
b0
SYMBOL
N+1
Lattice Semiconductor
ispGDX2 Family Data Sheet
Deserializer Timing
8B/10B DESERIALIZER DELAY TIMING
SYMBOL N+1
SYMBOL N
SIN
SYMBOL N+2
b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 b0 b1 b2 b3 b4 b5
TDSIN
RECCLK
SYMBOL N
SYMBOL N-1
RXD
10B/12B DESERIALIZER DELAY TIMING
SYMBOL N
SIN
SYMBOL N+2
SYMBOL N+1
"1" b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 "0" "1" b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 "0" "1" b0 b1 b2 b3 b4
TTDSIN
RECCLK
RXD
SYMBOL N-1
SYMBOL N-2
SYMBOL N
CDRX_SS DESERIALIZER DELAY TIMING
SYMBOL N
SIN
b0
b1
b2
b3
b4
SYMBOL N+2
SYMBOL N+1
b5
b6
b7
b0
b1
b2
b3
b4
b5
b6
b7
TDSIN
RECCLK
RXD
SYMBOL N-2
SYMBOL N-1
INTERNAL TIMING FOR sysHSI BLOCK
RECCLK
t HSIOUTVALIDPRE
t HSIOUTVALIDPOST
SYDT, RXD
44
SYMBOL N
b0
b1
b2
b3
b4
Lattice Semiconductor
ispGDX2 Family Data Sheet
sysCLOCK PLL Timing
Over Recommended Operating Conditions
Min
Max
Units
tPWH
Symbol
Input clock, high time
Parameter
80% to 80%
Conditions
0.5
—
ns
tPWL
Input clock, low time
20% to 20%
0.5
—
ns
tR, tF
Input Clock, rise and fall time
20% to 80%
—
3.0
ns
tINSTB
Input clock stability, cycle to cycle (peak)
—
+/- 300
ps
fMDIVIN
M Divider input, frequency range
10
320
MHz
fMDIVOUT
M Divider output, frequency range
10
320
MHz
fNDIVIN
N Divider input, frequency range
10
320
MHz
fNDIVOUT
N Divider output, frequency range
10
320
MHz
fVDIVIN
V Divider input, frequency range
100
400
MHz
fVDIVOUT
V Divider output, frequency range
10
320
MHz
tOUTDUTY
Output clock, duty cycle
40
60
%
Clean reference :
10 MHz ≤ fMDIVOUT ≤ 40 MHz or
100 MHz ≤ fVDIVIN ≤ 160 MHz
—
+/- 600
ps
Clean reference1:
40 MHz ≤ fMDIVOUT ≤ 320 MHz and
160 MHz ≤ fVDIVIN ≤ 400 MHz
—
+/- 150
ps
Clean reference1:
10 MHz ≤ fMDIVOUT ≤ 40 MHz or
100 MHz ≤ fVDIVIN ≤ 160 MHz
—
+/- 600
ps
Clean reference1:
40 MHz ≤ fMDIVOUT ≤ 320 MHz and
160 MHz ≤ fVDIVIN ≤ 400 MHz
—
+/- 150
ps
1
Output clock, cycle to cycle jitter (peak)
tJIT(CC)
TJIT(PERIOD)
2
Output clock, period jitter (peak)
tCLK_OUT_DLY
Input clock to CLK_OUT delay
Internal feedback
—
3.4
ns
tPHASE
Input clock to external feedback delta
External feedback
—
500
ps
tLOCK
Time to acquire phase lock after input stable
—
25
us
tPLL_DELAY
Delay increment (Lead/Lag)
tRANGE
Total output delay range (lead/lag)
tPLL_RSTW
Minimum reset pulse width
Typical = +/- 250ps
+/- 120 +/- 550
+/- 0.84 +/- 3.85
1.8
—
ps
ns
ns
1. This condition assures that the output phase jitter will remain within specification. Jitter specification is based on optimized M, N and V settings determined by the ispLEVER software.
2. Accumulated jitter measured over 10,000 waveform samples
45
Lattice Semiconductor
ispGDX2 Family Data Sheet
Boundary Scan Timing Specifications
Over Recommended Operating Conditions
Parameter
Description
Min
Max
Units
tBTCP
TCK [BSCAN] clock pulse width
40
—
ns
tBTCPH
TCK [BSCAN] clock pulse width high
20
—
ns
tBTCPL
TCK [BSCAN] clock pulse width low
20
—
ns
tBTS
TCK [BSCAN] setup time
8
—
ns
tBTH
TCK [BSCAN] hold time
10
—
ns
tBTRF
TCK [BSCAN] rise/fall time
50
—
mV/ns
tBTCO
TAP controller falling edge of clock to valid output
—
10
ns
tBTCODIS
TAP controller falling edge of clock to valid disable
—
10
ns
tBTCOEN
TAP controller falling edge of clock to valid enable
—
10
ns
tBTCRS
BSCAN test capture register setup time
8
—
ns
tBTCRH
BSCAN test capture register hold time
10
—
ns
tBUTCO
BSCAN test update register, falling edge of clock to valid output
—
25
ns
tBTUODIS
BSCAN test update register, falling edge of clock to valid disable
—
25
ns
tBTUPOEN
BSCAN test update register, falling edge of clock to valid enable
—
25
ns
46
Lattice Semiconductor
ispGDX2 Family Data Sheet
Power Consumption
ICORE
IHSI
mA
mA
150
100
50
0
0
50
100
150
200
250
300
350
IPLL
90
80
70
60
50
40
30
20
10
0
100
IHSI_D
IPLL_D
80
mA
200
60
40
20
IHSI_A
IPLL_A
0
0
200
400
MHz
600
800
1000
1200
0
200
Mbps
600
400
MHz
Power Estimation Coefficients – Core and PLL
Device
ispGDX2-256
IDC:
KREF:
KIN:
KCORE:
KPLLD:
KPLLA:
VCC
IDC (mA)
KREF
KIN
KCORE
KPLLD
KPLLA
3.3
10.0
3.25
0.0139
0.292
0.157
0.024
2.5
10.0
3.13
0.0139
0.292
0.157
0.024
1.8
4.0
3.00
0.0213
0.239
0.179
0.024
Blank chip background current
Reference voltage circuit current per bank
I/O current per input per MHz
Core current per MHz with GRP fanout of 1
PLL logic current per MHz per PLL
PLL analog portion current per MHz per PLL
Power Estimation Coefficients – sysHSI
Device
ispGDX2-256
KRXD:
KRXSTBY:
KRXA:
KTXD:
KTXSTBY:
KTXA:
VCC
KRXD
KRXSTBY
KRXA
KTXD
KTXSTBY
KTXA
3.3
0.027
1.3
0.0023
0.011
2.4
0.0018
2.5
0.027
1.3
0.0023
0.011
2.4
0.0018
1.8
0.019
3.7
0.0040
0.011
1.2
0.0023
Receiver Logic current per Mbps
Receiver Logic standby current
Receiver Analog portion current per Mbps
Transmitter Logic current per Mbps
Transmitter Logic standby current
Transmitter Analog portion current per Mbps
47
Lattice Semiconductor
ispGDX2 Family Data Sheet
Power Consumption (Continued)
Power consumption in the ispGDX2 family is the sum of three components:
ICC-TOTAL = ICORE + IPLL + IHSI (ICC-TOTAL combines current supplied via VCC pins and VCCP pins)
ICORE = IDC + IREF + IIN
= Blank chip background current
+ KREF * Number of Banks with VREF active
+ (KIN * Number of inputs + KCORE) * Average Input Switching Frequency (MHz)
IPLL
= IPLL_D + IPLL_A
= [KPLLD * FVCO * Number of PLLs used] + [KPLLA * FVCO * Number of PLLs used]
= [(KPLLD + KPLLA) * FVCO] * Number of PLLs used
IHSI
= IRX + ITX
= [(KRXD + KRXA) * FRX + IRXSTBY] * Number of Receiver Channels
+ [(KTXD + KTXA) * FTX + ITXSTBY] * Number of Transmitter Channels
Where:
FVCO: sysClock PLL VCO Frequency in MHz
FRX: sysHSI Receiver Serial Data Rate
FTX: sysHSI Transmitter Serial Data Rate
IHSI can also be determined by calculating IHSI_D, the current supplied by the VCC pin, and IHSI_A, the current supplied by the VCCP0 and VCCP1.
IHSI
= IHSI_D + IHSI_A
= [(KRXD * FRX + IRXSTBY)* Number of Receiver Channels
+ (KTXD * FTX + ITXSTBY) * Number of Transmitter Channels]
+[(KRXA * FRX) * Number of Receiver Channels
+ (KTXA * FTX) * Number of Transmitter Channels]
The ICCP is supplied through VCCP0 and VCCP1 pins for PLL and sysHSI analog portion. The equation for ICCP can
be derived from the equations below.
ICCP
= IPLL_A + IHSI_A
= [(KPLLA * FVCO) * Number of PLLs used]
+ [(KRXA * FRX) * Number of Receiver Channels
+ (KTXA * FTX) * Number of Transmitter Channels]
Where:
IPLL_A: PLL Analog Portion Current
IHSI_A: HSI Analog Portion Current
Note: For further information about the use of these coefficients, refer to Technical Note TN1034, Power Estimation
in the ispGDX2 Family.
ICC-TOTAL estimates are based on typical conditions. These values are for estimates only. Since the value of ICCTOTAL is sensitive to operating conditions and the program in the device, the actual current should be verified.
48
Lattice Semiconductor
ispGDX2 Family Data Sheet
Switching Test Conditions
Figure 23 shows the output test load used for AC testing. Specific values for resistance, capacitance, voltage and
other test conditions are shown in Table 7.
Figure 23. Output Test Load, LVTTL and LVCMOS Standards (1.8V)
VCCO
R1
Device
Output
Test
Point
R2
CL*
*CL includes Test Fixture and Probe Capacitance.
Table 7. Test Fixture Required Components
Test Condition
Default LVCMOS 1.8 I/O (L -> H, H -> L)
LVCMOS I/O (L -> H, H -> L)
R1
R2
CL
106
106
35pF
—
—
35pF
Timing Ref.
VCCO
VCCO/2
1.8V
LVCMOS3.3 = 1.5V
LVCMOS3.3 = 3.0V
LVCMOS2.5 = VCCO/2
LVCMOS2.5 = 2.3V
LVCMOS1.8 = VCCO/2
LVCMOS1.8 = 1.65V
Default LVCMOS 1.8 I/O (Z -> H)
—
106
35pF
VCCO/2
1.65V
Default LVCMOS 1.8 I/O (Z -> L)
106
—
35pF
VCCO/2
1.65V
Default LVCMOS 1.8 I/O (H -> Z)
—
106
5pF
VOH - 0.15
1.65V
Default LVCMOS 1.8 I/O (L -> Z)
106
—
5pF
VOL + 0.15
1.65V
Note: Output test conditions for all other interfaces are determined by the respective standards.
49
Lattice Semiconductor
ispGDX2 Family Data Sheet
Signal Descriptions1
Signal Names
Description
General Purpose
BKx_IOy
Input/Output – General purpose I/O number y in I/O Bank X.
GCLK/CE0, GCLK/CE1, GCLK/CE2,
GCLK/CE3
Input – Global clock/clock enable inputs.
SEL0, SEL1, SEL22, SEL32
Input – Global MUX select inputs.
GOE0, GOE1, GOE22, GOE32
Input – Global output enable inputs.
RESETb
Input – Global RESET signal (active low).
NC
No connect.
GND
GND – Ground.
VCC
VCC – The power supply pins for core logic.
VCCJ
VCC – The power supply for the JTAG logic.
VCCOx
VCC – The power supply pins for I/O Bank X.
VREFx
Input – Defines the reference voltage for I/O Bank X.
Testing and Programming
TMS
Input – Test Mode Select input, used to control the 1149.1 state machine.
TCK
Input – Test Clock Input pin, used to clock the 1149.1 state machine.
TDI
Input – Test Data In pin, used to load data into device using 1149.1 state machine.
TDO
Output – Test Data Out pin used to shift data out of device using 1149.1.
TOE
Input – Test Output Enable pin. TOE tristates all I/O pins when driven low.
PLL Functions
PLL_FBKz
Input – Optional feedback input allows external feedback for PLL z.
PLL_RSTz
Input – Optional input resets the M divider in PLL z.
CLK_OUTz
Output – Optional clock output from PLL z (clock signal occupies the input path of
this I/O pad).
PLL_LOCKz
Output – Optional lock output from PLL z (lock signal occupies the input path of this
I/O pad).
GNDP0, GNDP1
GND – Ground for PLLs.
VCCP0, VCCP1
VCC – The power supply pins for PLLs.
FIFO Functions
FIFOy_DINw
Input – DATA IN Bit w of FIFO y.
FIFOy_DOUTw
Internal Signal – DATA OUT Bit w of FIFO y
FIFOy_FIFORSTb
Input – Reset input for FIFO y (active low).
FIFOy_FULL
Output – FULL flag for FIFO y.
FIFOy_EMPTY
Output – EMPTY flag for FIFO y.
FIFOy_STRDb
Output – Start read (STRDb) flag for FIFO y.
SERDES Functions
HSImA_SINP, HSImB_SINP
Input – Positive sense serial input for sysHSI BLOCK m channel A, B.
HSImA_SINN, HSImB_SINN
Input – Negative (minus) sense serial input for sysHSI BLOCK m channel A, B.
HSImA_SOUTP, HSImB_SOUTP
Output – Positive sense serial output for sysHSI BLOCK m channel A, B.
HSImA_SOUTN, HSImB_SOUTN
Output – Negative (minus) sense serial output for sysHSI BLOCK m channel A, B.
HSImA_SYDT, HSImB_ SYDT
Output – Symbol alignment detect for sysHSI BLOCK m channel A, B.
HSImA_RECCLK, HSImB_RECCLK
Internal Signal – Recovered clock for sysHSI BLOCK m channel A, B.
HSImA_CDRRSTb, HSImB_CDRRSTb
Input – Resets the CDR circuit of sysHSI BLOCK m channel A, B.
HSIm_CSLOCK
Output – LOCK output of the PLL associated with channel m.
50
Lattice Semiconductor
ispGDX2 Family Data Sheet
Signal Descriptions1 (Continued)
Signal Names
Description
HSImA_TXDw, HSImB_ TXDw
Internal Signal – Parallel data in bit w for sysHSI BLOCK m channel A, B.
HSImA_RXDw, HSImB_ RXDw
Internal Signal – Parallel data out bit w for sysHSI BLOCK m channel A, B.
Source Synchronous Functions
SS_SCLKIN0P, SS_SCLKIN1P
Input – Positive sense clock input for Source Synchronous group A, B.
SS_SCLKIN0N, SS_SCLKIN1N
Input – Negative (minus) sense clock input for Source Synchronous group A, B.
SS_CLKOUT0N, SS_CLKOUT1P
Output – Positive sense clock output for Source Synchronous group A, B.
SS_CLKOUT0N, SS_CLKOUT1N
Output – Negative (minus) sense clock output for Source Synchronous group A, B.
CAL
Input – Initiates source synchronous calibration sequence.
1. m, w, x, y and z are variables.
2. Not on ispGDX2-64
ispGDX2-64 Power Supply and NC Connections1
ispGDX2-64 (100-Ball fpBGA)2
Signal
VCC
A1, K10
VCCO0
J7
VCCO1
F10
VCCO2
E10
VCCO3
B7
VCCO4
B4
VCCO5
E1
VCCO6
F1
VCCO7
K4
VCCJ
K1
VCCP0
G6
GNDP0
G5
GND
A10, B9, C8, E6, E5, F6, F5, H3, J2
1. All grounds must be electrically connected at the board level.
2. Pin orientation A1 starts from the upper left corner of the top
side view with alphabetical order ascending vertically and
numerical order ascending horizontally.
51
Lattice Semiconductor
ispGDX2 Family Data Sheet
ispGDX2 Power Supply and NC Connections1
ispGDX2-128 (208-Ball fpBGA)3
Signal
ispGDX2-256 (484-Ball fpBGA)3
VCC
B15, C14, R15, B2, C3, P3, R2,
AA3, AA20, B3, B20, C2, C11, C12, C21, H9, H10, H11,
H12, H13, H14, J8, J15, K8, K15, L8, L15, L20, M3, M8,
M15, M20, N8, N15, P8, P15, R9, R10, R11, R12, R13,
R14, Y2, Y11, Y12, Y21
VCCO0
N11, T12
AA14, AB20, Y17
VCCO1
L13, M16
P21, U20, Y22
VCCO2
E16, F13
C22, E20, J21
VCCO3
A12, D11
A20, B14, C17
VCCO4
A5, D6
A3, B9, C6
VCCO5
E1, F4
C1, F3, J2
VCCO6
L4, M1
P2, U3, Y1
VCCO7
N6, T5
AA9, AB3, Y6
VCCJ
P14
L3
VCCP0
J1
K1
VCCP1
J16
N22
GNDP0
H1
J1
GNDP1
H16
K22
GND
A16, D13, H15, J15, N13, T16, A1, B9, B8, D4, H2, J2, A2, A11, A12, A21, A1, A22, AA1, AA2, AA11, AA12,
N4, R8, R9, T1, G7, G8, G9, G10, H7, H8, H9, H10, J7, AA21, AA22, AB1, AB2, AB11, AB12, AB21, AB22, B1,
J8, J9, J10, K7, K8, K9, K10
B2, B11, B12, B21, B22, C3, C20, D4, D19, E5, E18, F6,
F17, G7, G16, H8, H15, J9, J10, J11, J12, J13, J14, K9,
K10, K11, K12, K13, K14, L1, L2, L7, L9, L10, L11, L12,
L13, L14,L16, L21, L22, M1, M2, M7, M9, M10, M11,
M12,M13, M14, M16, M21, M22, N9, N10, N11, N12,
N13, N14, P9, P10, P11, P12, P13, P14, R8, R15, T7,
T16, U6, U17, V5, V18, W4, W19,Y3, Y20
NC2
A11, B16
D8, D11, E6, E7, E8, E9, E12, E13, E14, E15, E16, F7,
F16, G5, G6, G18, G19, H19, K4, K19, L19, M4, M19,
N4, P4, P19, R4, R18, T4, T5, T17, T18, U5, U7, U16, V7,
V8, V9, V10, V11, V12, V15, V16, V17, W14, Y18
1. All grounds must be electrically connected at the board level.
2. NC pins should not be connected to any active signals, VCC or GND.
3. Pin orientation A1 starts from the upper left corner of the top side view with alphabetical order ascending vertically and numerical order
ascending horizontally.
52
Lattice Semiconductor
ispGDX2 Family Data Sheet
ispGDX2-64 Logic Signal Connections
Signal Name
sysIO
LVDS
Bank Pair/Polarity
GDX
Block
MRB
SERDES Mode
I/O Pin1
SERDES Mode
I/O Cell2
FIFO Mode I/O
Cell/Pin3
100
fpBGA
GOE0
-
-
-
-
-
-
-
H6
BK0_IO0/PLL_LOCK0
0
0N
0A
0
-
-
FIFO0_FULL
J6
BK0_IO1
0
0P
0A
1
HSI0A_CDRRSTb
-
FIFO0_FIFORSTb
K6
GND
0
-
-
-
-
-
-
GND
BK0_IO2
0
1N
0A
2
HSI0A_SINN
HSI0A_RECCLK
-
G7
BK0_IO3
0
1P
0A
3
HSI0A_SINP
-
-
H7
GND
0
-
-
-
-
-
-
GND
BK0_IO4/PLL_RST0
0
2N
0A
4
-
HSI0A_RXD0/TXD0
FIFO0_DIN0/DOUT0
K7
BK0_IO5
0
2P
0A
5
-
HSI0A_RXD1/TXD1
FIFO0_DIN1/DOUT1
K8
BK0_IO6
0
3N
0A
6
-
HSI0A_RXD2/TXD2
FIFO0_DIN2/DOUT2
J8
BK0_IO7
0
3P
0A
7
Note 4
HSI0A_RXD3/TXD3
FIFO0_DIN3/DOUT3
K9
GND
0
-
-
-
-
-
-
GND
TCK
-
-
-
-
-
-
-
J10
RESETb
-
-
-
-
-
-
-
J9
H10
5
BK1_IO0/PLL_FBK0
1
4P
0A
8
HSI0A_SYDT
HSI0A_RXD4/TXD4
FIFO0_DIN4/DOUT4
BK1_IO1
1
4N
0A
9
-
HSI0A_RXD5/TXD5
FIFO0_DIN5/DOUT5
H9
BK1_IO2
1
5P
0A
10
-
HSI0A_RXD6/TXD6
FIFO0_DIN6/DOUT6
H8
BK1_IO3/VREF(0,1)
1
5N
0A
11
FIFO0_STRDb6
HSI0A_RXD7/TXD7
FIFO0_DIN7/DOUT7
G10
GND
1
-
-
-
-
-
-
GND
BK1_IO4
1
6P
0A
12
HSI0A_SOUTP
HSI0A_RXD8/TXD8
FIFO0_DIN8/DOUT8
G9
BK1_IO5
1
6N
0A
13
HSI0A_SOUTN
HSI0A_RXD9/TXD9
FIFO0_DIN9/DOUT9
G8
GND
1
-
-
-
GND
BK1_IO6
1
7P
0A
14
SS_CLKIN1P
HSI0A_SYDT5
-
F9
BK1_IO7
1
7N
0A
15
SS_CLKIN1N
-
FIFO0_ EMPTY
F8
GCLK/CE2
-
CLK2P
-
-
-
-
-
F7
GCLK/CE3
-
CLK2N
-
-
-
-
-
E7
BK2_IO0
2
8N
0B
0
SS_CLKOUT0N
-
FIFO1_FULL
E8
BK2_IO1
2
8P
0B
1
SS_CLKOUT0P
-
FIFO1_EMPTY
E9
GND
2
-
-
-
-
-
-
GND
BK2_IO2
2
9N
0B
2
HSI0B_SOUTN
HSI0BA_SYDT5
-
D8
BK2_IO3
2
9P
0B
3
HSI0B_SOUTP
HSI0B_RXD0/TXD0
FIFO1_DIN0
D9
GND
2
-
-
-
-
-
-
GND
BK2_IO4/VREF (2,3)
2
10N
0B
4
-
HSI0B_RXD1/TXD1
FIFO1_DIN1/DOUT1
D10
BK2_IO5
2
10P
0B
5
-
HSI0B_RXD2/TXD2
FIFO1_DIN2/DOUT2
C9
BK2_IO6
2
11N
0B
6
HSI0_CSLOCK
HSI0B_RXD3/TXD3
FIFO1_DIN3/DOUT3
C10
BK2_IO7
2
11P
0B
7
Note 4
HSI0B_RXD4/TXD4
FIFO1_DIN4/DOUT4
B10
BK3_IO0
3
12P
0B
8
-
HSI0B_RXD5/TXD5
FIFO1_DIN5/DOUT5
A9
BK3_IO1
3
12N
0B
9
HSI0B_SYDT5
HSI0B_RXD6/TXD6
FIFO1_DIN6/DOUT6
B8
BK3_IO2
3
13P
0B
10
HSI0B_RXD7/TXD7
FIFO1_DIN7/DOUT7
A8
BK3_IO3
3
13N
0B
11
-
HSI0B_RXD8/TXD8
FIFO1_DIN8/DOUT8
A7
GND
3
-
-
-
-
-
-
GND
BK3_IO4
3
14P
0B
12
HSI0B_SINP
HSI0B_RXD9/TXD9
FIFO1_DIN9/DOUT9
C7
BK3_IO5
3
14N
0B
13
HSI0B_SINN
HSI0B_RECCLK
-
D7
GND
3
-
-
-
-
-
-
GND
BK3_IO6
3
15P
0B
14
FIFO1_STRDb6
-
-
B6
BK3_IO7/CLK_OUT0
3
15N
0B
15
HSI0B_CDRRSTb
-
FIFO1_FIFORSTb
C6
53
Lattice Semiconductor
ispGDX2 Family Data Sheet
ispGDX2-64 Logic Signal Connections (Continued)
Signal Name
sysIO
LVDS
Bank Pair/Polarity
GDX
Block
MRB
SERDES Mode
I/O Pin1
SERDES Mode
I/O Cell2
FIFO Mode I/O
Cell/Pin3
100
fpBGA
D6
SEL0
-
-
-
-
-
-
-
SEL1
-
-
-
-
-
-
-
D5
BK4_IO0/CLK_OUT2
4
16N
1A7
0
HSI1A_CDRRSTb
-
FIFO2_FIFORSTb
C5
BK4_IO1
4
16P
1A7
1
FIFO2_STRDb6
-
-
B5
GND
GND
4
-
-
-
-
-
-
BK4_IO2
4
17N
1A7
2
HSI1A_SINN
HSI1A_RECCLK
-
D4
BK4_IO3
4
17P
1A7
3
HSI1A_SINP
HSI1A_RXD9/TXD9
FIFO2_DIN9/DOUT9
C4
GND
4
-
-
-
GND
7
BK4_IO4
4
18N
1A
4
-
HSI1A_RXD8/TXD8
FIFO2_DIN8/DOUT8
A6
BK4_IO5
4
18P
1A7
5
CAL
HSI1A_RXD7/TXD7
FIFO2_DIN7/DOUT7
A5
BK4_IO6
4
19N
1A7
6
HSI1A_SYDT5
HSI1A_RXD6/TXD6
FIFO2_DIN6/DOUT6
A4
BK4_IO7
4
19P
1A7
7
-
HSI1A_RXD5/TXD5
FIFO2_DIN5/DOUT5
A3
TMS
-
-
-
-
-
-
B3
TDI
-
-
-
-
-
-
-
A2
GND
-
-
-
-
-
-
-
GND
TDO
-
-
-
-
-
-
-
B1
TOE
-
-
-
-
-
-
-
B2
BK5_IO0
5
20P
1A7
8
Note 4
HSI1A_RXD4/TXD4
FIFO2_DIN4/DOUT4
C1
BK5_IO1
5
20N
1A7
9
HSI1_CSLOCK
HSI1A_RXD3/TXD3
FIFO2_DIN3/DOUT3
C2
BK5_IO2
5
21P
1A7
10
-
HSI1A_RXD2/TXD2
FIFO2_DIN2/DOUT2
C3
7
BK5_IO3/Vref(4,5)
5
21N
1A
11
-
HSI1A_RXD1/TXD1
FIFO2_DIN1/DOUT1
D1
GND
5
-
-
-
-
-
-
GND
BK5_IO4
5
22P
1A7
12
HSI1A_SOUTP
HSI1A_RXD0/TXD0
FIFO2_DIN0/DOUT0
D3
BK5_IO5
5
22N
1A7
13
HSI1A_SOUTN
HSI1A_SYDT5
-
D2
GND
5
-
-
-
-
-
GND
BK5_IO6
5
23P
1A7
14
SS_CLKIN1P
-
FIFO2_EMPTY
E2
BK5_IO7
5
23N
1A7
15
SS_CLKIN1N
-
FIFO2_FULL
E3
GCLK/CE0
-
CLK0P
-
-
-
-
-
E4
GCLK/CE1
-
CLK0N
-
-
-
-
-
F4
BK6_IO0
6
24N
1B
0
SS_CLKOUT1N
-
FIFO3_EMPTY
F3
BK6_IO1
6
24P
1B
1
SS_CLKOUT1P
HSI1B_SYDT5
-
F2
GND
6
-
-
-
-
-
-
GND
BK6_IO2
6
25N
1B
2
HSI1B_SOUTN
HSI1B_RXD9/TXD9
FIFO3_DIN9/DOUT9
G3
BK6_IO3
6
25P
1B
3
HSI1B_SOUTP
HSI1B_RXD8/TXD8
FIFO3_DIN8/DOUT8
G2
GND
6
-
-
-
-
-
-
GND
BK6_IO4/Vref(Bank6,7)
6
26N
1B
4
FIFO3_STRDb6
HSI1B_RXD7/TXD7
FIFO3_DIN7/DOUT7
G1
BK6_IO5
6
26P
1B
5
-
HSI1B_RXD6/TXD6
FIFO3_DIN6/DOUT6
H1
BK6_IO6
6
27N
1B
6
-
HSI1B_RXD5/TXD5
FIFO3_DIN5/DOUT5
H2
BK6_IO7/PLL_FBK2
6
27P
1B
7
HSI1B_SYDT5
HSI1B_RXD4/TXD4
FIFO3_DIN4/DOUT4
J1
BK7_IO0
7
28P
1B
8
Note 4
HSI1B_RXD3/TXD3
FIFO3_DIN3/DOUT3
J3
BK7_IO1
7
28N
1B
9
-
HSI1B_RXD2/TXD2
FIFO3_DIN2/DOUT2
K2
BK7_IO2
7
29P
1B
10
-
HSI1B_RXD1/TXD1
FIFO3_DIN1/DOUT1
J4
BK7_IO3/PLL_RST2
7
29N
1B
11
-
HSI1B_RXD0/TXD0
FIFO3_DIN0/DOUT0
K3
GND
7
-
-
-
-
-
-
GND
BK7_IO4
7
30P
1B
12
HSI1B_SINP
-
-
G4
BK7_IO5
7
30N
1B
13
HSI1B_SINN
HSI1B_RECCLK
-
H4
54
Lattice Semiconductor
ispGDX2 Family Data Sheet
ispGDX2-64 Logic Signal Connections (Continued)
Signal Name
sysIO
LVDS
Bank Pair/Polarity
GDX
Block
MRB
SERDES Mode
I/O Pin1
SERDES Mode
I/O Cell2
FIFO Mode I/O
Cell/Pin3
100
fpBGA
GND
7
-
-
-
-
-
-
GND
BK7_IO6
7
31P
1B
14
HSI1B_CDRRSTb
-
FIFO3_FIFORSTb
K5
BK7_IO7/PLL_LOCK2
7
31N
1B
15
-
-
FIFO3_FULL
J5
GOE1
7
-
-
-
-
-
-
H5
1. The signals in this column route to/from the assigned pins of the associated I/O cell.
2. The signals in this column use the I/O cell. If a receiver signal is present in the I/O cell, the associated pin is available for output only. When
transmit data (TXD) is present in the cell, the associated pin is available for input only.
3. The DOUT outputs are routed to GRP through the input register of the cell and the DIN inputs are routed direct from the associated pins in
FIFO only mode. In SERDES with FIFO mode, the FULL and EMPTY flags are routed to the associated pins through the output MUX and
the pins.
4. If the Source Synchronous Receiver is used in the HSI Block, this pin is unavailable for another use and must be left unconnected.
5. The SYDT signal has two routing options. If direct output through the dedicated pin is used, the I/O cell (the whole HSI Block) is not available for transmitter. The SYDT in the I/O Cell column is routed to the GRP through the input register of the cell and frees the I/O cell for
transmitter.
6. FIFO_STRDb flag output is used in SERDES with FIFO Mode only.
7. sysHSI Source Synchronous Receive Mode is not available for channel 1A.
55
Lattice Semiconductor
ispGDX2 Family Data Sheet
ispGDX2-128 Logic Signal Connections
Signal Name
sysIO
LVDS
Bank Pair/Polarity
GDX
Block MRB
SERDES Mode
I/O Pin1
SERDES Mode
I/O Cell2
FIFO Mode I/O
Cell/Pin3
208
fpBGA
TOE
-
-
-
-
-
-
P8
BK0_IO0
0
0N
0A
0
-
-
FIFO0A_FULL
P9
BK0_IO1
0
0P
0A
1
-
-
-
T10
BK0_IO2 / PLL_LOCK2 /
PLL_RST2
0
1N
0A
2
-
-
-
R10
BK0_IO3
0
GND
0
1P
BK0_IO4
0
BK0_IO5
0
BK0_IO6
0
3N
BK0_IO7
0
3P
BK0_IO8
0
4N
BK0_IO9 / PLL_FB2
0
4P
BK0_IO10
0
5N
BK0_IO11
0
5P
5
0A
3
-
HSI0A_SYDT
-
-
-
-
FIFO0A_ EMPTY
T11
-
GND
2N
0A
4
HSI0A_SINN
HSI0A_RXD0/TXD0
FIFO0A_DIN0/DOUT0
P10
2P
0A
5
HSI0A_SINP
HSI0A_RXD1/TXD1
FIFO0A_DIN1/DOUT1
N10
6
-
HSI0A_RXD2/TXD2
FIFO0A_DIN2/DOUT2
R11
0A
7
-
HSI0A_RXD3/TXD3
FIFO0A_DIN3/DOUT3
T13
0A
8
Note 4
HSI0A_RXD4/TXD4
FIFO0A_DIN4/DOUT4
P11
0A
9
-
HSI0A_RXD5/TXD5
FIFO0A_DIN5/DOUT5
R12
0A
10
HSI0A_SOUTN
HSI0A_RXD6/TXD6
FIFO0A_DIN6/DOUT6
P12
0A
11
HSI0A_SOUTP
HSI0A_RXD7/TXD7
FIFO0A_DIN7/DOUT7
N12
GND
GND
0
-
-
-
-
-
BK0_IO12
0
6N
0A
12
-
HSI0A_RXD8/TXD8
FIFO0A_DIN8/DOUT8
T14
BK0_IO13
0
6P
0A
13
HSI0A_SYDT5
HSI0A_RXD9/TXD9
FIFO0A_DIN9/DOUT9
R13
BK0_IO14
0
7N
0A
14
HSI0A_CDRRSTb
HSI0A_RECCLK
FIFO0A_FIFORSTb
T15
P13
7P
6
BK0_IO15 / VREF0
0
0A
15
FIFO0A_STRDb
-
-
GOE3
-
-
-
-
-
-
T9
TDO
-
-
-
-
-
-
R16
GND
1
-
-
-
-
-
GND
FIFO0B_FULL
N14
5
BK1_IO0 / VREF1
1
8P
0B
0
-
HSI0B_SYDT
BK1_IO1
1
8N
0B
1
-
HSI0B_RXD0/TXD0
FIFO0B_DIN0/DOUT0
P15
BK1_IO2
1
9P
0B
2
Note 4
HSI0B_RXD1/TXD1
FIFO0B_DIN1/DOUT1
N15
BK1_IO3
1
9N
0B
3
-
HSI0B_RXD2/TXD2
FIFO0B_DIN2/DOUT2
L14
BK1_IO4
1
10P
0B
4
HSI0B_SOUTP
HSI0B_RXD3/TXD3
FIFO0B_DIN3/DOUT3
M14
BK1_IO5
1
10N
0B
5
HSI0B_SOUTN
HSI0B_RXD4/TXD4
FIFO0B_DIN4/DOUT4
M13
BK1_IO6
1
11P
0B
6
HSI0_CSLOCK
HSI0B_RXD5/TXD5
FIFO0B_DIN5/DOUT5
M15
BK1_IO7
1
11N
0B
7
HSI0B_SYDT5
HSI0B_RXD6/TXD6
FIFO0B_DIN6/DOUT6
L15
BK1_IO8
1
12P
0B
8
-
HSI0B_RXD7/TXD7
FIFO0B_DIN7/DOUT7
P16
BK1_IO9
1
12N
0B
9
-
HSI0B_RXD8/TXD8
FIFO0B_DIN8/DOUT8
N16
BK1_IO10
1
13P
0B
10
HSI0B_SINP
HSI0B_RXD9/TXD9
FIFO0B_DIN9/DOUT9
K14
BK1_IO11
1
13N
0B
11
HSI0B_SINN
HSI0B_RECCLK
-
K13
GND
1
-
-
-
-
-
GND
BK1_IO12
1
14P
0B
12
FIFO0B_STRDb6
-
-
K15
BK1_IO13
1
14N
0B
13
HSI0B_CDRRSTb
-
FIFO0B_FIFORSTb
L16
BK1_IO14
1
15P
0B
14
SS_CLKIN1P
-
-
J14
BK1_IO15 / CLK_OUT2
1
15N
0B
15
SS_CLKIN1N
-
FIFO0B_ EMPTY
J13
GCLK/CE2
-
-
-
-
-
-
N8
SEL2
-
-
-
-
-
-
K16
SEL3
-
-
-
-
-
-
G16
GCLK/CE3
-
-
-
-
-
-
N9
BK2_IO0
2
16N
1A7
0
SS_CLKOUT1N
-
FIFO1A_FULL
H13
BK2_IO1
2
16P
1A7
1
SS_CLKOUT1P
-
-
H14
BK2_IO2
2
17N
1A7
2
-
HSI1A_SYDT5
-
G15
56
Lattice Semiconductor
ispGDX2 Family Data Sheet
ispGDX2-128 Logic Signal Connections (Continued)
Signal Name
sysIO
LVDS
Bank Pair/Polarity
GDX
Block MRB
SERDES Mode
I/O Pin1
SERDES Mode
I/O Cell2
FIFO Mode I/O
Cell/Pin3
208
fpBGA
1A7
3
-
HSI1A_RXD0/TXD0
FIFO1A_DIN0/DOUT0
F16
-
-
-
-
-
GND
18N
1A7
4
HSI1A_SINN
HSI1A_RXD1/TXD1
FIFO1A_DIN1/DOUT1
G13
2
18P
1A7
5
HSI1A_SINP
HSI1A_RXD2/TXD2
FIFO1A_DIN2/DOUT2
G14
BK2_IO6
2
19N
1A7
6
HSI1_CSLOCK
HSI1A_RXD3/TXD3
FIFO1A_DIN3/DOUT3
F14
BK2_IO7
2
19P
1A7
7
Note 4
HSI1A_RXD4/TXD4
FIFO1A_DIN4/DOUT4
F15
BK2_IO8
2
20N
1A7
8
CAL
HSI1A_RXD5/TXD5
FIFO1A_DIN5/DOUT5
D16
BK2_IO9
2
20P
1A7
9
-
HSI1A_RXD6/TXD6
FIFO1A_DIN6/DOUT6
E15
7
10
HSI1A_SOUTN
HSI1A_RXD7/TXD7
FIFO1A_DIN7/DOUT7
E13
11
HSI1A_SOUTP
HSI1A_RXD8/TXD8
FIFO1A_DIN8/DOUT8
E14
BK2_IO3
2
GND
2
BK2_IO4
2
BK2_IO5
17P
BK2_IO10
2
21N
1A
BK2_IO11
2
21P
1A7
-
-
-
-
-
GND
22N
1A7
12
HSI1A_SYDT5
HSI1A_RXD9/TXD9
FIFO1A_DIN9/DOUT9
C16
7
D15
GND
2
BK2_IO12
2
BK2_IO13
2
22P
1A
13
HSI1A_CDRRSTb
HSI1A_RECCLK
FIFO1A_FIFORSTb
BK2_IO14
2
23N
1A7
14
FIFO1A_STRDb6
-
-
C15
BK2_IO15 / VREF2
2
23P
1A7
15
-
-
FIFO1A_EMPTY
D14
TCK
-
-
-
-
-
-
R14
GOE2
-
BK3_IO0 / VREF3
3
24P
BK3_IO1
3
24N
BK3_IO2
3
25P
BK3_IO3
3
25N
1B
GND
3
BK3_IO4
3
26P
1B
BK3_IO5
3
26N
1B
BK3_IO6
3
27P
1B
BK3_IO7
3
BK3_IO8
BK3_IO9
BK3_IO10
BK3_IO11
GND
3
BK3_IO12
3
30P
BK3_IO13
3
30N
BK3_IO14
3
31P
BK3_IO15
3
31N
RESET
-
BK4_IO0
4
BK4_IO1 / PLL_LOCK0 /
PLL_RST0
-
-
-
-
-
A9
1B
0
-
HSI1B_RXD0/TXD0
FIFO1B_DIN0/DOUT0
C13
1B
1
Note 4
HSI1B_RXD1/TXD1
FIFO1B_DIN1/DOUT1
B14
1B
2
-
HSI1B_RXD2/TXD2
FIFO1B_DIN2/DOUT2
A15
3
-
HSI1B_RXD3/TXD3
FIFO1B_DIN3/DOUT3
B13
-
-
-
-
GND
4
HSI1B_SOUTP
HSI1B_RXD4/TXD4
FIFO1B_DIN4/DOUT4
D12
5
HSI1B_SOUTN
HSI1B_RXD5/TXD5
FIFO1B_DIN5/DOUT5
C12
6
-
HSI1B_RXD6/TXD6
FIFO1B_DIN6/DOUT6
A14
-
HSI1B_RXD7/TXD7
FIFO1B_DIN7/DOUT7
/ FIFO1B_STRDb
A13
27N
1B
7
3
28P
1B
8
-
HSI1B_RXD8/TXD8
FIFO1B_DIN8/DOUT8
B12
3
28N
1B
9
HSI1B_SYDT5
HSI1B_RXD9/TXD9
FIFO1B_DIN9/DOUT9
C11
3
29P
1B
10
HSI1B_SINP
HSI1B_RECCLK
-
D10
3
29N
1B
11
HSI1B_SINN
-
-
C10
-
-
-
-
-
GND
1B
12
-
HSI1B_SYDT5
FIFO1B_FULL
B11
1B
13
HSI1B_CDRRSTb
-
FIFO1B_FIFORSTb
B10
1B
14
-
-
-
A10
1B
15
-
-
FIFO1B_ EMPTY
C9
-
-
-
-
-
A7
32N
2A
0
-
-
FIFO2A_EMPTY
C8
4
32P
2A
1
-
-
-
B7
BK4_IO2
4
33N
2A
2
HSI2A_CDRRSTb
-
FIFO2A_FIFORSTb
A6
BK4_IO3
4
33P
2A
3
-
HSI2A_SYDT5
FIFO2A_FULL
B6
GND
GND
4
-
-
-
BK4_IO4
4
34N
2A
4
HSI2A_SINN
-
-
C7
BK4_IO5
4
34P
2A
5
HSI2A_SINP
HSI2A_RECCLK
-
D7
BK4_IO6
4
35N
2A
6
HSI2A_SYDT5
HSI2A_RXD9/TXD9
FIFO2A_DIN9/DOUT9
C6
BK4_IO7
4
35P
2A
7
-
HSI2A_RXD8/TXD8
FIFO2A_DIN8/DOUT8
B5
57
Lattice Semiconductor
ispGDX2 Family Data Sheet
ispGDX2-128 Logic Signal Connections (Continued)
Signal Name
sysIO
LVDS
Bank Pair/Polarity
GDX
Block MRB
SERDES Mode
I/O Pin1
SERDES Mode
I/O Cell2
FIFO Mode I/O
Cell/Pin3
208
fpBGA
BK4_IO8
4
36N
2A
8
FIFO2A_STRDb6
HSI2A_RXD7/TXD7
FIFO2A_DIN7/DOUT7
A4
BK4_IO9 / PLL_FB0
4
36P
2A
9
-
HSI2A_RXD6/TXD6
FIFO2A_DIN6/DOUT6
A3
BK4_IO10
4
37N
2A
10
HSI2A_SOUTN
HSI2A_RXD5/TXD5
FIFO2A_DIN5/DOUT5
C5
BK4_IO11
4
37P
2A
11
HSI2A_SOUTP
HSI2A_RXD4/TXD4
FIFO2A_DIN4/DOUT4
D5
GND
GND
4
-
-
-
-
BK4_IO12
4
38N
2A
12
-
HSI2A_RXD3/TXD3
FIFO2A_DIN3/DOUT3
B4
BK4_IO13
4
38P
2A
13
-
HSI2A_RXD2/TXD2
FIFO2A_DIN2/DOUT2
A2
BK4_IO14
4
39N
2A
14
Note 4
HSI2A_RXD1/TXD1
FIFO2A_DIN1/DOUT1
B3
BK4_IO15 / VREF4
4
39P
2A
15
-
HSI2A_RXD0/TXD0
FIFO2A_DIN0/DOUT0
C4
GOE1
-
-
-
-
-
A8
TMS
-
-
-
-
-
-
R1
GND
5
-
-
-
-
-
GND
BK5_IO0 / VREF5
5
40P
2B
0
-
-
FIFO2B_EMPTY
D3
BK5_IO1
5
40N
2B
1
FIFO2B_STRDb6
-
-
C2
BK5_IO2
5
41P
2B
2
HSI2B_CDRRSTb
HSI2B_RECCLK
FIFO2B_FIFORSTb
D2
BK5_IO3
5
41N
2B
3
HSI2B_SYDT5
HSI2B_RXD9/TXD9
FIFO2B_DIN9/DOUT9
B1
BK5_IO4
5
42P
2B
4
HSI2B_SOUTP
HSI2B_RXD8/TXD8
FIFO2B_DIN8/DOUT8
E3
BK5_IO5
5
42N
2B
5
HSI2B_SOUTN
HSI2B_RXD7/TXD7
FIFO2B_DIN7/DOUT7
E4
BK5_IO6
5
43P
2B
6
-
HSI2B_RXD6/TXD6
FIFO2B_DIN6/DOUT6
F3
BK5_IO7
5
43N
2B
7
-
HSI2B_RXD5/TXD5
FIFO2B_DIN5/DOUT5
E2
BK5_IO8
5
44P
2B
8
Note 4
HSI2B_RXD4/TXD4
FIFO2B_DIN4/DOUT4
F2
BK5_IO9
5
44N
2B
9
HSI2_CSLOCK
HSI2B_RXD3/TXD3
FIFO2B_DIN3/DOUT3
C1
BK5_IO10
5
45P
2B
10
HSI2B_SINP
HSI2B_RXD2/TXD2
FIFO2B_DIN2/DOUT2
G3
BK5_IO11
5
45N
2B
11
HSI2B_SINN
HSI2B_RXD1/TXD1
FIFO2B_DIN1/DOUT1
G4
GND
GND
5
-
-
-
-
-
BK5_IO12
5
46P
2B
12
-
HSI2B_RXD0/TXD0
FIFO2B_DIN0/DOUT0
D1
BK5_IO13
5
46N
2B
13
-
HSI2B_SYDT5
-
G2
BK5_IO14
5
47P
2B
14
SS_CLKIN0P
-
-
H4
BK5_IO15 / CLK_OUT0
5
47N
2B
15
SS_CLKIN0N
-
FIFO2B_FULL
H3
GCLK/CE0
-
CLK0P
-
-
-
-
-
D9
SEL0
-
-
-
-
-
-
F1
SEL1
-
-
-
-
-
-
G1
GCLK/CE1
-
CLK0N
-
-
-
-
-
D8
BK6_IO0
6
48N
3A
0
SS_CLKOUT0N
-
FIFO3A_EMPTY
J4
BK6_IO1
6
48P
3A
1
SS_CLKOUT0P
-
-
J3
BK6_IO2
6
49N
3A
2
HSI3A_CDRRSTb
-
FIFO3A_FIFORSTb
K1
BK6_IO3
6
49P
3A
3
FIFO3A_STRDb6
-
-
K2
GND
6
-
-
-
-
-
GND
BK6_IO4
6
50N
3A
4
HSI3A_SINN
HSI3A_RECCLK
-
K4
BK6_IO5
6
50P
3A
5
HSI3A_SINP
HSI3A_RXD9/TXD9
FIFO3A_DIN9/DOUT9
K3
BK6_IO6
6
51N
3A
6
-
HSI3A_RXD8/TXD8
FIFO3A_DIN8/DOUT8
L1
BK6_IO7
6
51P
3A
7
-
HSI3A_RXD7/TXD7
FIFO3A_DIN7/DOUT7
L2
BK6_IO8
6
52N
3A
8
HSI3A_SYDT5
HSI3A_RXD6/TXD6
FIFO3A_DIN6/DOUT6
N1
BK6_IO9
6
52P
3A
9
HSI3_CSLOCK
HSI3A_RXD5/TXD5
FIFO3A_DIN5/DOUT5
M2
BK6_IO10
6
53N
3A
10
HSI3A_SOUTN
HSI3A_RXD4/TXD4
FIFO3A_DIN4/DOUT4
M4
BK6_IO11
6
53P
3A
11
HSI3A_SOUTP
HSI3A_RXD3/TXD3
FIFO3A_DIN3/DOUT3
M3
58
Lattice Semiconductor
ispGDX2 Family Data Sheet
ispGDX2-128 Logic Signal Connections (Continued)
Signal Name
sysIO
LVDS
Bank Pair/Polarity
GDX
Block MRB
SERDES Mode
I/O Pin1
SERDES Mode
I/O Cell2
FIFO Mode I/O
Cell/Pin3
208
fpBGA
GND
GND
6
-
-
-
-
-
BK6_IO12
6
54N
3A
12
-
HSI3A_RXD2/TXD2
FIFO3A_DIN2/DOUT2
L3
BK6_IO13
6
54P
3A
13
Note 4
HSI3A_RXD1/TXD1
FIFO3A_DIN1/DOUT1
N2
BK6_IO14
6
55N
3A
14
-
HSI3A_RXD0/TXD0
FIFO3A_DIN0/DOUT0
P1
55P
5
BK6_IO15 / VREF6
6
3A
15
-
HSI3A_SYDT
FIFO3A_ FULL
P2
TDI
-
-
-
-
-
-
N3
GOE0
-
-
-
-
-
-
T8
GND
7
-
-
-
-
-
GND
BK7_IO0 / VREF7
7
56P
3B
0
FIFO3B_STRDb6
-
-
T2
BK7_IO1
7
56N
3B
1
HSI3B_CDRRSTb
HSI3B_RECCLK
FIFO3B_FIFORSTb
R3
BK7_IO2
7
57P
3B
2
HSI3B_SYDT5
HSI3B_RXD9/TXD9
FIFO3B_DIN9/DOUT9
P4
BK7_IO3
7
57N
3B
3
-
HSI3B_RXD8/TXD8
FIFO3B_DIN8/DOUT8
T3
BK7_IO4
7
58P
3B
4
HSI3B_SOUTP
HSI3B_RXD7/TXD7
FIFO3B_DIN7/DOUT7
N5
BK7_IO5
7
58N
3B
5
HSI3B_SOUTN
HSI3B_RXD6/TXD6
FIFO3B_DIN6/DOUT6
P5
BK7_IO6
7
59P
3B
6
-
HSI3B_RXD5/TXD5
FIFO3B_DIN5/DOUT5
R4
BK7_IO7
7
59N
3B
7
Note 4
HSI3B_RXD4/TXD4
FIFO3B_DIN4/DOUT4
T4
BK7_IO8
7
60P
3B
8
-
HSI3B_RXD3/TXD3
FIFO3B_DIN3/DOUT3
R5
BK7_IO9
7
60N
3B
9
-
HSI3B_RXD2/TXD2
FIFO3B_DIN2/DOUT2
P6
BK7_IO10
7
61P
3B
10
HSI3B_SINP
HSI3B_RXD1/TXD1
FIFO3B_DIN1/DOUT1
N7
BK7_IO11
7
61N
3B
11
HSI3B_SINN
HSI3B_RXD0/TXD0
FIFO3B_DIN0/DOUT0
P7
GND
7
-
-
-
-
-
GND
BK7_IO12
7
62P
3B
12
-
HSI3B_SYDT5
FIFO3B_ EMPTY
R6
BK7_IO13
7
62N
3B
13
-
-
-
T6
BK7_IO14
7
63P
3B
14
-
-
-
R7
BK7_IO15
7
63N
3B
15
-
-
FIFO3B_FULL
T7
1. The signals in this column route to/from the assigned pins of the associated I/O cell.
2. The signals in this column use the I/O cell. If a receiver signal is present in the I/O cell, the associated pin is available for output only. When
transmit data (TXD) is present in the cell, the associated pin is available for input only.
3. The DOUT outputs are routed to GRP through the input register of the cell and the DIN inputs are routed direct from the associated pins in
FIFO only mode. In SERDES with FIFO mode, the FULL and EMPTY flags are routed to the associated pins through the output MUX and
the pins.
4. If the Source Synchronous Receiver is used in the HSI Block, this pin is unavailable for another use and must be left unconnected.
5. The SYDT signal has two routing options. If direct output through the dedicated pin is used, the I/O cell (the whole HSI Block) is not available for transmitter. The SYDT in the I/O Cell column is routed to the GRP through the input register of the cell and frees the I/O cell for
transmitter.
6. FIFO_STRDb flag output is used in SERDES with FIFO Mode only.
7. sysHSI Source Synchronous Receive Mode is not available for channel 1A.
59
Lattice Semiconductor
ispGDX2 Family Data Sheet
ispGDX2-256 Logic Signal Connections
Signal
Name
sysIO
Bank
LVDS
GDX
Pair/Polarity Block MRB
SERDES Mode
I/O Pin1
SERDES Mode
I/O Cell2
FIFO Mode I/O
Cell/Pin3
484
fpBGA
BK0_IO0
0
0N
0A
0
-
-
FIFO0A_FULL
AB13
BK0_IO1
0
0P
0A
1
-
-
-
AA13
BK0_IO2/
PLL_LOCK2
0
1N
0A
2
-
-
-
V13
BK0_IO3
0
1P
0A
3
-
-
FIFO0A_ EMPTY
V14
GND
0
-
-
-
-
SYDT_HSI0A5
-
GND
BK0_IO4
0
2N
0A
4
HSI0A_SINN
HSI0A_RXD0/TXD0
FIFO0A_DIN0/DOUT0
U12
BK0_IO5
0
2P
0A
5
HSI0A_SINP
HSI0A_RXD1/TXD1
FIFO0A_DIN1/DOUT1
U13
BK0_IO6
0
3N
6
-
HSI0A_RXD2/TXD2
FIFO0A_DIN2/DOUT2
W12
BK0_IO7
0
3P
0A
7
-
HSI0A_RXD3/TXD3
FIFO0A_DIN3/DOUT3
Y13
BK0_IO8
0
4N
0A
8
Note 4
HSI0A_RXD4/TXD4
FIFO0A_DIN4/DOUT4
W13
BK0_IO9/
PLL_FB2
0
4P
0A
9
-
HSI0A_RXD5/TXD5
FIFO0A_DIN5/DOUT5
Y14
BK0_IO10
0
5N
0A
10
HSI0A_SOUTN
HSI0A_RXD6/TXD6
FIFO0A_DIN6/DOUT6
T12
BK0_IO11
0
5P
0A
11
HSI0A_SOUTP
HSI0A_RXD7/TXD7
FIFO0A_DIN7/DOUT7
T13
GND
0
-
-
-
-
-
-
GND
BK0_IO12
0
6N
0A
12
-
HSI0A_RXD8/TXD8
FIFO0A_DIN8/DOUT8
AB14
BK0_IO13
0
6P
0A
13
HSI0A_SYDT5
HSI0A_RXD9/TXD9
FIFO0A_DIN9/DOUT9
AB15
BK0_IO14
0
7N
0A
14
HSI0A_CDRRSTb
HSI0A_RECCLK
FIFO0A_FIFORSTb
Y15
BK0_IO15
0
7P
0A
15
FIFO0A_STRDb6
-
-
W15
BK0_IO16
0
8N
1A
0
-
-
FIFO1A_FULL
AA15
BK0_IO17/
PLL_RST2
0
8P
1A
1
-
-
-
AA16
5
BK0_IO18
0
9N
1A
2
-
HSI1A_SYDT
BK0_IO19
0
9P
1A
3
-
HSI1A_RXD0/TXD0
-
Y16
FIFO1A_DIN0/DOUT0
W16
GND
0
-
-
-
-
-
-
GND
BK0_IO20
0
10N
1A
4
HSI1A_SOUTN
HSI1A_RXD1/TXD1
FIFO1A_DIN1/DOUT1
U14
BK0_IO21/
VREF0
0
10P
1A
5
HSI1A_SOUTP
HSI1A_RXD2/TXD2
FIFO1A_DIN2/DOUT2
U15
BK0_IO22
0
11N
1A
6
-
HSI1A_RXD3/TXD3
FIFO1A_DIN3/DOUT3
AB16
BK0_IO23
0
11P
1A
7
Note 4
HSI1A_RXD4/TXD4
FIFO1A_DIN4/DOUT4
AB17
BK0_IO24
0
12N
1A
8
-
HSI1A_RXD5/TXD5
FIFO1A_DIN5/DOUT5
AA17
BK0_IO25
0
12P
1A
9
-
HSI1A_RXD6/TXD6
FIFO1A_DIN6/DOUT6
W17
BK0_IO26
0
13N
1A
10
HSI1A_SINN
HSI1A_RXD7/TXD7
FIFO1A_DIN7/DOUT7
T14
BK0_IO27
0
13P
1A
11
HSI1A_SINP
HSI1A_RXD8/TXD8
FIFO1A_DIN8/DOUT8
T15
BK0_IO28
0
14N
1A
12
HSI1A_SYDT5
HSI1A_RXD9/TXD9
FIFO1A_DIN9/DOUT9
AA18
BK0_IO29
0
14P
1A
13
HSI1A_CDRRSTb5
HSI1A_RECCLK
FIFO1A_FIFORSTb
AB18
BK0_IO30
0
15N
1A
14
FIFO1A_STRDb6
-
-
W18
BK0_IO31
0
15P
1A
15
-
-
FIFO1A_EMPTY
Y19
GND
0
-
-
-
-
-
-
GND
GOE3
-
-
-
-
-
-
-
AA19
TDO
-
-
-
-
-
-
-
AB19
GND
1
-
-
-
-
-
-
GND
BK1_IO0
1
16P
0B
0
-
-
FIFO0B_ FULL
W21
BK1_IO1
1
16N
0B
1
-
HSI0B_SYDT5
-
W20
BK1_IO2
1
17P
0B
2
-
HSI0B_RXD0/TXD0
FIFO0B_DIN0/DOUT0
V22
BK1_IO3
1
17N
0B
3
Note 4
HSI0B_RXD1/TXD1
FIFO0B_DIN1/DOUT1
W22
BK1_IO4
1
18P
0B
4
HSI0B_SINP
HSI0B_RXD2/TXD2
FIFO0B_DIN2/DOUT2
P16
60
Lattice Semiconductor
ispGDX2 Family Data Sheet
ispGDX2-256 Logic Signal Connections (Continued)
Signal
Name
sysIO
Bank
LVDS
GDX
Pair/Polarity Block MRB
SERDES Mode
I/O Pin1
SERDES Mode
I/O Cell2
FIFO Mode I/O
Cell/Pin3
484
fpBGA
BK1_IO5
1
18N
0B
5
HSI0B_SINN
HSI0B_RXD3/TXD3
FIFO0B_DIN3/DOUT3
P17
BK1_IO6
1
19P
0B
6
HSI0_CSLOCK
HSI0B_RXD4/TXD4
FIFO0B_DIN4/DOUT4
U18
BK1_IO7
1
19N
0B
7
-
HSI0B_RXD5/TXD5
FIFO0B_DIN5/DOUT5
V19
BK1_IO8
1
20P
0B
8
-
HSI0B_RXD6/TXD6
FIFO0B_DIN6/DOUT6
V20
HSI0B_RXD7/TXD7
FIFO0B_DIN7/DOUT7
V21
R16
5
BK1_IO9
1
20N
0B
9
HSI0B_SYDT
BK1_IO10/
VREF1
1
21P
0B
10
HSI0B_SOUTP
HSI0B_RXD8/TXD8
FIFO0B_DIN8/DOUT8
BK1_IO11
1
21N
0B
11
HSI0B_SOUTN
HSI0B_RXD9/TXD9
FIFO0B_DIN9/DOUT9
R17
GND
1
-
-
-
-
-
-
GND
BK1_IO12
1
22P
0B
12
HSI0B_CDRRSTb
HSI0B_RECCLK
FIFO0B_FIFORSTb
U19
BK1_IO13
1
22N
0B
13
FIFO0B_STRDb6
-
-
T19
BK1_IO14
1
23P
0B
14
-
-
-
U21
BK1_IO15
1
23N
0B
15
-
-
FIFO0B_EMPTY
U22
FIFO1B_FULL
R19
5
BK1_IO16
1
24P
1B
0
-
HSI1B_SYDT
BK1_IO17
1
24N
1B
1
-
HSI1B_RXD0/TXD0
FIFO1B_DIN0/DOUT0
T20
BK1_IO18
1
25P
1B
2
Note 4
HSI1B_RXD1/TXD1
FIFO1B_DIN1/DOUT1
T21
BK1_IO19
1
25N
1B
3
-
HSI1B_RXD2/TXD2
FIFO1B_DIN2/DOUT2
T22
GND
1
-
-
-
-
-
-
GND
BK1_IO20
1
26P
1B
4
HSI1B_SOUTP
HSI1B_RXD3/TXD3
FIFO1B_DIN3/DOUT3
N16
BK1_IO21
1
26N
1B
5
HSI1B_SOUTN
HSI1B_RXD4/TXD4
FIFO1B_DIN4/DOUT4
N17
BK1_IO22
1
27P
1B
6
HSI1_CSLOCK
HSI1B_RXD5/TXD5
FIFO1B_DIN5/DOUT5
R20
5
BK1_IO23
1
27N
1B
7
HSI1B_SYDT
BK1_IO24
1
28P
1B
8
-
HSI1B_RXD6/TXD6
FIFO1B_DIN6/DOUT6
R21
HSI1B_RXD7/TXD7
FIFO1B_DIN7/DOUT7
N19
BK1_IO25
1
28N
1B
9
-
HSI1B_RXD8/TXD8
FIFO1B_DIN8/DOUT8
P20
BK1_IO26
1
29P
1B
10
HSI1B_SINP
HSI1B_RXD9/TXD9
FIFO1B_DIN9/DOUT9
P18
BK1_IO27
1
29N
1B
11
HSI1B_SINN
HSI1B_RECCLK
-
N18
GND
1
-
-
-
-
-
GND
BK1_IO28
1
30P
1B
12
FIFO1B_STRDb6
-
-
R22
BK1_IO29
1
30N
1B
13
HSI1B_CDRRSTb
-
FIFO1B_FIFORSTb
P22
BK1_IO30
1
31P
1B
14
SS_CLKIN1P
-
-
M18
BK1_IO31/
CLK_OUT2
1
31N
1B
15
SS_CLKIN1N
-
FIFO1B_EMPTY
M17
GCLK/CE2
-
CLK2P
-
-
-
-
-
N20
SEL2
-
-
-
-
-
-
-
N21
SEL3
-
-
-
-
-
-
-
K21
GCLK/CE3
-
CLK2N
-
-
-
-
-
K20
BK2_IO0/
CLK_OUT3
2
32N
3A7
0
SS_CLKOUT1N
-
FIFO3A_FULL
K17
BK2_IO1
2
32P
3A7
1
SS_CLKOUT1P
-
-
K18
7
2
-
HSI3A_SYDT
3
-
HSI3A_RXD0/TXD0
BK2_IO2
2
33N
3A
BK2_IO3
2
33P
3A7
-
-
-
34N
3A7
4
HSI3A_SINN
7
GND
2
BK2_IO4
2
5
-
L17
FIFO3A_DIN0/DOUT0
L18
-
-
GND
HSI3A_RXD1/TXD1
FIFO3A_DIN1/DOUT1
J17
BK2_IO5
2
34P
3A
5
HSI3A_SINP
HSI3A_RXD2/TXD2
FIFO3A_DIN2/DOUT2
J18
BK2_IO6
2
35N
3A7
6
HSI3_CSLOCK
HSI3A_RXD3/TXD3
FIFO3A_DIN3/DOUT3
J22
BK2_IO7
2
35P
3A7
7
Note 4
HSI3A_RXD4/TXD4
FIFO3A_DIN4/DOUT4
J20
BK2_IO8
2
36N
3A7
8
CAL
HSI3A_RXD5/TXD5
FIFO3A_DIN5/DOUT5
H22
BK2_IO9
2
36P
3A7
9
-
HSI3A_RXD6/TXD6
FIFO3A_DIN6/DOUT6
H21
61
Lattice Semiconductor
ispGDX2 Family Data Sheet
ispGDX2-256 Logic Signal Connections (Continued)
Signal
Name
sysIO
Bank
LVDS
GDX
Pair/Polarity Block MRB
SERDES Mode
I/O Pin1
SERDES Mode
I/O Cell2
FIFO Mode I/O
Cell/Pin3
484
fpBGA
K16
BK2_IO10
2
37N
3A7
10
HSI3A_SOUTN
HSI3A_RXD7/TXD7
FIFO3A_DIN7/DOUT7
BK2_IO11
2
37P
3A7
11
HSI3A_SOUTP
HSI3A_RXD8/TXD8
FIFO3A_DIN8/DOUT8
J16
GND
2
-
-
-
-
-
-
GND
BK2_IO12
2
38N
3A7
12
HSI3A_SYDT5
HSI3A_RXD9/TXD9
FIFO3A_DIN9/DOUT9
J19
7
BK2_IO13
2
38P
3A
13
HSI3A_CDRRSTb
HSI3A_RECCLK
FIFO3A_FIFORSTb
H20
BK2_IO14
2
39N
3A7
14
FIFO3A_STRDb6
-
-
G21
BK2_IO15
2
39P
3A7
15
-
-
FIFO3A_EMPTY
G20
BK2_IO16
2
40N
2A
0
-
-
FIFO2A_FULL
G22
BK2_IO17
2
40P
2A
1
-
HSI2A_SYDT5
-
F22
BK2_IO18
2
41N
2A
2
-
HSI2A_RXD0/TXD0
FIFO2A_DIN0/DOUT0
F20
BK2_IO19
2
41P
2A
3
Note 4
HSI2A_RXD1/TXD1
FIFO2A_DIN1/DOUT1
F21
GND
2
-
-
-
-
-
-
GND
BK2_IO20/
PLL_FB3
2
42N
2A
4
HSI2A_SOUTN
HSI2A_RXD2/TXD2
FIFO2A_DIN2/DOUT2
H18
BK2_IO21/
VREF2
2
42P
2A
5
HSI2A_SOUTP
HSI2A_RXD3/TXD3
FIFO2A_DIN3/DOUT3
G17
BK2_IO22
2
43N
2A
6
HSI2_CSLOCK
HSI2A_RXD4/TXD4
FIFO2A_DIN4/DOUT4
E21
BK2_IO23
2
43P
2A
7
-
HSI2A_RXD5/TXD5
FIFO2A_DIN5/DOUT5
F19
BK2_IO24
2
44N
2A
8
-
HSI2A_RXD6/TXD6
FIFO2A_DIN6/DOUT6
E22
BK2_IO25
2
44P
2A
9
HSI2A_SYDT5
HSI2A_RXD7/TXD7
FIFO2A_DIN7/DOUT7
D22
BK2_IO26
2
45N
2A
10
HSI2A_SINN
HSI2A_RXD8/TXD8
FIFO2A_DIN8/DOUT8
H17
BK2_IO27
2
45P
2A
11
HSI2A_SINP
HSI2A_RXD9/TXD9
FIFO2A_DIN9/DOUT9
H16
BK2_IO28
2
46N
2A
12
HSI2A_CDRRSTb
HSI2A_RECCLK
FIFO2A_FIFORSTb
E19
BK2_IO29
2
46P
2A
13
FIFO2A_STRDb6
-
-
F18
BK2_IO30
2
47N
2A
14
-
-
-
D20
BK2_IO31
2
47P
2A
15
-
-
FIFO2A_EMPTY
D21
GND
2
-
-
-
-
-
-
GND
TCK
-
-
-
-
-
-
-
B19
GOE2
-
-
-
-
-
-
-
C19
BK3_IO0
3
48P
3B
0
-
HSI3B_SYDT5
FIFO3B_FULL
E17
BK3_IO1
3
48N
3B
1
-
HSI3B_RXD0/TXD0
FIFO3B_DIN0/DOUT0
D18
BK3_IO2
3
49P
3B
2
Note 4
HSI3B_RXD1/TXD1
FIFO3B_DIN1/DOUT1
A19
BK3_IO3
3
49N
3B
3
-
HSI3B_RXD2/TXD2
FIFO3B_DIN2/DOUT2
A18
GND
3
-
-
-
-
-
-
GND
BK3_IO4
3
50P
3B
4
HSI3B_SINP
HSI3B_RXD3/TXD3
FIFO3B_DIN3/DOUT3
G15
BK3_IO5
3
50N
3B
5
HSI3B_SINN
HSI3B_RXD4/TXD4
FIFO3B_DIN4/DOUT4
G14
BK3_IO6
3
51P
3B
6
-
HSI3B_RXD5/TXD5
FIFO3B_DIN5/DOUT5
D17
BK3_IO7
3
51N
3B
7
HSI3B_SYDT5
HSI3B_RXD6/TXD6
FIFO3B_DIN6/DOUT6
D16
BK3_IO8
3
52P
3B
8
-
HSI3B_RXD7/TXD7
FIFO3B_DIN7/DOUT7
C18
BK3_IO9
3
52N
3B
9
-
HSI3B_RXD8/TXD8
FIFO3B_DIN8/DOUT8
B18
BK3_IO10/
VREF3
3
53P
3B
10
HSI3B_SOUTP
HSI3B_RXD9/TXD9
FIFO3B_DIN9/DOUT9
F15
BK3_IO11
3
53N
3B
11
HSI3B_SOUTN
HSI3B_RECCLK
-
F14
GND
GND
3
-
-
-
-
-
-
BK3_IO12
3
54P
3B
12
FIFO3B_STRDb6
-
-
B17
BK3_IO13
3
54N
3B
13
HSI3B_CDRRSTb
HSI3B_RECCLK
FIFO3B_FIFORSTb
A17
BK3_IO14/
PLL_RST3
3
55P
3B
14
-
-
-
A16
62
Lattice Semiconductor
ispGDX2 Family Data Sheet
ispGDX2-256 Logic Signal Connections (Continued)
Signal
Name
sysIO
Bank
LVDS
GDX
Pair/Polarity Block MRB
SERDES Mode
I/O Pin1
SERDES Mode
I/O Cell2
FIFO Mode I/O
Cell/Pin3
484
fpBGA
BK3_IO15
3
55N
3B
15
-
-
FIFO3B_EMPTY
C16
BK3_IO16
3
56P
2B
0
-
HSI2B_RXD0/TXD0
FIFO2B_DIN0/DOUT0
D15
BK3_IO17
3
56N
2B
1
Note 4
HSI2B_RXD1/TXD1
FIFO2B_DIN1/DOUT1
D14
BK3_IO18
3
57P
2B
2
-
HSI2B_RXD2/TXD2
FIFO2B_DIN2/DOUT2
B16
BK3_IO19
3
57N
2B
3
-
HSI2B_RXD3/TXD3
FIFO2B_DIN3/DOUT3
C15
GND
3
-
-
-
-
-
-
GND
BK3_IO20
3
58P
2B
4
HSI2B_SOUTP
HSI2B_RXD4/TXD4
FIFO2B_DIN4/DOUT4
G13
BK3_IO21
3
58N
2B
5
HSI2B_SOUTN
HSI2B_RXD5/TXD5
FIFO2B_DIN5/DOUT5
G12
BK3_IO22
3
59P
2B
6
-
HSI2B_RXD6/TXD6
FIFO2B_DIN6/DOUT6
B15
BK3_IO23
3
59N
2B
7
FIFO2B_STRDb6
HSI2B_RXD7/TXD7
FIFO2B_DIN7 /DOUT7
A15
BK3_IO24
3
60P
2B
8
-
HSI2B_RXD8/TXD8
FIFO2B_DIN8/DOUT8
C14
BK3_IO25
3
60N
2B
9
HSI2B_SYDT5
HSI2B_RXD9/TXD9
FIFO2B_DIN9/DOUT9
A14
BK3_IO26
3
61P
2B
10
HSI2B_SINP
HSI2B_RECCLK
-
F13
BK3_IO27
3
61N
2B
11
HSI2B_SINN
-
-
F12
GND
3
-
-
-
-
-
-
GND
BK3_IO28
3
62P
2B
12
-
HSI2B_SYDT5
FIFO2B_FULL
D13
BK3_IO29
3
62N
2B
13
HSI2B_CDRRSTb
-
FIFO2B_FIFORSTb
C13
BK3_IO30/
PLL_LOCK3
3
63P
2B
14
-
-
-
B13
BK3_IO31
3
63N
2B
15
-
-
FIFO2B_ EMPTY
A13
RESETb
-
-
-
-
-
-
D12
BK4_IO0
4
64N
4A
0
-
-
FIFO4A_EMPTY
A10
BK4_IO1/
PLL_LOCK0
4
64P
4A
1
-
-
-
B10
BK4_IO2
4
65N
4A
2
HSI4A_CDRRSTb
-
FIFO4A_FIFORSTb
E11
BK4_IO3
4
65P
4A
3
-
HSI4A_SYDT5
FIFO4A_FULL
E10
GND
GND
4
-
-
-
BK4_IO4
4
66N
4A
4
HSI4A_SINN
-
-
F11
BK4_IO5
4
66P
4A
5
HSI4A_SINP
HSI4A_RECCLK
-
F10
BK4_IO6
4
67N
4A
6
HSI4A_SYDT5
HSI4A_RXD9/TXD9
FIFO4A_DIN9/DOUT9
C10
BK4_IO7
4
67P
4A
7
-
HSI4A_RXD8/TXD8
FIFO4A_DIN8/DOUT8
C9
BK4_IO8
4
68N
4A
8
FIFO4A_STRDb6
HSI4A_RXD7/TXD7
FIFO4A_DIN7 /DOUT7
D10
BK4_IO9/
PLL_FB0
4
68P
4A
9
-
HSI4A_RXD6/TXD6
FIFO4A_DIN6/DOUT6
D9
BK4_IO10
4
69N
4A
10
HSI4A_SOUTN
HSI4A_RXD5/TXD5
FIFO4A_DIN5/DOUT5
G11
BK4_IO11
4
69P
4A
11
HSI4A_SOUTP
HSI4A_RXD4/TXD4
FIFO4A_DIN4/DOUT4
G10
GND
4
-
-
-
-
GND
BK4_IO12
4
70N
4A
12
-
HSI4A_RXD3/TXD3
FIFO4A_DIN3/DOUT3
A9
BK4_IO13
4
70P
4A
13
-
HSI4A_RXD2/TXD2
FIFO4A_DIN2/DOUT2
C8
BK4_IO14
4
71N
4A
14
Note 4
HSI4A_RXD1/TXD1
FIFO4A_DIN1/DOUT1
B8
BK4_IO15
4
71P
4A
15
-
HSI4A_RXD0/TXD0
FIFO4A_DIN0/DOUT0
A8
BK4_IO16
4
72N
5A
0
-
-
FIFO5A_EMPTY
B7
BK4_IO17/
PLL_RST0
4
72P
5A
1
-
-
-
C7
BK4_IO18
4
73N
5A
2
HSI5A_CDRRSTb
-
FIFO5A_FIFORSTb
A7
BK4_IO19
4
73P
5A
3
FIFO5A_STRDb6
-
-
B6
GND
4
-
-
-
-
-
-
GND
BK4_IO20
4
74N
5A
4
HSI5A_SOUTN
HSI5A_RECCLK
-
F9
63
Lattice Semiconductor
ispGDX2 Family Data Sheet
ispGDX2-256 Logic Signal Connections (Continued)
Signal
Name
sysIO
Bank
LVDS
GDX
Pair/Polarity Block MRB
SERDES Mode
I/O Pin1
SERDES Mode
I/O Cell2
FIFO Mode I/O
Cell/Pin3
484
fpBGA
BK4_IO21/
VREF4
4
74P
5A
5
HSI5A_SOUTP
HSI5A_RXD9/TXD9
FIFO5A_DIN9/DOUT9
F8
BK4_IO22
4
75N
5A
6
-
HSI5A_RXD8/TXD8
FIFO5A_DIN8/DOUT8
D7
BK4_IO23
4
75P
5A
7
-
HSI5A_RXD7/TXD7
FIFO5A_DIN7/DOUT7
D6
BK4_IO24
4
76N
5A
8
HSI5A_SYDT5
HSI5A_RXD6/TXD6
FIFO5A_DIN6/DOUT6
A6
BK4_IO25
4
76P
5A
9
-
HSI5A_RXD5/TXD5
FIFO5A_DIN5/DOUT5
A5
BK4_IO26
4
77N
5A
10
HSI5A_SINN
HSI5A_RXD4/TXD4
FIFO5A_DIN4/DOUT4
G9
BK4_IO27
4
77P
5A
11
HSI5A_SINP
HSI5A_RXD3/TXD3
FIFO5A_DIN3/DOUT3
G8
BK4_IO28
4
78N
5A
12
-
HSI5A_RXD2/TXD2
FIFO5A_DIN2/DOUT2
C5
BK4_IO29
4
78P
5A
13
Note 4
HSI5A_RXD1/TXD1
FIFO5A_DIN1/DOUT1
B5
BK4_IO30
4
79N
5A
14
-
HSI5A_RXD0/TXD0
FIFO5A_DIN0/DOUT0
D5
BK4_IO31
4
79P
5A
15
-
HSI5A_SYDT5
FIFO5A_FULL
C4
GND
4
-
-
-
-
-
GND
GOE1
-
-
-
-
-
B4
TMS
-
-
-
-
-
-
A4
GND
5
-
-
-
-
-
GND
BK5_IO0
5
80P
4B
0
-
-
FIFO4B_EMPTY
D2
BK5_IO1
5
80N
4B
1
-
-
-
D3
BK5_IO2
5
81P
4B
2
FIFO4B_STRDb6
-
-
F5
BK5_IO3
5
81N
4B
3
HSI4B_CDRRSTb
HSI4B_RECCLK
FIFO4B_FIFORSTb
E4
BK5_IO4
5
82P
4B
4
HSI4B_SINP
HSI4B_RXD9/TXD9
FIFO4B_DIN9/DOUT9
J7
BK5_IO5
5
82N
4B
5
HSI4B_SINN
HSI4B_RXD8/TXD8
FIFO4B_DIN8/DOUT8
J6
BK5_IO6
5
83P
4B
6
HSI4B_SYDT5
HSI4B_RXD7/TXD7
FIFO4B_DIN7/DOUT7
D1
BK5_IO7
5
83N
4B
7
-
HSI4B_RXD6/TXD6
FIFO4B_DIN6/DOUT6
E1
BK5_IO8
5
84P
4B
8
-
HSI4B_RXD5/TXD5
FIFO4B_DIN5/DOUT5
F4
BK5_IO9
5
84N
4B
9
HSI4_CSLOCK
HSI4_RXD4/TXD4
FIFO4B_DIN4/DOUT4
E3
BK5_IO10/
VREF5
5
85P
4B
10
HSI4B_SOUTP
HSI4B_RXD3/TXD3
FIFO4B_DIN3/DOUT3
H7
BK5_IO11
5
85N
4B
11
HSI4B_SOUTN
HSI4B_RXD2/TXD2
FIFO4B_DIN2/DOUT2
H6
GND
5
-
-
-
-
-
-
GND
BK5_IO12
5
86P
4B
12
Note 4
HSI4B_RXD1/TXD1
FIFO4B_DIN1/DOUT1
E2
BK5_IO13
5
86N
4B
13
-
HSI4B_RXD0/TXD0
FIFO4B_DIN0/DOUT0
F2
BK5_IO14
5
87P
4B
14
-
HSI4B_SYDT5
-
G4
BK5_IO15
5
87N
4B
15
-
-
FIFO4B_FULL
H5
BK5_IO16
5
88P
5B
0
-
-
FIFO5B_EMPTY
F1
BK5_IO17
5
88N
5B
1
FIFO5B_STRDb6
-
-
G1
BK5_IO18
5
89P
5B
2
HSI5B_CDRRSTb
HSI5B_RECCLK
FIFO5B_FIFORSTb
G3
BK5_IO19
5
89N
5B
3
HSI5B_SYDT5
HSI5B_RXD9/TXD9
FIFO5B_DIN9/DOUT9
G2
GND
5
-
-
-
-
-
-
GND
BK5_IO20
5
90P
5B
4
HSI5B_SOUTP
HSI5B_RXD8/TXD8
FIFO5B_DIN8/DOUT8
K7
BK5_IO21
5
90N
5B
5
HSI5B_SOUTN
HSI5B_RXD7/TXD7
FIFO5B_DIN7/DOUT7
K6
BK5_IO22
5
91P
5B
6
-
HSI5B_RXD6/TXD6
FIFO5B_DIN6/DOUT6
H4
BK5_IO23
5
91N
5B
7
-
HSI5B_RXD5/TXD5
FIFO5B_DIN5/DOUT5
H3
BK5_IO24
5
92P
5B
8
Note 4
HSI5B_RXD4/TXD4
FIFO5B_DIN4/DOUT4
H1
BK5_IO25
5
92N
5B
9
HSI5_CSLOCK
HSI5B_RXD3/TXD3
FIFO5B_DIN3/DOUT3
H2
BK5_IO26
5
93P
5B
10
HSI5B_SINP
HSI5B_RXD2/TXD2
FIFO5B_DIN2/DOUT2
J5
BK5_IO27
5
93N
5B
11
HSI5B_SINN
HSI5B_RXD1/TXD1
FIFO5B_DIN1/DOUT1
K5
64
Lattice Semiconductor
ispGDX2 Family Data Sheet
ispGDX2-256 Logic Signal Connections (Continued)
Signal
Name
sysIO
Bank
LVDS
GDX
Pair/Polarity Block MRB
SERDES Mode
I/O Pin1
SERDES Mode
I/O Cell2
FIFO Mode I/O
Cell/Pin3
484
fpBGA
GND
5
-
-
-
-
-
-
GND
BK5_IO28
5
94P
5B
12
-
HSI5B_RXD0/TXD0
FIFO5B_DIN0/DOUT0
J4
BK5_IO29
5
94N
5B
13
-
HSI5B_SYDT5
-
J3
BK5_IO30
5
95P
5B
14
SS_CLKIN0P
-
-
L6
BK5_IO31/
CLK_OUT0
5
95N
5B
15
SS_CLKIN0N
-
FIFO5B_FULL
L5
GCLK/CE0
-
CLK0P
-
-
-
-
-
L4
SEL0
-
-
-
-
-
-
-
K3
SEL1
-
-
-
-
-
-
-
K2
GCLK/CE1
-
CLK0N
-
-
-
-
-
N1
BK6_IO0/
CLK_OUT1
6
96N
7A
0
SS_CLKOUT0N
-
FIFO7A_EMPTY
N6
BK6_IO1
6
96P
7A
1
SS_CLKOUT0P
-
-
N5
BK6_IO2
6
97N
7A
2
HSI7A_CDRRST
-
FIFO7A_FIFORSTb
M5
BK6_IO3
6
97P
7A
3
FIFO7A_STRDb6
-
-
M6
GND
6
-
-
-
-
-
-
GND
BK6_IO4
6
98N
7A
4
HSI7A_SINN
HSI7A_RECCLK
-
P6
BK6_IO5
6
98P
7A
5
HSI7A_SINP
HSI7A_RXD9/TXD9
FIFO7A_DIN9/DOUT9
P5
BK6_IO6
6
99N
7A
6
-
HSI7A_RXD8/TXD8
FIFO7A_DIN8/DOUT8
N3
BK6_IO7
6
99P
7A
7
-
HSI7A_RXD7/TXD7
FIFO7A_DIN7/DOUT7
N2
BK6_IO8
6
100N
7A
8
HSI7A_SYDT5
HSI7A_RXD6/TXD6
FIFO7A_DIN6/DOUT6
P3
BK6_IO9
6
100P
7A
9
HSI7_CSLOCK
HSI7A_RXD5/TXD5
FIFO7A_DIN5/DOUT5
P1
BK6_IO10
6
101N
7A
10
HSI7A_SOUTN
HSI7A_RXD4/TXD4
FIFO7A_DIN4/DOUT4
N7
BK6_IO11
6
101P
7A
11
HSI7A_SOUTP
HSI7A_RXD3/TXD3
FIFO7A_DIN3/DOUT3
P7
GND
6
-
-
-
-
-
-
GND
BK6_IO12
6
102N
7A
12
-
HSI7A_RXD2/TXD2
FIFO7A_DIN2/DOUT2
R3
BK6_IO13
6
102P
7A
13
Note 4
HSI7A_RXD1/TXD1
FIFO7A_DIN1/DOUT1
R2
BK6_IO14
6
103N
7A
14
-
HSI7A_RXD0/TXD0
FIFO7A_DIN0/DOUT0
R1
BK6_IO15
6
103P
7A
15
-
HSI7A_SYDT5
FIFO7A_ FULL
T1
BK6_IO16
6
104N
6A
0
-
-
FIFO6A_EMPTY
T2
BK6_IO17
6
104P
6A
1
-
-
-
T3
BK6_IO18
6
105N
6A
2
FIFO6A_STRDb6
-
-
U1
BK6_IO19
6
105P
6A
3
HSI6A_CDRRSTb
HSI6_RECCLK
FIFO6A_FIFORSTb
U2
GND
6
-
-
-
-
-
-
GND
BK6_IO20/
PLL_FB1
6
106N
6A
4
HSI6A_SOUTN
HSI6A_RXD9/TXD9
FIFO6A_DIN9/DOUT9
R5
BK6_IO21/
VREF6
6
106P
6A
5
HSI6A_SOUTP
HSI6A_RXD8/TXD8
FIFO6A_DIN8/DOUT8
T6
HSI6A_RXD7/TXD7
FIFO6A_DIN7/DOUT7
U4
HSI6A_RXD6/TXD6
FIFO6A_DIN6/DOUT6
V4
5
BK6_IO22
6
107N
6A
6
HSI6A_SYDT
BK6_IO23
6
107P
6A
7
-
BK6_IO24
6
108N
6A
8
-
HSI6A_RXD5/TXD5
FIFO6A_DIN5/DOUT5
V3
BK6_IO25
6
108P
6A
9
HSI6_CSLOCK
HSI6A_RXD4/TXD4
FIFO6A_DIN4/DOUT4
V2
BK6_IO26
6
109N
6A
10
HSI6A_SINN
HSI6A_RXD3/TXD3
FIFO6A_DIN3/DOUT3
R6
BK6_IO27
6
109P
6A
11
HSI6A_SINP
HSI6A_RXD2/TXD2
FIFO6A_DIN2/DOUT2
R7
BK6_IO28
6
110N
6A
12
Note 4
HSI6A_RXD1/TXD1
FIFO6A_DIN1/DOUT1
W1
BK6_IO29
6
110P
6A
13
-
HSI6A_RXD0/TXD0
FIFO6A_DIN0/DOUT0
V1
BK6_IO30
6
111N
6A
14
-
HSI6A_SYDT5
-
W2
BK6_IO31
6
111P
6A
15
-
-
FIFO6A_ FULL
W3
65
Lattice Semiconductor
ispGDX2 Family Data Sheet
ispGDX2-256 Logic Signal Connections (Continued)
Signal
Name
sysIO
Bank
LVDS
GDX
Pair/Polarity Block MRB
SERDES Mode
I/O Pin1
SERDES Mode
I/O Cell2
FIFO Mode I/O
Cell/Pin3
484
fpBGA
GND
6
-
-
-
-
-
-
GND
TDI
-
-
-
-
-
-
-
AA4
GOE0
-
-
-
-
-
-
-
Y4
GND
7
-
-
-
-
-
-
GND
BK7_IO0
7
112P
7B
0
-
-
FIFO7B_ EMPTY
AB4
BK7_IO1
7
112N
7B
1
FIFO7B_STRDb6
-
-
AB5
BK7_IO2
7
113P
7B
2
HSI7B_CDRRSTb
HSI7B_RECCLK
FIFO7B_FIFORSTb
V6
BK7_IO3
7
113N
7B
3
HSI7B_SYDT5
HSI7B_RXD9/TXD9
FIFO7B_DIN9/DOUT9
W5
BK7_IO4
7
114P
7B
4
HSI7B_SINP
HSI7B_RXD8/TXD8
FIFO7B_DIN8/DOUT8
T8
BK7_IO5
7
114N
7B
5
HSI7B_SINN
HSI7B_RXD7/TXD7
FIFO7B_DIN7/DOUT7
T9
BK7_IO6
7
115P
7B
6
-
HSI7B_RXD6/TXD6
FIFO7B_DIN6/DOUT6
W6
BK7_IO7
7
115N
7B
7
-
HSI7B_RXD5/TXD5
FIFO7B_DIN5/DOUT5
Y5
BK7_IO8
7
116P
7B
8
Note 4
HSI7B_RXD4/TXD4
FIFO7B_DIN4/DOUT4
AA5
BK7_IO9
7
116N
7B
9
-
HSI7B_RXD3/TXD3
FIFO7B_DIN3/DOUT3
AA6
BK7_IO10/
VREF7
7
117P
7B
10
HSI7B_SOUTP
HSI7B_RXD2/TXD2
FIFO7B_DIN2/DOUT2
U8
BK7_IO11
7
117N
7B
11
HSI7B_SOUTN
HSI7B_RXD1/TXD1
FIFO7B_DIN1/DOUT1
U9
GND
7
-
-
-
-
-
-
GND
BK7_IO12
7
118P
7B
12
-
HSI7B_RXD0/TXD0
FIFO7B_DIN0/DOUT0
W7
BK7_IO13
7
118N
7B
13
-
HSI7B_SYDT5
-
W8
BK7_IO14/
PLL_RST1
7
119P
7B
14
-
-
-
AB6
BK7_IO15
7
119N
7B
15
-
-
FIFO7B_FULL
AB7
BK7_IO16
7
120P
6B
0
FIFO6B_STRDb6
-
-
Y7
BK7_IO17
7
120N
6B
1
HSI6B_CDRRSTb
HSI6B_RECCLK
FIFO6B_FIFORSTb
AA7
BK7_IO18
7
121P
6B
2
HSI6B_SYDT5
HSI6B_RXD9/TXD9
FIFO6B_DIN9/DOUT9
W9
BK7_IO19
7
121N
6B
3
-
HSI6B_RXD8/TXD8
FIFO6B_DIN8/DOUT8
Y8
GND
7
-
-
-
-
-
-
GND
BK7_IO20
7
122P
6B
4
HSI6B_SOUTP
HSI6B_RXD7/TXD7
FIFO6B_DIN7/DOUT7
T10
BK7_IO21
7
122N
6B
5
HSI6B_SOUTN
HSI6B_RXD6/TXD6
FIFO6B_DIN6/DOUT6
T11
BK7_IO22
7
123P
6B
6
-
HSI6B_RXD5/TXD5
FIFO6B_DIN5/DOUT5
AA8
BK7_IO23
7
123N
6B
7
-
HSI6B_RXD4/TXD4
FIFO6B_DIN4/DOUT4
AB8
BK7_IO24
7
124P
6B
8
Note 4
HSI6B_RXD3/TXD3
FIFO6B_DIN3/DOUT3
W10
BK7_IO25
7
124N
6B
9
-
HSI6B_RXD2/TXD2
FIFO6B_DIN2/DOUT2
Y9
BK7_IO26
7
125P
6B
10
HSI6B_SINP
HSI6B_RXD1/TXD1
FIFO6B_DIN1/DOUT1
U10
BK7_IO27
7
125N
6B
11
HSI6B_SINN
HSI6B_RXD0/TXD0
FIFO6B_DIN0/DOUT0
U11
GND
7
-
-
-
-
-
-
GND
BK7_IO28
7
126P
6B
12
-
HSI6B_SYDT5
FIFO6B_ EMPTY
W11
BK7_IO29/
PLL_LOCK1
7
126N
6B
13
-
-
-
Y10
BK7_IO30
7
127P
6B
14
-
-
-
AA10
BK7_IO31
7
127N
6B
15
-
-
FIFO6B_FULL
AB9
66
Lattice Semiconductor
ispGDX2 Family Data Sheet
ispGDX2-256 Logic Signal Connections (Continued)
Signal
Name
TOE
sysIO
Bank
-
LVDS
GDX
Pair/Polarity Block MRB
-
-
-
SERDES Mode
I/O Pin1
SERDES Mode
I/O Cell2
FIFO Mode I/O
Cell/Pin3
484
fpBGA
-
-
-
AB10
1. The signals in this column route to/from the assigned pins of the associated I/O cell.
2. The signals in this column use the I/O cell. If a receiver signal is present in the I/O cell, the associated pin is available for output only. When
transmit data (TXD) is present in the cell, the associated pin is available for input only.
3. The DOUT outputs are routed to GRP through the input register of the cell and the DIN inputs are routed direct from the associated pins in
FIFO only mode. In SERDES with FIFO mode, the FULL and EMPTY flags are routed to the associated pins through the output MUX and
the pins.
4. If the Source Synchronous Receiver is used in the HSI Block, this pin is unavailable for another use and must be left unconnected.
5. The SYDT signal has two routing options. If direct output through the dedicated pin is used, the I/O cell (the whole HSI Block) is not available for transmitter. The SYDT in the I/O Cell column is routed to the GRP through the input register of the cell and frees the I/O cell for
transmitter.
6. FIFO_STRDb flag output is used in SERDES with FIFO Mode only.
7. sysHSI Source Synchronous Receive Mode is not available for channel 3A.
67
Lattice Semiconductor
ispGDX2 Family Data Sheet
Part Number Description
LX XXX X X – XX FXXX X
Device Family
LX
Grade
C = Commercial
I = Industrial
Package
F100 = 100-Ball fpBGA
FN100 = Lead-Free 100-Ball fpBGA
F208 = 208-Ball fpBGA
FN208 = Lead-Free 208-Ball fpBGA
F484 = 484-Ball fpBGA
FN484 = Lead-Free 484-Ball fpBGA
Speed
3 = 3.0ns
32 = 3.2ns
35 = 3.5ns
5 = 5.0ns
Device Number
64 = 64 I/Os
128 = 128 I/Os
256 = 256 I/Os
sysHSI Support
Blank = Supports sysHSI
E = No sysHSI support
Power Supply Voltage
V = 3.3V
B = 2.5V
C = 1.8V
Ordering Information
Conventional Packaging
Commercial
Family
LX64V
LX128V
LX256V
LX64B
LX128B
LX256B
LX64C
LX128C
LX256C
Part Number
I/Os
Voltage
tPD
Package
Pins
Grade
64
3.3
3
fpBGA
100
C
LX64V-5F100C
64
3.3
5
fpBGA
100
C
LX128V-32F208C
128
3.3
3.2
fpBGA
208
C
LX128V-5F208C
128
3.3
5
fpBGA
208
C
LX256V-35F484C
256
3.3
3.5
fpBGA
484
C
LX256V-5F484C
256
3.3
5
fpBGA
484
C
LX64B-3F100C
64
2.5
3
fpBGA
100
C
LX64B-5F100C
64
2.5
5
fpBGA
100
C
LX128B-32F208C
128
2.5
3.2
fpBGA
208
C
LX128B-5F208C
128
2.5
5
fpBGA
208
C
LX256B-35F484C
256
2.5
3.5
fpBGA
484
C
LX256B-5F484C
256
2.5
5
fpBGA
484
C
LX64C-3F100C
64
1.8
3
fpBGA
100
C
LX64C-5F100C
64
1.8
5
fpBGA
100
C
LX128C-32F208C
128
1.8
3.2
fpBGA
208
C
LX128C-5F208C
128
1.8
5
fpBGA
208
C
LX256C-35F484C
256
1.8
3.5
fpBGA
484
C
LX256C-5F484C
256
1.8
5
fpBGA
484
C
LX64V-3F100C
68
Lattice Semiconductor
ispGDX2 Family Data Sheet
“E-Series” Commercial
Family
LX64EV
LX128EV
LX256EV
LX64EB
LX128EB
LX256EB
LX64EC
LX128EC
Part Number
I/Os
Voltage
tPD
Package
Pins
Grade
64
3.3
3
fpBGA
100
C
LX64EV-5F100C
64
3.3
5
fpBGA
100
C
LX128EV-32F208C
128
3.3
3.2
fpBGA
208
C
LX128EV-5F208C
128
3.3
5
fpBGA
208
C
LX256EV-35F484C
256
3.3
3.5
fpBGA
484
C
LX256EV-5F484C
256
3.3
5
fpBGA
484
C
LX64EB-3F100C
64
2.5
3
fpBGA
100
C
LX64EB-5F100C
64
2.5
5
fpBGA
100
C
LX128EB-32F208C
128
2.5
3.2
fpBGA
208
C
LX128EB-5F208C
128
2.5
5
fpBGA
208
C
LX256EB-35F484C
256
2.5
3.5
fpBGA
484
C
LX256EB-5F484C
256
2.5
5
fpBGA
484
C
LX64EC-3F100C
64
1.8
3
fpBGA
100
C
LX64EC-5F100C
64
1.8
5
fpBGA
100
C
LX128EC-32F208C
128
1.8
3.2
fpBGA
208
C
LX128EC-5F208C
128
1.8
5
fpBGA
208
C
LX64EV-3F100C
“E-Series” Industrial
I/Os
Voltage
tPD
Package
Pins
Grade
LX64EV
Family
LX64EV-5F100I
Part Number
64
3.3
5
fpBGA
100
I
LX64EB
LX64EB-5F100I
64
2.5
5
fpBGA
100
I
LX64EC
LX64EC-5F100I
64
1.8
5
fpBGA
100
I
LX128EV LX128EV-5F208I
128
3.3
5
fpBGA
208
I
LX128EB LX128EB-5F208I
128
2.5
5
fpBGA
208
I
LX128EC LX128EC-5F208I
128
1.8
5
fpBGA
208
I
LX256EV LX256EV-5F484I
256
3.3
5
fpBGA
484
I
LX256EB LX256EB-5F484I
256
2.5
5
fpBGA
484
I
LX256EC LX256EC-5F484I
256
1.8
5
fpBGA
484
I
69
Lattice Semiconductor
ispGDX2 Family Data Sheet
Lead-Free Packaging
Commercial
Family
LX64V
LX64B
LX64C
LX128V
LX128B
LX128C
LX256V
LX256B
LX256C
Part Number
I/Os
Voltage
tPD
Package
Pins
Grade
LX64V-3FN100C
64
3.3
3.0
Lead-free fpBGA
100
C
LX64V-5FN100C
64
3.3
5.0
Lead-free fpBGA
100
C
LX64B-3FN100C
64
2.5
3.0
Lead-free fpBGA
100
C
LX64B-5FN100C
64
2.5
5.0
Lead-free fpBGA
100
C
LX64C-3FN100C
64
1.8
3.0
Lead-free fpBGA
100
C
LX64C-5FN100C
64
1.8
5.0
Lead-free fpBGA
100
C
LX128V-32FN208C
128
3.3
3.2
Lead-free fpBGA
208
C
LX128V-5FN208C
128
3.3
5.0
Lead-free fpBGA
208
C
LX128B-32FN208C
128
2.5
3.2
Lead-free fpBGA
208
C
LX128B-5FN208C
128
2.5
5.0
Lead-free fpBGA
208
C
LX128C-32FN208C
128
1.8
3.2
Lead-free fpBGA
208
C
LX128C-5FN208C
128
1.8
5.0
Lead-free fpBGA
208
C
LX256V-35FN484C
256
3.3
3.5
Lead-free fpBGA
484
C
LX256V-5FN484C
256
3.3
5.0
Lead-free fpBGA
484
C
LX256B-35FN484C
256
2.5
3.5
Lead-free fpBGA
484
C
LX256B-5FN484C
256
2.5
5.0
Lead-free fpBGA
484
C
LX256C-35FN484C
256
1.8
3.5
Lead-free fpBGA
484
C
LX256C-5FN484C
256
1.8
5.0
Lead-free fpBGA
484
C
“E-Series” Commercial
Family
LX64EV
LX64EB
LX64EC
LX128EV
LX128EB
LX128EC
LX256EV
LX256EB
LX256EC
Part Number
I/Os
Voltage
tPD
Package
Pins
Grade
LX64EV-3FN100C
64
3.3
3.0
Lead-free fpBGA
100
C
LX64EV-5FN100C
64
3.3
5.0
Lead-free fpBGA
100
C
LX64EB-3FN100C
64
2.5
3.0
Lead-free fpBGA
100
C
LX64EB-5FN100C
64
2.5
5.0
Lead-free fpBGA
100
C
LX64EC-3FN100C
64
1.8
3.0
Lead-free fpBGA
100
C
LX64EC-5FN100C
64
1.8
5.0
Lead-free fpBGA
100
C
LX128EV-32FN208C
128
3.3
3.2
Lead-free fpBGA
208
C
LX128EV-5FN208C
128
3.3
5.0
Lead-free fpBGA
208
C
LX128EB-32FN208C
128
2.5
3.2
Lead-free fpBGA
208
C
LX128EB-5FN208C
128
2.5
5.0
Lead-free fpBGA
208
C
LX128EC-32FN208C
128
1.8
3.2
Lead-free fpBGA
208
C
LX128EC-5FN208C
128
1.8
5.0
Lead-free fpBGA
208
C
LX256EV-35FN484C
256
3.3
3.5
Lead-free fpBGA
484
C
LX256EV-5FN484C
256
3.3
5.0
Lead-free fpBGA
484
C
LX256EB-35FN484C
256
2.5
3.5
Lead-free fpBGA
484
C
LX256EB-5FN484C
256
2.5
5.0
Lead-free fpBGA
484
C
LX256EC-35FN484C
256
1.8
3.5
Lead-free fpBGA
484
C
LX256EC-5FN484C
256
1.8
5.0
Lead-free fpBGA
484
C
70
Lattice Semiconductor
ispGDX2 Family Data Sheet
“E-Series” Industrial
Family
Part Number
I/Os
Voltage
tPD
Package
Pins
Grade
LX64EV
LX64EV-5FN100I
64
3.3
5.0
Lead-free fpBGA
100
I
LX64EB
LX64EB-5FN100I
64
2.5
5.0
Lead-free fpBGA
100
I
LX64EC
LX64EC-5FN100I
64
1.8
5.0
Lead-free fpBGA
100
I
LX128EV
LX128EV-5FN208I
128
3.3
5.0
Lead-free fpBGA
208
I
LX128EB
LX128EB-5FN208I
128
2.5
5.0
Lead-free fpBGA
208
I
LX128EC
LX128EC-5FN208I
128
1.8
5.0
Lead-free fpBGA
208
I
LX256EV
LX256EV-5FN484I
256
3.3
5.0
Lead-free fpBGA
484
I
LX256EB
LX256EB-5FN484I
256
2.5
5.0
Lead-free fpBGA
484
I
LX256EC
LX256EC-5FN484I
256
1.8
5.0
Lead-free fpBGA
484
I
71
Lattice Semiconductor
ispGDX2 Family Data Sheet
For Further Information
In addition to this data sheet, the following Lattice technical notes may be helpful when designing with the ispGDX2
Family:
•
•
•
•
sysIO Design and Usage Guidelines (TN1000)
sysCLOCK PLL Design and Usage Guidelines (TN1003)
sysHSI Usage Guide (TN1020)
Power Estimation in ispGDX2 Devices (TN1021)
72