MCP2025 LIN Transceiver with Voltage Regulator Features: Description: • Compliant with LIN Bus Specifications Version 1.3, 2.1 and with SAE J2602-2 • Supports Baud Rates up to 20 kBaud • 43V Load Dump Protected • Maximum Continuous Input Voltage: 30V • Wide LIN-Compliant Supply Voltage: 6.0-18.0V • Extended Temperature Range: -40°C to +125°C • Interface to PIC® EUSART and Standard USARTs • Wake-Up on LIN Bus Activity or Local Wake Input • Local Interconnect Network (LIN) Bus Pin: - Internal Pull-Up Termination Resistor and Diode for Slave Node - Protected Against VBAT Shorts - Protected Against Loss of Ground - High-Current Drive • TXD and LIN Bus Dominant Time-Out Function • Two Low-Power Modes: - Transmitter Off: 90 µA (typical) - Power Down: 4.5 µA (typical) • MCP2025 On-Chip Voltage Regulator: - Output Voltage of 5.0V or 3.3V at 70 mA Capability with Tolerances of ±3% Over the Temperature Range - Internal Short-Circuit Current Limit - External Components Limited to Filter Capacitor and Load Capacitor • Automatic Thermal Shutdown • High Electromagnetic Immunity (EMI), Low Electromagnetic Emission (EME) • Robust ESD Performance: ±15 kV for LBUS and VBB Pin (IEC61000-4-2) • Transient Protection for LBUS and VBB pins in Automotive Environment (ISO7637) • Meets Stringent Automotive Design Requirements, including “OEM Hardware Requirements for LIN, CAN and FlexRay Interfaces in Automotive Applications”, Version 1.3, May 2012 • Multiple Package Options, Including Small 4x4 mm DFN Package The MCP2025 provides a bidirectional, half-duplex communication physical interface to meet the LIN bus specification Revision 2.1 and SAE J2602-2. The device incorporates a voltage regulator with 5V or 3.3V at 70 mA regulated power supply output. The device has been designed to meet the stringent quiescent current requirements of the automotive industry, and will survive +43V load dump transients and double battery jumps. 2012-2014 Microchip Technology Inc. The MCP2025 family members include: - MCP2025-500, 8-pin, LIN driver with 5.0V regulator - MCP2025-330, 8-pin, LIN driver with 3.3V regulator Package Types MCP2025 PDIP, SOIC VBB CS/LWAKE VSS LBUS 1 2 3 4 8 7 6 5 VREG RESET TXD RXD MCP2025 4x4 DFN VBB CS/LWAKE VSS LBUS 1 2 3 4 EP 9 8 VREG 7 RESET 6 TXD 5 RXD DS20002306B-page 1 MCP2025 MCP2025 Block Diagram RESET Thermal Protection Short-Circuit Protection Voltage Regulator VBB Ratiometric Reference VREG Internal Circuits 4.2V Wake-Up Logic and Power Control VREG Bus Wake-Up RXD CS/LWAKE ~ 30 k Slope Control LBUS TXD Bus Dominant Timer VSS Thermal and Short-Circuit Protection DS20002306B-page 2 2012-2014 Microchip Technology Inc. MCP2025 1.0 DEVICE OVERVIEW 1.1 The MCP2025 provides a physical interface between a microcontroller and a LIN half-duplex bus. It is intended for automotive and industrial applications with serial bus baud rates up to 20 kBaud. This device will translate the CMOS/TTL logic levels to LIN logic levels, and vice versa. Modes of Operation The MCP2025 works in five modes: Power-On Reset, Power-Down, Ready, Operation and Transmitter Off. For an overview of all operational modes, please refer to Table 1-1. For the operational mode transition, please refer to Figure 1-1. The device offers optimum EMI and ESD performance and it can withstand high voltage on the LIN bus. The device supports two low-power modes to meet automotive industry power consumption requirements. The MCP2025 also provides a +5V or 3.3V regulated power output at 70 mA. FIGURE 1-1: STATE DIAGRAM CS/LWAKE = 0 POR(2) VREG OFF RX OFF TX OFF VBB > VON READY VREG ON RX ON TX OFF CS = 1 &TXD = 0& CS/LWAKE = 1 OR Voltage Rising Edge on LBUS TX OFF VREG ON RX ON TX OFF CS/LWAKE = 1 &TXD = 1 VREG_OK = 1 (1) CS/LWAKE = 1& TXD = 1& No Fault(3) CS/LWAKE = 0 or Fault detected(3) OPERATION VREG ON RX ON TX ON CS/LWAKE = 0 &TXD = 0 POWER-DOWN VREG OFF RX OFF TX OFF Note 1: VREG_OK: Regulator Output Voltage > 0.8VREG_NOM. 2: If the voltage on pin VBB falls below VOFF, the device will enter Power-On Reset mode from all other modes, which is not shown in the figure. 3: Faults include TXD/LBUS permanent dominant, LBUS short to VBB, thermal protection and VREG_OK is false. 2012-2014 Microchip Technology Inc. DS20002306B-page 3 MCP2025 1.1.1 POWER-ON RESET MODE 1.1.4 TRANSMITTER OFF MODE Upon application of VBB, or whenever the voltage on VBB is below the threshold of regulator turn-off voltage VOFF (typically 4.50V), the device enters Power-On Reset (POR) mode. During this mode, the device maintains the digital section in a Reset mode and waits until the voltage on the VBB pin rises above the threshold of regulator turn-on voltage VON (typically 5.75V) to enter Ready mode. In Power-On Reset mode, the LIN physical layer and voltage regulator are disabled and the RESET pin is switched to ground. If VREG is OK (VREG > 0.8*VREG_NOM), the Transmitter Off mode can be reached from Ready mode by setting CS/LWAKE to high when the TXD pin is low, or from Operation mode by pulling down CS/LWAKE to low. 1.1.2 The transmitter is also turned off whenever the voltage regulator is unstable or recovering from a fault. This prevents unwanted disruption on the bus during times of uncertain operation. READY MODE The device enters Ready mode from POR mode after the voltage on VBB rises above the threshold of regulator turn-on voltage VON, or from Power-Down mode when a remote or local wake-up event happens. Upon entering Ready mode, the voltage regulator and the receiver section of the transceiver are powered-up. The transmitter remains in an off state. The device is ready to receive data, but not to transmit. In order to minimize the power consumption, the regulator operates in a reduced-power mode. It has a lower GBW product and it is thus slower. However, the 70 mA drive capability is unchanged. The device stays in Ready mode until the output of the voltage regulator has stabilized and the CS/LWAKE pin is high (‘1’). 1.1.3 OPERATION MODE If the CS/LWAKE pin changes to high while VREG is OK (VREG > 0.8*VREG_NOM) and the TXD pin is high, the part enters Operation mode from either Ready or Transmitter Off mode. In this mode, all internal modules are operational. The internal pull-up resistor between LBUS and VBB is connected only in this mode. The device goes into Transmitter Off mode at the falling edge on the CS/LWAKE pin or when a fault is detected. Note: The TXD pin needs to be set high before setting the CS/LWAKE pin to low in order to jump and stay in Transmitter Off mode. If the TXD pin is set or maintained low before setting the CS/LWAKE pin to low, the part will transition to Transmitter Off mode and then jump to Power-Down mode after a deglitch delay of about 20 µs. DS20002306B-page 4 In Transmitter Off mode, the receiver is enabled but the LBUS transmitter is off. It is a lower-power mode. In order to minimize power consumption, the regulator operates in a reduced-power mode. It has a lower GBW product and it is thus slower. However, the 70 mA drive capability is unchanged. 1.1.5 POWER-DOWN MODE Power-Down mode is entered by pulling down both the CS/LWAKE pin and the TXD pin to low from Transmitter Off mode. In Power-Down mode, the transceiver and the voltage regulator are both off. Only the bus wake-up section and the CS/LWAKE pin wake-up circuits are in operation. This is the lowest-power mode. If any bus activity (e.g., a Break character) occurs or CS/LWAKE is set to high during Power-Down mode, the device will immediately enter Ready mode and enable the voltage regulator. Then, once the regulator output has stabilized (approximately 0.3 ms to 1.2 ms), it can go into either Operation mode or Transmitter Off mode. Refer to Section 1.1.6 “Remote Wake-Up” for more details. 1.1.6 REMOTE WAKE-UP The Remote Wake-Up sub-module observes the LBUS in order to detect bus activity. In Power-Down mode, the normal LIN recessive/dominant threshold is disabled and the LIN bus wake-up voltage threshold VWK(LBUS) is used to detect bus activities. Bus activity is detected when the voltage on the LBUS falls below the LIN bus wake-up voltage threshold VWK(LBUS) (approximately 3.4V) for at least tBDB (a typical duration of 80 µs) followed by a rising edge. Such a condition causes the device to leave Power-Down mode. 2012-2014 Microchip Technology Inc. MCP2025 TABLE 1-1: State OVERVIEW OF OPERATIONAL MODES Transmitter Receiver Internal Voltage Wake Regulator Module Operation Comments POR OFF OFF OFF OFF Proceed to Ready mode after VBB > VON. Ready OFF ON OFF ON If CS/LWAKE is high, then proceed to Bus Off Operation or Transmitter Off mode. state Operation ON ON OFF ON If CS/LWAKE is low, then proceed to Transmitter Off mode. Power-Down OFF OFF ON Activity Detect OFF On LIN bus rising edge or CS/LWAKE Lowesthigh level, go to Ready mode. Power mode Transmitter Off OFF ON OFF ON If TXD and CS/LWAKE are low, then proceed to Power-Down mode. If TXD and CS/LWAKE are high, then proceed to Operation mode. 2012-2014 Microchip Technology Inc. — Normal Operation mode Bus Off state, lower-power mode DS20002306B-page 5 MCP2025 1.2 Pin Descriptions The descriptions of the pins are listed in Table 1-2. TABLE 1-2: PIN FUNCTION TABLE Pin Number Pin Name Pin Type Description 1 Power Battery 8-lead PDIP 4x4 DFN 1 VBB CS/LWAKE 2 2 TTL input, HV-tolerant Chip Select and Local Wake-up Input VSS 3 3 Power Ground LBUS 4 4 I/O, HV LIN Bus RXD 5 5 Output Receive Data Output TXD 6 6 Input, HV-tolerant Transmit Data Input RESET 7 7 Open-drain output, HV-tolerant Reset Output VREG 8 8 Output Voltage Regulator Output EP — 9 — Exposed Thermal Pad 1.2.1 BATTERY POSITIVE SUPPLY VOLTAGE (VBB) Battery Positive Supply Voltage pin. An external diode is connected in series to prevent the device from being reversely powered (refer to Figure 1-7). 1.2.2 CHIP SELECT AND LOCAL WAKE-UP INPUT (CS/LWAKE) Chip Select and Local Wake-Up Input pin (TTL level, high-voltage tolerant). This pin controls the device state transition. Refer to Figure 1-1. An internal pull-down resistor will keep the CS/LWAKE pin low to ensure that no disruptive data will be present on the bus while the microcontroller is executing a Power-On Reset and I/O initialization sequence. When CS/LWAKE is ‘1’, a weak pull-down (~600 kΩ) is used to reduce current. When CS/LWAKE is ‘0’, a stronger pull-down (~300 kΩ) is used to maintain the logic level. This pin may also be used as a local wake-up input (see Figure 1-7). The microcontroller will set the I/O pin to control the CS/LWAKE. An external switch or another source can then wake up both the transceiver and the microcontroller. Note: 1.2.3 CS/LWAKE should NOT be tied directly to the VREG pin, as this could force the MCP2025 into Operation mode before the microcontroller is initialized. GROUND (VSS) Ground pin. DS20002306B-page 6 1.2.4 LIN BUS (LBUS) LIN Bus pin. LBUS is a bidirectional LIN bus interface pin and is controlled by the signal TXD. It has an open collector output with a current limitation. To reduce electromagnetic emission, the slopes during signal changes are controlled and the LBUS pin has corner-rounding control for both falling and rising edges. The internal LIN receiver observes the activities on the LIN bus and generates the output signal RXD that follows the state of the LBUS. A 1st degree 160 kHz low-pass input filter optimizes electromagnetic immunity. 1.2.5 RECEIVE DATA OUTPUT (RXD) Receive Data Output pin. The RXD pin is a standard CMOS output pin and it follows the state of the LBUS pin. 1.2.6 TRANSMIT DATA INPUT (TXD) Transmit Data Input pin (TTL level, HV-compliant, adaptive pull-up). The transmitter reads the data stream on the TXD pin and sends it to the LIN bus. The LBUS pin is low (dominant) when TXD is low, and high (recessive) when TXD is high. TXD is internally pulled-up to approximately 4.2V. When TXD is ‘0’, a weak pull-up (~900 kΩ) is used to reduce current. When TXD is ‘1’, a stronger pull-up (~300 kΩ) is used to maintain the logic level. A series reverse-blocking diode allows applying TXD input voltages greater than the internally generated 4.2V and renders the TXD pin HV-compliant up to 30V (see MCP2025 Block Diagram). 2012-2014 Microchip Technology Inc. MCP2025 1.2.7 RESET FIGURE 1-2: Reset output pin. This is an open-drain output pin. It indicates the internal voltage has reached a valid, stable level. As long as the internal voltage is valid (above 0.8 VREG), this pin will present high impedance; otherwise, the RESET pin switches to ground. 1.2.8 Output Overload Voltage Regulator Shutdown POSITIVE SUPPLY VOLTAGE REGULATOR OUTPUT (VREG) Positive Supply Voltage Regulator Output pin. An on-chip Low Dropout Regulator (LDO) gives +5.0 or +3.3V at 70 mA regulated voltage on this pin. 1.2.9 EXPOSED THERMAL PAD (EP) There is an internal electrical connection between the Exposed Thermal Pad (EP) and the VSS pin; they must be connected to the same potential on the Printed Circuit Board (PCB). This pad can be connected to a PCB ground plane to provide a larger heat sink. This improves the package thermal resistance (JA). 1.3 1.3.1 Fail-Safe Features GENERAL FAIL-SAFE FEATURES • An internal pull-down resistor on the CS/LWAKE pin disables the transmitter if the pin is floating. • An internal pull-up resistor on the TXD pin places TXD in high and the LBUS in recessive if the TXD pin is floating. • High-Impedance and low-leakage current on LBUS during loss of power or ground. • The current limit on LBUS protects the transceiver from being damaged if the pin is shorted to VBB. 1.3.2 THERMAL PROTECTION The thermal protection circuit monitors the die temperature and is able to shut down the LIN transmitter and voltage regulator. There are three causes for a thermal overload. A thermal shutdown can be triggered by any one, or a combination of, the following thermal overload conditions: • Voltage regulator overload • LIN bus output overload • Increase in die temperature due to increase in environment temperature The recovery time from the thermal shutdown is equal to adequate cooling time. Driving the TXD and checking the RXD pin make it possible to determine whether there is a bus contention (TXD = high, RXD = low) or a thermal overload condition (TXD = low, RXD = high). 2012-2014 Microchip Technology Inc. THERMAL SHUTDOWN STATE DIAGRAMS LIN Bus Shorted to VBB Operation Mode Transmitter Shutdown Temp < SHUTDOWNTEMP Temp < SHUTDOWNTEMP 1.3.3 TXD/LBUS TIME-OUT TIMER The LIN bus can be driven to a dominant level, either from the TXD pin or externally. An internal timer deactivates the LBUS transmitter if a dominant status (low) on the LIN bus lasts longer than Bus Dominant Time-Out Time, tTO(LIN) (approximately 20 milliseconds). At the same time, the RXD output is put in recessive (high) and the internal pull-up resistor between LBUS and VBB is disconnected. The timer is reset on any recessive LBUS status or POR mode. The recessive status on LBUS can be caused either by the bus being externally pulled-up or by the TXD pin being returned high. 1.4 Internal Voltage Regulator The MCP2025 has a positive regulator capable of supplying +5.00 or +3.30 VDC ±3% at up to 70 mA of load current over the entire operating temperature range of -40°C to +125°C. The regulator uses an LDO design, is short-circuit-protected and will turn the regulator output off if its output falls below the shutdown voltage threshold, VSD. With a load current of 70 mA, the minimum input-to-output voltage differential required for the output to remain in regulation is typically +0.5V (+1V maximum over the full operating temperature range). Quiescent current is less than 100 µA with a full 70 mA load current when the input-to-output voltage differential is greater than +3.00V. Regarding the correlation between VBB, VREG and IDD, please refer to Figures 1-4 and 1-5. When the input voltage (VBB) drops below the differential needed to provide stable regulation, the voltage regulator output, VREG, will track the input down to approximately VOFF, at which point the regulator will turn off the output. This will allow PIC® microcontrollers with internal POR circuits to generate a clean arming of the POR trip point. The MCP2025 will then monitor VBB and turn on the regulator when VBB is above the threshold of regulator turn-on voltage, VON. In Power-Down mode, the VBB monitor is turned off. DS20002306B-page 7 MCP2025 Under specific ambient temperature and battery voltage range, the voltage regulator can output as high as 150 mA current. For current load capability of the voltage regulator, refer to Figures 2-8 and 2-9. Note: The regulator has an overload current limit of approximately 250 mA. The regulator output voltage, VREG, is monitored. If output voltage VREG is lower than VSD, the voltage regulator will turn off. After a recovery time of about 3 ms, the VREG will be checked again. If there is no short circuit, (VREG > VSD), then the voltage regulator remains on. In worst-case scenarios, the ceramic capacitor may derate by 50%, based on tolerance, voltage and temperature. Therefore, in order to ensure stability, ceramic capacitors smaller than 10 µF may require a small series resistance to meet the ESR requirements, as shown in Table 1-3. TABLE 1-3: Resistance The regulator requires an external output bypass capacitor for stability. See Figure 2-1 for correct capacity and ESR for stable operation. Note: RECOMMENDED SERIES RESISTANCE FOR CERAMIC CAPACITORS Capacitor 1 1 µF 0.47 2.2 µF 0.22 4.7 µF 0.1 6.8 µF A ceramic capacitor of at least 10 µF or a tantalum capacitor of at least 2.2 µF is recommended for stability. FIGURE 1-3: VOLTAGE REGULATOR BLOCK DIAGRAM Pass Element VREG Sampling Network VBB Fast Transient Loop Buffer VSS VREF DS20002306B-page 8 2012-2014 Microchip Technology Inc. MCP2025 FIGURE 1-4: VOLTAGE REGULATOR OUTPUT ON POWER-ON RESET 8 VBB V Minimum VBB to maintain regulation VON 6 VOFF 4 2 0 t VREG V VREG-NOM 5 4 3 2 1 0 t Note 1: 2: 3: 4: FIGURE 1-5: (4) (1) (2) (3) Start-up, VBB < VON, regulator off. VBB > VON, regulator on. VBB Minimum VBB to maintain regulation. VBB < VOFF, regulator will turn off. VOLTAGE REGULATOR OUTPUT ON OVERCURRENT SITUATION IREG mA ILIM 0 6 5 t VREG V VREG-NOM 4 VSD 3 2 1 0 Note 1: 2: t (1) (2) IREG less than lLIM, regulator on. After IREG exceeds lLIM, the voltage regulator output will be reduced until VSD is reached. 2012-2014 Microchip Technology Inc. DS20002306B-page 9 MCP2025 1.5 1.5.1 Optional External Protection V RECESSIVE R TP ---------------------------------I REGMAX REVERSE BATTERY PROTECTION An external reverse-battery-blocking diode should be used to provide polarity protection (see Figure 1-7). 1.5.2 EQUATION 1-2: TRANSIENT VOLTAGE PROTECTION (LOAD DUMP) An external 43V transient suppressor (TVS) diode, between VBB and ground, with a transient protection resistor (RTP) in series with the battery supply and the VBB pin, protects the device from power transients and ESD events greater than 43V (see Figure 1-7). The maximum value for the RTP protection resistor depends upon two parameters: the minimum voltage the part will start at and the impacts of this RTP resistor on the VBB value, thus on the bus recessive level and slopes. This leads to a set of three equations to fulfill. Equation 1-1 provides a maximum RTP value according to the minimum battery voltage the user wants. Equation 1-2 provides a maximum RTP value according to the maximum error on the recessive level, thus VBB, since the part uses VBB as the reference value for the recessive level. Equation 1-3 provides a maximum RTP value according to the maximum relative variation the user can accept on the slope when IREG varies. Since both Equations 1-1 and 1-2 must be fulfilled, the maximum allowed value for RTP is thus the smaller of the two values found when solving Equations 1-1 and 1-2. Usually, Equation 1-1 gives the higher constraint (smaller value) for RTP, as shown in the following example where VBATMIN is 8V. However, the user needs to verify that the value found with Equation 1-1 fulfills Equations 1-2 and 1-3. While this protection is optional, it should be considered as good engineering practice. EQUATION 1-1: VBATMIN – 5.5V R TP ---------------------------------------250 mA 5.5V = V OFF + 1.0V Where: Where: VRECESSIVE = Maximum variation tolerated on the recessive level Assume that VRECCESSIVE = 1V IREGMAX = 50 mA. Equation 1-2 gives 20. EQUATION 1-3: Slope V BATMIN – 1V R TP ----------------------------------------------------------------I REGMAX Where: Slope = Maximum variation tolerated on the slope level IREGMAX = Maximum current the current will provide to the load VBATMIN > VOFF + 1.0V Assume that Slope = 15%, VBATMIN = 8V IREGMAX = 50 mA. Equation 1-3 gives 20. 1.5.3 and CBAT CAPACITOR Selecting CBAT = 10 x CREG is recommended. However, this leads to a high-value capacitor. Lower values for CBAT capacitor can be used with respect to some rules. In any case, the voltage at the VBB pin should remain above VOFF when the device is turned on. The current peak at start-up (due to the fast charge of the CREG and CBAT capacitors) may induce a significant drop on the VBB pin. This drop is proportional to the impedance of the VBAT connection (see Figure 1-7). The VBAT connection is mainly inductive and resistive. Therefore, it can be modeled as a resistor (RTOT) in series with an inductor (L). RTOT and L can be measured. The following formula gives an indication of the minimum value of CBAT using RTOT and L: EQUATION 1-4: C BAT -------------- = CREG 250 mA = Peak current at power-on when VBB = 5.5V Assume that VBATMIN = 8V. Equation 1-1 gives 10. and 2 2 100L + RTOT ----------------------------------2 R TOT 2 1 + L + ------------100 Where: L = Inductor (measured in mH) RTOT = RLINE + RTP (measured in ) Equation 1-4 allows lower CBAT/CREG values than the 10x ratio we recommend. DS20002306B-page 10 2012-2014 Microchip Technology Inc. MCP2025 Assume that we have a good quality VBAT connection with RTOT = 0.1 and L = 0.1 mH. Solving the equation gives CBAT/CREG = 1. If we increase RTOT up to 1, the result becomes CBAT/CREG = 1.4. However, if the connection is highly resistive or highly inductive (poor connection), the CBAT/CREG ratio greatly increases. CBAT/CREG RATIO BY VBAT CONNECTION TYPE TABLE 1-4: Connection Type RTOT L CBAT/CREG Ratio Good 0.1 0.1 mH 1 Typical 1 0.1 mH 1.4 Highly inductive 0.1 1 mH 7 Highly resistive 10 0.1 mH 7 Figure 1-6 shows the minimum recommended CBAT/CREG ratio as a function of the impedance of the VBAT connection. FIGURE 1-6: Minimum Recommended CBAT/CREG Ratio CBAT/CREG Ratio as Function of the VBAT Line Impedance 10 RBAT = 10 RBAT = 4 RBAT = 2 RBAT = 1 RBAT = 0.3 RBAT = 0.1 1 0.1 1 VBAT Line Inductance [mH] 2012-2014 Microchip Technology Inc. DS20002306B-page 11 MCP2025 1.6 Typical Applications FIGURE 1-7: TYPICAL APPLICATION CIRCUIT VBAT VBAT RTP 220 k CBAT Master Node Only VBB 43V(5) CREG Wake-Up VDD (6) RXD I/O VBB VREG TXD TXD RXD 1 k CS/LWAKE (3) RESET LIN Bus LBUS RESET VSS MMBZ27V (4) VSS 220 pF 100 nF Note 1: CREG, the load capacitor, should be ceramic or tantalum rated for extended temperatures, 1.0-22 µF. See Figure 2-1 to select the correct ESR. 2: CBAT is the filter capacitor for the external voltage supply. Typically 10 x CREG, with no ESR restriction. See Figure 1-6 to select the minimum recommended value for CBAT. The RTP value is added to the line resistance. 3: This diode is only needed if CS/LWAKE is connected to the VBAT supply. 4: ESD protection diode. 5: This component is for additional load dump protection. 6: An external 10 kΩ resistor is recommended for some applications. FIGURE 1-8: TYPICAL LIN NETWORK CONFIGURATION 40m + Return LIN bus 1 k VBB LIN bus MCP2025 LIN bus MCP205X Slave 1 (MCU) LIN bus MCP202XA Slave 2 (MCU) LIN bus MCP2003 Slave n <16 (MCU) Master (MCU) DS20002306B-page 12 2012-2014 Microchip Technology Inc. MCP2025 1.7 ICSP™ Considerations The following should be considered when the MCP2025 are connected to pins supporting in-circuit programming: • Power used for programming the microcontroller can be supplied from the programmer or from the MCP2025. The voltage on the VREG pin should not exceed the maximum value of VREG in DC Specifications. 2012-2014 Microchip Technology Inc. DS20002306B-page 13 MCP2025 2.0 ELECTRICAL CHARACTERISTICS 2.1 Absolute Maximum Ratings† VIN DC Voltage on RXD and RESET ................................................................................................. -0.3V to VREG + 0.3 VIN DC Voltage on TXD, CS/LWAKE.............................................................................................................. -0.3 to +40V VBB Battery Voltage, continuous, non-operating (Note 1)............................................................................. -0.3 to +40V VBB Battery Voltage, non-operating (LIN bus recessive, no regulator load, t < 60s) (Note 2) ...................... -0.3 to +43V VBB Battery Voltage, transient ISO 7637 Test 1 ..................................................................................................... -100V VBB Battery Voltage, transient ISO 7637 Test 2a .....................................................................................................+75V VBB Battery Voltage, transient ISO 7637 Test 3a ................................................................................................... -150V VBB Battery Voltage, transient ISO 7637 Test 3b ...................................................................................................+100V VLBUS Bus Voltage, continuous ...................................................................................................................... -18 to +30V VLBUS Bus Voltage, transient (Note 3) ........................................................................................................... -27 to +43V ILBUS Bus Short Circuit Current Limit ....................................................................................................................200 mA ESD protection on LIN, VBB (IEC 61000-4-2) (Note 4) ............................................................................................±15 V ESD protection on LIN, VBB (Human Body Model) (Note 5) ....................................................................................±8 kV ESD protection on all other pins (Human Body Model) (Note 5) .............................................................................±4 kV ESD protection on all pins (Charge Device Model) (Note 6).................................................................................±1500V ESD protection on all pins (Machine Model) (Note 7).............................................................................................±200V Maximum Junction Temperature ............................................................................................................................. 150C Storage Temperature...................................................................................................................................-65 to +150C † Notice: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational sections of this specification is not intended. Exposure to maximum rating conditions for extended periods may affect device reliability. Note 1: LIN 2.x compliant specification. 2: SAE J2602-2 compliant specification. 3: ISO 7637/1 load dump compliant (t < 500 ms). 4: According to IEC 61000-4-2, 330, 150 pF and Transceiver EMC Test Specifications [2] to [4]. 5: According to AEC-Q100-002/JESD22-A114. 6: According to AEC-Q100-011B. 7: According to AEC-Q100-003/JESD22-A115. 2.2 Nomenclature Used in this Document Some terms and names used in this data sheet deviate from those referred to in the LIN specifications. Equivalent values are shown below. LIN 2.1 Name Term used in the following tables VBAT not used VSUP VBB Supply voltage at device pin VBUS_LIM ISC Current limit of driver VBUSREC VIH(LBUS) Recessive state VBUSDOM VIL(LBUS) Dominant state DS20002306B-page 14 Definition ECU operating voltage 2012-2014 Microchip Technology Inc. MCP2025 2.3 DC Specifications DC Specifications Parameter Electrical Characteristics: Unless otherwise indicated, all limits are specified for VBB = 6.0V to 18.0V, TA = -40°C to +125°C, CREG = 10 µF. Sym. Min. Typ. Max. Units Conditions IBBQ — — 200 µA IOUT = 0 mA LBUS recessive VREG = 5.0V — — 200 µA IOUT = 0 mA LBUS recessive VREG = 3.3V — — 100 µA IOUT = 0 mA LBUS recessive VREG = 5.0V — — 100 µA IOUT = 0 mA LBUS recessive VREG = 3.3V — — 100 µA With voltage regulator on, transmitter off, receiver on, CS = VIH,VREG = 5.0V — — 100 µA With voltage regulator on, transmitter off, receiver on, CS = VIH,VREG = 3.3V IBBPD — 4.5 8 µA With voltage regulator off, receiver on and transmitter off, CS = VIL IBBNOGND -1 — 1 mA VBB = 12V, GND to VBB, VLIN = 0 – 18V High-Level Input Voltage (TXD) VIH 2.0 — 30 V Low-Level Input Voltage (TXD) VIL -0.3 — 0.8 V High-Level Input Current (TXD) IIH -2.5 — 0.4 µA Input voltage = 4.0V ~800 k internal adaptive pull-up Low-Level Input Current (TXD) IIL -10 — — µA Input voltage = 0.5V ~800 k internal adaptive pull-up High-Level Input Voltage (CS/LWAKE) VIH 2 — 30 V Through a current-limiting resistor Low-Level Input Voltage (CS/LWAKE) VIL -0.3 — 0.8 V High-Level Input Current (CS/LWAKE) IIH — — 8.0 µA Power VBB Quiescent Operating Current VBB Ready Current VBB Transmitter-Off Current with Watchdog Disabled VBB Power-Down Current VBB Current with VSS Floating IBBRD IBBTO Microcontroller Interface Note 1: 2: 3: Input voltage = 0.8VREG ~1.3 M internal pull-down to VSS Internal current limited. 2.0 ms maximum recovery time (RLBUS = 0, TX = 0, VLBUS = VBB). Characterized, not 100% tested. In Power-Down mode, normal LIN recessive/dominant threshold is disabled; VWK(LBUS) is used to detect bus activities. 2012-2014 Microchip Technology Inc. DS20002306B-page 15 MCP2025 2.3 DC Specifications (Continued) DC Specifications Parameter Electrical Characteristics: Unless otherwise indicated, all limits are specified for VBB = 6.0V to 18.0V, TA = -40°C to +125°C, CREG = 10 µF. Sym. Min. Typ. Max. Units IIL — — 5.0 µA Input voltage = 0.2VREG ~1.3 M internal pull-down to VSS Low-Level Output Voltage (RXD) VOLRXD — — 0.2VREG V IOL = 2 mA High-Level Output Voltage (RXD) VOHRXD 0.8VREG — — V IOH = 2 mA High-Level Input Voltage VIH(LBUS) 0.6 VBB — — V Recessive state Low-Level Input Voltage VIL(LBUS) -8 — 0.4 VBB V Dominant state Low-Level Input Current (CS/LWAKE) Conditions Bus Interface Input Hysteresis VHYS — — 0.175 VBB V Low-Level Output Current IOL(LBUS) 40 — 200 mA Output voltage = 0.1 VBB, VBB = 12V Pull-Up Current on Input IPU(LBUS) -180 — -72 µA ~30 k internal pull-up @ VIH(LBUS) = 0.7 VBB, VBB = 12V Short Circuit Current Limit ISC 50 — 200 mA Note 1 High-Level Output Voltage VOH(LBUS) 0.8 VBB — VBB V V_LOSUP — — 1.1 V VBB = 7.3V RLOAD = 1000 V_HISUP — — 1.2 V VBB = 18V RLOAD = 1000 Input Leakage Current (at the receiver during dominant bus level) IBUS_PAS_DOM -1 — — mA Driver off VBUS = 0V VBB = 12V Input Leakage Current (at the receiver during recessive bus level) IBUS_PAS_REC -20 — 20 µA Driver off 8V < VBB < 18V 8V < VBUS < 18V VBUS VBB Leakage Current (disconnected from ground) IBUS_NO_GND -10 — +10 µA GNDDEVICE = VBB 0V < VBUS < 18V VBB = 12V Leakage Current (disconnected from VBB) IBUS_NO_PWR -10 — +10 µA VBB = GND 0 < VBUS < 18V Receiver Center Voltage VBUS_CNT 0.475 VBB 0.5 VBB 0.525 VBB V VBUS_CNT = (VIL(LBUS) + VIH(LBUS))/2 RSLAVE 20 30 47 k Note 2 Driver Dominant Voltage Slave Termination Capacitance of Slave Node Wake-Up Voltage Threshold on LIN Bus Note 1: 2: 3: VIH(LBUS) – VIL(LBUS) CSLAVE — — 50 pF Note 2 VWK(LBUS) — — 3.4 V Wake up from Power-Down mode (Note 3) Internal current limited. 2.0 ms maximum recovery time (RLBUS = 0, TX = 0, VLBUS = VBB). Characterized, not 100% tested. In Power-Down mode, normal LIN recessive/dominant threshold is disabled; VWK(LBUS) is used to detect bus activities. DS20002306B-page 16 2012-2014 Microchip Technology Inc. MCP2025 2.3 DC Specifications (Continued) DC Specifications Parameter Electrical Characteristics: Unless otherwise indicated, all limits are specified for VBB = 6.0V to 18.0V, TA = -40°C to +125°C, CREG = 10 µF. Sym. Min. Typ. Max. Units Conditions VREG 4.85 5.00 5.15 V Line Regulation VOUT1 — 10 50 mV IOUT = 1 mA 6.0V < VBB < 18V Load Regulation VOUT2 — 10 50 mV 5 mA < IOUT < 70 mA 6.0V < VBB < 12V PSRR — — 50 dB 1 VPP @ 10-20 kHz ILOAD = 20 mA Output Noise Voltage eN — — 100 Shutdown Voltage Threshold VSD 3.5 — 4.0 V Input Voltage to Turn-Off Output VOFF 3.9 — 4.5 V — Input Voltage to Turn-On Output VON 5.25 — 6.0 V — Output Voltage VREG 3.20 3.30 3.40 V Line Regulation VOUT1 — 10 50 mV IOUT = 1 mA 6.0V < VBB < 18V Load Regulation VOUT2 — 10 50 mV 5 mA < IOUT < 70 mA 6.0V < VBB < 12V PSRR — 50 — dB 1 VPP @ 10-20 kHz ILOAD = 20 mA Output Noise Voltage eN — — 100 Shutdown Voltage VSD 2.5 — 2.7 V Input Voltage to Turn-Off Output VOFF 3.9 — 4.5 V — Input Voltage to Turn-On Output VON 5.25 — 6 V — Voltage Regulator – 5.0V Output Voltage Range Power Supply Ripple Reject 0 mA < IOUT < 70 mA µVRMS 10 Hz – 40 MHz CFILTER = 10 µf CBP = 0.1 µf ILOAD = 20 mA See Figure 1-5 (Note 2) Voltage Regulator – 3.3V Power Supply Ripple Reject Note 1: 2: 3: 0 mA < IOUT < 70 mA µVRMS 10 Hz – 40 MHz /Hz CFILTER = 10 µF CBP = 0.1 µF ILOAD = 20 mA See Figure 1-5 (Note 2) Internal current limited. 2.0 ms maximum recovery time (RLBUS = 0, TX = 0, VLBUS = VBB). Characterized, not 100% tested. In Power-Down mode, normal LIN recessive/dominant threshold is disabled; VWK(LBUS) is used to detect bus activities. 2012-2014 Microchip Technology Inc. DS20002306B-page 17 MCP2025 FIGURE 2-1: ESR CURVES FOR LOAD CAPACITOR SELECTION ESR Curves 10 Unstable Instable Stable only ESR [ohm] 1 with Tantalum or Electrolytic cap. Stable with Tantalum, Electrolytic and Ceramic cap. Unstable Instable 0.1 0.01 Unstable Instable 0.001 0.1 1 10 100 1000 Load Capacitance [uF] Note 1: The graph shows the minimum required capacitance after derating due to tolerance, temperature and voltage. DS20002306B-page 18 2012-2014 Microchip Technology Inc. MCP2025 2.4 AC Specifications AC Characteristics Parameter Electrical Characteristics: Unless otherwise indicated, all limits are specified for VBB = 6.0V to 18.0V; TA = -40°C to +125°C. Sym. Min. Typ. Max. Units Conditions Bus Interface – Constant Slope Time Parameters tSLOPE 3.5 — 22.5 µs 7.3V VBB 18V Propagation Delay of Transmitter tTRANSPD — — 6.0 µs tTRANSPD = max. (tTRANSPDR or tTRANSPDF) Propagation Delay of Receiver tRECPD — — 6.0 µs tRECPD = max. (tRECPDR or tRECPDF) tRECSYM -2.0 — 2.0 µs tRECSYM = max. (tRECPDF – tRECPDR) RRXD = 2.4 kto VCC CRXD = 20 pF tTRANSSYM -2.0 — 2.0 µs tTRANSSYM = max. (tTRANSPDF – tTRANSPDR) tTO(LIN) — 25 — mS Duty Cycle 1 @ 20.0 kbps — 0.396 — — %tBIT CBUS; RBUS conditions: 1 nF; 1 k | 6.8 nF; 660 | 10 nF; 500 THREC(MAX) = 0.744 x VBB, THDOM(MAX) = 0.581 x VBB, VBB = 7.0V – 18V; tBIT = 50 µs. D1 = tBUS_REC(MIN)/2 x tBIT Duty Cycle 2 @ 20.0 kbps — — — 0.581 %tBIT CBUS; RBUS conditions: 1 nF; 1 k | 6.8 nF; 660 | 10 nF; 500 THREC(MAX) = 0.284 x VBB, THDOM(MAX) = 0.422 x VBB, VBB = 7.6V – 18V; tBIT = 50 µs. D2 = tBUS_REC(MAX)/2 x tBIT Duty Cycle 3 @ 10.4 kbps — 0.417 — — %tBIT CBUS; RBUS conditions: 1 nF; 1 k | 6.8 nF; 660 | 10 nF; 500 THREC(MAX) = 0.778 x VBB, THDOM(MAX) = 0.616 x VBB, VBB = 7.0V – 18V; tBIT = 96 µs. D3 = tBUS_REC(MIN)/2 x tBIT Duty Cycle 4 @ 10.4 kbps — — — 0.590 %tBIT CBUS; RBUS conditions: 1 nF; 1 k | 6.8 nF; 660 | 10 nF; 500 THREC(MAX) = 0.251 x VBB, THDOM(MAX) = 0.389 x VBB, VBB = 7.6V – 18V; tBIT = 96 µs. D4 = tBUS_REC(MAX)/2 x tBIT Slope Rising and Falling Edges Symmetry of Propagation Delay of Receiver Rising Edge w.r.t. Falling Edge Symmetry of Propagation Delay of Transmitter Rising Edge w.r.t. Falling Edge Bus Dominant Time-Out Time Note 1: 2: — Time depends on external capacitance and load. Test condition: CREG = 4.7 µF, no resistor load. Characterized, not 100% tested. 2012-2014 Microchip Technology Inc. DS20002306B-page 19 MCP2025 2.4 AC Specifications (Continued) AC Characteristics Electrical Characteristics: Unless otherwise indicated, all limits are specified for VBB = 6.0V to 18.0V; TA = -40°C to +125°C. Parameter Sym. Min. Typ. Max. Units Conditions tBDB 30 80 250 µs — tBACTIVE 35 — 200 µs — Voltage Regulator Enabled to Ready tVEVR 300 — 1200 µs Chip Select to Ready Mode tCSR — — 230 µs Chip Select to Power-Down tCSPD — — 300 µs tSHUTDOWN 20 — 100 µs VREG OK Detect to RESET Inactive tRPU — — 60.0 µs Note 2 VREG Not OK Detect to RESET Active tRPD — — 60.0 µs Note 2 Voltage Regulator Bus Activity Debounce Time Bus Activity to Voltage Regulator Enabled Short Circuit to Shutdown Note 1 — Note 2 — RESET Timing Note 1: 2: 2.5 Time depends on external capacitance and load. Test condition: CREG = 4.7 µF, no resistor load. Characterized, not 100% tested. Thermal Specifications Parameter Sym. Min. Specified Temperature Range TA -40 Maximum Junction Temperature TJ — Typ. Max. Units Test Conditions — +125 C — — +150 C — TA -65 — — RECOVERY — +140 +150 — C Recovery Temperature C — Shutdown Temperature SHUTDOWN — +150 — C — tTHERM — 1.5 5.0 ms — Thermal Resistance, 8-PDIP JA — 89.3 — C/W — Thermal Resistance, 8-SOIC JA — 149.5 — C/W — Thermal Resistance, 8L-DFN JA — 48.0 — C/W — Storage Temperature Range Short Circuit Recovery Time Thermal Package Resistances Note 1: JA and ambient temperature, TA. The maximum The maximum power dissipation is a function of allowable power dissipation at an ambient temperature is PD = (TJMAX – TA) JA. If this dissipation is exceeded, the die temperature will rise above 150C and the MCP2025 will go into thermal shutdown. DS20002306B-page 20 TJMAX, 2012-2014 Microchip Technology Inc. MCP2025 2.6 Typical Performance Curves Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. Note: Unless otherwise indicated, VBB = 6.0V to 18.0V; TA = -40°C to +125°C. 180 VBB = 12V 160 VBB = 18V 120 IBBQ (μA) IBBQ (μA) 140 100 VBB = 6V 80 60 40 20 0 -45 -10 25 90 Temperature (ͼC) VBB = 18V VBB = 6V VBB = 12V -45 130 -10 25 90 Temperature (ͼC) 130 FIGURE 2-5: Typical IBBQ vs. Temperature – 3.3V. FIGURE 2-2: Typical IBBQ vs. Temperature – 5.0V. 80 90 80 70 VBB = 18V 60 50 VBB = 18V 70 VBB = 12V IBBQ (μA) IBBQ (μA) 200 180 160 140 120 100 80 60 40 20 0 VBB = 6V 40 30 60 VBB = 12V 50 VBB = 6V 40 30 20 20 10 10 0 0 -45 -10 25 90 Temperature (ͼC) 130 FIGURE 2-3: IBBQ Transmitter-Off vs. Temperature – 5.0V. -45 -10 25 90 Temperature (ͼC) 130 FIGURE 2-6: IBBQ Transmitter-Off vs. Temperature – 3.3V. 6 6 VBB = 12V 5 5 VBB = 18V VBB = 12V 4 IBBQ (μA) IBBQ (μA) VBB = 18V VBB = 6V 3 4 3 2 2 1 1 VBB = 6V 0 0 -45 -10 25 90 Temperature (ͼC) 130 FIGURE 2-4: IBBQ Power-Down vs. Temperature – 5.0V. 2012-2014 Microchip Technology Inc. -45 -10 25 90 Temperature (ͼC) 130 FIGURE 2-7: IBBQ Power-Down vs. Temperature – 3.3V. DS20002306B-page 21 MCP2025 3.5 VREG (V) 3 +90°C 2.5 +25°C -40°C +125°C 2 1.5 1 0.5 0 0 100 200 300 IREG (mA) FIGURE 2-8: VBB = 12V. 5.0V VREG vs. IREG at 6 -40°C VREG (V) 5 4 +25°C +125°C 3 +90°C 2 1 0 0 100 200 300 IREG (mA) FIGURE 2-9: VBB = 12V. DS20002306B-page 22 3.3V VREG vs. IREG at 2012-2014 Microchip Technology Inc. MCP2025 2.7 Timing Diagrams and Specifications FIGURE 2-10: TXD BUS TIMING DIAGRAM 50% 50% LBUS 0.95 VLBUS 0.50 VBB 0.05 VLBUS tTRANSPDR tTRANSPDF tRECPDF RXD FIGURE 2-11: 0.0V tRECPDR 50% 50% REGULATOR BUS WAKE TIMING DIAGRAM LBUS VWK(LBUS) tVEVR tBDB tBACTIVE VREG-NOM VREG 2012-2014 Microchip Technology Inc. DS20002306B-page 23 MCP2025 FIGURE 2-12: CS/LWAKE, REGULATOR AND RESET TIMING DIAGRAM CS/LWAKE tCSR tVEVR VREG-NOM VREG tRPD tRPU tCSPD RESET DS20002306B-page 24 2012-2014 Microchip Technology Inc. MCP2025 3.0 PACKAGING INFORMATION 3.1 Package Marking Information 8-Lead DFN (4x4x0.9 mm) Example XXXXXX XXXXXX YYWW NNN 202550 3 E/MD e^^ 1426 256 PIN 1 8-Lead PDIP (300 mil) XXXXXXXX XXXXXNNN YYWW 8-Lead SOIC (3.90 mm) e3 * Note: Example 2025330 3 E/P e^^256 1426 Example 2025-500 E/SN1426 256 NNN Legend: XX...X Y YY WW NNN PIN 1 Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code Pb-free JEDEC® designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 2012-2014 Microchip Technology Inc. DS20002306B-page 25 MCP2025 8-Lead Plastic Dual Flat, No Lead Package (MD) – 4x4x0.9 mm Body [DFN] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Microchip Technology Drawing C04-131E Sheet 1 of 2 DS20002306B-page 26 2012-2014 Microchip Technology Inc. MCP2025 8-Lead Plastic Dual Flat, No Lead Package (MD) – 4x4x0.9 mm Body [DFN] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Microchip Technology Drawing C04-131E Sheet 2 of 2 2012-2014 Microchip Technology Inc. DS20002306B-page 27 MCP2025 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS20002306B-page 28 2012-2014 Microchip Technology Inc. MCP2025 8-Lead Plastic Dual In-Line (P) - 300 mil Body [PDIP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D A N B E1 NOTE 1 1 2 TOP VIEW E C A2 A PLANE L A1 e c eB 8X b1 8X b .010 C SIDE VIEW END VIEW Microchip Technology Drawing No. C04-018D Sheet 1 of 2 2012-2014 Microchip Technology Inc. DS20002306B-page 29 MCP2025 8-Lead Plastic Dual In-Line (P) - 300 mil Body [PDIP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging ALTERNATE LEAD DESIGN (VENDOR DEPENDENT) DATUM A DATUM A b b e 2 e 2 e Units Dimension Limits Number of Pins N e Pitch Top to Seating Plane A Molded Package Thickness A2 Base to Seating Plane A1 Shoulder to Shoulder Width E Molded Package Width E1 Overall Length D Tip to Seating Plane L c Lead Thickness Upper Lead Width b1 b Lower Lead Width Overall Row Spacing eB § e MIN .115 .015 .290 .240 .348 .115 .008 .040 .014 - INCHES NOM 8 .100 BSC .130 .310 .250 .365 .130 .010 .060 .018 - MAX .210 .195 .325 .280 .400 .150 .015 .070 .022 .430 Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. § Significant Characteristic 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side. 4. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. Microchip Technology Drawing No. C04-018D Sheet 2 of 2 DS20002306B-page 30 2012-2014 Microchip Technology Inc. MCP2025 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2012-2014 Microchip Technology Inc. DS20002306B-page 31 MCP2025 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS20002306B-page 32 2012-2014 Microchip Technology Inc. MCP2025 & !"#$% ! "# $% &"' "" ($ ) % *++&&&! !+ $ 2012-2014 Microchip Technology Inc. DS20002306B-page 33 MCP2025 NOTES: DS20002306B-page 34 2012-2014 Microchip Technology Inc. MCP2025 APPENDIX A: REVISION HISTORY Revision B (August 2014) The following is the list of modifications: 1. 2. 3. Clarified CREG selection. Updated Section 1.6 “Typical Applications” with values used during ESD tests. Minor typographical corrections. Revision A (June 2012) • Original Release of this Document. 2012-2014 Microchip Technology Inc. DS20002306B-page 35 MCP2025 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. Examples: PART NO. –X X /XX Device Voltage Temperature Range Package a) b) c) d) Device: MCP2025: MCP2025T: Voltage: 330 = 3.3V 500 = 5.0V Temperature Range: E Package: LIN Transceiver with Voltage Regulator LIN Transceiver with Voltage Regulator (Tape and Reel) e) f) g) h) i) j) MCP2025-330E/MD: 3.3V, 8-lead DFN package MCP2025-500E/MD: 5.0V, 8-lead DFN package MCP2025T-330E/MD: 3.3V, 8-lead DFN package, Tape and Reel MCP2025T-500E/MD: 5.0V, 8-lead DFN package, Tape and Reel MCP2025-330E/P: 3.3V, 8-lead PDIP package MCP2025-500E/P: 5.0V, 8-lead PDIP package MCP2025-330E/SN: 3.3V, 8-lead SOIC package MCP2025-500E/SN: 5.0V, 8-lead SOIC package MCP2025T-330E/SN: 3.3V, 8-lead SOIC package, Tape and Reel MCP2025T-500E/SN: 5.0V, 8-lead SOIC package, Tape and Reel = -40°C to +125°C MD = 8LD Plastic Dual Flat, No Lead – 4x4x0.8 mm Body P = 8LD/14LD Plastic Dual In-Line – 300 mil Body SN = 8LD Plastic Small Outline – Narrow, 3.90 mm Body DS20002306B-page 36 2012-2014 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, dsPIC, FlashFlex, flexPWR, JukeBlox, KEELOQ, KEELOQ logo, Kleer, LANCheck, MediaLB, MOST, MOST logo, MPLAB, OptoLyzer, PIC, PICSTART, PIC32 logo, RightTouch, SpyNIC, SST, SST Logo, SuperFlash and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. The Embedded Control Solutions Company and mTouch are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, ECAN, In-Circuit Serial Programming, ICSP, Inter-Chip Connectivity, KleerNet, KleerNet logo, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, RightTouch logo, REAL ICE, SQI, Serial Quad I/O, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries. GestIC is a registered trademarks of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2012-2014, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. ISBN: 978-1-63276-499-7 QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV == ISO/TS 16949 == 2012-2014 Microchip Technology Inc. Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. DS20002306B-page 37 Worldwide Sales and Service AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://www.microchip.com/ support Web Address: www.microchip.com Asia Pacific Office Suites 3707-14, 37th Floor Tower 6, The Gateway Harbour City, Kowloon Hong Kong Tel: 852-2943-5100 Fax: 852-2401-3431 India - Bangalore Tel: 91-80-3090-4444 Fax: 91-80-3090-4123 Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 Australia - Sydney Tel: 61-2-9868-6733 Fax: 61-2-9868-6755 Atlanta Duluth, GA Tel: 678-957-9614 Fax: 678-957-1455 China - Beijing Tel: 86-10-8569-7000 Fax: 86-10-8528-2104 Austin, TX Tel: 512-257-3370 China - Chengdu Tel: 86-28-8665-5511 Fax: 86-28-8665-7889 Boston Westborough, MA Tel: 774-760-0087 Fax: 774-760-0088 Chicago Itasca, IL Tel: 630-285-0071 Fax: 630-285-0075 Cleveland Independence, OH Tel: 216-447-0464 Fax: 216-447-0643 Dallas Addison, TX Tel: 972-818-7423 Fax: 972-818-2924 Detroit Novi, MI Tel: 248-848-4000 Houston, TX Tel: 281-894-5983 Indianapolis Noblesville, IN Tel: 317-773-8323 Fax: 317-773-5453 Los Angeles Mission Viejo, CA Tel: 949-462-9523 Fax: 949-462-9608 New York, NY Tel: 631-435-6000 San Jose, CA Tel: 408-735-9110 Canada - Toronto Tel: 905-673-0699 Fax: 905-673-6509 DS20002306B-page 38 China - Chongqing Tel: 86-23-8980-9588 Fax: 86-23-8980-9500 China - Hangzhou Tel: 86-571-8792-8115 Fax: 86-571-8792-8116 China - Hong Kong SAR Tel: 852-2943-5100 Fax: 852-2401-3431 China - Nanjing Tel: 86-25-8473-2460 Fax: 86-25-8473-2470 China - Qingdao Tel: 86-532-8502-7355 Fax: 86-532-8502-7205 China - Shanghai Tel: 86-21-5407-5533 Fax: 86-21-5407-5066 China - Shenyang Tel: 86-24-2334-2829 Fax: 86-24-2334-2393 China - Shenzhen Tel: 86-755-8864-2200 Fax: 86-755-8203-1760 China - Wuhan Tel: 86-27-5980-5300 Fax: 86-27-5980-5118 China - Xian Tel: 86-29-8833-7252 Fax: 86-29-8833-7256 India - New Delhi Tel: 91-11-4160-8631 Fax: 91-11-4160-8632 France - Paris Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 India - Pune Tel: 91-20-3019-1500 Japan - Osaka Tel: 81-6-6152-7160 Fax: 81-6-6152-9310 Germany - Dusseldorf Tel: 49-2129-3766400 Germany - Munich Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Japan - Tokyo Tel: 81-3-6880- 3770 Fax: 81-3-6880-3771 Germany - Pforzheim Tel: 49-7231-424750 Korea - Daegu Tel: 82-53-744-4301 Fax: 82-53-744-4302 Italy - Milan Tel: 39-0331-742611 Fax: 39-0331-466781 Korea - Seoul Tel: 82-2-554-7200 Fax: 82-2-558-5932 or 82-2-558-5934 Italy - Venice Tel: 39-049-7625286 Malaysia - Kuala Lumpur Tel: 60-3-6201-9857 Fax: 60-3-6201-9859 Netherlands - Drunen Tel: 31-416-690399 Fax: 31-416-690340 Malaysia - Penang Tel: 60-4-227-8870 Fax: 60-4-227-4068 Poland - Warsaw Tel: 48-22-3325737 Philippines - Manila Tel: 63-2-634-9065 Fax: 63-2-634-9069 Singapore Tel: 65-6334-8870 Fax: 65-6334-8850 Taiwan - Hsin Chu Tel: 886-3-5778-366 Fax: 886-3-5770-955 Spain - Madrid Tel: 34-91-708-08-90 Fax: 34-91-708-08-91 Sweden - Stockholm Tel: 46-8-5090-4654 UK - Wokingham Tel: 44-118-921-5800 Fax: 44-118-921-5820 Taiwan - Kaohsiung Tel: 886-7-213-7830 Taiwan - Taipei Tel: 886-2-2508-8600 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 China - Xiamen Tel: 86-592-2388138 Fax: 86-592-2388130 China - Zhuhai Tel: 86-756-3210040 Fax: 86-756-3210049 03/25/14 2012-2014 Microchip Technology Inc.