Maxim MAX1282BCUE 300ksps/400ksps, single-supply, 4-channel, serial 12-bit adcs with internal reference Datasheet

19-1688; Rev 0; 5/00
300ksps/400ksps, Single-Supply, 4-Channel,
Serial 12-Bit ADCs with Internal Reference
Features
♦ 4-Channel Single-Ended or 2-Channel
Pseudo-Differential Inputs
The 4-wire serial interface connects directly to
SPI™/QSPI™/MICROWIRE™ devices without external
logic. A serial strobe output allows direct connection to
TMS320-family digital signal processors. The MAX1282/
MAX1283 use an external serial-interface clock to perform
successive-approximation analog-to-digital conversions.
The devices feature an internal +2.5V reference and a reference-buffer amplifier with a ±1.5% voltage-adjustment
range. An external reference with a 1V to VDD range may
also be used.
♦ 400kHz Sampling Rate (MAX1282)
The MAX1282/MAX1283 provide a hardwired SHDN pin
and four software-selectable power modes (normal operation, reduced power (REDP), fast power-down (FASTPD),
and full power-down (FULLPD)). These devices can be
programmed to automatically shut down at the end of a
conversion or to operate with reduced power. When using
the power-down modes, accessing the serial interface
automatically powers up the devices, and the quick turnon time allows them to be shut down between all conversions.
♦ 16-Pin TSSOP Package
The MAX1282/MAX1283 are available in 16-pin TSSOP
packages.
♦ Internal Multiplexer and Track/Hold
♦ Single-Supply Operation
+4.5V to +5.5V (MAX1282)
+2.7V to +3.6V (MAX1283)
♦ Internal +2.5V Reference
♦ Low Power: 2.5mA (400ksps)
1.3mA (REDP)
0.9mA (FASTPD)
2µA (FULLPD)
♦ SPI/QSPI/MICROWIRE/TMS320-Compatible 4-Wire
Serial Interface
♦ Software-Configurable Unipolar or Bipolar Inputs
Ordering Information
TEMP.
RANGE
PART
PINPACKAGE
INL
(LSB)
MAX1282BCUE
0°C to +70°C
16 TSSOP
±1
MAX1282BEUE
-40°C to +85°C
16 TSSOP
±1
MAX1283BCUE
0°C to +70°C
16 TSSOP
±1
MAX1283BEUE
-40°C to +85°C
16 TSSOP
±1
Pin Configuration
Applications
Portable Data Logging
Data Acquisition
TOP VIEW
Medical Instruments
VDD1 1
16 VDD2
Battery-Powered Instruments
CH0 2
15 SCLK
Pen Digitizers
CH1 3
Process Control
CH2 4
CH3 5
Typical Operating Circuit appears at end of data sheet.
14 CS
MAX1282/
MAX1283
13 DIN
12 SSTRB
COM 6
11 DOUT
SHDN 7
10 GND
REF 8
9
REFADJ
TSSOP
SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
________________________________________________________________ Maxim Integrated Products
1
For free samples and the latest literature, visit www.maxim-ic.com or phone 1-800-998-8800.
For small orders, phone 1-800-835-8769.
MAX1282/MAX1283
General Description
The MAX1282/MAX1283 12-bit analog-to-digital converters (ADCs) combine a 4-channel analog-input multiplexer,
high-bandwidth track/hold (T/H), and serial interface with
high conversion speed and low power consumption. The
MAX1282 operates from a single +4.5V to +5.5V supply;
the MAX1283 operates from a single +2.7V to +3.6V supply. Both devices’ analog inputs are software configurable
for unipolar/bipolar and single-ended/pseudo-differential
operation.
MAX1282/MAX1283
300ksps/400ksps, Single-Supply, 4-Channel,
Serial 12-Bit ADCs with Internal Reference
ABSOLUTE MAXIMUM RATINGS
VDD_ to GND ........................................................... -0.3V to +6V
VDD1 to VDD2 ....................................................... -0.3V to +0.3V
CH0–CH3, COM to GND .......................... -0.3V to (VDD_ +0.3V)
REF, REFADJ to GND ................................ -0.3V to VDD_ +0.3V)
Digital Inputs to GND .............................................. -0.3V to +6V
Digital Outputs to GND............................. -0.3V to (VDD_ +0.3V)
Digital Output Sink Current .................................................25mA
Continuous Power Dissipation (TA = +70°C)
16-Pin TSSOP (derate 6.7mW/°C above +70°C) ........ 535mW
Operating Temperature Ranges
MAX1282BCUE/MAX1283BCUE ....................... 0°C to +70°C
MAX1282BEUE/MAX1283BEUE ..................... -40°C to +85°C
Storage Temperature Range ............................ -60°C to +150°C
Lead Temperature (soldering, 10s) ................................ +300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS—MAX1282
(VDD1 = VDD2 = +4.5V to +5.5V, COM = GND, fOSC = 6.4MHz, 50% duty cycle, 16 clocks/conversion cycle (400ksps), external
+2.5V at REF, REFADJ = VDD1, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DC ACCURACY (Note 1)
12
Resolution
Bits
±1.0
LSB
±1.0
LSB
Offset Error
±6.0
LSB
Gain Error (Note 3)
±6.0
LSB
Relative Accuracy (Note 2)
INL
Differential Nonlinearity
DNL
No missing codes over temperature
Gain-Error Temperature
Coefficient
±1.6
ppm/°C
Channel-to-Channel Offset-Error
Matching
±0.2
LSB
DYNAMIC SPECIFICATIONS (100kHz sine-wave input, 2.5Vp-p, 400ksps, 6.4MHz clock, bipolar input mode)
Signal-to-Noise plus Distortion
Ratio
SINAD
Total Harmonic Distortion
THD
Spurious-Free Dynamic Range
SFDR
Up to the 5th harmonic
70
dB
-81
dB
80
dB
fIN1 = 99kHz, fIN2 =102kHz
76
dB
Channel-to-Channel Crosstalk
(Note 4)
200kHz, VIN = 2.5Vp-p
-78
dB
Full-Power Bandwidth
-3dB point
6
MHz
Full-Linear Bandwidth
SINAD > 68dB
350
kHz
Intermodulation Distortion
IMD
CONVERSION RATE
Conversion Time (Note 5)
tCONV
Track/Hold Acquisition Time
tACQ
2.5
µs
400
ns
Aperture Delay
10
ns
Aperture Jitter
<50
ps
Serial Clock Frequency
Duty Cycle
2
fSCLK
0.5
6.4
MHz
40
60
%
_______________________________________________________________________________________
300ksps/400ksps, Single-Supply, 4-Channel,
Serial 12-Bit ADCs with Internal Reference
(VDD1 = VDD2 = +4.5V to +5.5V, COM = GND, fOSC = 6.4MHz, 50% duty cycle, 16 clocks/conversion cycle (400ksps), external
+2.5V at REF, REFADJ = VDD1, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
ANALOG INPUTS (CH3–CH0, COM)
Input Voltage Range, SingleEnded and Differential (Note 6)
VREF
Unipolar, VCOM = 0
VCH_
Bipolar, VCOM or VCH_ = VREF/2, referenced
to COM or CH_
±VREF/2
On/off leakage current, VCOM, VCH_ = 0 or
VDD1
Multiplexer Leakage Current
±0.001
Input Capacitance
±1
18
V
µA
pF
INTERNAL REFERENCE
REF Output Voltage
VREF
TA = +25°C
2.480
REF Short-Circuit Current
REF Output Temperature
Coefficient
TC VREF
2.500
2.520
V
15
mA
±15
ppm/°C
2.0
mV/mA
Capacitive Bypass at REF
4.7
10
µF
Capacitive Bypass at REFADJ
0.01
10
µF
Load Regulation (Note 7)
0.05
0 to 1mA output load
REFADJ Output Voltage
REFADJ Input Range
For small adjustments, from 1.22V
REFADJ Buffer Disable
Threshold
To power down the internal reference
1.22
V
±100
mV
1.4
VDD1 - 1.0
+2.05
Buffer Voltage Gain
V
V/V
EXTERNAL REFERENCE (reference buffer disabled, reference applied to REF)
REF Input Voltage Range
(Note 8)
1.0
VREF = 2.500V, fSCLK = fMAX
REF Input Current
VDD1 +
50mV
200
VREF = 2.500V, fSCLK = 0
350
320
In full power-down mode, fSCLK = 0
V
µA
5
DIGITAL INPUTS (DIN, SCLK, CS, SHDN)
Input High Voltage
VINH
Input Low Voltage
3.0
V
VINL
Input Hysteresis
VHYST
Input Leakage
IIN
Input Capacitance
CIN
0.8
V
±1
µA
0.2
VIN = 0 or VDD2
V
15
pF
DIGITAL OUTPUTS (DOUT, SSTRB)
Output Voltage Low
VOL
ISINK = 5mA
Output Voltage High
VOH
ISOURCE = 1mA
Three-State Leakage Current
Three-State Output Capacitance
IL
CS = VDD2
COUT
CS = VDD2
0.4
V
±10
µA
4
V
15
pF
_______________________________________________________________________________________
3
MAX1282/MAX1283
ELECTRICAL CHARACTERISTICS—MAX1282 (continued)
MAX1282/MAX1283
300ksps/400ksps, Single-Supply, 4-Channel,
Serial 12-Bit ADCs with Internal Reference
ELECTRICAL CHARACTERISTICS—MAX1282 (continued)
(VDD1 = VDD2 = +4.5V to +5.5V, COM = GND, fOSC = 6.4MHz, 50% duty cycle, 16 clocks/conversion cycle (400ksps), external
+2.5V at REF, REFADJ = VDD1, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
5.5
V
POWER SUPPLY
Positive Supply Voltage
(Note 9)
Supply Current
VDD1,
VDD2
IVDD1+
IVDD2
4.5
VDD1 =
VDD2 =
5.5V
Normal operating mode (Note 10)
2.5
4.0
Reduced-power mode (Note 11)
1.3
2.0
Fast power-down mode (Note 11)
0.9
1.5
Full power-down mode (Note 11)
Power-Supply Rejection
PSR
VDD1 = VDD2 = 5V ±10%, midscale input
mA
2.0
10
µA
±0.5
±2.0
mV
ELECTRICAL CHARACTERISTICS—MAX1283
(VDD1 = VDD2 = +2.7V to +3.6V, COM = GND, fOSC = 4.8MHz, 50% duty cycle, 16 clocks/conversion cycle (300ksps), external
+2.5V at REF, REFADJ = VDD1, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
±1.0
LSB
±1.0
LSB
Offset Error
±6.0
LSB
Gain Error (Note 3)
±6.0
LSB
DC ACCURACY (Note 1)
12
Resolution
Relative Accuracy (Note 2)
INL
Differential Nonlinearity
DNL
Bits
No missing codes over temperature
Gain-Error Temperature
Coefficient
±1.6
ppm/°C
Channel-to-Channel Offset-Error
Matching
±0.2
LSB
DYNAMIC SPECIFICATIONS (100kHz sine-wave input, 2.5Vp-p, 400ksps, 6.4MHz clock, bipolar input mode)
Signal-to-Noise plus Distortion
Ratio
70
dB
-70
dB
72
dB
fIN1 = 73kHz, fIN2 = 77kHz
76
dB
Channel-to-Channel Crosstalk
(Note 4)
f = 150kHz, VIN = 2.5Vp-p
-78
dB
Full-Power Bandwidth
-3dB point
3
MHz
Full-Linear Bandwidth
SINAD > 68dB
250
kHz
SINAD
Total Harmonic Distortion
THD
Spurious-Free Dynamic Range
SFDR
Intermodulation Distortion
4
IMD
Up to the 5th harmonic
_______________________________________________________________________________________
300ksps/400ksps, Single-Supply, 4-Channel,
Serial 12-Bit ADCs with Internal Reference
(VDD1 = VDD2 = +2.7V to +3.6V, COM = GND, fOSC = 4.8MHz, 50% duty cycle, 16 clocks/conversion cycle (300ksps), external
+2.5V at REF, REFADJ = VDD1, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
CONVERSION RATE
Conversion Time (Note 5)
tCONV
Normal operating mode
Track/Hold Acquisition Time
tACQ
Normal operating mode
3.3
µs
625
Aperture Delay
10
Aperture Jitter
<50
Serial Clock Frequency
fSCLK
Normal operating mode
Duty Cycle
ns
ns
ps
0.5
4.8
MHz
40
60
%
ANALOG INPUTS (CH3–CH0, COM)
Input Voltage Range, Single
Ended and Differential (Note 6)
VREF
Unipolar, VCOM = 0
VCH_
Multiplexer Leakage Current
Bipolar, VCOM or VCH_ = VREF/2,
referenced to COM or CH_
±VREF/2
On/off leakage current, VCH_ = 0 or VDD1
±0.001
Input Capacitance
±1
18
V
µA
pF
INTERNAL REFERENCE
REF Output Voltage
VREF
TA = +25°C
2.480
REF Short-Circuit Current
REF Output Temperature
Coefficient
TC VREF
Load Regulation (Note 7)
4.7
Capacitive Bypass at REFADJ
0.01
REFADJ Output Voltage
For small adjustments, from 1.22V
REFADJ Buffer Disable
Threshold
To power down the internal reference
2.520
mA
±15
ppm/°C
2.0
mV/mA
10
µF
10
µF
1.22
V
±100
mV
1.4
VDD1 - 1.0
2.05
Buffer Voltage Gain
EXTERNAL
REFERENCE
(reference buffer disabled, reference applied to REF)
Buffer Voltage
Gain
REF Input Voltage Range
(Note 8)
V/V
VDD1 +
50mV
200
V
350
320
VREF = 2.500V, fSCLK = 0
V
V/V
2.05
1.0
VREF = 2.500V, fSCLK = fMAX
REF Input Current
V
15
0.1
0 to 0.75mA output load
Capacitive Bypass at REF
REFADJ Input Range
2.500
µA
5
In full power-down mode, fSCLK = 0
DIGITAL INPUTS (DIN, SCLK, CS, SHDN)
Input High Voltage
VINH
Input Low Voltage
VINL
Input Hysteresis
2.0
0.2
VHYST
Input Leakage
IIN
Input Capacitance
CIN
V
0.8
V
±1
VIN = 0 or VDD2
15
V
µA
pF
_______________________________________________________________________________________
5
MAX1282/MAX1283
ELECTRICAL CHARACTERISTICS—MAX1283 (continued)
MAX1282/MAX1283
300ksps/400ksps, Single-Supply, 4-Channel,
Serial 12-Bit ADCs with Internal Reference
ELECTRICAL CHARACTERISTICS—MAX1283 (continued)
(VDD1 = VDD2 = +2.7V to +3.6V, COM = GND, fOSC = 4.8MHz, 50% duty cycle, 16 clocks/conversion cycle (300ksps), external
+2.5V at REF, REFADJ = VDD1, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DIGITAL OUTPUTS (DOUT, SSTRB)
Output Voltage Low
VOL
ISINK = 5mA
Output Voltage High
VOH
ISOURCE = 0.5mA
Three-State Leakage Current
Three-State Output Capacitance
IL
CS = VDD2
COUT
CS = VDD2
0.4
VDD2 - 0.5V
V
V
±10
15
µA
pF
POWER SUPPLY
Positive Supply Voltage
(Note 9)
Supply Current
VDD1,
VDD2
IVDD1 +
IVDD2
2.7
VDD1 =
VDD2 =
3.6V
Normal operating mode (Note 10)
2.5
3.5
Reduced-power mode (Note 11)
1.3
2.0
Fast power-down mode (Note 11)
0.9
1.5
Full power-down mode (Note 11)
Power-Supply Rejection
PSR
3.6
VDD1 = VDD2 = 2.7V to 3.6V, midscale input
V
mA
2.0
10
µA
±0.5
±2.0
mV
TYP
MAX
UNITS
TIMING CHARACTERISTICS—MAX1282
(Figures 1, 2, 5, 6; VDD1 = VDD2 = +4.5V to +5.5V, TA = TMIN to TMAX, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
SCLK Period
tCP
156
ns
SCLK Pulse Width High
tCH
62
ns
SCLK Pulse Width Low
tCL
62
ns
DIN to SCLK Setup
tDS
35
ns
DIN to SCLK Hold
tDH
0
ns
CS Fall to SCLK Rise Setup
tCSS
35
ns
SCLK Rise to CS Rise Hold
tCSH
0
ns
SCLK Rise to CS Fall Ignore
tCSO
35
ns
CS Rise to SCLK Rise Ignore
tCS1
35
ns
SCLK Rise to DOUT Hold
tDOH
CLOAD = 20pF
10
20
SCLK Rise to SSTRB Hold
tSTH
CLOAD = 20pF
10
20
SCLK Rise to DOUT Valid
tDOV
CLOAD = 20pF
SCLK Rise to SSTRB Valid
tSTV
CLOAD = 20pF
CS Rise to DOUT Disable
tDOD
CLOAD = 20pF
10
CS Rise to SSTRB Disable
tSTD
CLOAD = 20pF
10
CS Fall to DOUT Enable
tDOE
CS Fall to SSTRB Enable
tSTE
CS Pulse Width High
tCSW
6
ns
ns
80
ns
80
ns
65
ns
65
ns
CLOAD = 20pF
65
ns
CLOAD = 20pF
65
ns
100
_______________________________________________________________________________________
ns
300ksps/400ksps, Single-Supply, 4-Channel,
Serial 12-Bit ADCs with Internal Reference
(Figures 1, 2, 5, 6; VDD1 = VDD2 = +2.7V to +3.6V, TA = TMIN to TMAX, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SCLK Period
tCP
208
ns
SCLK Pulse Width High
tCH
83
ns
SCLK Pulse Width Low
tCL
83
ns
DIN to SCLK Setup
tDS
45
ns
DIN to SCLK Hold
tDH
0
ns
CS Fall to SCLK Rise Setup
tCSS
45
ns
SCLK Rise to CS Rise Hold
tCSH
0
ns
SCLK Rise to CS Fall Ignore
tCSO
45
ns
CS Rise to SCLK Rise Ignore
tCS1
45
ns
SCLK Rise to DOUT Hold
tDOH
CLOAD = 20pF
13
20
SCLK Rise to SSTRB Hold
tSTH
CLOAD = 20pF
13
20
SCLK Rise to DOUT Valid
tDOV
CLOAD = 20pF
SCLK Rise to SSTRB Valid
tSTV
CLOAD = 20pF
CS Rise to DOUT Disable
tDOD
CLOAD = 20pF
13
CS Rise to SSTRB Disable
tSTD
CLOAD = 20pF
13
CS Fall to DOUT Enable
tDOE
CS Fall to SSTRB Enable
tSTE
CS Pulse Width High
tCSW
ns
ns
100
ns
100
ns
85
ns
85
ns
CLOAD = 20pF
85
ns
CLOAD = 20pF
85
ns
100
ns
Note 1: Tested at VDD1 = VDD2 = VDD(MIN), COM = GND, unipolar single-ended input mode.
Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has
been calibrated.
Note 3: Offset nulled.
Note 4: Ground the “on” channel; sine wave is applied to all “off” channels.
Note 5: Conversion time is defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle.
Note 6: The common-mode range for the analog inputs (CH3–CH0 and COM) is from GND to VDD1.
Note 7: External load should not change during conversion for specified accuracy.
Note 8: ADC performance is limited by the converter’s noise floor, typically 300µVp-p. An external reference below 2.5V compromises the performance of the ADC.
Note 9: Electrical characteristics are guaranteed from VDD1(MIN) = VDD2(MIN) to VDD1(MAX) = VDD2(MIN). For operations beyond
this range, see Typical Operating Characteristics. For guaranteed specifications beyond the limits, contact the factory.
Note 10: AIN = midscale, unipolar mode. MAX1282 tested with 20pF on DOUT, 20pF on SSTRB, and fSCLK = 6.4MHz, 0 to 5V.
MAX1283 tested with same loads, fSCLK = 4.8MHz, 0 to 3V.
Note 11: SCLK = DIN = GND, CS = VDD1.
_______________________________________________________________________________________
7
MAX1282/MAX1283
TIMING CHARACTERISTICS—MAX1283
Typical Operating Characteristics
(MAX1282: VDD1 = VDD2 = 5.0V, fSCLK = 6.4MHz; MAX1283: VDD1 = VDD2 = 3.0V, fSCLK = 4.8MHz; CLOAD = 20pF, 4.7µF capacitor
at REF, 0.01µF capacitor at REFADJ, TA = +25°C, unless otherwise noted.)
INTEGRAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
SUPPLY CURRENT vs. SUPPLY
VOLTAGE (CONVERTING)
DIFFERENTIAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
0.3
0.2
0.1
DNL (LSB)
0
-0.1
0.1
0
-0.1
-0.2
-0.2
-0.4
-0.4
-0.5
0
500 1000 1500 2000 2500 3000 3500 4000 4500
1.5
0
2.5
500 1000 1500 2000 2500 3000 3500 4000 4500
3.0
3.5
4.0
4.5
5.0
5.5
DIGITAL OUTPUT CODE
DIGITAL OUTPUT CODE
SUPPLY VOLTAGE (V)
SUPPLY CURRENT vs. TEMPERATURE
SUPPLY CURRENT vs. SUPPLY
VOLTAGE (STATIC)
SUPPLY CURRENT vs. TEMPERATURE
(STATIC)
2.6
2.4
MAX1283
2.2
1.5
REDP (PD1 = 1, PD0 = 0)
1.0
FASTDP (PD1 = 0, PD0 = 1)
MAX1282 (PD1 = 1, PD0 = 1)
2.0
SUPPLY CURRENT (mA)
MAX1282
2.8
NORMAL OPERATION (PD1 = PD0 = 1)
2.0
SUPPLY CURRENT (mA)
3.0
2.5
MAX1282/3-05
2.5
MAX1282/3-04
3.2
SUPPLY CURRENT (mA)
2.5
2.0
-0.3
-0.3
3.0
MAX1282/3-06
INL (LSB)
0.2
MAX1282/3-03
0.4
SUPPLY CURRENT (mA)
0.3
3.5
MAX1280/1-02
0.5
MAX1280/1-01
0.4
MAX1283 (PD1 = 1, PD0 = 1)
1.5
MAX1282 (PD1 = 1, PD0 = 0)
MAX1283 (PD1 = 1, PD0 = 0)
1.0
0.5
0.5
0
0
MAX1282 (PD1 = 0, PD0 = 1)
MAX1283 (PD1 = 0, PD0 = 1)
2.0
0
20
40
60
80
3.0
3.5
4.0
4.5
5.0
5.5
0
20
40
60
SHUTDOWN CURRENT
vs. SUPPLY VOLTAGE
SHUTDOWN SUPPLY CURRENT
vs. TEMPERATURE
REFERENCE VOLTAGE
vs. SUPPLY VOLTAGE
(PD1 = PD0 = 0)
SUPPLY CURRENT (µA)
3
2
1
MAX1282
2.0
1.5
MAX1283
1.0
4.0
4.5
SUPPLY VOLTAGE (V)
5.0
5.5
5.0
5.5
2.5005
2.5003
2.5001
2.4999
2.4995
0
3.5
100
2.4997
0.5
0
80
MAX1282/3-09
2.5
MAX1282/3-07
4
3.0
-20
TEMPERATURE (°C)
(PD1 = PD0 = 0)
2.5
-40
SUPPLY VOLTAGE (V)
5
8
2.5
100
TEMPERATURE (°C)
MAX1282/3-08
-20
REFERENCE VOLTAGE (V)
-40
SUPPLY CURRENT (µA)
MAX1282/MAX1283
300ksps/400ksps, Single-Supply, 4-Channel,
Serial 12-Bit ADCs with Internal Reference
-40
-20
0
20
40
60
TEMPERATURE (°C)
80
100
2.5
3.0
3.5
4.0
4.5
SUPPLY VOLTAGE (V)
_______________________________________________________________________________________
300ksps/400ksps, Single-Supply, 4-Channel,
Serial 12-Bit ADCs with Internal Reference
REFERENCE VOLTAGE
vs. TEMPERATURE
OFFSET ERROR vs. SUPPLY VOLTAGE
MAX1283
2.4996
2.4994
0
1.0
OFFSET ERROR (LSB)
2.4998
0.5
0
-0.5
2.4992
-1.0
2.4990
-1.5
0
20
40
60
80
2.5
100
3.0
3.5
4.0
4.5
5.0
-1.0
-1.5
-2.5
5.5
-40
-15
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
0.6
60
85
0.5
0
GAIN ERROR (LSB)
0.4
0.2
0
-0.2
MAX1282/3-14
0.8
35
GAIN ERROR vs. TEMPERATURE
GAIN ERROR vs. SUPPLY VOLTAGE
1.0
10
TEMPERATURE (°C)
MAX1282/3-13
-20
GAIN ERROR (LSB)
-40
-0.5
-2.0
-2.0
2.4988
MAX1282/3-12
1.5
OFFSET ERROR (LSB)
MAX1282
OFFSET ERROR vs. TEMPERATURE
0.5
MAX1282/3-11
2.5000
REFERENCE VOLTAGE (V)
2.0
MAX1282/3-10
2.5002
-0.5
-1.0
-0.4
-1.5
-0.6
-0.8
-2.0
-1.0
2.5
3.0
3.5
4.0
4.5
SUPPLY VOLTAGE (V)
5.0
5.5
-40
-15
10
35
60
85
TEMPERATURE (°C)
_______________________________________________________________________________________
9
MAX1282/MAX1283
Typical Operating Characteristics (continued)
(MAX1282: VDD1 = VDD2 = 5.0V, fSCLK = 6.4MHz; MAX1283: VDD1 = VDD2 = 3.0V, fSCLK = 4.8MHz; CLOAD = 20pF, 4.7µF capacitor
at REF, 0.01µF capacitor at REFADJ, TA = +25°C, unless otherwise noted.)
MAX1282/MAX1283
300ksps/400ksps, Single-Supply, 4-Channel,
Serial 12-Bit ADCs with Internal Reference
Pin Description
PIN
NAME
FUNCTION
1
VDD1
Positive Supply Voltage
2–5
CH0–CH3
Sampling Analog Inputs
6
COM
Ground Reference for Analog Inputs. COM sets zero-code voltage in single-ended mode. Must be
stable to ±0.5LSB.
7
SHDN
Active-Low Shutdown Input. Pulling SHDN low shuts down the device, reducing supply current to 2µA (typ).
8
REF
Reference-Buffer Output/ADC Reference Input. Reference voltage for analog-to-digital conversion. In
internal reference mode, the reference buffer provides a 2.500V nominal output, externally adjustable at
REFADJ. In external reference mode, disable the internal buffer by pulling REFADJ to VDD1.
9
REFADJ
Input to the Reference-Buffer Amplifier. To disable the reference-buffer amplifier, connect REFADJ to VDD1.
10
GND
Ground
11
DOUT
Serial-Data Output. Data is clocked out at SCLK’s rising edge. High impedance when CS is high.
12
SSTRB
Serial Strobe Output. SSTRB pulses high for one clock period before the MSB decision. High impedance
when CS is high.
13
DIN
Serial-Data Input. Data is clocked in at SCLK’s rising edge.
14
CS
Active-Low Chip Select. Data will not be clocked into DIN unless CS is low. When CS is high, DOUT and
SSTRB are high impedance.
15
SCLK
Serial-Clock Input. Clocks data in and out of serial interface and sets the conversion speed. (Duty cycle
must be 40% to 60%.)
16
VDD2
Positive Supply Voltage
VDD2
VDD2
DOUT
DOUT
CLOAD
50pF
3k
CLOAD
50pF
GND
GND
a) High-Z to VOH and VOL to VOH
b) High-Z to VOL and VOH to VOL
Figure 1. Load Circuits for Enable Time
10
3k
3k
DOUT
DOUT
CLOAD
70pF
3k
GND
a) VOH to High-Z
Figure 2. Load Circuits for Disable Time
______________________________________________________________________________________
CLOAD
20pF
GND
b) VOL to High-Z
300ksps/400ksps, Single-Supply, 4-Channel,
Serial 12-Bit ADCs with Internal Reference
The MAX1282/MAX1283 ADCs use a successiveapproximation conversion technique and input T/H circuitry to convert an analog signal to a 12-bit digital output. A flexible serial interface provides easy interface to
microprocessors (µPs). Figure 3 shows a functional diagram of the MAX1282/MAX1283.
Pseudo-Differential Input
The equivalent circuit of Figure 4 shows the MAX1282/
MAX1283’s input architecture, which is composed of a
T/H, input multiplexer, input comparator, switchedcapacitor DAC, and reference.
In single-ended mode, the positive input (IN+) is connected to the selected input channel and the negative
input (IN-) is set to COM. In differential mode, IN+ and
IN- are selected from the following pairs: CH0/CH1 and
CH2/CH3. Configure the channels according to Tables
1 and 2.
The MAX1282/MAX1283 input configuration is pseudodifferential because only the signal at IN+ is sampled.
The return side (IN-) is connected to the sampling
capacitor while converting and must remain stable
within ±0.5LSB (±0.1LSB for best results) with respect
to GND during a conversion.
If a varying signal is applied to the selected IN-, its
amplitude and frequency must be limited to maintain
accuracy. The following equations express the relationship between the maximum signal amplitude and its
frequency to maintain ±0.5LSB accuracy. Assuming a
CS
SCLK
DIN
SHDN
CH0
CH1
CH2
CH3
COM
REF
νIN − = (VIN − ) sin(2πft)
The maximum voltage variation is determined by:
max
13
7
2
3
4
5
d( νIN − )
dt
= VIN − 2πf ≤
1LSB
VREF
=
12
t CONV
2 t CONV
A 0.65Vp-p, 60Hz signal at IN- will generate a ±0.5LSB
error when using a +2.5V reference voltage and a
2.5µs conversion time (15 / fSCLK). When a DC reference voltage is used at IN-, connect a 0.1µF capacitor
to GND to minimize noise at the input.
During the acquisition interval, the channel selected as
the positive input (IN+) charges capacitor CHOLD. The
acquisition interval spans three SCLK cycles and ends
on the falling SCLK edge after the input control word’s
last bit has been entered. At the end of the acquisition
interval, the T/H switch opens, retaining charge on
CHOLD as a sample of the signal at IN+. The conversion interval begins with the input multiplexer switching
CHOLD from IN+ to IN-. This unbalances node ZERO at
the comparator’s input. The capacitive DAC adjusts
during the remainder of the conversion cycle to restore
node ZERO to VDD1 / 2 within the limits of 12-bit resolution. This action is equivalent to transferring a
12pF ✕ (VIN+ - VIN-) charge from CHOLD to the binaryweighted capacitive DAC, which in turn forms a digital
representation of the analog input signal.
14
15
GND
INPUT
SHIFT
REGISTER
INT
CLOCK
CH0
CH1
OUTPUT
SHIFT
REGISTER
ANALOG
INPUT
MUX
CAPACITIVE
DAC
REF
CONTROL
LOGIC
11
12
DOUT
SSTRB
CH2
CH3
COM
INPUT
MUX
CHOLD
12pF
ZERO
CSWITCH*
CLOCK
IN
12-BIT
SAR ADC
OUT
REF
6
17k
A ≈ 2.05
+2.500V
Figure 3. Functional Diagram
16
10
9
8
HOLD
1
MAX1282
MAX1283
TRACK
AT THE SAMPLING INSTANT,
THE MUX INPUT SWITCHES FROM
THE SELECTED IN+ CHANNEL TO
THE SELECTED IN- CHANNEL.
VDD1
VDD2
GND
COMPARATOR
RIN
800Ω
6pF
T/H
+1.22V
REFERENCE
REFADJ
sinusoidal signal at IN-, the input voltage is determined
by:
VDD1/2
SINGLE-ENDED MODE: IN+ = CH0–CH3, IN- = COM.
PSEUDO-DIFFERENTIAL MODE: IN+ AND IN- SELECTED FROM
PAIRS OF CH0/CH1 AND CH2/CH3.
*INCLUDES ALL INPUT PARASITICS
Figure 4. Equivalent Input Circuit
______________________________________________________________________________________
11
MAX1282/MAX1283
Detailed Description
MAX1282/MAX1283
300ksps/400ksps, Single-Supply, 4-Channel,
Serial 12-Bit ADCs with Internal Reference
Table 1. Channel Selection in Single-Ended Mode (SGL/DIF = 1)
SEL2
0
SEL1
0
SEL0
1
1
0
1
0
1
0
1
1
0
CH0
+
CH1
CH2
CH3
COM
–
+
–
+
–
+
–
Table 2. Channel Selection in Pseudo-Differential Mode (SGL/DIF = 0)
SEL2
SEL1
SEL0
CH0
CH1
0
0
1
+
–
0
1
0
1
0
1
1
1
0
Track/Hold
The T/H enters its tracking mode on the falling clock
edge after the fifth bit of the 8-bit control word has been
shifted in. It enters its hold mode on the falling clock
edge after the eighth bit of the control word has been
shifted in. If the converter is set up for single-ended
inputs, IN- is connected to COM and the converter
samples the “+” input. If the converter is set up for differential inputs, the difference of [(IN+) - (IN-)] is converted. At the end of the conversion, the positive input
connects back to IN+ and CHOLD charges to the input
signal.
The time required for the T/H to acquire an input signal
is a function of how quickly its input capacitance is
charged. If the input signal’s source impedance is high,
the acquisition time lengthens, and more time must be
allowed between conversions. The acquisition time,
tACQ, is the maximum time the device takes to acquire
the signal and the minimum time needed for the signal
to be acquired. It is calculated by the following equation:
tACQ = 9 ✕ (RS + RIN) ✕ 18pF
where RIN = 800Ω and RS = the source impedance of
the input signal; t ACQ is never less than 400ns
(MAX1282) or 625ns (MAX1283). Note that source
impedances below 2kΩ do not significantly affect the
ADC’s AC performance.
Input Bandwidth
The ADC’s input tracking circuitry has a 6MHz
(MAX1282) or 3MHz (MAX1283) small-signal bandwidth, so it is possible to digitize high-speed transient
12
–
CH2
CH3
+
–
–
+
+
events and measure periodic signals with bandwidths
exceeding the ADC’s sampling rate by using undersampling techniques. To avoid high-frequency signals
being aliased into the frequency band of interest, antialias filtering is recommended.
Analog Input Protection
Internal protection diodes, which clamp the analog input
to VDD1 and GND, allow the channel input pins to swing
from GND - 0.3V to V DD1 + 0.3V without damage.
However, for accurate conversions near full scale, the
inputs must not exceed VDD1 by more than 50mV or be
lower than GND by 50mV.
If the analog input exceeds 50mV beyond the supplies, do not allow the input current to exceed 2mA.
Starting a Conversion
Start a conversion by clocking a control byte into DIN.
With CS low, each rising edge on SCLK clocks a bit from
DIN into the MAX1282/MAX1283’s internal shift register.
After CS falls, the first arriving logic “1” bit defines the
control byte’s MSB. Until this first “start” bit arrives, any
number of logic “0” bits can be clocked into DIN with no
effect. Table 3 shows the control-byte format.
The MAX1282/MAX1283 are compatible with SPI/
QSPI/MICROWIRE devices. For SPI, select the correct
clock polarity and sampling edge in the SPI control registers: set CPOL = 0 and CPHA = 0. MICROWIRE, SPI,
and QSPI all transmit a byte and receive a byte at the
same time. Using the Typical Operating Circuit, the simplest software interface requires only three 8-bit transfers
to perform a conversion (one 8-bit transfer to configure
the ADC, and two more 8-bit transfers to clock out the
______________________________________________________________________________________
300ksps/400ksps, Single-Supply, 4-Channel,
Serial 12-Bit ADCs with Internal Reference
Simple Software Interface
Make sure the CPU’s serial interface runs in master
mode so the CPU generates the serial clock. Choose a
clock frequency from 500kHz to 6.4MHz (MAX1282) or
4.8MHz (MAX1283).
1) Set up the control byte and call it TB1. TB1 should
be in the format: 1XXXXXXX binary, where the Xs
denote the particular channel, selected conversion
mode, and power mode.
2) Use a general-purpose I/O line on the CPU to pull
CS low.
3) Transmit TB1 and, simultaneously, receive a byte
and call it RB1. Ignore RB1.
4) Transmit a byte of all zeros ($00 hex) and, simultaneously, receive byte RB2.
5) Transmit a byte of all zeros ($00 hex) and, simultaneously, receive byte RB3.
6) Pull CS high.
Figure 5 shows the timing for this sequence. Bytes RB2
and RB3 contain the result of the conversion, padded
with three leading zeros, and one trailing zero. The total
conversion time is a function of the serial-clock frequency and the amount of idle time between 8-bit
transfers. To avoid excessive T/H droop, make sure the
total conversion time does not exceed 120µs.
Data Framing
The falling edge of CS does not start a conversion.
The first logic high clocked into DIN is interpreted as a
start bit and defines the first bit of the control byte. A
conversion starts on SCLK’s falling edge, after the eighth
bit of the control byte (the PD0 bit) is clocked into DIN.
The start bit is defined as follows:
The first high bit clocked into DIN with CS low any
time the converter is idle, e.g., after VDD1 and VDD2
are applied.
or
The first high bit clocked into DIN after B6 of a conversion in progress is clocked onto the DOUT pin
(Figure 7).
Once a start bit has been recognized, the current conversion may only be terminated by pulling SHDN low.
The fastest the MAX1282/MAX1283 can run with CS held
low between conversions is 16 clocks per conversion.
Figure 7 shows the serial-interface timing necessary to
perform a conversion every 16 SCLK cycles. If CS is tied
low and SCLK is continuous, guarantee a start bit by first
clocking in 16 zeros.
___________Applications Information
Power-On Reset
Serial Clock
When power is first applied, and if SHDN is not pulled
low, internal power-on reset circuitry activates the
MAX1282/MAX1283 in normal operating mode, ready to
convert with SSTRB = low. After the power supplies stabilize, the internal reset time is 10µs, and no conversions should be performed during this phase. If CS is
low, the first logic 1 on DIN is interpreted as a start bit.
Until a conversion takes place, DOUT shifts out zeros.
Additionally, wait for the reference to stabilize when
using the internal reference.
The external clock not only shifts data in and out, but it
also drives the analog-to-digital conversion steps.
SSTRB pulses high for one clock period after the last bit
of the control byte. Successive-approximation bit decisions are made and appear at DOUT on each of the
next 12 SCLK rising edges, MSB first (Figure 5). SSTRB
and DOUT go into a high-impedance state when CS
goes high; after the next CS falling edge, SSTRB outputs a logic low. Figure 6 shows the detailed serial-interface timings.
The conversion must complete in 120µs or less, or
droop on the sample-and-hold capacitors may degrade
conversion results.
Save power by placing the converter in one of two lowcurrent operating modes or in full power-down between
conversions. Select the power-down mode through bit
1 and bit 0 of the DIN control byte (Tables 3 and 4), or
force the converter into hardware shutdown by driving
SHDN to GND.
The software power-down modes take effect after the
conversion is completed; SHDN overrides any software
power mode and immediately stops any conversion in
progress. In software power-down mode, the serial
interface remains active while waiting for a new control
byte to start conversion and switch to full-power mode.
Digital Output
In unipolar input mode, the output is straight binary
(Figure 13). For bipolar input mode, the output is two’s
complement (Figure 14). Data is clocked out on the rising edge of SCLK in MSB-first format.
Power Modes
______________________________________________________________________________________
13
MAX1282/MAX1283
conversion result). (See Figure 16 for MAX1282/
MAX1283 QSPI connections.)
MAX1282/MAX1283
300ksps/400ksps, Single-Supply, 4-Channel,
Serial 12-Bit ADCs with Internal Reference
Table 3. Control-Byte Format
BIT 7
(MSB)
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
(LSB)
START
SEL2
SEL1
SEL0
UNI/BIP
SGL/DIF
PD1
PD0
BIT
NAME
DESCRIPTION
7(MSB)
START
The first logic 1 bit after CS goes low defines the beginning of the control byte.
6
5
4
SEL2
SEL1
SEL0
These three bits select which of the eight channels are used for the conversion (Tables 1 and 2).
3
UNI/BIP
1 = unipolar, 0 = bipolar. Selects unipolar or bipolar conversion mode. In unipolar mode, an
analog input signal from 0 to VREF can be converted; in bipolar mode, the differential signal can
range from -VREF/2 to +VREF/2.
2
SGL/DIF
1 = single ended, 0 = pseudo-differential. Selects single-ended or pseudo-differential conversions. In single-ended mode, input signal voltages are referred to COM. In pseudo-differential
mode, the voltage difference between two channels is measured (Tables 1 and 2).
1
0(LSB)
PD1
PD0
Select operating mode.
PD1
PD0
Mode
0
0
Full power-down
0
1
Fast power-down
1
0
Reduced power
1
1
Normal operation
Table 4. Software-Controlled Power Modes
TOTAL SUPPLY CURRENT
PD1/PD0
MODE
CIRCUIT SECTIONS*
CONVERTING
(mA)
AFTER
CONVERSION
INPUT COMPARATOR
REFERENCE
00
Full Power-Down
(FULLPD)
2.5
2µA
Off
Off
01
Fast Power-Down
(FASTPD)
2.5
0.9mA
Reduced Power
On
10
Reduced-Power
Mode (REDP)
2.5
1.3mA
Reduced Power
On
11
Normal Operating
2.5
2.0mA
Full Power
On
*Circuit operation between conversions; during conversion all circuits are fully powered up.
Once conversion is completed, the device goes into the
programmed power mode until a new control byte is
written.
The power-up delay is dependent on the power-down
state. Software low-power modes will be able to start
conversion immediately when running at decreased
clock rates (see Power-Down Sequencing). Upon
power-on reset, when exiting software full power-down
mode, or when exiting hardware shutdown, the device
goes immediately into full-power mode and is ready to
14
convert after 2µs when using an external reference.
When using the internal reference, wait for the typical
power-up delay from a full power-down (software or
hardware) as shown in Figure 8.
Software Power-Down
Software power-down is activated using bits PD1 and
PD0 of the control byte. When software power-down is
asserted, the ADC completes the conversion in
______________________________________________________________________________________
300ksps/400ksps, Single-Supply, 4-Channel,
Serial 12-Bit ADCs with Internal Reference
MAX1282/MAX1283
CS
tACQ
SCLK
1
4
8
9
12
16
20
24
SEL SEL SEL UNI/ SGL/
2
1 0 BIP DIF PD2 PD2
DIN
START
SSTRB
RB1
RB2
RB3
B11 B10 B9 B8 B7
B6
B5 B4 B3 B2
B1 B0
DOUT
A/D STATE
IDLE
400ns
CONVERSION
IDLE
(CLK = 6.4MHz)
Figure 5. Single-Conversion Timing
progress and powers down into the specified low-quiescent-current state (2µA, 0.9mA, or 1.3mA).
and power-down modes may attain the lowest power
consumption in other applications.
The first logic 1 on DIN is interpreted as a start bit and
puts the MAX1282/MAX1283 into its full-power mode.
Following the start bit, the data input word or control
byte also determines the next power-down state. For
example, if the DIN word contains PD1 = 0 and PD0 = 1,
a 0.9mA power-down resumes after one conversion.
Table 4 details the four power modes with the corresponding supply current and operating sections.
Using Full Power-Down Mode
Full power-down mode (FULLPD) achieves the lowest
power consumption, up to 1000 conversions per channel per second. Figure 9a shows the MAX1283’s power
consumption for one- or four-channel conversions utilizing full power-down mode (PD1 = PD0 = 0), with the
internal reference and conversion controlled at the
maximum clock speed. A 0.01µF bypass capacitor at
REFADJ forms an RC filter with the internal 17kΩ reference resistor, with a 170µs time constant. To achieve
full 12-bit accuracy, nine time constants or 1.5ms are
required after power-up if the bypass capacitor is fully
discharged between conversions. Waiting this 1.5ms
duration in fast power-down (FASTPD) or reducedpower (REDP) mode instead of in full power-up can further reduce power consumption. This is achieved by
using the sequence shown in Figure 11a.
Figure 9b shows the MAX1283’s power consumption for
one- or four-channel conversions utilizing FULLPD
mode (PD1 = PD0 = 0), with an external reference and
conversion controlled at the maximum clock speed.
One dummy conversion to power up the device is
needed, but no waiting time is necessary to start the
second conversion, thereby achieving lower power
consumption as low as half the full sampling rate.
Hardware Power-Down
Pulling SHDN low places the converter in hardware
power-down. Unlike software power-down mode, the
conversion is not completed; it stops coincidentally with
SHDN being brought low. When returning to normal
operation—from SHDN, with an external reference—the
MAX1282/MAX1283 can be considered fully powered
up within 2µs of actively pulling SHDN high. When
using the internal reference, the conversion should be
initiated only when the reference has settled; its recovery time is dependent on the external bypass capacitors and the time between conversions.
Power-Down Sequencing
The MAX1282/MAX1283 auto power-down modes can
save considerable power when operating at less than
maximum sample rates. Figures 9 and 10 show the
average supply current as a function of the sampling
rate. The following sections discuss the various powerdown sequences. Other combinations of clock rates
______________________________________________________________________________________
15
MAX1282/MAX1283
300ksps/400ksps, Single-Supply, 4-Channel,
Serial 12-Bit ADCs with Internal Reference
CS
tCSW
tCSS
tCP
tCH
tCSO
tCSH
tCS1
tCL
#10
SCLK
tDH
tDS
tDOH
DIN
tDOV
tDOD
tDOE
DOUT
tSTH
tSTV
tSTE
tSTD
SSTRB
Figure 6. Detailed Serial-Interface Timing
Using Fast Power-Down
and Reduced-Power Modes
FASTPD and REDP modes achieve the lowest power
consumption at speeds close to the maximum sampling
rate. Figure 10 shows the MAX1283’s power
consumption in FASTPD mode (PD1 = 0, PD0 = 1),
REDP mode (PD1 = 1, PD0 = 0), and, for comparison,
normal operating mode (PD1 = 1, PD0 = 1). The figure
shows power consumption using the specified powerdown mode, with the internal reference and conversion
controlled at the maximum clock speed. The clock
speed in FASTPD or REDP should be limited to 4.8MHz
for the MAX1282/MAX1283. FULLPD mode may provide
increased power savings in applications where the
MAX1282/MAX1283 are inactive for long periods of time,
but intermittent bursts of high-speed conversions are
required. Figure 11b shows FASTPD and REDP timing.
Internal and External References
The MAX1282/MAX1283 can be used with an internal
or external reference voltage. An external reference
can be connected directly at REF or at the REFADJ pin.
An internal buffer is designed to provide 2.5V at
REF for the MAX1282/MAX1283. The internally trimmed
1.22V reference is buffered with a 2.05 gain.
Internal Reference
The MAX1282/MAX1283’s full-scale range with the internal reference is 2.5V with unipolar inputs and ±1.25V
with bipolar inputs. The internal reference voltage is
adjustable by ±100mV with the circuit in Figure 12.
External Reference
The MAX1282/MAX1283’s external reference can be
placed at the input (REFADJ) or the output (REF) of the
internal reference-buffer amplifier. The REFADJ input
impedance is typically 17kΩ. At REF, the DC input
resistance is a minimum of 18kΩ. During conversion, an
external reference at REF must deliver up to 350µA DC
load current and have 10Ω or less output impedance. If
the reference has a higher output impedance or is
noisy, bypass it close to the REF pin with a 4.7µF
capacitor.
Table 5. Full Scale and Zero Scale
UNIPOLAR MODE
Full Scale
VREF + VCOM
16
BIPOLAR MODE
Zero Scale
VCOM
Positive
Full Scale
Zero
Scale
Negative
Full Scale
VREF / 2
+ VCOM
VCOM
VREF / 2
+ VCOM
______________________________________________________________________________________
300ksps/400ksps, Single-Supply, 4-Channel,
Serial 12-Bit ADCs with Internal Reference
MAX1282/MAX1283
CS
DIN
S CONTROL BYTE 0
1
S CONTROL BYTE 1
8
12
16 1
5
8
S CONTROL BYTE 2
12
16 1
5
S
8
12
ETC
16 1
5
SCLK
B11
DOUT
B6
B0
CONVERSION RESULT 0
B11
B6
B0
CONVERSION RESULT 1
B11
B6
SSTRB
Figure 7. Continuous 16-Clock/Conversion Timing
10k
MAX1283, VDD1 = VDD 2 = 3.0V
CLOAD = 20pF
CODE = 101010000000
1.25
SUPPLY CURRENT (µA)
REFERENCE POWER-UP DELAY (ms)
1.50
1.00
0.75
0.50
1k
4 CHANNELS
100
1 CHANNEL
10
0.25
0
0.0001
1
0.001
0.01
0.1
1
1
10
10
Figure 8. Reference Power-Up Delay vs. Time in Shutdown
1k
10k
100k
Figure 9b. Average Supply Current vs. Conversion Rate with
External Reference in FULLPD
1k
2.5
MAX1283, VDD1 = VDD2 = 3.0V
CLOAD = 20pF
CODE = 101010000000
NORMAL OPERATION
SUPPLY CURRENT (mA)
SUPPLY CURRENT (µA)
100
SAMPLING RATE (sps)
TIME IN SHUTDOWN (s)
100
4 CHANNELS
10
1 CHANNEL
1
2.0
REDP
FASTPD
1.5
1.0
MAX1283, VDD1 = VDD2 = 3.0V
CLOAD = 20pF
CODE = 101010000000
0.5
0.1
1
10
100
1k
10k
SAMPLING RATE (sps)
Figure 9a. Average Supply Current vs. Conversion Rate with
Internal Reference in FULLPD
0
50
100
150
200
250
300
350
SAMPLING RATE (sps)
Figure 10. Average Supply Current vs. Sampling Rate (in
FASTPD, REDP, and Normal Operation)
______________________________________________________________________________________
17
MAX1282/MAX1283
300ksps/400ksps, Single-Supply, 4-Channel,
Serial 12-Bit ADCs with Internal Reference
To use the direct REF input, disable the internal buffer by
connecting REFADJ to VDD1. Using the REFADJ input
makes buffering the external reference unnecessary.
Figure 15 shows the recommended system ground
connections. Establish a single-point analog ground
(star ground point) at GND. Connect all other analog
grounds to the star ground. Connect the digital system
ground to this ground only at this point. For lowestnoise operation, the ground return to the star ground’s
power supply should be low impedance and as short
as possible.
High-frequency noise in the VDD1 power supply may
affect the high-speed comparator in the ADC. Bypass
the supply to the star ground with 0.1µF and 10µF
capacitors close to VDD1 of the MAX1282/MAX1283.
Minimize capacitor lead lengths for best supply-noise
rejection. If the power supply is very noisy, a 10Ω resistor can be connected as a lowpass filter (Figure 15).
Transfer Function
Table 5 shows the full-scale voltage ranges for unipolar
and bipolar modes.
Figure 13 depicts the nominal, unipolar input/output
(I/O) transfer function, and Figure 14 shows the bipolar
I/O transfer function. Code transitions occur halfway
between successive-integer LSB values. Output coding
is binary, with 1LSB = 0.61mV (2.500V / 4096) for unipolar operation, and 1LSB = 0.61mV [(2.500V / 2) / 4096]
for bipolar operation.
Layout, Grounding, and Bypassing
For best performance, use PC boards; wire-wrap
boards are not recommended. Board layout should
ensure that digital and analog signal lines are separated
from each other. Do not run analog and digital (especially clock) lines parallel to one another, or digital lines
underneath the ADC package.
High-Speed Digital Interfacing with QSPI
The MAX1282/MAX1283 can interface with QSPI using
the circuit in Figure 16 (CPOL = 0, CPHA = 0). This
QSPI circuit can be programmed to do a conversion on
each of the four channels. The result is stored in memory
without taxing the CPU, since QSPI incorporates its own
microsequencer.
WAIT 2ms (10 x RC)
0 0
1
DIN
1 0
1
REDP
FULLPD
0 0
1
FULLPD
DUMMY CONVERSION
1.22V
1
1.22V
RE FADJ
0V
γ = RC = 17kΩ x 0.01µF
2.5V
2.5V
REF
0V
2.5mA
IVDD1 + IVDD2
2.5mA
2.5mA
1.3mA OR 0.9mA
0mA
0mA
Figure 11a. Full Power-Down Timing
1 0
1
DIN
REF
1 0
1
REDP
REDP
0 1
1
FASTPD
2.5V (ALWAYS ON)
2.5mA
IVDD1 + IVDD2
2.5mA
0.9mA
2.5mA
0.9mA
1.3mA
Figure 11b. FASTPD and REDP Timing
18
______________________________________________________________________________________
300ksps/400ksps, Single-Supply, 4-Channel,
Serial 12-Bit ADCs with Internal Reference
MAX1282/MAX1283
+3.3V
OUTPUT CODE
24k
MAX1282
MAX1283
510k
100k
12
011 . . . 111
FS = VREF + VCOM
2
011 . . . 110
ZS = VCOM
REFADJ
000 . . . 010
000 . . . 001
0.047µF
-FS =
-VREF
+ VCOM
2
1LSB =
000 . . . 000
VREF
4096
111 . . . 111
111 . . . 110
Figure 12. MAX1282/MAX1283 Reference-Adjust Circuit
OUTPUT CODE
111 . . . 101
100 . . . 001
100 . . . 000
FULL-SCALE
TRANSITION
11 . . . 111
- FS
11 . . . 110
+FS - 1LSB
INPUT VOLTAGE (LSB)
11 . . . 101
*VCOM ≤ VREF / 2
FS = VREF + VCOM
ZS = VCOM
V
1LSB = REF
4096
00 . . . 011
00 . . . 010
00 . . . 001
00 . . . 000
0 1
(COM)
COM*
2
3
FS
INPUT VOLTAGE (LSB)
FS - 3/2LSB
Figure 13. Unipolar Transfer Function, Full Scale (FS) =
VREF + VCOM, Zero Scale (ZS) = VCOM
TMS320LC3x Interface
Figure 17 shows an application circuit to interface the
MAX1282/MAX1283 to the TMS320 in external clock
mode. The timing diagram for this interface circuit is
shown in Figure 18.
Use the following steps to initiate a conversion in the
MAX1282/MAX1283 and to read the results:
1) The TMS320 should be configured with CLKX (transmit clock) as an active-high output clock and CLKR
(TMS320 receive clock) as an active-high input clock.
CLKX and CLKR on the TMS320 are connected to
the MAX1282/MAX1283’s SCLK input.
Figure 14. Bipolar Transfer Function, Full Scale (FS) =
VREF / 2 + VCOM, Zero Scale (ZS) = VCOM
2) The MAX1282/MAX1283’s CS pin is driven low by the
TMS320’s XF_ I/O port to enable data to be clocked
into the MAX1282/MAX1283’s DIN pin.
3) An 8-bit word (1XXXXX11) should be written to the
MAX1282/MAX1283 to initiate a conversion and
place the device into normal operating mode. See
Table 3 to select the proper XXXXX bit values for your
specific application.
4) The MAX1282/MAX1283’s SSTRB output is monitored through the TMS320’s FSR input. A falling
edge on the SSTRB output indicates that the conversion is in progress and data is ready to be received
from the device.
5) The TMS320 reads in 1 data bit on each of the next
16 rising edges of SCLK. These data bits represent
the 12-bit conversion result followed by 4 trailing bits,
which should be ignored.
6) Pull CS high to disable the MAX1282/MAX1283 until
the next conversion is initiated.
______________________________________________________________________________________
19
MAX1282/MAX1283
300ksps/400ksps, Single-Supply, 4-Channel,
Serial 12-Bit ADCs with Internal Reference
Signal-to-Noise Ratio (SNR)
For a waveform perfectly reconstructed from digital
samples, the SNR is the ratio of the full-scale analog
input (RMS value) to the RMS quantization error (residual error). The ideal, theoretical minimum analog-to-digital noise is caused only by quantization error and
results directly from the ADC’s resolution (N bits):
SUPPLIES
+3V
+3V
GND
SNR = (6.02
*R = 10Ω
VDD1
GND
COM
VDD2
+3V
DGND
DIGITAL
CIRCUITRY
MAX1282
MAX1283
✕
N + 1.76)dB
In reality, there are other noise sources besides quantization noise, including thermal noise, reference noise,
clock jitter, etc. Therefore, SNR is calculated by taking
the ratio of the RMS signal to the RMS noise, which
includes all spectral components minus the fundamental, the first five harmonics, and the DC offset.
Signal-to-Noise Plus
Distortion (SINAD)
SINAD is the ratio of the fundamental input frequency’s
RMS amplitude to RMS equivalent of all other ADC output signals:
*OPTIONAL
Figure 15. Power-Supply Grounding Connection
Definitions
Integral Nonlinearity
Integral nonlinearity (INL) is the deviation of the values
from a straight line on an actual transfer function. This
straight line can be a best-straight-line fit or a line
drawn between the endpoints of the transfer function,
once offset and gain errors have been nullified. The
static linearity parameters for the MAX1282/MAX1283
are measured using the best straight-line fit method.
Differential Nonlinearity
Differential nonlinearity (DNL) is the difference between
an actual step width and the ideal value of 1LSB. A
DNL error specification of less than 1LSB guarantees
no missing codes and a monotonic transfer function.
Aperture Width
Aperture width (tAW) is the time the T/H circuit requires
to disconnect the hold capacitor from the input circuit
(for instance, to turn off the sampling bridge, and put
the T/H unit in hold mode).
Aperture Jitter
Aperture jitter (tAJ) is the sample-to-sample variation in
the time between the samples.
Aperture Delay
SINAD (dB) = 20 ✕ log (SignalRMS / NoiseRMS)
Effective Number of Bits (ENOB)
ENOB indicates the global accuracy of an ADC at a
specific input frequency and sampling rate. An ideal
ADC’s error consists only of quantization noise. With an
input range equal to the ADC’s full-scale range, calculate ENOB as follows:
ENOB = (SINAD - 1.76) / 6.02
Total Harmonic Distortion (THD)
THD is the ratio of the RMS sum of the input signal’s
first five harmonics to the fundamental itself. This is
expressed as:

2
2
2
2
2
 V2 + V3 + V4 + V4 + V5 


THD = 20 × log
V1
where V1 is the fundamental amplitude, and V2 through
V5 are the amplitudes of the 2nd- through 5th-order
harmonics.
Spurious-Free Dynamic Range (SFDR)
SFDR is the ratio of the RMS amplitude of the fundamental (maximum signal component) to the RMS value
of the next-largest distortion component.
Aperture delay (tAD) is the time defined between the
rising edge of the sampling clock and the instant when
an actual sample is taken.
20
______________________________________________________________________________________
300ksps/400ksps, Single-Supply, 4-Channel,
Serial 12-Bit ADCs with Internal Reference
10µF
MAX1282/MAX1283
+5V
OR
+3V
+5V
OR
+3V
0.1µF
1 VDD1
VDD2 16
2 CH0
SCLK 15
0.1µF
10µF
(POWER SUPPLIES)
SCK
3 CH1
ANALOG
INPUTS
MAX1282
MAX1283
CSB 14
4 CH2
DIN 13
5 CH3
SSTRB 12
6 COM
DOUT 11
7 SHDN
GND 10
PCS0
MOSI
MC683XX
MISO
VDD1
4.7µF
REFADJ 9
8 REF
0.01µF
(GND)
Figure 16. QSPI Connections
XF
CLKX
CS
SCLK
TMS320LC3x
MAX1282
MAX1283
CLKR
DX
DIN
DR
DOUT
FSR
SSTRB
Figure 17. MAX1282/MAX1283-to-TMS320 Serial Interface
______________________________________________________________________________________
21
MAX1282/MAX1283
300ksps/400ksps, Single-Supply, 4-Channel,
Serial 12-Bit ADCs with Internal Reference
CS
SCLK
START
DIN
SSTRB
SEL2
SEL1
SEL0
UNI/BIP SGI/DIF
PD1
PD0
HIGH IMPEDANCE
DOUT
MSB
B10
B1
B0
HIGH IMPEDANCE
Figure 18. MAX1282/MAX1283-to-TMS320 Serial Interface
Chip Information
Typical Operating Circuit
TRANSISTOR COUNT: 4286
+5V OR
+3V
CH0
0 TO
+2.5V
ANALOG
INPUTS
VDD1
VDD2
MAX1282 GND
MAX1283
CH3
REF
4.7µF
CS
SCLK
REFADJ
DOUT
SSTRB
SHDN
22
CPU
COM
DIN
0.01µF
PROCESS: BiCMOS
VDD
0.1µF
I/O
SCK (SK)
MOSI (SO)
MISO (SI)
VSS
______________________________________________________________________________________
300ksps/400ksps, Single-Supply, 4-Channel,
Serial 12-Bit ADCs with Internal Reference
TSSOP.EPS
Note: The MAX1282/MAX1283 do not have an exposed die pad.
______________________________________________________________________________________
23
MAX1282/MAX1283
________________________________________________________Package Information
MAX1282/MAX1283
300ksps/400ksps, Single-Supply, 4-Channel,
Serial 12-Bit ADCs with Internal Reference
NOTES
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
24 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2000 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.