Dual Bootstrapped, High Voltage MOSFET Driver with Output Disable ADP3419 APPLICATIONS Mobile computing CPU core power converters Multiphase desk-note CPU supplies Single-supply synchronous buck converters Nonsynchronous-to-synchronous drive conversion GENERAL DESCRIPTION The ADP3419 is a dual MOSFET driver optimized for driving two N-channel switching MOSFETs in nonisolated synchronous buck power converters used to power CPUs in portable computers. The driver impedances have been chosen to provide optimum performance in multiphase regulators at up to 25 A per phase. The high-side driver can be bootstrapped relative to the switch node of the buck converter and is designed to accommodate the high voltage slew rate associated with floating high-side gate drivers. The ADP3419 includes an anticross-conduction protection circuit, undervoltage lockout to hold the switches off until the driver has sufficient voltage for proper operation, a crowbar input that turns on the low-side MOSFET independently of the input signal state, and a low-side MOSFET disable pin to provide higher efficiency at light loads. The SD pin shuts off both the high-side and the low-side MOSFETs to prevent rapid output capacitor discharge during system shutdown. VCC BST 5 10 IN 1 UVLO, OVERLAP PROTECTION, SHUTDOWN AND CROWBAR CIRCUITS SD 2 DRVLSD 3 CROWBAR 4 ADP3419 9 DRVH 8 SW 6 DRVL 7 GND Figure 1. GENERAL APPLICATION CIRCUIT 5V VDC 5 FROM CONTROLLER PWM OUTPUT FROM SYSTEM ENABLE CONTROL FROM CONTROLLER FROM CONTROLLER CLAMP OUTPUT VCC 1 IN 2 SD BST 10 ADP3419 DRVH 9 SW 8 3 DRVLSD 4 VOUT CROWBAR DRVL 6 GND 7 04620-0-002 All-in-one synchronous buck driver One PWM signal generates both drives Anticross-conduction protection circuitry Output disable function Crowbar control Synchronous override control Undervoltage lockout SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM 04620-0-001 FEATURES Figure 2. The ADP3419 is specified over the extended commercial temperature range of 0°C to 100°C and is available in a 10-lead MSOP package. ©2008 SCILLC. All rights reserved. January 2008 – Rev. 2 Publication Order Number: ADP3419/D ADP3419 TABLE OF CONTENTS Specifications .....................................................................................3 Low-Side Driver Shutdown .......................................................10 Absolute Maximum Ratings ............................................................5 Low-Side Driver Timeout..........................................................10 ESD Caution ..................................................................................5 Crowbar Function.......................................................................10 Pin Configuration and Function Descriptions .............................6 Application Information ................................................................11 Typical Performance Characteristics..............................................7 Supply Capacitor Selection........................................................11 Theory of Operation.........................................................................9 Bootstrap Circuit ........................................................................11 Undervoltage Lockout ..................................................................9 Power and Thermal Considerations.........................................11 Driver Control Input ....................................................................9 PC Board Layout Considerations .............................................12 Low-Side Driver ............................................................................9 Outline Dimensions........................................................................13 High-Side Driver...........................................................................9 Ordering Guide ...........................................................................13 Overlap Protection Circuit ..........................................................9 REVISION HISTORY 01/08 - Rev 2: Conversion to ON Semiconductor 3/05—Rev. 0 to Rev. A Updated Format ................................................................. Universal Changes to Specifications.................................................................3 4/04—Revision 0: Initial Version Rev. 2 | Page 2 of 13 | www.onsemi.com ADP3419 SPECIFICATIONS VCC = SD = 5 V, BST = 4 V to 26 V, TA = 0°C to 100°C, unless otherwise noted. All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC) methods. Table 1. Parameter Symbol Conditions Min Typ Max Unit 0.8 +1 V V μA ns 1.7 0.8 14 11 32 28 3.3 2.3 35 25 70 60 Ω Ω ns ns ns ns 1.7 0.8 13 11 25 16 350 1 3.3 2.3 30 25 48 30 600 Ω Ω ns ns ns ns ns V 6 V 0.8 325 1.5 600 mA μA 4.25 120 4.5 V mV LOGIC INPUTS (IN, SD, DRVLSD, CROWBAR) Input Voltage High Input Voltage Low Input Current DRVLSD Propagation Delay Time VIH VIL IIN tpdlDRVLSD, 2.0 Inputs = 0 V or 5 V CLOAD = 3 nF, Figure 3 −1 20 tpdhDRVLSD HIGH-SIDE DRIVER Output Resistance, Sourcing Current Output Resistance, Sinking Current Transition Times Propagation Delay Times1 LOW-SIDE DRIVER Output Resistance, Sourcing Current Output Resistance, Sinking Current Transition Times Propagation Delay Times1, 2 SW Transition Timeout2 Zero-Crossing Threshold SUPPLY Supply Voltage Range Supply Current Normal Mode Shutdown Mode Undervoltage Lockout Threshold Undervoltage Lockout Hysteresis3 trDRVH tfDRVH tpdhDRVH tpdlDRVH trDRVL tfDRVL tpdhDRVL tpdlDRVL tSWTO VZC BST − SW = 4.6 V BST − SW = 4.6 V BST − SW = 4.6 V, CLOAD = 3 nF, Figure 4 BST − SW = 4.6 V, CLOAD = 3 nF, Figure 4 BST − SW = 4.6 V, CLOAD = 3 nF, Figure 4 BST − SW = 4.6 V, CLOAD = 3 nF, Figure 4 CLOAD = 3 nF, Figure 4 CLOAD = 3 nF, Figure 4 CLOAD = 3 nF, Figure 4 CLOAD = 3 nF, Figure 4 BST − SW = 4.6 V VCC ISYS(NM) ISYS(SD) 15 150 4.6 ICC + IBST, IN = 0 V or 5 V ICC + IBST, SD = 0 V VCC rising VCC falling 1 3.8 50 For propagation delays, tpdh refers to the specified signal going high, and tpdl refers to the signal going low with transitions measured at 50%. The turn-on of DRVL is initiated after IN goes low by either SW crossing a ~1 V threshold or by expiration of tSWTO. 3 Guaranteed by characterization, not production tested. 2 Rev. 2 | Page 3 of 13 | www.onsemi.com ADP3419 IN 2.0V DRVLSD 0.8V tpdhDRVLSD 04620-0-003 tpdlDRVLSD DRVL Figure 3. Output Disable Timing Diagram (Timing is Referenced to the 90% and 10% Points Unless Otherwise Noted) IN tpdlDRVL tfDRVL trDRVL tpdlDRVH DRVL tpdhDRVH VTH VTH tpdhDRVL SW ≤ tSWTO 1V Figure 4. Nonoverlap Timing Diagram (Timing is Referenced to the 90% and 10% Points Unless Otherwise Noted) Rev. 2 | Page 4 of 13 | www.onsemi.com 04620-0-004 DRVH-SW tfDRVH trDRVH ADP3419 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter VCC BST BST to SW SW DRVH DRVL All Other Inputs and Outputs θJA 2-Layer Board 4-Layer Board Operating Ambient Temperature Range Junction Temperature Range Storage Temperature Range Lead Temperature Range Soldering (10 s) Vapor Phase (60 s) Infrared (15 s) Rating −0.3 V to +7 V −0.3 V to +30 V −0.3 V to +7 V −3 V to +25 V SW − 0.3 V to BST + 0.3 V −0.3 V to VCC + 0.3 V −0.3 V to VCC + 0.3 V Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Unless otherwise specified, all voltages are referenced to GND. 340°C/W 220°C/W 0°C to 100°C 0°C to 150°C −65°C to +150°C 300°C 215°C 220°C ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. 2 | Page 5 of 13 | www.onsemi.com ADP3419 IN 1 SD 2 DRVLSD 3 CROWBAR 4 VCC 5 ADP3419 TOP VIEW (Not to Scale) 10 BST 9 DRVH 8 SW 7 GND 6 DRVL 04620-0-018 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 5. Pin Configuration Table 3. Pin Function Descriptions Pin No. 1 Mnemonic IN Function Logic Level PWM Input. This pin has primary control of the drive outputs. In normal operation, pulling this pin low turns on the low-side driver; pulling it high turns on the high-side driver. 2 SD 3 DRVLSD 4 5 6 7 8 CROWBAR VCC DRVL GND SW 9 10 DRVH BST Shutdown Input. When low, this pin disables normal operation, forcing DRVH and DRVL low. Synchronous Rectifier Shutdown Input. When low, DRVL is forced low; when high, DRVL is enabled and controlled by IN and by the adaptive overlap protection control circuitry. Crowbar Input. When high, DRVL is forced high regardless of the high-side MOSFET switch condition. Input Supply. This pin should be bypassed to GND with a 4.7 μF or larger ceramic capacitor. Synchronous Rectifier Drive. Output drive for the lower (synchronous rectifier) MOSFET. Ground. This pin should be closely connected to the source of the lower MOSFET. Switch Node Input. This pin is connected to the buck-switching node, close to the upper MOSFET’s source. It is the floating return for the upper MOSFET drive signal. It is also used to monitor the switched voltage to prevent turn-on of the lower MOSFET until the voltage is below ~1 V. Buck Drive. Output drive for the upper (buck) MOSFET. Upper MOSFET Floating Bootstrap Supply. A capacitor connected between the BST and SW pins holds this bootstrapped voltage for the high-side MOSFET as it is switched. Rev. 2 | Page 6 of 13 | www.onsemi.com ADP3419 TYPICAL PERFORMANCE CHARACTERISTICS 25 VCC = 5V CLOAD = 3nF TIME (ns) 20 RISE TIME 15 FALLTIME 10 0 0 Figure 6. DRVH Rise and DRVL Fall Times CH1 = IN, CH2 = DRVH, CH3 = DRVL 25 50 75 100 JUNCTION TEMPERATURE (°C) 125 04620-0-008 5 Figure 9. DRVL Rise and Fall Times vs. Temperature 80 VCC = 5V TA = 25°C RISE TIME (ns) 60 DRVH 40 DRVL 0 0 2 4 6 8 10 LOAD CAPACITANCE (nF) Figure 7. DRVH Fall and DRVL Rise Times CH1 = IN, CH2 = DRVH, CH3 = DRVL 04620-0-009 20 Figure 10. DRVH and DRVL Rise Times vs. Load Capacitance 25 25 VCC = 5V TA = 25°C VCC = 5V CLOAD = 3nF 20 DRVH 20 FALL TIME (ns) 15 FALLTIME 10 5 10 0 25 50 75 100 JUNCTION TEMPERATURE (°C) 125 Figure 8. DRVH Rise and Fall Times vs. Temperature 0 0 2 4 6 LOAD CAPACITANCE (nF) 8 10 Figure 11. DRVH and DRVL Fall Times vs. Load Capacitance Rev. 2 | Page 7 of 13 | www.onsemi.com 04620-0-010 0 DRVL 15 5 04620-0-007 TIME (ns) RISE TIME ADP3419 50 50 VCC = 5V CLOAD = 3nF 40 ISYS CURRENT (mA) 30 tpdhDRVL 20 30 20 25 50 75 100 JUNCTION TEMPERATURE (°C) 125 0 Figure 12. DRVH and DRVL tpdh vs. Temperature 200 400 600 800 IN FREQUENCY (kHz) 1000 125 Figure 15. Supply Current vs. Frequency 40 1.5 VCC = 5V CLOAD = 3nF 1200 0 04620-0-011 0 04620-0-014 10 10 04620-0-015 TIME (ns) 40 0 VCC = BST = 5V CLOAD = 3nF TA = 25°C tpdhDRVH VCC = 5V CLOAD = 3nF tpdlDRVH ISYS CURRENT (mA) TIME (ns) 30 20 tpdlDRVL 1.0 0.5 0 0 25 50 75 100 JUNCTION TEMPERATURE (°C) 125 04620-0-012 10 0 0 Figure 13. DRVH and DRVL tpdl vs. Temperature 40 20 0 1 2 3 INPUT VOLTAGE (V) 4 5 04620-0-013 PEAK INPUT CURRENT (μA) VCC = 5V CLOAD = 3nF TA = 25°C 60 0 50 75 100 JUNCTION TEMPERATURE (°C) Figure 16. Supply Current vs. Temperature 100 80 25 Figure 14. IN Pin Input Current vs. Input Voltage Rev. 2 | Page 8 of 13 | www.onsemi.com ADP3419 THEORY OF OPERATION The ADP3419 is a dual MOSFET driver optimized for driving two N-channel MOSFETs in a synchronous buck converter topology. A single PWM input signal is all that is required to properly drive the high-side and the low-side MOSFETs. Each driver is capable of driving a 3 nF load at speeds up to 1 MHz. A more detailed description of the ADP3419 and its features follows. Refer to the detailed block diagram in Figure 17. 5V VDCIN D1 VCC 5 ADP3419 UVLO AND BIAS CROWBAR 4 IN 1 BST 10 RBST CBST + DRVH 9 Q1 SD 2 OVERLAP PROTECTION AND TIME-OUT CIRCUIT 8 SW DRVL Q2 3 The high-side driver is designed to drive a floating low RDS(ON) N-channel MOSFET. The bias voltage for the high-side driver is developed by an external bootstrap supply circuit, which is connected between the BST and SW pins. The bootstrap circuit comprises a diode, D1, and bootstrap capacitor, CBST. When the ADP3419 is starting up, the SW pin is at ground, so the bootstrap capacitor charges up to VCC through D1. Once the supply voltage ramps up and exceeds the UVLO threshold, the driver is enabled. When IN goes high, the high-side driver begins to turn on the high-side MOSFET (Q1) by transferring charge from CBST. As Q1 turns on, the SW pin rises up to VDCIN, forcing the BST pin to VDCIN + VC(BST), which is enough gate-to-source voltage to hold Q1 on. To complete the cycle, Q1 is switched off by pulling the gate down to the voltage at the SW pin. When the low-side MOSFET (Q2) turns on, the SW pin is pulled to ground. This allows the bootstrap capacitor to charge up to VCC again. When the driver is enabled, the driver’s output is in phase with the IN pin. Table 4 shows the relationship between DRVH and the different control inputs of the ADP3419. VCC 6 DRVLSD HIGH-SIDE DRIVER OVERLAP PROTECTION CIRCUIT 7 04620-0-016 GND Figure 17. Detailed Block Diagram of the ADP3419 UNDERVOLTAGE LOCKOUT The undervoltage lockout (UVLO) circuit holds both MOSFET driver outputs low during VCC supply ramp-up. The UVLO logic becomes active and in control of the driver outputs at a supply voltage of no greater than 1.5 V. The UVLO circuit waits until the VCC supply has reached a voltage high enough to bias logic level MOSFETs fully on before releasing control of the drivers to the control pins. DRIVER CONTROL INPUT The driver control input (IN) is connected to the duty ratio modulation signal of a switch-mode controller. IN can be driven by 2.5 V to 5.0 V logic. The output MOSFETs are driven so that the SW node follows the polarity of IN. LOW-SIDE DRIVER The low-side driver is designed to drive a ground-referenced low RDS(ON) N-channel synchronous rectifier MOSFET. The bias to the low-side driver is internally connected to the VCC supply and GND. Once the supply voltage ramps up and exceeds the UVLO threshold, the driver is enabled. When the driver is enabled, the driver’s output is 180° out of phase with the IN pin. Table 4 shows the relationship between DRVL and the different control inputs of the ADP3419. The overlap protection circuit prevents both main power switches, Q1 and Q2, from being on at the same time. This is done to prevent shoot-through currents from flowing through both power switches and the associated losses that can occur during their on-off transitions. The overlap protection circuit accomplishes this by adaptively controlling the delay from Q1’s turn-off to Q2’s turn-on, and the delay from Q2’s turn-off to Q1’s turn-on. To prevent the overlap of the gate drives during Q1’s turn-off and Q2’s turn-on, the overlap circuit monitors the voltage at the SW pin and DRVH pin. When IN goes low, Q1 begins to turn off. The overlap protection circuit waits for the voltage at the SW and DRVH pins to both fall below 1.6 V. Once both of these conditions are met, Q2 begins to turn on. Using this method, the overlap protection circuit ensures that Q1 is off before Q2 turns on, regardless of variations in temperature, supply voltage, gate charge, and drive current. There is, however, a timeout circuit that overrides the waiting period for the SW and DRVH pins to reach 1.6 V. After the timeout period has expired, DRVL is asserted high regardless of the SW and DRVH voltages. In the opposite case, when IN goes high, Q2 begins to turn off after a propagation delay. The overlap protection circuit waits for the voltage at DRVL to fall below 1.6 V, after which DRVH is asserted high and Q1 turns on. Rev. 2 | Page 9 of 13 | www.onsemi.com ADP3419 LOW-SIDE DRIVER SHUTDOWN CROWBAR FUNCTION The low-side driver shutdown DRVLSD allows a control signal to shut down the synchronous rectifier. Under light load conditions, DRVLSD should be pulled low before the polarity reversal of the inductor current to maximize light load conversion efficiency. DRVLSD can also be pulled low for reverse voltage protection purposes. In addition to the internal low-side drive time-out circuit, the ADP3419 includes a CROWBAR input pin to provide a means for additional overvoltage protection. When CROWBAR goes high, the ADP3419 turns off DRVH and turns on DRVL. The crowbar logic overrides the overlap protection circuit, the shutdown logic, the DRVLSD logic, and the UVLO protection on DRVL. Thus, the crowbar function maximizes the overvoltage protection coverage in the application. The CROWBAR can be either driven by the CLAMP pin of buck controllers, such as the ADP3422, ADP3203, ADP3204, or ADP3205, or controlled by an independent overvoltage monitoring circuit. When DRVLSD is low, the low-side driver stays low. When DRVLSD is high, the low-side driver is enabled and controlled by the driver signals, as previously described. LOW-SIDE DRIVER TIMEOUT In normal operation, the DRVH signal tracks the IN signal and turns off the Q1 high-side switch with a few 10 ns delay (tpdlDRVH) following the falling edge of the input signal. When Q1 is turned off, DRVL is allowed to go high, Q2 turns on, and the SW node voltage collapses to zero. But in a fault condition such as a high-side Q1 switch drain-source short circuit, the SW node cannot fall to zero, even when DRVH goes low. The ADP3419 has a timer circuit to address this scenario. Every time the IN goes low, a DRVL on-time delay timer is triggered. If the SW node voltage does not trigger a low-side turn-on, the DRVL on-time delay circuit does it instead, when it times out with tSW(TO) delay. If Q1 is still turned on, that is, its drain is shorted to the source, Q2 turns on and creates a direct short circuit across the VDCIN voltage rail. The crowbar action causes the fuse in the VDCIN current path to open. The opening of the fuse saves the load (CPU) from potential damage that the highside switch short circuit could have caused. Table 4. ADP3419 Truth Table CROWBAR UVLO SD DRVLSD IN DRVH DRVL L L L L L L H H L L L L L H L H H H H H L * * * H H L L * * * * H L H L * * * * H L H L L L L L L H L L L L H H * = Don’t Care. Rev. 2 | Page 10 of 13 | www.onsemi.com ADP3419 APPLICATION INFORMATION SUPPLY CAPACITOR SELECTION POWER AND THERMAL CONSIDERATIONS For the supply input (VCC) of the ADP3419, a local bypass capacitor is recommended to reduce the noise and to supply some of the peak currents drawn. Use a 10 μF or 4.7 μF multilayer ceramic (MLC) capacitor. MLC capacitors provide the best combination of low ESR and small size, and can be obtained from the following vendors. The major power consumption of the ADP3419-based driver circuit is from the dissipation of MOSFET gate charge. It can be estimated as Table 5. Vendor Murata Taiyo-Yuden Tokin Part Number GRM235Y5V106Z16 EMK325F106ZF C23Y5V1C106ZP Web Address www.murata.com www.t-yuden.com www.tokin.com Keep the ceramic capacitor as close as possible to the ADP3419. BOOTSTRAP CIRCUIT The bootstrap circuit uses a charge storage capacitor (CBST) and a Schottky diode (D1), as shown in Figure 17. Selection of these components can be done after the high-side MOSFET has been chosen. The bootstrap capacitor must have a voltage rating that is able to handle at least 5 V more than the maximum supply voltage. The capacitance is determined by C BST = Q HSGATE (1) ΔV BST where: QHSGATE is the total gate charge of the high-side MOSFET. ΔVBST is the voltage droop allowed on the high-side MOSFET drive. For example, two IRF7811 MOSFETs in parallel have a total gate charge of about 36 nC. For an allowed droop of 100 mV, the required bootstrap capacitance is 360 nF. A good quality ceramic capacitor should be used, and derating for the significant capacitance drop of MLCs at high temperature must be applied. In this example, selection of 470 nF or even 1 μF would be recommended. A Schottky diode is recommended for the bootstrap diode due to its low forward drop, which maximizes the drive available for the high-side MOSFET. The bootstrap diode must also be able to handle at least 5 V more than the maximum battery voltage. The average forward current can be estimated by I F ( AVG) = QHSGATE × f MAX (2) where fMAX is the maximum switching frequency of the controller. PMAX ≈ VCC × (Q HSGATE + Q LSGATE ) × f MAX (3) where: VCC is the supply voltage 5 V. fMAX is the highest switching frequency. QHSGATE and QLSGATE are the total gate charge of high-side and low-side MOSFETs, respectively. For example, the ADP3419 drives two IRF7821 high-side MOSFETs and two IRF7832 low-side MOSFETs. According to the MOSFET data sheets, QHSGATE = 18.6 nC and QLSGATE = 68 nC. Given that fMAX is 300 kHz, PMAX would be about 130 mW. Part of this power consumption generates heat inside the ADP3419. The temperature rise of the ADP3419 against its environment is estimated as ΔT ≈ θ JA × PMAX × η (4) where θJA is ADP3419’s thermal resistance from junction to air, given in the absolute maximum ratings as 220°C/W for a 4-layer board. The total MOSFET drive power dissipates in the output resistance of ADP3419 and in the MOSFET gate resistance as well. η represents the ratio of power dissipation inside the ADP3419 over the total MOSFET gate driving power. For normal applications, a rough estimation for η is 0.7. A more accurate estimation can be calculated using Q HSGATE 0.5 × R1 0.5 × R2 ⎞ ⎛ ×⎜ + ⎟ Q HSGATE + Q LSGATE ⎝ R1 + R HSGATE + R R2 + RHSGATE ⎠ (5) Q LSGATE 0.5 × R4 ⎞ ⎛ 0.5 × R3 + ×⎜ + ⎟ Q HSGATE + Q LSGATE ⎝ R3 + RLSGATE R4 + R LSGATE ⎠ η≈ where: R1 and R2 are the output resistances of the high-side driver: R1 = 1.7 (DRVH − BST), R2 = 0.8 (DRVH − SW). R3 and R4 are the output resistances of the low-side driver: R3 = 1.7 (DRVL − VCC), R4 = 0.8 (DRVL − GND). R is the external resistor between the BST pin and the BST capacitor. RHSGATE and RLSGATE are gate resistances of high-side and low-side MOSFETs, respectively. Rev. 2 | Page 11 of 13 | www.onsemi.com ADP3419 PC BOARD LAYOUT CONSIDERATIONS Use the following general guidelines when designing printed circuit boards. Figure 18 gives an example of the typical land patterns based on the guidelines given here. • • • The VCC bypass capacitor should be located as close as possible to the VCC and GND pins. Place the ADP3419 and bypass capacitor on the same layer of the board, so that the PCB trace between the ADP3419 VCC pin and the MLC capacitor does not contain any via. An ideal location for the bypass MLC capacitor is near Pin 5 and Pin 6 of the ADP3419. • Fast switching of the high-side MOSFET can reduce switching loss. However, EMI problems can arise due to the severe ringing of the switch node voltage. Depending on the character of the low-side MOSFET, a very fast turn-on of the high-side MOSFET may falsely turn on the low-side MOSFET through the dv/dt coupling of its Miller capacitance. Therefore, when fast turn-on of the high-side MOSFET is not required by the application, a resistor of about 1 Ω to 2 Ω can be placed between the BST pin and the BST capacitor to limit the turn-on speed of the high-side MOSFET. D1 RBST High frequency switching noise can be coupled into the VCC pin of the ADP3419 via the BST diode. Therefore, do not connect the anode of the BST diode to the VCC pin with a short trace. Use a separate via or trace to connect the anode of the BST diode directly to the VCC 5 V power rail. It is best to have the low-side MOSFET gate close to the DRVL pin; otherwise, use a short and very thick PCB trace between the DRVL pin and the low-side MOSFET gate. CBST TO SWITCH NODE SHORT, THICK TRACE TO THE GATES OF LOW-SIDE MOSFETS CVCC Figure 18. External Component Placement Example Rev. 2 | Page 12 of 13 | www.onsemi.com 04620-0-017 Assuming that R = 0 and that RHSGATE = RLSGATE = 0.5, Equation 5 gives a value of η = 0.71. Based on Equation 4, the estimated temperature rise in this example is about 22°C. ADP3419 OUTLINE DIMENSIONS 3.00 BSC 6 10 4.90 BSC 3.00 BSC 1 5 PIN 1 0.50 BSC 0.95 0.85 0.75 1.10 MAX 0.15 0.00 0.27 0.17 SEATING PLANE 0.23 0.08 8° 0° 0.80 0.60 0.40 COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-187-BA Figure 19. 10-Lead Mini Small Outline Package [MSOP] (RM-10) Dimensions shown in millimeters ORDERING GUIDE Model ADP3419JRM-REEL ADP3419JRMZ-REEL1 1 Temperature Range 0°C to 100°C 0°C to 100°C Package Description 10-Lead Mini Small Outline Package (MSOP) 10-Lead Mini Small Outline Package (MSOP) Package Option RM-10 RM-10 Quantity per Reel 3000 3000 Branding P9A P9B Z = Pb-free part. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: [email protected] N. American Technical Support: 800-282-9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81-3-5773-3850 Rev. 2 | Page 13 of 13 | www.onsemi.com ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative