Freescale MC68HSC05C8A Microcontroller Datasheet

MC68HC05C8A
MC68HCL05C8A
MC68HSC05C8A
Data Sheet
M68HC05
Microcontrollers
MC68HC05C8A
Rev. 5.1
08/2005
freescale.com
MC68HC05C8A
MC68HCL05C8A
MC68HSC05C8A
Technical Data
To provide the most up-to-date information, the revision of our documents on the World Wide Web will be
the most current. Your printed copy may be an earlier revision. To verify you have the latest information
available, refer to:
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The following revision history table summarizes changes contained in this document. For your
convenience, the page number designators have been linked to the appropriate location.
Revision History
Date
Revision
Level
April, 2002
5.0
Corrected World Wide Web address and qualification status
August, 2005
5.1
Updated to meet Freescale identity guidelines.
Description
Page
Number(s)
N/A
Throughout
MC68HC05C8A • MC68HCL05C8A • MC68HSC05C8A Data Sheet, Rev. 5.1
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Revision History
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List of Chapters
Chapter 1 General Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Chapter 2 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Chapter 3 Central Processor Unit (CPU). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Chapter 4 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Chapter 5 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Chapter 6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Chapter 7 Input/Output (I/O) Ports. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Chapter 8 Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Chapter 9 Serial Communications Interface (SCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Chapter 10 Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Chapter 11 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
Chapter 12 Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Chapter 13 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Chapter 14 Mechanical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Chapter 15 Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Appendix A MC68HCL05C8A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105
Appendix B MC68HSC05C8A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
Appendix C M68HC05Cx Family Feature Comparisons . . . . . . . . . . . . . . . . . . . . . . . . . . 113
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List of Chapters
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Table of Contents
Chapter 1
General Description
1.1
1.2
1.3
1.4
1.4.1
1.4.2
1.4.3
1.4.4
1.4.5
1.4.6
1.4.7
1.4.8
1.4.9
1.4.10
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Mask Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VDD and VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IRQ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OSC1 and OSC2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TCAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TCMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port A (PA0–PA7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port B (PB0–PB7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port C (PC0–PC7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port D (PD0–PD5 and PD7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13
13
15
15
19
19
19
19
19
19
19
19
19
20
Chapter 2
Memory
2.1
2.2
2.3
2.4
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Read-Only Memory (ROM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ROM Security Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Random-Access Memory (RAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
21
21
21
21
Chapter 3
Central Processor Unit (CPU)
3.1
3.2
3.2.1
3.2.2
3.2.3
3.2.4
3.2.5
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
27
27
28
28
28
28
28
Chapter 4
Interrupts
4.1
4.2
4.3
4.4
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Hardware Controlled Interrupt Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Software Interrupt (SWI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External Interrupt (IRQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
29
29
30
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4.5
4.6
4.7
Timer Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Serial Communications Interrupt (SCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Serial Peripheral Interrupt (SPI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Chapter 5
Resets
5.1
5.2
5.3
5.4
5.4.1
5.4.2
5.4.3
5.4.4
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power-On Reset (POR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RESET Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Computer Operating Properly (COP) Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Resetting the COP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
COP During Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
COP During Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
COP During Self-Check Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
33
33
33
33
33
33
34
34
Chapter 6
Low-Power Modes
6.1
6.2
6.3
6.4
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stop Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
35
36
36
36
Chapter 7
Input/Output (I/O) Ports
7.1
7.2
7.3
7.4
7.5
7.6
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port D. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input/Output Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
37
37
37
38
38
38
Chapter 8
Timer
8.1
8.2
8.3
8.4
8.5
8.6
8.7
8.8
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Compare Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Capture Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer During Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer During Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
41
41
43
44
45
46
46
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Chapter 9
Serial Communications Interface (SCI)
9.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.2
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.3
SCI Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.4
SCI Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.4.1
Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.4.1.1
Character Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.4.1.2
Character Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.4.1.3
Break Characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.4.1.4
Idle Characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.4.1.5
Transmitter Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.4.2
Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.4.2.1
Character Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.4.2.2
Character Reception. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.4.2.3
Receiver Wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.4.2.4
Receiver Noise Immunity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.4.2.5
Framing Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.4.2.6
Receiver Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.5
SCI Input/Output (I/O) Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.5.1
SCI Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.5.2
SCI Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.5.3
SCI Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.5.4
SCI Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.5.5
Baud Rate Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
47
47
47
48
48
48
48
48
48
50
50
50
50
50
52
52
52
52
52
53
54
55
57
Chapter 10
Serial Peripheral Interface (SPI)
10.1
10.2
10.3
10.3.1
10.3.2
10.3.3
10.3.4
10.4
10.5
10.5.1
10.5.2
10.5.3
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Master In Slave Out (MISO). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Master Out Slave In (MOSI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial Clock (SCK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Slave Select (SS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial Peripheral Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial Peripheral Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial Peripheral Data I/O Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
59
59
59
59
59
60
60
61
62
63
64
65
Chapter 11
Operating Modes
11.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.2 User Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.3 Self-Check Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.3.1
Self-Check Tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.3.2
Self-Check Results. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
67
67
68
68
70
MC68HC05C8A • MC68HCL05C8A • MC68HSC05C8A Data Sheet, Rev. 5.1
Freescale Semiconductor
9
Table of Contents
Chapter 12
Instruction Set
12.1
12.2
12.2.1
12.2.2
12.2.3
12.2.4
12.2.5
12.2.6
12.2.7
12.2.8
12.3
12.3.1
12.3.2
12.3.3
12.3.4
12.3.5
12.4
12.5
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Indexed, No Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Indexed, 8-Bit Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Indexed, 16-Bit Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Relative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Instruction Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Register/Memory Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Read-Modify-Write Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Jump/Branch Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bit Manipulation Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
71
71
71
71
71
72
72
72
72
72
73
73
74
75
76
76
77
82
Chapter 13
Electrical Specifications
13.1
13.2
13.3
13.4
13.5
13.6
13.7
13.8
13.9
13.10
13.11
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.0-V DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3-V DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.0-V Control Timing
.......................................................
3.3-V Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.0-V Serial Peripheral Interface Timing
........................................
3.3-V Serial Peripheral Interface Timing
........................................
85
85
85
86
86
87
88
90
91
94
95
Chapter 14
Mechanical Specifications
14.1
14.2
14.3
14.4
14.5
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
40-Pin Plastic Dual In-Line (DIP) Package (Case 711-03) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
42-Pin Plastic Shrink Dual In-Line (SDIP) Package (Case 858-01). . . . . . . . . . . . . . . . . . . . . 100
44-Lead Plastic Leaded Chip Carrier (PLCC) (Case 777-02) . . . . . . . . . . . . . . . . . . . . . . . . . 101
44-Lead Quad Flat Pack (QFP) (Case 824A-01) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
MC68HC05C8A • MC68HCL05C8A • MC68HSC05C8A Data Sheet, Rev. 5.1
10
Freescale Semiconductor
Chapter 15
Ordering Information
15.1
15.2
15.3
15.4
15.5
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MCU Ordering Forms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Application Program Media . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ROM Program Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ROM Verification Units (RVUs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
103
103
103
104
104
Appendix A
MC68HCL05C8A
A.1
A.2
A.3
A.4
A.5
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Low-Power Operating Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.5-V to 3.6-V DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.8-V to 2.4-V DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Low-Power Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
105
105
105
106
106
Appendix B
MC68HSC05C8A
B.1
B.2
B.3
B.4
B.5
B.6
B.7
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
High-Speed Operating Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.5-V to 5.5-V Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4-V to 3.6-V Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.5-V to 5.5-V High-Speed SPI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4-V to 3.6-V High-Speed SPI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
107
107
108
109
110
111
112
Appendix C
M68HC05Cx Family Feature Comparisons
MC68HC05C8A • MC68HCL05C8A • MC68HSC05C8A Data Sheet, Rev. 5.1
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11
Table of Contents
MC68HC05C8A • MC68HCL05C8A • MC68HSC05C8A Data Sheet, Rev. 5.1
12
Freescale Semiconductor
Chapter 1
General Description
1.1 Introduction
The MC68HC05C8A is an enhanced version of the MC68HC05C8. It includes keyboard scanning logic,
a high current pin, a computer operating properly (COP) watchdog timer, and read-only memory (ROM)
security feature.
1.2 Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
M68HC05 core
Single 3.0- to 5.5-volt supply
Available packages:
– 40-pin dual in-line (DIP)
– 42-pin plastic shrink dual in-line (SDIP)
– 44-lead plastic leaded chip carrier (PLCC)
– 44-lead quad flat pack (QFP)
On-chip oscillator for crystal/ceramic resonator
Fully static operation
7744 bytes of user ROM
ROM security feature
176 bytes of on-chip random-access memory (RAM)
Asynchronous serial communications interface (SCI) system
Synchronous serial peripheral interface (SPI) system
16-bit capture/compare timer system
Computer operating properly (COP) watchdog timer
24 bidirectional input/output (I/O) lines
Seven input-only lines
User mode
Self-check mode
Power-saving stop and wait modes
High current sink and source on one port pin (PC7)
Mask selectable external interrupt sensitivity
Mask-programmable keyscan logic
MC68HC05C8A • MC68HCL05C8A • MC68HSC05C8A Data Sheet, Rev. 5.1
Freescale Semiconductor
13
General Description
PA0
PA1
DATA DIRECTION A
USER ROM AND USER VECTORS — 7744 BYTES
PORT A
SELF-CHECK ROM — 240 BYTES
PA2
PA3
PA4
PA5
PA6
PA7
SRAM — 176 BYTES
PB0*
ALU
M68HC05 CPU
PB2*
PORT B
CPU
CONTROL
DATA DIRECTION B
IRQ
RESET
PB1*
PB3*
PB4*
PB5*
PB6*
PB7*
CPU REGISTERS
ACCUMULATOR
PC0
INDEX REGISTER
0
0
0
STACK POINTER
OSCILLATOR
÷2
1
1
1
H
I
N
Z
C
PC2
PC4
PC6
PD7
RDI(PD0)
SCI
SYSTEM
PC3
PC5
PORT D
COP
V
DD
V
SS
PC1
PC7=½½°
INTERNAL
PROCESSOR
CLOCK
OSC1
1
PROGRAM COUNTER
0
CONDITION CODE REGISTER
OSC2
1
PORT C
0
0
DATA DIRECTION C
0
0
BAUD RATE
GENERATOR
TDO(PD1)
MISO(PD2)
MOSI(PD3)
SPI
POWER
SCK(PD4)
SS(PD5)
BAUD RATE
GENERATOR
TCMP
16-BIT
CAPTURE/COMPARE
TIMER SYSTEM
TCAP
* Port B pins also function as external interrupts.
= PC7 has a high current sink and source capability.
Figure 1-1. Block Diagram
MC68HC05C8A • MC68HCL05C8A • MC68HSC05C8A Data Sheet, Rev. 5.1
14
Freescale Semiconductor
Mask Options
1.3 Mask Options
Eight mask options are available to select the pullup/interrupts on port B on a pin-by-pin basis.
There are also four mask options for:
1. IRQ (edge-sensitive only or edge- and level-sensitive)
2. CLOCK (crystal or RC)
3. COP (enable or disable)
4. STOP (enable or disable).
1.4 Functional Pin Description
The MC68HC05C8A is available in a 40-pin DIP (see Figure 1-2), 42-pin SDIP (see Figure 1-3), 44-pin
PLCC (see Figure 1-4), and 44-pin QFP (see Figure 1-5). The following paragraphs describe the general
function of each pin.
NOTE
A line over a signal name indicates an active low signal. For example,
RESET is active high and RESET is active low. Any reference to voltage,
current, resistance, capacitance, time, or frequency specified in the
following paragraphs will refer to the nominal values. The exact values and
their tolerance or limits are specified in Chapter 13 Electrical Specifications.
MC68HC05C8A • MC68HCL05C8A • MC68HSC05C8A Data Sheet, Rev. 5.1
Freescale Semiconductor
15
General Description
RESET
1
40
VDD
IRQ
2
39
OSC1
NC*
3
38
OSC2
PA7
4
37
TCAP
PA6
5
36
PD7
PA5
6
35
TCMP
PA4
7
34
PD5/SS
PA3
8
33
PD4/SCK
PA2
9
32
PD3/MOSI
PA1
10
31
PD2/MISO
PA0
11
30
PD1/TDO
PB0
12
29
PD0/RDI
PB1
13
28
PC0
PB2
14
27
PC1
PB3
15
26
PC2
PB4
16
25
PC3
PB5
17
24
PC4
PB6
18
23
PC5
PB7
19
22
PC6
VSS
20
21
PC7
* If MC68HC705C8A OTPs are to be used in the same application,
this pin should be tied to VDD.
Figure 1-2. 40-Pin Dual In-Line Package
MC68HC05C8A • MC68HCL05C8A • MC68HSC05C8A Data Sheet, Rev. 5.1
16
Freescale Semiconductor
Functional Pin Description
RESET
1
42
VDD
IRQ
2
41
OSC1
NC*
3
40
OSC2
PA7
4
39
TCAP
PA6
5
38
PD7
PA5
6
37
TCMP
PA4
7
36
PD5/SS
PA3
8
35
PD4/SCK
PA2
9
34
PD3/MOSI
PA1
10
33
PD2/MISO
PA0
11
32
PD1/TDO
PB0
12
31
PD0/RDI
PB1
13
30
PC0
PB2
14
29
PC1
PB3
15
28
PC2
NC
16
27
NC
PB4
17
26
PC3
PB5
18
25
PC4
PB6
19
24
PC5
PB7
20
23
PC6
VSS
21
22
PC7
* If MC68HC705C8A OTPs are to be used in the same application,
this pin should be tied to VDD.
Figure 1-3. 42-Pin Plastic Shrink Dual In-Line Package
MC68HC05C8A • MC68HCL05C8A • MC68HSC05C8A Data Sheet, Rev. 5.1
Freescale Semiconductor
17
PA7
NC*
NC
IRQ
RESET
VDD
OSC1
OSC2
TCAP
NC
4
3
2
1
44
43
41
40
42
PA6
5
39
38
7
8
9
10
11
12
13
14
15
16
17
28
27
PD7
TCMP
PD5/SS
PD4/SCK
PD3/MOSI
PD2/MISO
PD1/TDO
PD0/RDI
PC0
PC1
PC2
PC3
25
PC6
PC4
24
PC7
26
23
NC
PC5
21
22
PB7
VSS
20
NC
PB5
PB6
37
36
35
34
33
32
31
30
29
18
PA3
PA2
PA1
PA0
PB0
PB1
PB2
PB3
PB4
19
PA5
PA4
6
General Description
* If MC68HC705C8A OTPs are to be used in the same application,
this pin should be tied to VDD.
PD7
PC3
PC2
PC1
PC0
PD0/RDI
PD1/TDO
PD2/MISO
PD3/MOSI
PD4/SCK
PD5/SS
TCMP
Figure 1-4. 44-Lead Plastic Leaded Chip Carrier
33 32 31 30 29 28 27 26 25 24 23
34
22
NC
TCAP
35
21
PC4
OSC2
36
20
PC5
OSC1
37
19
PC6
VDD
38
18
PC7
NC
39
17
VSS
PB6
NC*
43
44
1
13
PB5
PB4
3
4
5
6
7
8
PB3
2
12
9 10 11
PB2
PA6
PA7
PB1
14
PB0
42
PA0
IRQ
PA1
PB7
PA2
NC
15
PA3
16
41
PA4
40
PA5
NC
RESET
* If MC68HC705C8A OTPs are to be used in the same application,
this pin should be tied to VDD.
Figure 1-5. 44-Lead Quad Flat Pack
MC68HC05C8A • MC68HCL05C8A • MC68HSC05C8A Data Sheet, Rev. 5.1
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Freescale Semiconductor
Functional Pin Description
1.4.1 VDD and VSS
Power is supplied to the microcontroller using these two pins. VDD is the positive supply and VSS is
ground.
1.4.2 IRQ
This pin has a mask selectable option that provides two different choices of interrupt triggering sensitivity.
The IRQ pin contains an internal Schmitt trigger as part of its input to improve noise immunity. Refer to
Chapter 4 Interrupts for more detail.
1.4.3 OSC1 and OSC2
These pins provide control input for an on-chip clock oscillator circuit. A crystal, a ceramic resonator, a
resistor/capacitor combination, or an external signal connects to these pins providing a system clock. The
internal bus rate is one-half the external oscillator frequency.
1.4.4 RESET
This active low pin is used to reset the MCU to a known startup state by pulling RESET low. The RESET
pin contains an internal Schmitt trigger as part of its input to improve noise immunity.
1.4.5 TCAP
This pin controls the input capture feature for the on-chip programmable timer. The TCAP pin contains an
internal Schmitt trigger as part of its input to improve noise immunity.
1.4.6 TCMP
The TCMP pin provides an output for the output compare feature of the on-chip timer subsystem.
1.4.7 Port A (PA0–PA7)
These eight input/output (I/O) lines comprise port A. The state of any pin is software programmable and
all port A lines are configured as input during power-on or reset. For detailed information on I/O
programming, see 7.6 Input/Output Programming.
1.4.8 Port B (PB0–PB7)
These eight I/O lines comprise port B. The state of any pin is software programmable, and all port B lines
are configured as input during power-on or reset. Port B has mask option enabled pullup devices and
interrupt capability by pin. The interrupts and pullups are enabled together. For a detailed description on
I/O programming, refer to 7.6 Input/Output Programming.
1.4.9 Port C (PC0–PC7)
These eight I/O lines comprise port C. The state of any pin is software programmable and all port C lines
are configured as input during power-on or reset. PC7 has high current sink and source capability. For a
detailed description on I/O programming, refer to 7.6 Input/Output Programming.
MC68HC05C8A • MC68HCL05C8A • MC68HSC05C8A Data Sheet, Rev. 5.1
Freescale Semiconductor
19
General Description
1.4.10 Port D (PD0–PD5 and PD7)
These seven port lines comprise port D. PD7 and PD5–PD0 are input only. PD0 and PD1 are shared with
the SCI subsystem and PD2–PD5 are shared with the SPI subsystem. For a detailed description on I/O
programming, refer to 7.6 Input/Output Programming.
MC68HC05C8A • MC68HCL05C8A • MC68HSC05C8A Data Sheet, Rev. 5.1
20
Freescale Semiconductor
Chapter 2
Memory
2.1 Introduction
The MC68HC05C8A has an 8-Kbyte memory map, consisting of user read-only memory (ROM), user
random-access memory (RAM), self-check ROM, and input/output (I/O) registers. See Figure 2-1 and
Figure 2-2.
2.2 Read-Only Memory (ROM)
The user ROM consists of 48 bytes of page zero ROM from $0020 to $004F, 7680 bytes of user ROM
from $0100 to $1EFF, and 16 bytes of user vectors from $1FF0 to $1FFF. The self-check ROM and
vectors are located from $1F00 to $1FEF. See Figure 2-1.
Twelve of the user vectors, $1FF4–$1FFF, are dedicated to user-defined reset and interrupt vectors. The
remaining four bytes from $1FF0–$1FF3 are not used.
2.3 ROM Security Feature
A security(1) feature has been incorporated into the MC68HC05C8A to help prevent externally reading of
code in the ROM. This feature aids in keeping customer developed software proprietary.
2.4 Random-Access Memory (RAM)
The user RAM consists of 176 bytes and is used both for general-purpose RAM and stack area. The stack
begins at address $00FF. The stack pointer can access 64 bytes of RAM in the range $00FF to $00C0.
See Figure 2-1.
NOTE
Using the stack area for data storage or temporary work locations requires
care to prevent it from being overwritten due to stacking from an interrupt
or subroutine call.
1. No security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the ROM difficult for
unauthorized users.
MC68HC05C8A • MC68HCL05C8A • MC68HSC05C8A Data Sheet, Rev. 5.1
Freescale Semiconductor
21
Memory
$0000
I/O REGISTERS
32 BYTES
$001F
$0020
USER ROM
48 BYTES
$004F
$0050
RAM
176 BYTES
$00BF
$00C0
(STACK)
64 BYTES
$00FF
$0100
USER ROM
7680 BYTES
PORT A DATA REGISTER
PORT B DATA REGISTER
PORT C DATA REGISTER
PORT D DATA REGISTER
PORT A DATA DIRECTION REGISTER
PORT B DATA DIRECTION REGISTER
PORT C DATA DIRECTION REGISTER
UNUSED
UNUSED
UNUSED
SPI CONTROL REGISTER
SPI STATUS REGISTER
SPI DATA REGISTER
SCI BAUD RATE REGISTER
SCI CONTROL REGISTER 1
SCI CONTROL REGISTER 2
SCI STATUS REGISTER
SCI DATA REGISTER
TIMER CONTROL REGISTER
TIMER STATUS REGISTER
INPUT CAPTURE REGISTER (HIGH)
INPUT CAPTURE REGISTER (LOW)
OUTPUT COMPARE REGISTER (HIGH)
OUTPUT COMPARE REGISTER (LOW)
TIMER COUNTER REGISTER (HIGH)
TIMER COUNTER REGISTER (LOW)
ALTERNATE COUNTER REGISTER (HIGH)
ALTERNATE COUNTER REGISTER (LOW)
UNUSED
UNUSED
UNUSED
UNUSED
COP REGISTER
$1EFF
$1F00
$1FEF
$1FF0
$1FFF
$1FF0
$1FF1
$1FF2
$1FF3
$1FF4
$1FF5
$1FF6
$1FF7
$1FF8
$1FF9
$1FFA
$1FFB
$1FFC
$1FFD
$1FFE
$1FFF
NOT USED (3 BYTES)
SELF-CHECK
ROM
AND VECTORS
240 BYTES
USER ROM VECTORS
16 BYTES
$0000
$0001
$0002
$0003
$0004
$0005
$0006
$0007
$0008
$0009
$000A
$000B
$000C
$000D
$000E
$000F
$0010
$0011
$0012
$0013
$0014
$0015
$0016
$0017
$0018
$0019
$001A
$001B
$001C
$001D
$001E
$001F
SPI VECTOR (HIGH)
SPI VECTOR (LOW)
SCI VECTOR (HIGH)
SCI VECTOR (LOW)
TIMER VECTOR (HIGH)
TIMER VECTOR (LOW)
IRQ VECTOR (HIGH)
IRQ VECTOR (LOW)
SWI VECTOR (HIGH)
SWI VECTOR (LOW)
RESET VECTOR (HIGH BYTE)
RESET VECTOR (LOW BYTE)
Figure 2-1. Memory Map
MC68HC05C8A • MC68HCL05C8A • MC68HSC05C8A Data Sheet, Rev. 5.1
22
Freescale Semiconductor
Random-Access Memory (RAM)
Addr.
$0000
$0001
$0002
$0003
$0004
$0005
$0006
Register Name
Port A Data Register
(PORTA)
See page 37.
Read:
Port B Data Register
(PORTB)
See page 37.
Read:
Port C Data Register
(PORTC)
See page 38.
Read:
Port D Data Register
(PORTD)
See page 38.
Read:
Port A Data Direction Register
(DDRA)
See page 37.
Read:
Port B Data Direction Register
(DDRB)
See page 37.
Read:
Port C Data Direction Register
(DDRC)
See page 38.
Read:
Write:
Write:
Write:
4
3
2
1
Bit 0
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
PB2
PB1
PB0
PC2
PC1
PC0
PD2
PD1
PD0
Unaffected by reset
PB7
PB6
PB5
Write:
PC7
PC6
PC5
Reset
Write:
Reset
Write:
Reset
Read:
$000A
SPI Status Register
(SPSR)
See page 64.
Read:
SPI Data Register
(SPDR)
See page 65.
Read:
SCI Baud Rate Register
BAUD
See page 57.
Read:
Write:
Reset
Write:
Reset
Write:
PD7
PD5
Reset
PC4
PC3
PD4
PD3
Unaffected by reset
DDRA7
DDRA6
DDRA5
DDRA4
DDRA3
DDRA2
DDRA1
DDRA0
0
0
0
0
0
0
0
0
DDRB7
DDRB6
DDRB5
DDRB4
DDRB3
DDRB2
DDRB1
DDRB0
0
0
0
0
0
0
0
0
DDRC7
DDRC6
DDRC5
DDRC4
DDRC3
DDRC2
DDRC1
DDRC0
0
0
0
0
0
0
0
0
SPIE
SPE
MSTR
CPOL
CPHA
SPR1
SPR0
0
0
0
0
0
U
U
0
0
0
0
0
0
SPIF
WCOL
0
0
0
0
0
0
U
U
SPD7
SPD6
SPD5
SPD4
SPD31
SPD2
SPD1
SPD0
Reset
Write:
PB3
Unaffected by reset
Reset
Write:
PB4
Unaffected by reset
Reset
SPI Control Register
(SPCR)
See page 63.
$000D
5
Reset
Unimplemented
$000C
6
Reset
$0007
↓
$0009
$000B
Bit 7
MODF
Unaffected by reset
0
0
SCP1
SCP0
0
SCR2
SCR1
SCR0
0
0
0
0
0
U
U
U
= Unimplemented
R
= Reserved
U = Unaffected
Figure 2-2. Input/Output Registers (Sheet 1 of 3)
MC68HC05C8A • MC68HCL05C8A • MC68HSC05C8A Data Sheet, Rev. 5.1
Freescale Semiconductor
23
Memory
Addr.
$000E
$000F
$0010
$0011
$0012
$0013
$0014
$0015
$0016
$0017
$0018
$0019
Register Name
Bit 7
SCI Control Register 1
(SCCR1)
See page 53.
Read:
SCI Control Register 2
(SCCR2)
See page 54.
Read:
R8
Write:
6
5
4
3
2
1
Bit 0
T8
0
M
WAKE
0
0
0
Reset
Write:
Reset
SCI Status Register Read:
(SCSR) Write:
See page 55. Reset:
SCI Data Register
(SCDAT)
See page 52.
Read:
Timer Control Register
(TCR)
See page 45.
Read:
Write:
Unaffected by reset
TIE
TCIE
RIE
ILIE
TE
RE
RMW
SBK
0
0
0
0
0
0
0
0
TDRE
TC
RDRF
IDLE
OR
NF
FE
0
0
0
0
0
0
0
0
SCD7
SDC5
SCD5
SCD4
SCD3
SCD2
SCD1
SCD0
Reset
0
Unaffected by reset
ICIE
OCIE
TOIE
0
0
0
IEDGE
OLVL
Reset
0
0
0
0
0
0
U
0
Timer Status Register
(TSR)
See page 46.
Read:
ICF
OCF
TOF
0
0
0
0
0
Reset
U
U
U
0
0
0
0
0
Input Capture Register High
(ICR)
See page 44.
Read:
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Input Capture Register Low
(ICR)
See page 44.
Read:
Bit 2
Bit 1
Bit 0
Output Compare Register
High (OCR)
See page 43.
Read:
Bit 10
Bit 9
Bit 8
Output Compare Register
Low (OCR)
See page 43.
Read:
Bit 2
Bit 1
Bit 0
Timer Counter Register High
(TCNT)
See page 41.
Read:
Write:
Write:
Write:
Reset
Unaffected by reset
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Write:
Reset
Write:
Unaffected by reset
Bit 15
Bit 14
Bit 13
Reset
Write:
Bit 12
Bit 11
Unaffected by reset
Bit 7
Bit 6
Bit 5
Reset
Bit 4
Bit 3
Unaffected by reset
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
1
1
1
1
1
1
1
1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
1
1
1
1
1
1
= Unimplemented
R
= Reserved
Write:
Reset
Timer Counter Register Low Read:
(TCNT) Write:
See page 41. Reset:
1
U = Unaffected
Figure 2-2. Input/Output Registers (Sheet 2 of 3)
MC68HC05C8A • MC68HCL05C8A • MC68HSC05C8A Data Sheet, Rev. 5.1
24
Freescale Semiconductor
Random-Access Memory (RAM)
Addr.
$001A
$001B
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Alternate Counter Register High
(ALTCNT)
See page 41.
Read:
Reset
1
1
1
1
1
1
1
1
Alternate Counter Register Low
(ALTCNT)
See page 41.
Read:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
1
1
1
1
1
1
1
R
R
R
R
R
R
R
R
0
0
$001C
↓
$001F
Unimplemented
$001F
Reserved
$1FF0
COP Reset Register
See page 33.
Write:
Write:
Reset
Read:
User ROM data
COPC
Write:
Reset
0
0
0
0
0
= Unimplemented
R
= Reserved
0
U = Unaffected
Figure 2-2. Input/Output Registers (Sheet 3 of 3)
MC68HC05C8A • MC68HCL05C8A • MC68HSC05C8A Data Sheet, Rev. 5.1
Freescale Semiconductor
25
Memory
MC68HC05C8A • MC68HCL05C8A • MC68HSC05C8A Data Sheet, Rev. 5.1
26
Freescale Semiconductor
Chapter 3
Central Processor Unit (CPU)
3.1 Introduction
This section describes the central processor unit (CPU) registers.
3.2 CPU Registers
The five CPU registers are shown in Figure 3-1 and the interrupt stacking order in Figure 3-2.
7
A
0
7
ACCUMULATOR
0
X
INDEX REGISTER
12
0
PC
PROGRAM COUNTER
7
12
0
0
0
0
0
0
1
1
STACK POINTER
SP
CCR
H
I
N
Z
C
CONDITION CODE REGISTER
Figure 3-1. Programming Model
7
1
INCREASING
MEMORY
ADDRESSES
R
E
T
U
R
N
0
1
1
CONDITION CODE REGISTER
ACCUMULATOR
INDEX REGISTER
PCH
PCL
STACK
I
N
T
E
R
R
U
P
T
DECREASING
MEMORY
ADDRESSES
UNSTACK
NOTE: Since the stack pointer decrements during pushes, the PCL is stacked first,
followed by PCH, etc. Pulling from the stack is in the reverse order.
Figure 3-2. Stacking Order
MC68HC05C8A • MC68HCL05C8A • MC68HSC05C8A Data Sheet, Rev. 5.1
Freescale Semiconductor
27
Central Processor Unit (CPU)
3.2.1 Accumulator
The accumulator (A) shown in Figure 3-1 is a general-purpose 8-bit register used to hold operands and
results of arithmetic calculations or data manipulations.
3.2.2 Index Register
The index register (X) is an 8-bit register used by the indexed addressing value to create an effective
address. The index register also may be used as a temporary storage area.
3.2.3 Program Counter
The program counter (PC) is a 13-bit register that contains the address of the next byte to be fetched.
3.2.4 Stack Pointer
The stack pointer (SP) contains the address of the next free location on the stack. During an MCU reset
or the reset stack pointer (RSP) instruction, the stack pointer is set to location $00FF. The stack pointer
is then decremented as data is pushed onto the stack and incremented as data is pulled from the stack.
When accessing memory, the seven most significant bits (MSB) are permanently set to 0000011. These
eight bits are appended to the six least significant register bits (LSB) to produce an address within the
range of $00FF to $00C0. Subroutines and interrupts may use up to 64 (decimal) locations. If 64 locations
are exceeded, the stack pointer wraps around and loses the previously stored information. A subroutine
call occupies two locations on the stack; an interrupt uses five locations.
3.2.5 Condition Code Register
The condition code register (CCR) is a 5-bit register in which four bits are used to indicate the results of
the instruction just executed, and the fifth bit indicates whether interrupts are masked. These bits can be
tested individually by a program, and specific actions can be taken as a result of their state. Each bit is
explained here.
H — Half Carry
This bit is set during ADD and ADC operations to indicate that a carry occurred between bits 3 and 4.
I — Interrupt
When this bit is set, the timer and external interrupt are masked (disabled). If an interrupt occurs while
this bit is set, the interrupt is latched and processed as soon as the interrupt bit is cleared.
N — Negative
When set, this bit indicates that the result of the last arithmetic, logical, or data manipulation was
negative.
Z — Zero
When set, this bit indicates that the result of the last arithmetic, logical, or data manipulation was 0.
C — Carry/Borrow
When set, this bit indicates that a carry or borrow out of the arithmetic logical unit (ALU) occurred
during the last arithmetic operation. This bit also is affected during bit test and branch instructions and
during shifts and rotates.
MC68HC05C8A • MC68HCL05C8A • MC68HSC05C8A Data Sheet, Rev. 5.1
28
Freescale Semiconductor
Chapter 4
Interrupts
4.1 Introduction
The microcontroller unit (MCU) can be interrupted five different ways:
• Four maskable hardware interrupts, IRQ (interrupt request), SPI (serial peripheral interface),
SCI (serial communications interface), and timer
• Non-maskable software interrupt instruction (SWI)
Port B interrupts, if enabled, are combined with the IRQ to form a single interrupt source.
Interrupts cause the processor to save register contents on the stack and to set the interrupt mask (I bit)
to prevent additional interrupts. The RTI (return to interrupt) instruction causes the register contents to be
recovered from the stack and normal processing to resume.
Unlike reset, hardware interrupts do not cause the current instruction execution to be halted, but they are
considered pending until the current instruction is complete.
NOTE
The current instruction is the one already fetched and being operated on.
When the current instruction is complete, the processor checks all pending hardware interrupts. If
interrupts are not masked (CCR I bit clear) and if the corresponding interrupt enable bit is set, the
processor proceeds with interrupt processing; otherwise, the next instruction is fetched and executed.
If both an external interrupt and a timer interrupt are pending at the end of an instruction execution, the
external interrupt is serviced first. The SWI is executed the same as any other instruction, regardless of
the I-bit state.
Vector addresses for all interrupts, including reset, are listed in Table 4-1.
4.2 Hardware Controlled Interrupt Sequence
Three functions (RESET, STOP, and WAIT) are not in the strictest sense interrupts; however, they are
acted upon in a similar manner. Flowcharts for hardware interrupts are shown in Figure 4-1.
1. RESET — A low input on the RESET input pin causes the program to vector to its starting address,
which is specified by the contents of memory locations $1FFE and $1FFF. The I bit in the condition
code register is also set. Much of the MCU is configured to a known state during this type of reset,
as previously described in Chapter 5 Resets.
2. STOP — The STOP instruction causes the oscillator to be turned off and the processor to “sleep”
until an external interrupt (IRQ) or reset occurs.
3. WAIT — The WAIT instruction causes all processor clocks to stop, but leaves the timer clock
running. This “rest” state of the processor can be cleared by reset, an external interrupt (IRQ),
serial peripheral interface, serial communications interface, or timer interrupt. These individual
interrupts have no special wait vectors.
MC68HC05C8A • MC68HCL05C8A • MC68HSC05C8A Data Sheet, Rev. 5.1
Freescale Semiconductor
29
Interrupts
Table 4-1. Vector Addresses for Interrupts and Reset
Register
Flag Name
Interrupts
CPU Interrupt
Vector Address
N/A
N/A
Reset
RESET
$1FFE–$1FFF
N/A
N/A
Software
SWI
$1FFC–$1FFD
N/A
N/A
External interrupt
IRQ
$1FFA–$1FFB
TSR
ICF
Timer input capture
TIMER
$1FF8–$1FF9
TSR
OCF
Timer output compare
TIMER
$1FF8–$1FF9
TSR
TOF
Timer overflow
TIMER
$1FF8–$1FF9
SCSR
TDRE
Transmit buffer empty
SCI
$1FF6–$1FF7
SCSR
TC
Transmit complete
SCI
$1FF6–$1FF7
SCSR
RDRF
Receiver buffer full
SCI
$1FF6–$1FF7
SCSR
IDLE
Idle line detect
SCI
$1FF6–$1FF7
SCSR
OR
Overrun
SCI
$1FF6–$1FF7
SPSR
SPIF
Transfer complete
SPI
$1FF4–$1FF5
SPSR
MODF
Mode fault
SPI
$1FF4–$1FF5
4.3 Software Interrupt (SWI)
The software interrupt (SWI) is an executable instruction and a non-maskable interrupt. It is executed
regardless of the state of the I bit in the CCR. If the I bit is 0 (interrupts enabled), SWI executes after
interrupts which were pending when the SWI was fetched but before interrupts generated after the SWI
was fetched. The interrupt service routine address is specified by the contents of memory locations
$1FFC and $1FFD.
4.4 External Interrupt (IRQ)
If the interrupt mask bit (I bit) of the CCR is set, all maskable interrupts (internal and external) are disabled.
Clearing the I bit enables interrupts. The interrupt request is latched immediately following the falling edge
of IRQ. It is then synchronized internally and serviced as specified by the contents of $1FFA and $1FFB.
When any of the port B pullups are enabled, that pin becomes an additional external interrupt source
which is coupled to the IRQ pin logic. It follows the same edge/edge-level selection that the IRQ pin has.
See Figure 7-1. Port B Pullup Option.
Either a level-sensitive and edge-sensitive trigger, or an edge-sensitive-only trigger operation is
selectable by mask option.
NOTE
The internal interrupt latch is cleared in the first part of the interrupt service
routine; therefore, one external interrupt pulse could be latched and
serviced as soon as the I bit is cleared.
MC68HC05C8A • MC68HCL05C8A • MC68HSC05C8A Data Sheet, Rev. 5.1
30
Freescale Semiconductor
External Interrupt (IRQ)
FROM
RESET
Y
I BIT
IN CCR SET?
N
IRQ
EXTERNAL
INTERRUPT
?
Y
CLEAR IRQ
REQUEST LATCH
N
INTERNAL
TIMER
INTERRUPT
?
N
Y
INTERNAL
SCI
INTERRUPT
?
N
Y
INTERNAL
SPI
INTERRUPT
?
N
Y
STACK
PC, X, A, CCR
FETCH NEXT
INSTRUCTION
SWI
INSTRUCTION
?
SET I BIT IN
CC REGISTER
Y
N
Y
LOAD PC FROM:
SWI: $1FFC-$1FFD
IRQ: $1FFA-$1FFB
TIMER: $1FF8-$1FF9
SCI: $1FF6-$1FF7
RTI
INSTRUCTION
?
N
RESTORE REGISTERS
FROM STACK:
CCR, A, X, PC
EXECUTE
INSTRUCTION
Figure 4-1. Interrupt Flowchart
MC68HC05C8A • MC68HCL05C8A • MC68HSC05C8A Data Sheet, Rev. 5.1
Freescale Semiconductor
31
Interrupts
4.5 Timer Interrupt
Three different timer interrupt flags cause a timer interrupt whenever they are set and enabled. The
interrupt flags are in the timer status register (TSR), and the enable bits are in the timer control register
(TCR). Any of these interrupts will vector to the same interrupt service routine, located at the address
specified by the contents of memory locations $1FF8 and $1FF9.
4.6 Serial Communications Interrupt (SCI)
Five different SCI interrupt flags cause an SCI interrupt whenever they are set and enabled. The interrupt
flags are in the SCI status register (SCSR), and the enable bits are in the SCI control register 2 (SCCR2).
Any of these interrupts will vector to the same interrupt service routine, located at the address specified
by the contents of memory locations $1FF6 and $1FF7.
4.7 Serial Peripheral Interrupt (SPI)
Two different SPI interrupt flags cause an SPI interrupt whenever they are set and enabled. The interrupt
flags are in the SPI status register (SPSR), and the enable bits are in the SPI control register (SPCR).
Either of these interrupts will vector to the same interrupt service routine, located at the address specified
by the contents of memory locations $1FF4 and $1FF5.
MC68HC05C8A • MC68HCL05C8A • MC68HSC05C8A Data Sheet, Rev. 5.1
32
Freescale Semiconductor
Chapter 5
Resets
5.1 Introduction
The microcontroller unit (MCU) can be reset three ways:
1. Initial power-on reset function
2. Active low input to the RESET pin
3. Computer operating properly (COP) reset
5.2 Power-On Reset (POR)
An internal reset is generated on power-up to allow the internal clock generator to stabilize. The power-on
reset is strictly for power turn-on conditions and should not be used to detect a drop in the power supply
voltage. There is a 4064 internal processor clock cycle (tCYC) oscillator stabilization delay after the
oscillator becomes active. If the RESET pin is low after the end of this 4064-cycle delay, the MCU will
remain in the reset condition until RESET goes high.
For additional information, refer to Figure 13-8. Power-On Reset Timing Diagram.
5.3 RESET Pin
The MCU is reset when a logic 0 is applied to the RESET input for a period of one and one-half machine
cycles (tRL).
5.4 Computer Operating Properly (COP) Reset
This device includes a watchdog COP feature as a mask option. The COP is implemented with an 18-bit
ripple counter. This provides a timeout period of 64 milliseconds at a bus rate of 2 MHz. If the COP should
time out, a system reset will occur and the device will be re-initialized in the same fashion as a power-on
reset (POR) or external reset.
5.4.1 Resetting the COP
Preventing a COP reset is done by writing a logic 0 to the COPC bit. This action will reset the counter and
begin the timeout period again. The COPC bit is bit 0 of address $1FF0. A read of address $1FF0 will
result in the user defined ROM data at that location.
5.4.2 COP During Wait Mode
The COP will continue to operate normally during wait mode. The software should pull the device out of
wait mode periodically and reset the COP by writing to the COPC bit to prevent a COP reset.
MC68HC05C8A • MC68HCL05C8A • MC68HSC05C8A Data Sheet, Rev. 5.1
Freescale Semiconductor
33
Resets
5.4.3 COP During Stop Mode
Stop mode disables the oscillator circuit and thereby turns the clock off for the entire device. The COP
counter will be reset when stop mode is entered. If a reset is used to exit stop mode, the COP counter will
be reset after the 4064 cycles of delay after stop mode. If an interrupt is used to exit stop mode, the COP
counter will not be reset after the
4064-cycle delay and will have that many cycles already counted when control is returned to the program.
5.4.4 COP During Self-Check Mode
The COP is disabled by hardware during self-check mode.
MC68HC05C8A • MC68HCL05C8A • MC68HSC05C8A Data Sheet, Rev. 5.1
34
Freescale Semiconductor
Chapter 6
Low-Power Modes
6.1 Introduction
This section describes the two low-power modes — stop and wait. Figure 6-1 shows the sequence of
events caused by the STOP and WAIT instructions.
STOP
STOP OSCILLATOR
AND ALL CLOCKS
CLEAR I BIT
N
N
EXTERNAL
INTERRUPT
(IRQ)
WAIT
OSCILLATOR ACTIVE
TIMER CLOCK ACTIVE
PROCESSOR CLOCKS STOPPED
CLEAR I BIT
RESET
RESET
Y
Y
N
EXTERNAL
INTERRUPT
(IRQ)
Y
N
TIMER
INTERRUPT
Y
Y
TURN ON OSCILLATOR
WAIT FOR TIME
DELAY TO STABILIZE
RESTART
PROCESSOR CLOCK
1. FETCH RESET VECTOR
OR
2. SERVICE INTERRUPT
A. STACK
B. SET I BIT
C. VECTOR TO
INTERRUPT
ROUTINE
1. FETCH RESET VECTOR
OR
2. SERVICE INTERRUPT
A. STACK
B. SET I BIT
C. VECTOR TO
INTERRUPT
ROUTINE
N
Y
SCI
INTERRUPT
N
SPI
INTERRUPT
N
Figure 6-1. Stop/Wait Mode Flowchart
MC68HC05C8A • MC68HCL05C8A • MC68HSC05C8A Data Sheet, Rev. 5.1
Freescale Semiconductor
35
Low-Power Modes
6.2 Stop Mode
The STOP instruction places the microcontroller unit (MCU) in its lowest-power consumption mode. In
stop mode, the internal oscillator is turned off, halting all internal processing, including timer operation.
During stop mode, the TCR bits are altered to remove any pending timer interrupt request and to disable
any further timer interrupts. The timer prescaler is cleared. The I bit in the condition code register is
cleared to enable external interrupts. All other registers and memory remain unaltered. All input/output
lines remain unchanged. The processor can be brought out of stop mode only by an external interrupt or
reset.
6.3 Stop Recovery
The processor can be brought out of stop mode only by an external interrupt or reset. See Figure 6-2.
6.4 Wait Mode
The WAIT instruction places the MCU in a low-power consumption mode, but the wait mode consumes
more power than the stop mode. All CPU action is suspended, but the timer, serial communications
interface (SCI), serial peripheral interface (SPI), and the oscillator remain active. Any interrupt or reset will
cause the MCU to exit wait mode.
During wait mode, the I bit in the CCR is cleared to enable interrupts. All other registers, memory, and
input/output lines remain in their previous state. The timer may be enabled to allow a periodic exit from
wait mode.
OSC1
(1)
tRL
RESET
t
ILIH
IRQ(2)
IRQ
(3)
t
ILCH
4064 tcyc
INTERNAL CLOCK
INTERNAL ADDRESS BUS
Notes:
1. Represents the internal gating of the OSC1 pin
2. IRQ pin edge-sensitive option
3. IRQ pin level and edge sensitive option
1FFE
1FFE
1FFE
1FFE
1FFF
RESET ($1FFE, $1FFF) OR
INTERRUPT ($1FFA, $1FFB)
VECTOR FETCH
Figure 6-2. Stop Recovery Timing Diagram
MC68HC05C8A • MC68HCL05C8A • MC68HSC05C8A Data Sheet, Rev. 5.1
36
Freescale Semiconductor
Chapter 7
Input/Output (I/O) Ports
7.1 Introduction
The MC68HC05C8A has three 8-bit input/output (I/O) ports.These 24 port pins are programmable as
either inputs or outputs under software control of the data direction registers. Port D does not have a data
direction register, and its seven pins are input only with the exception of certain serial communications
(SCI)/serial peripheral interface (SPI) functions.
NOTE
To avoid a glitch on the output pins, write data to the I/O port data register
before writing a 1 to the corresponding data direction register.
7.2 Port A
Port A is an 8-bit bidirectional port which does not share any of its pins with other subsystems. The port
A data register is at $0000 and the data direction register (DDR) is at $0004. Reset does not affect the
data registers, but clears the data direction registers, thereby returning the ports to inputs. Writing a 1 to
a DDR bit sets the corresponding port bit to output mode.
7.3 Port B
Port B is an 8-bit bidirectional port. The port B data register is at $0001 and the data direction register
(DDR) is at $0005. Reset does not affect the data registers, but clears the data direction registers, thereby
returning the ports to inputs. Writing a 1 to a DDR bit sets the corresponding port pin to output mode. Each
of the port B pins has a mask programmable interrupt capability. This interrupt option also enables a
pullup device when the pin is configured as an input (see Figure 7-1). The edge or edge and level
sensitivity of the IRQ pin also will pertain to the enabled port B pins via mask options. Be careful when
using port B pins that have the pullup enabled. Before switching from an output to an input, the data
should be preconditioned to a 1 to prevent an interrupt from occurring.
VDD
VDD
MASK OPTION
DDR BIT
IRQ
SCHMITT
TRIGGER
PB0
NORMAL PORT CIRCUITRY
AS SHOWN IN Figure 7-2
FROM ALL OTHER PORT B PINS
TO INTERRUPT
LOGIC
Figure 7-1. Port B Pullup Option
MC68HC05C8A • MC68HCL05C8A • MC68HSC05C8A Data Sheet, Rev. 5.1
Freescale Semiconductor
37
Input/Output (I/O) Ports
7.4 Port C
Port C is an 8-bit bidirectional port. The port C data register is at $0002 and the data direction register
(DDR) is at $0006. Reset does not affect the data registers, but clears the data direction registers, thereby
returning the ports to inputs. Writing a 1 to a DDR bit sets the corresponding port bit to output mode. PC7
has a high current sink and source capability.
7.5 Port D
Port D is a 7-bit fixed input port. Four of its pins are shared with the SPI subsystem, two more are shared
with the SCI subsystem. Reset does not affect the data registers. During reset, all seven bits become valid
input ports because all special function output drivers associated with the SCI, timer, and SPI subsystems
are disabled.
7.6 Input/Output Programming
I/O port pins may be programmed as inputs or outputs under software control. The direction of the pins is
determined by the state of the corresponding bit in the port data direction register (DDR). Each I/O port
has an associated DDR. Any I/O port pin is configured as an output if its corresponding DDR bit is set to
a logic 1. A pin is configured as an input if its corresponding DDR bit is cleared to a logic 0.
At power-on or reset, all DDRs are cleared, which configures all I/O pins as inputs. The data direction
registers are capable of being written to or read by the processor. During the programmed output state,
a read of the data register actually reads the value of the output data latch and not the I/O pin. For further
information, refer to Table 7-1 and Figure 7-2.
Table 7-1. I/O Pin Functions
R/W(1)
DDR
0
0
The I/O pin is in input mode. Data is written into the output data latch.
0
1
Data is written into the output data latch and output to the I/O pin.
1
0
The state of the I/O pin is read.
1
1
The I/O pin is in an output mode. The output data latch is read.
I/O Pin Function
1. R/W is an internal signal.
MC68HC05C8A • MC68HCL05C8A • MC68HSC05C8A Data Sheet, Rev. 5.1
38
Freescale Semiconductor
Input/Output Programming
READ DDRx
INTERNAL DATA BUS
WRITE DDRx
RESET
WRITE PORTx
DATA DIRECTION
REGISTER x BIT
PORT x DATA
REGISTER BIT
(LATCHED OUTPUT)
[1]
I/O
PIN
[3]
READ PORTx
[2]
[1] This output buffer enables the latched output to drive the pin when DDR bit is 1 (output mode).
[2] This input buffer is enabled when DDR bit is 0 (input mode).
[3] This input buffer is enabled when DDR bit is 1 (output mode).
Figure 7-2. I/O Circuitry
MC68HC05C8A • MC68HCL05C8A • MC68HSC05C8A Data Sheet, Rev. 5.1
Freescale Semiconductor
39
Input/Output (I/O) Ports
MC68HC05C8A • MC68HCL05C8A • MC68HSC05C8A Data Sheet, Rev. 5.1
40
Freescale Semiconductor
Chapter 8
Timer
8.1 Introduction
The timer consists of a 16-bit, software-programmable counter driven by a fixed divide-by-four prescaler.
This timer can be used for many purposes, including input waveform measurements while simultaneously
generating an output waveform. Pulse widths can vary from several microseconds to many seconds.
Refer to Figure 8-1 for a timer block diagram.
Because the timer has a 16-bit architecture, each specific functional segment (capability) is represented
by two registers. These registers contain the high and low byte of that functional segment. Generally,
accessing the low byte of a specific timer function allows full control of that function; however, an access
of the high byte inhibits that specific timer function until the low byte is also accessed.
NOTE
The I bit in the condition code register should be set while manipulating both
the high and low byte register of a specific timer function to ensure that an
interrupt does not occur.
8.2 Counter
The key element in the programmable timer is a 16-bit, free-running counter or counter register, preceded
by a prescaler that divides the internal processor clock by four. The prescaler gives the timer a resolution
of 2.0 microseconds if the internal bus clock is 2.0 MHz. The counter is incremented during the low portion
of the internal bus clock. Software can read the counter at any time without affecting its value.
The double-byte, free-running counter can be read from either of two locations, $18, $19 (counter register)
or $1A, $1B (counter alternate register). A read from only the least significant byte (LSB) of the
free-running counter ($19, $1B) receives the count value at the time of the read. If a read of the
free-running counter or counter alternate register first addresses the most significant byte (MSB) ($18,
$1A), the LSB ($19, $1B) is transferred to a buffer. This buffer value remains fixed after the first MSB read,
even if the user reads the MSB several times. This buffer is accessed when reading the free-running
counter or counter alternate register LSB ($19 or $1B) and, thus, completes a read sequence of the total
counter value. In reading either the free-running counter or counter alternate register, if the MSB is read,
the LSB must also be read to complete the sequence.
The counter alternate register differs from the counter register in one respect: A read of the counter
register MSB can clear the timer overflow flag (TOF). Therefore, the counter alternate register can be read
at any time without the possibility of missing timer overflow interrupts due to clearing of the TOF.
MC68HC05C8A • MC68HCL05C8A • MC68HSC05C8A Data Sheet, Rev. 5.1
Freescale Semiconductor
41
Timer
INTERNAL BUS
HIGH
BYTE
INTERNAL
PROCESSOR
CLOCK
LOW
BYTE
8-BIT
BUFFER
÷4
$16
$17
OUTPUT
COMPARE
REGISTER
HIGH
BYTE
HIGH
BYTE
OUTPUT
COMPARE
CIRCUIT
LOW
BYTE
LOW
BYTE
16-BIT FREE
RUNNING
COUNTER
$18
$19
COUNTER
ALTERNATE
REGISTER
$1A
$1B
INPUT
CAPTURE
REGISTER
$14
$15
EDGE
DETECT
CIRCUIT
OVERFLOW
DETECT
CIRCUIT
D
Q
CLK
TIMER
ICF
STATUS
REGISTER
OCF
TOF
OUTPUT
LEVEL
REGISTER
$13
ICIE
OCIE
TOIE
IEDG
OLVL
TIMER
CONTROL
REGISTER
$12
C
RESET
OUTPUT
LEVEL
(TCMP)
INTERRUPT
CIRCUIT
EDGE
INPUT
(TCAP)
Figure 8-1. Timer Block Diagram
The free-running counter is configured to $FFFC during reset and is always a read-only register. During
a power-on reset, the counter is also preset to $FFFC and begins running after the oscillator start-up
delay. Because the free-running counter is 16 bits preceded by a fixed divide-by-four prescaler, the value
in the free-running counter repeats every 262,144 internal bus clock cycles. When the counter rolls over
from $FFFF to $0000, the TOF bit is set. An interrupt can also be enabled whenever counter rollover
occurs by setting its interrupt enable bit (TOIE).
MC68HC05C8A • MC68HCL05C8A • MC68HSC05C8A Data Sheet, Rev. 5.1
42
Freescale Semiconductor
Output Compare Register
8.3 Output Compare Register
The 16-bit output compare register is made up of two 8-bit registers at locations $16 (MSB) and $17
(LSB). The output compare register is used for several purposes, such as indicating when a period of time
has elapsed. All bits are readable and writable and are not altered by the timer hardware or reset. If the
compare function is not needed, the two bytes of the output compare register can be used as storage
locations.
The output compare register contents are compared with the contents of the free-running counter
continually, and if a match is found, the corresponding output compare flag (OCF) bit is set and the
corresponding output level (OLVL) bit is clocked to an output level register. The output compare register
values and the output level bit should be changed after each successful comparison to establish a new
elapsed timeout. An interrupt also can accompany a successful output compare, provided the
corresponding interrupt enable bit (OCIE) is set.
After a processor write cycle to the output compare register containing the MSB ($16), the output compare
function is inhibited until the LSB ($17) is written also. The user must write both bytes (locations) if the
MSB is written first. A write made only to the LSB ($17) will not inhibit the compare function. The
free-running counter is updated every four internal bus clock cycles. The minimum time required to update
the output compare register is a function of the program rather than the internal hardware.
The processor can write to either byte of the output compare register without affecting the other byte. The
output level (OLVL) bit is clocked to the output level register regardless of whether the output compare
flag (OCF) is set or clear. Figure 8-2 shows the logic of the output compare function.
15
0
COUNTER HIGH BYTE
COUNTER LOW BYTE
PIN
CONTROL
LOGIC
16-BIT COMPARATOR
15
8 7
TCMP
0
OUTPUT COMPARE REGISTER HIGH OUTPUT COMPARE REGISTER LOW
TOF
ICF
OCF
TOIE
ICIE
OCIE
TIMER
INTERRUPT
REQUEST
TIMER CONTROL REGISTER
TIMER STATUS REGISTER
$0012
$0013
Figure 8-2. Output Compare Operation
MC68HC05C8A • MC68HCL05C8A • MC68HSC05C8A Data Sheet, Rev. 5.1
Freescale Semiconductor
43
Timer
8.4 Input Capture Register
Two 8-bit registers, which make up the 16-bit input capture register, are read-only and are used to latch
the value of the free-running counter after the corresponding input capture edge detector senses a
defined transition. The level transition which triggers the counter transfer is defined by the corresponding
input edge bit (IEDG). Reset does not affect the contents of the input capture register except when exiting
stop mode.
The result obtained by an input capture will be one more than the value of the free-running counter on the
rising edge of the internal bus clock preceding the external transition. This delay is required for internal
synchronization. Resolution is one count of the free-running counter, which is four internal bus clock
cycles.
The free-running counter contents are transferred to the input capture register on each proper signal
transition regardless of whether the input capture flag (ICF) is set or clear. The input capture register
always contains the free-running counter value that corresponds to the most recent input capture.
After a read of the input capture register ($14) MSB, the counter transfer is inhibited until the LSB ($15)
is also read. This characteristic causes the time used in the input capture software routine and its
interaction with the main program to determine the minimum pulse period.
A read of the input capture register LSB ($15) does not inhibit the free-running counter transfer, since they
occur on opposite edges of the internal bus clock. Figure 8-3 shows the logic of the input capture function.
$0018
15
$0019
8 7
TIMER REGISTER HIGH
TCMP
EDGE
SELECT/DETECT
LOGIC
LATCH
15
0
TIMER REGISTER LOW
8 7
INPUT CAPTURE REGISTER HIGH
$0014
0
INPUT CAPTURE REGISTER LOW
$0015
OCF
TOF
ICF
ICIE
OCIE
TOIE
TIMER
INTERRUPT
REQUEST
TIMER STATUS REGISTER
$0012
$0013
IEDG
TIMER CONTROL REGISTER
Figure 8-3. Input Capture Operation
MC68HC05C8A • MC68HCL05C8A • MC68HSC05C8A Data Sheet, Rev. 5.1
44
Freescale Semiconductor
Timer Control Register
8.5 Timer Control Register
The timer control register (TCR) is a read/write register containing five control bits. Three bits control
interrupts associated with the timer status register flags ICF, OCF, and TOF.
Address:
$0012
Bit 7
6
5
4
3
2
1
Bit 0
ICIE
OCIE
TOIE
0
0
0
IEDG
OLVL
0
0
0
0
0
0
U
0
Read:
Write:
Reset:
U = Unaffected
Table 8-1. Timer Control Register (TCR)
ICIE — Input Capture Interrupt Enable Bit
1 = Interrupt enabled
0 = Interrupt disabled
OCIE — Output Compare Interrupt Enable Bit
1 = Interrupt enabled
0 = Interrupt disabled
TOIE — Timer Overflow Interrupt Enable Bit
1 = Interrupt enabled
0 = Interrupt disabled
IEDG — Input Edge Bit
Value of input edge determines which level transition on TCAP pin will trigger free-running counter
transfer to the input capture register.
1 = Positive edge
0 = Negative edge
Reset does not affect the IEDG bit.
OLVL — Output Level Bit
Value of output level is clocked into output level register by the next successful output compare and
will appear on the TCMP pin.
1 = High output
0 = Low output
Bits 2, 3, and 4 — Not used
Always read 0
MC68HC05C8A • MC68HCL05C8A • MC68HSC05C8A Data Sheet, Rev. 5.1
Freescale Semiconductor
45
Timer
8.6 Timer Status Register
The timer status register (TSR) is a read-only register containing three status flag bits.
Address:
Read:
$0013
Bit 7
6
5
4
3
2
1
Bit 0
ICF
OCF
TOF
0
0
0
0
0
U
U
0
0
0
0
0
Write:
Reset:
U
= Unimplemented
U = Unaffected
Figure 8-4. Timer Status Register (TSR)
ICF — Input Capture Flag
1 = Flag set when selected polarity edge is sensed by input capture edge detector
0 = Flag cleared when TSR and input capture low register ($15) are accessed
OCF — Output Compare Flag
1 = Flag set when output compare register contents match the free-running counter contents
0 = Flag cleared when TSR and output compare low register ($17) are accessed
TOF — Timer Overflow Flag
1 = Flag set when free-running counter transition from $FFFF to $0000 occurs
0 = Flag cleared when TSR and counter low register ($19) are accessed
Bits 0–4 — Not used
Always read 0
Accessing the timer status register satisfies the first condition required to clear status bits. The remaining
step is to access the register corresponding to the status bit.
A problem can occur when using the timer overflow function and reading the free-running counter at
random times to measure an elapsed time. Without incorporating the proper precautions into software,
the timer overflow flag could unintentionally be cleared if:
1. The timer status register is read or written when TOF is set.
2. The LSB of the free-running counter is read but not for the purpose of servicing the flag.
The counter alternate register at addresses $1A and $1B contains the same value as the free-running
counter (at address $18 and $19); therefore, this alternate register can be read at any time without
affecting the timer overflow flag in the timer status register.
8.7 Timer During Wait Mode
The central processor unit (CPU) clock halts during wait mode, the timer remains active. If interrupts are
enabled, a timer interrupt will cause the processor to exit the wait mode.
8.8 Timer During Stop Mode
In stop mode, the timer stops counting and holds the last count value if stop is exited by an interrupt. If
reset is used, the counter is forced to $FFFC. During stop, if at least one valid input capture edge occurs
at the TCAP pin, the input capture detect circuit is armed. This does not set any timer flags or wake up
the microcontroller unit (MCU). But if the MCU exits stop due to an external interrupt, there is an active
input capture flag and data from the first valid edge that occurred during the stop mode. If reset is used
to exit stop mode, then no input capture flag or data remains, even if a valid input capture edge occurred.
MC68HC05C8A • MC68HCL05C8A • MC68HSC05C8A Data Sheet, Rev. 5.1
46
Freescale Semiconductor
Chapter 9
Serial Communications Interface (SCI)
9.1 Introduction
The serial communications interface (SCI) module allows high-speed asynchronous communication with
peripheral devices and other microcontroller units (MCU).
9.2 Features
Features of the SCI module include:
• Standard mark/space non-return-to-zero format
• Full duplex operation
• 32 programmable baud rates
• Programmable 8-bit or 9-bit character length
• Separately enabled transmitter and receiver
• Two receiver wakeup methods:
– Idle line wakeup
– Address mark wakeup
• Interrupt-driven operation capability with five interrupt flags:
– Transmitter data register empty
– Transmission complete
– Receiver data register full
– Receiver overrun
– Idle receiver input
• Receiver framing error detection
• 1/16 bit-time noise detection
9.3 SCI Data Format
The SCI uses the standard non-return-to-zero mark/space data format illustrated in Figure 9-1.
8-BIT DATA FORMAT
(BIT M IN SCCR1 CLEAR)
START
BIT
BIT 0
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
STOP
BIT
BIT 6
BIT 7
BIT 8
NEXT
START
BIT
9-BIT DATA FORMAT
(BIT M IN SCCR1 SET)
START
BIT
BIT 0
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
STOP
BIT
NEXT
START
BIT
Figure 9-1. SCI Data Format
MC68HC05C8A • MC68HCL05C8A • MC68HSC05C8A Data Sheet, Rev. 5.1
Freescale Semiconductor
47
Serial Communications Interface (SCI)
9.4 SCI Operation
The SCI allows full-duplex, asynchronous, RS232 or RS422 serial communication between the MCU and
remote devices, including other MCUs. The SCI’s transmitter and receiver operate independently,
although they use the same baud-rate generator. This subsection describes the operation of the SCI
transmitter and receiver.
9.4.1 Transmitter
Figure 9-2 shows the structure of the SCI transmitter.
9.4.1.1 Character Length
The transmitter can accommodate either 8-bit or 9-bit data. The state of the M bit in SCI control register 1
(SCCR1) determines character length. When transmitting 9-bit data, bit T8 in SCCR1 is the ninth bit
(bit 8).
9.4.1.2 Character Transmission
During transmission, the transmit shift register shifts a character out to the PD1/TDO pin. The SCI data
register (SCDR) is the write-only buffer between the internal data bus and the transmit shift register.
Writing a logic 1 to the TE bit in SCI control register 2 (SCCR2) and then writing data to the SCDR begins
the transmission. At the start of a transmission, transmitter control logic automatically loads the transmit
shift register with a preamble of logic 1s. After the preamble shifts out, the control logic transfers the
SCDR data into the shift register. A logic 0 start bit automatically goes into the least significant bit position
of the shift register, and a logic 1 stop bit goes into the most significant bit position.
When the data in the SCDR transfers to the transmit shift register, the transmit data register empty
(TDRE) flag in the SCI status register (SCSR) becomes set. The TDRE flag indicates that the SCDR can
accept new data from the internal data bus.
When the shift register is not transmitting a character, the PD1/TDO pin goes to the idle condition, logic 1.
If software clears the TE bit during the idle condition, and while TDRE is set, the transmitter relinquishes
control of the PD1/TDO pin.
9.4.1.3 Break Characters
Writing a logic 1 to the SBK bit in SCCR2 loads the shift register with a break character. A break character
contains all logic 0s and has no start and stop bits. Break character length depends on the M bit in
SCCR1. As long as SBK is at logic 1, transmitter logic continuously loads break characters into the shift
register. After software clears the SBK bit, the shift register finishes transmitting the last break character
and then transmits at least one logic 1. The automatic logic 1 at the end of a break character is to
guarantee the recognition of the start bit of the next character.
9.4.1.4 Idle Characters
An idle character contains all logic 1s and has no start or stop bits. Idle character length depends on the
M bit in SCCR1. The preamble is a synchronizing idle character that begins every transmission.
MC68HC05C8A • MC68HCL05C8A • MC68HSC05C8A Data Sheet, Rev. 5.1
48
Freescale Semiconductor
SCI Operation
INTERNAL DATA BUS
SCDR ($0011)
TRANSMIT SHIFT REGISTER
1X
BAUD RATE
CLOCK
PIN BUFFER
AND CONTROL
H 8 7 6 5 4 3 2 1 0 L
PD1/
TDO
BREAK (ALL LOGIC 0S)
SHIFT ENABLE
LOAD FROM SCDR
T8
PREAMBLE (ALL LOGIC 1S)
M
SBK
TRANSMITTER
CONTROL LOGIC
TE
TDRE
TIE
TC
TCIE
SCI
INTERRUPT
REQUEST
SCI
RECEIVE
REQUESTS
BIT 7
0
BAUD RATE REGISTER (BAUD)
SCI CONTROL REGISTER 1 (SCCR1)
R8
SCI CONTROL REGISTER 2 (SCCR2) TIE
SCI STATUS REGISTER (SCSR) TDRE
SCI DATA REGISTER (SCDR) BIT 7
6
0
T8
TCIE
TC
BIT 6
5
SCP1
0
RIE
RDRF
BIT 5
4
SCP0
M
ILIE
IDLR
BIT 4
3
0
WAKE
TE
OR
BIT 3
2
SCR2
0
RE
NF
BIT 2
1
SCR1
0
RWU
FE
BIT 1
BIT 0
SCR0
0
SBK
0
BIT 0
$000D
$000E
$000F
$0010
$0011
Figure 9-2. SCI Transmitter
MC68HC05C8A • MC68HCL05C8A • MC68HSC05C8A Data Sheet, Rev. 5.1
Freescale Semiconductor
49
Serial Communications Interface (SCI)
Clearing the TE bit during a transmission relinquishes the PD1/TDO pin after the last character to be
transmitted is shifted out. The last character may already be in the shift register, or waiting in the SCDR,
or in a break character generated by writing to the SBK bit. Toggling TE from logic 0 to logic 1 while the
last character is in transmission generates an idle character (a preamble) that allows the receiver to
maintain control of the PD1/TDO pin.
9.4.1.5 Transmitter Interrupts
Two sources can generate SCI transmitter interrupt requests:
1. Transmit data register empty (TDRE) — The TDRE bit in the SCSR indicates that the SCDR has
transferred a character to the transmit shift register. TDRE is a source of SCI interrupt requests.
The transmission complete interrupt enable bit (TCIE) in SCCR2 is the local mask for TDRE
interrupts.
2. Transmission complete (TC) — The TC bit in the SCSR indicates that both the transmit shift
register and the SCDR are empty and that no break or idle character has been generated. TC is a
source of SCI interrupt requests. The transmission complete interrupt enable bit (TCIE) in SCCR2
is the local mask for TC interrupts.
9.4.2 Receiver
Figure 9-3 shows the structure of the SCI receiver.
9.4.2.1 Character Length
The receiver can accommodate either 8-bit or 9-bit data. The state of the M bit in SCI control register 1
(SCCR1) determines character length. When receiving 9-bit data, bit R8 in SCCR1 is the ninth bit (bit 8).
9.4.2.2 Character Reception
During reception, the receive shift register shifts characters in from the PD0/RDI pin. The SCI data register
(SCDR) is the read-only buffer between the internal data bus and the receive shift register.
After a complete character shifts into the receive shift register, the data portion of the character is
transferred to the SCDR, setting the receive data register full (RDRF) flag. The RDRF flag can be used
to generate an interrupt.
9.4.2.3 Receiver Wakeup
So that the MCU can ignore transmissions intended only for other receivers in multiple-receiver systems,
the receiver can be put into a standby state. Setting the receiver wakeup enable (RWU) bit in SCI control
register 2 (SCCR2) puts the receiver into a standby state during which receiver interrupts are disabled.
Either of two conditions on the PD0/RDI pin can bring the receiver out of the standby state:
1. Idle input line condition — If the PD0/RDI pin is at logic 1 long enough for 10 or 11 logic 1s to shift
into the receive shift register, receiver interrupts are again enabled.
2. Address mark — If a logic 1 occurs in the most significant bit position of a received character,
receiver interrupts are again enabled.
The state of the WAKE bit in SCCR1 determines which of the two conditions wakes up the MCU.
MC68HC05C8A • MC68HCL05C8A • MC68HSC05C8A Data Sheet, Rev. 5.1
50
Freescale Semiconductor
SCI Operation
INTERNAL DATA BUS
SCDR ($0011)
STOP
8
7
6
5
4
FULL
NF
3
2
1
0
MSB
DATA
RECOVERY
IDLE
PIN BUFFER
AND CONTROL
OVERRUN
PD0/
RDI
÷³16
START
RECEIVE SHIFT REGISTER
16X
BAUD RATE
CLOCK
FE
R8
RE
M
RDRF
RIE
SCI
INTERRUPT
REQUEST
OR
SCI
TRANSMIT
REQUESTS
RIE
IDLE
ILIE
WAKEUP
LOGIC
RWU
BIT 7
0
BAUD RATE REGISTER (BAUD)
SCI CONTROL REGISTER 1 (SCCR1)
R8
SCI CONTROL REGISTER 2 (SCCR2) TIE
SCI STATUS REGISTER (SCSR) TDRE
SCI DATA REGISTER (SCDR) BIT 7
6
0
T8
TCIE
TC
BIT 6
5
SCP1
0
RIE
RDRF
BIT 5
4
SCP0
M
ILIE
IDLR
BIT 4
3
0
WAKE
TE
OR
BIT 3
2
SCR2
0
RE
NF
BIT 2
1
SCR1
0
RWU
FE
BIT 1
BIT 0
SCR0
0
SBK
0
BIT 0
$000D
$000E
$000F
$0010
$0011
Figure 9-3. SCI Receiver
MC68HC05C8A • MC68HCL05C8A • MC68HSC05C8A Data Sheet, Rev. 5.1
Freescale Semiconductor
51
Serial Communications Interface (SCI)
9.4.2.4 Receiver Noise Immunity
The data recovery logic samples each bit 16 times to identify and verify the start bit and to detect noise.
Any conflict between noise-detection samples sets the noise flag (NF) in the SCSR. The NF bit is set at
the same time that the RDRF bit is set.
9.4.2.5 Framing Errors
If the data recovery logic does not detect a logic 1 where the stop bit should be in an incoming character,
it sets the framing error (FE) bit in the SCSR. The FE bit is set at the same time that the RDRF bit is set.
9.4.2.6 Receiver Interrupts
Three sources can generate SCI receiver interrupt requests:
1. Receive data register full (RDRF) — The RDRF bit in the SCSR indicates that the receive shift
register has transferred a character to the SCDR.
2. Receiver overrun (OR) — The OR bit in the SCSR indicates that the receive shift register shifted
in a new character before the previous character was read from the SCDR.
3. Idle input (IDLE) — The IDLE bit in the SCSR indicates that 10 or 11 consecutive logic 1s shifted
in from the PD0/RDI pin.
9.5 SCI Input/Output (I/O) Registers
These I/O registers control and monitor SCI operation:
• SCI data register (SCDR)
• SCI control register 1 (SCCR1)
• SCI control register 2 (SCCR2)
• SCI status register (SCSR)
9.5.1 SCI Data Register
The SCI data register is the buffer for characters received and for characters transmitted.
Address:
Read:
Write:
Reset:
$0011
Bit 7
6
5
4
3
2
1
Bit 0
SCD7
SDC5
SCD5
SCD4
SCD3
SCD2
SCD1
SCD0
Unaffected by reset
Figure 9-4. SCI Data Register (SCDR)
MC68HC05C8A • MC68HCL05C8A • MC68HSC05C8A Data Sheet, Rev. 5.1
52
Freescale Semiconductor
SCI Input/Output (I/O) Registers
9.5.2 SCI Control Register 1
SCI control register 1 has these functions:
• Stores ninth SCI data bit received and ninth SCI data bit transmitted
• Controls SCI character length
• Controls SCI wakeup method
Address: $000E
Bit 7
Read:
Write:
R8
6
5
4
3
2
1
Bit 0
T8
0
M
WAKE
0
0
0
Reset:
Unaffected by reset
= Unimplemented
Figure 9-5. SCI Control Register 1 (SCCR1)
R8 — Bit 8 (Received)
When the SCI is receiving 9-bit characters, R8 is the ninth bit of the received character. R8 receives
the ninth bit from the receive shift register at the same time that the SCDR receives the other eight bits.
Reset has no effect on the R8 bit.
T8 — Bit 8 (Transmitted)
When the SCI is transmitting 9-bit characters, T8 is the ninth bit of the transmitted character. T8 is
loaded into the transmit shift register at the same time that SCDR is loaded into the transmit shift
register. Reset has no effect on the T8 bit.
M — Character Length Bit
This read/write bit determines whether SCI characters are 8 bits long or 9 bits long. The ninth bit can
be used as an extra stop bit, as a receiver wakeup signal, or as a mark or space parity bit. Reset has
no effect on the M bit.
1 = 9-bit SCI characters
0 = 8-bit SCI characters
WAKE — Wakeup Bit
This read/write bit determines which condition wakes up the SCI: a logic 1 (address mark) in the most
significant bit position of a received character or an idle condition of the PD0/RDI pin. Reset has no
effect on the WAKE bit.
1 = Address mark wakeup
0 = Idle line wakeup
MC68HC05C8A • MC68HCL05C8A • MC68HSC05C8A Data Sheet, Rev. 5.1
Freescale Semiconductor
53
Serial Communications Interface (SCI)
9.5.3 SCI Control Register 2
SCI control register 2 has these functions:
• Enables the SCI receiver and SCI receiver interrupts
• Enables the SCI transmitter and SCI transmitter interrupts
• Enables SCI receiver idle interrupts
• Enables SCI transmission complete interrupts
• Enables SCI wakeup
• Transmits SCI break characters
Address: $000F
Read:
Write:
Reset:
Bit 7
6
5
4
3
2
1
Bit 0
TIE
TCIE
RIE
ILIE
TE
RE
RWU
SBK
0
0
0
0
0
0
0
0
Figure 9-6. SCI Control Register 2 (SCCR2)
TIE — Transmit Interrupt Enable Bit
This read/write bit enables SCI interrupt requests when the TDRE bit becomes set. Reset clears the
TIE bit.
1 = TDRE interrupt requests enabled
0 = TDRE interrupt requests disabled
TCIE — Transmission Complete Interrupt Enable Bit
This read/write bit enables SCI interrupt requests when the TC bit becomes set. Reset clears the TCIE
bit
1 = TC interrupt requests enabled
0 = TC interrupt requests disabled
RIE — Receive Interrupt Enable Bit
This read/write bit enables SCI interrupt requests when the RDRF bit or the OR bit becomes set. Reset
clears the RIE bit.
1 = RDRF interrupt requests enabled
0 = RDRF interrupt requests disabled
ILIE — Idle Line Interrupt Enable Bit
This read/write bit enables SCI interrupt requests when the IDLE bit becomes set. Reset clears the
ILIE bit.
1 = IDLE interrupt requests enabled
0 = IDLE interrupt requests disabled
TE — Transmit Enable Bit
Setting this read/write bit begins the transmission by sending a preamble of 10 or 11 logic 1s from the
transmit shift register to the PD1/TDO pin. Reset clears the TE bit.
1 = Transmission enabled
0 = Transmission disabled
MC68HC05C8A • MC68HCL05C8A • MC68HSC05C8A Data Sheet, Rev. 5.1
54
Freescale Semiconductor
SCI Input/Output (I/O) Registers
RE — Receive Enable Bit
Setting this read/write bit enables the receiver. Clearing the RE bit disables the receiver and receiver
interrupts but does not affect the receiver interrupt flags. Reset clears the RE bit.
1 = Receiver enabled
0 = Receiver disabled
RWU — Receiver Wakeup Enable Bit
This read/write bit puts the receiver in a standby state. Typically, data transmitted to the receiver clears
the RWU bit and returns the receiver to normal operation. The WAKE bit in SCCR1 determines
whether an idle input or an address mark brings the receiver out of the standby state. Reset clears the
RWU bit.
1 = Standby state
0 = Normal operation
SBK — Send Break Bit
Setting this read/write bit continuously transmits break codes in the form of 10-bit or 11-bit groups of
logic 0s. Clearing the SBK bit stops the break codes and transmits a logic 1 as a start bit. Reset clears
the SBK bit.
1 = Break codes being transmitted
0 = No break codes being transmitted
9.5.4 SCI Status Register
The SCI status register contains flags to signal these conditions:
• Transfer of SCDR data to transmit shift register complete
• Transmission complete
• Transfer of receive shift register data to SCDR complete
• Receiver input idle
• Receiver overrun
• Noisy data
• Framing error
Address:
Read:
$0010
Bit 7
6
5
4
3
2
1
TDRE
TC
RDRF
IDLE
OR
NF
FE
0
0
0
0
0
0
0
Write:
Reset:
Bit 0
0
0
= Unimplemented
Figure 9-7. SCI Status Register (SCSR)
TDRE — Transmit Data Register Empty Bit
This clearable, read-only bit is set when the data in the SCDR transfers to the transmit shift register.
TDRE generates an interrupt request if the TIE bit in SCCR2 is also set. Clear the TDRE bit by reading
the SCSR with TDRE set, and then writing to the SCDR. Reset sets the TDRE bit. Software must
initialize the TDRE bit to logic 0 to avoid an instant interrupt request when turning on the transmitter.
1 = SCDR data transferred to transmit shift register
0 = SCDR data not transferred to transmit shift register
MC68HC05C8A • MC68HCL05C8A • MC68HSC05C8A Data Sheet, Rev. 5.1
Freescale Semiconductor
55
Serial Communications Interface (SCI)
TC — Transmission Complete Bit
This clearable, read-only bit is set when the TDRE bit is set, and no data, preamble, or break character
is being transmitted. TC generates an interrupt request if the TCIE bit in SCCR2 is also set. Clear the
TC bit by reading the SCSR with TC set, and then writing to the SCDR. Reset sets the TC bit. Software
must initialize the TC bit to logic 0 to avoid an instant interrupt request when turning on the transmitter.
1 = No transmission in progress
0 = Transmission in progress
RDRF — Receive Data Register Full Bit
This clearable, read-only bit is set when the data in the receive shift register transfers to the SCI data
register. RDRF generates an interrupt request if the RIE bit in SCCR2 is also set. Clear the RDRF bit
by reading the SCSR with RDRF set, and then reading the SCDR. Reset clears the RDRF bit.
1 = Received data available in SCDR
0 = Received data not available in SCDR
IDLE — Receiver Idle Bit
This clearable, read-only bit is set when 10 or 11 consecutive logic 1s appear on the receiver input.
IDLE generates an interrupt request if the ILIE bit in SCCR2 is also set. Clear the IDLE bit by reading
the SCSR with IDLE set, and then reading the SCDR. Reset clears the IDLE bit.
1 = Receiver input idle
0 = Receiver input not idle
OR — Receiver Overrun Bit
This clearable, read-only bit is set if the SCDR is not read before the receive shift register receives the
next word. OR generates an interrupt request if the RIE bit in SCCR2 is also set. The data in the shift
register is lost, but the data already in the SCDR is not affected. Clear the OR bit by reading the SCSR
with OR set and then reading the SCDR. Reset clears the OR bit.
1 = Receiver shift register full and RDRF = 1
0 = No receiver overrun
NF — Receiver Noise Flag
This clearable, read-only bit is set when noise is detected in data received in the SCI data register.
Clear the NF bit by reading the SCSR and then reading the SCDR. Reset clears the NF bit.
1 = Noise detected in SCDR
0 = No noise detected in SCDR
FE — Receiver Framing Error Flag
This clearable, read-only flag is set when there is a logic 0 where a stop bit should be in the character
shifted into the receive shift register. If the received word causes both a framing error and an overrun
error, the OR bit is set and the FE bit is not set. Clear the FE bit by reading the SCSR, and then reading
the SCDR. Reset clears the FE bit.
1 = Framing error
0 = No framing error
MC68HC05C8A • MC68HCL05C8A • MC68HSC05C8A Data Sheet, Rev. 5.1
56
Freescale Semiconductor
SCI Input/Output (I/O) Registers
9.5.5 Baud Rate Register
The baud rate register (BAUD) selects the baud rate for both the receiver and the transmitter.
Address: $000D
Read:
Write:
Reset:
Bit 7
6
5
4
3
2
1
Bit 0
0
0
SCP1
SCP0
0
SCR2
SCR2
SCR0
0
0
0
0
0
U
U
U
U = Unaffected
Figure 9-8. Baud Rate Register (BAUD)
SCP1 and SCP0 — SCI Prescaler Select Bits
These read/write bits control prescaling of the baud rate generator clock, as shown in Table 9-1.
Resets clear both SCP1 and SCP0.
Table 9-1. Baud Rate Generator Clock Prescaling
SCP0–SCP1
Baud Rate Generator Clock
00
Internal clock divided by 1
01
Internal clock divided by 3
10
Internal clock divided by 4
11
Internal clock divided by 13
SCR2–SCR0 — SCI Baud Rate Select Bits
These read/write bits select the SCI baud rate, as shown in Table 9-2. Reset has no effect on the
SCR2–SCR0 bits.
Table 9-2. Baud Rate Selection
SCR2–SCR0
SCI Baud Rate (Baud)
000
Prescaled clock divided by 1
001
Prescaled clock divided by 2
010
Prescaled clock divided by 4
011
Prescaled clock divided by 8
100
Prescaled clock divided by 16
101
Prescaled clock divided by 32
110
Prescaled clock divided by 64
111
Prescaled clock divided by 128
Table 9-3 shows all possible SCI baud rates derived from crystal frequencies of 2 MHz, 4 MHz, and
4.194304 MHz.
MC68HC05C8A • MC68HCL05C8A • MC68HSC05C8A Data Sheet, Rev. 5.1
Freescale Semiconductor
57
Serial Communications Interface (SCI)
Table 9-3. Baud Rate Selection Examples
SCI Baud Rate
SCP[1:0]
SCR
[2:1:0]
fOSC = 2 MHz
fOSC = 4 MHz
fOSC = 4.194304 MHz
00
000
62.50 kBaud
125 kBaud
131.1 kBaud
00
001
31.25 kBaud
62.50 kBaud
65.54 kBaud
00
010
15.63 kBaud
31.25 kBaud
32.77 kBaud
00
011
7813 Baud
15.63 kBaud
16.38 kBaud
00
100
3906 Baud
7813 Baud
8192 Baud
00
101
1953 Baud
3906 Baud
4096 Baud
00
110
976.6 Baud
1953 Baud
2048 Baud
00
111
488.3 Baud
976.6 Baud
1024 Baud
01
000
20.83 kBaud
41.67 kBaud
43.69 kBaud
01
001
10.42 kBaud
20.83 kBaud
21.85 kBaud
01
010
5208 Baud
10.42 kBaud
10.92 kBaud
01
011
2604 Baud
5208 Baud
5461 Baud
01
100
1302 Baud
2604 Baud
2731 Baud
01
101
651.0 Baud
1302 Baud
1365 Baud
01
110
325.5 Baud
651.0 Baud
682.7 Baud
01
111
162.8 Baud
325.5 Baud
341.3 Baud
10
000
15.63 kBaud
31.25 kBaud
32.77 kBaud
10
001
7813 Baud
15.63 kBaud
16.38 kBaud
10
010
3906 Baud
7813 Baud
8192 Baud
10
011
1953 Baud
3906 Baud
4906 Baud
10
100
976.6 Baud
1953 Baud
2048 Baud
10
101
488.3 Baud
976.6 Baud
1024 Baud
10
110
244.1 Baud
488.3 Baud
512.0 Baud
10
111
122.1 Baud
244.1 Baud
256.0 Baud
11
000
4808 Baud
9615 Baud
10.08 kBaud
11
001
2404 Baud
4808 Baud
5041 Baud
11
010
1202 Baud
2404 Baud
2521 Baud
11
011
601.0 Baud
1202 Baud
1260 Baud
11
100
300.5 Baud
601.0 Baud
630.2 Baud
11
101
150.2 Baud
300.5 Baud
315.1 Baud
11
110
75.12 Baud
150.2 Baud
157.5 Baud
11
111
37.56 Baud
75.12 Baud
78.77 Baud
MC68HC05C8A • MC68HCL05C8A • MC68HSC05C8A Data Sheet, Rev. 5.1
58
Freescale Semiconductor
Chapter 10
Serial Peripheral Interface (SPI)
10.1 Introduction
The serial peripheral interface (SPI) is an interface built into the MC68HC05 microcontroller unit (MCU)
which allows several MC68HC05 MCUs or MC68HC05 MCU plus peripheral devices to be interconnected
within a single printed circuit board. In an SPI, separate wires are required for data and clock. In the SPI
format, the clock is not included in the data stream and must be furnished as a separate signal. An SPI
system may be configured in a system containing one master MCU and several slave MCUs or in a
system in which an MCU is capble of being a master or a slave.
10.2 Features
Features include:
• Full duplex, 4-wire synchronous transfers
• Master or slave operation
• Bus frequency divided by 2 (maximum) master bit frequency
• Bus frequency (maximum) slave bit frequency
• Four programmable master bit rates
• Programmable clock polarity and phase
• End-of-transmission interrupt flag
• Write collision flag protection
• Master-master mode fault protection capability
10.3 SPI Signal Description
The four basic signals (MOSI, MISO, SCK, and SS) are described in this subsection. Each signal function
is described for both the master and slave mode.
10.3.1 Master In Slave Out (MISO)
The MISO line is configured as an input in a master device and as an output in a slave device. It is one
of the two lines that transfer serial data in one direction, with the most significant bit sent first. The MISO
line of a slave device is placed in the high-impedance state if the slave is not selected.
10.3.2 Master Out Slave In (MOSI)
The MOSI line is configured as an output in a master device and as an input in a slave device. It is one
of the two lines that transfer serial data in one direction with the most significant bit sent first.
MC68HC05C8A • MC68HCL05C8A • MC68HSC05C8A Data Sheet, Rev. 5.1
Freescale Semiconductor
59
Serial Peripheral Interface (SPI)
10.3.3 Serial Clock (SCK)
The master clock is used to synchronize data movement both in and out of the device through its MOSI
and MISO lines. The master and slave devices are capable of exchanging a byte of information during a
sequence of eight clock cycles. Since SCK is generated by the master device, this line becomes an input
on a slave device.
As shown in Figure 10-1, four possible timing relationships may be chosen by using control bits CPOL
and CPHA in the serial peripheral control register (SPCR). Both master and slave devices must operate
with the same timing. The master device always places data on the MOSI line one-half cycle before the
clock edge (SCK), so the slave device can latch the data.
Two bits (SPR0 and SPR1) in the SPCR of the master device select the clock rate. In a slave device,
SPR0 and SPR1 have no effect on the SPI operation.
SS
SCK
SCK
SCK
SCK
MISO/MOSI
MSB
6
5
4
3
2
1
0
INTERNAL STROBE FOR DATA CAPTURE (ALL MODES)
Figure 10-1. Data Clock Timing Diagram
10.3.4 Slave Select (SS)
The slave select (SS) input line is used to select a slave device. It has to be low prior to data transactions
and must stay low for the duration of the transaction.
The SS line on the master must be tied high. If it goes low, a mode fault error flag (MODF) is set in the
SPSR.
When CPHA = 0, the shift clock is the OR of SS with SCK. In this clock phase mode, SS must go high
between successive characters in an SPI message. When CPHA = 1, SS may be left low for several SPI
characters. In cases where there is only one SPI slave MCU, its SS line could be tied to VSS as long as
CPHA = 1 clock modes are used.
MC68HC05C8A • MC68HCL05C8A • MC68HSC05C8A Data Sheet, Rev. 5.1
60
Freescale Semiconductor
Functional Description
10.4 Functional Description
Figure 10-2 shows a block diagram of the SPI circuitry. When a master device transmits data to a slave
via the MOSI line, the slave device responds by sending data to the master device via the master’s MISO
line. This implies full duplex transmission with both data out and data in synchronized with the same clock
signal. Thus, the byte transmitted is replaced by the byte received and eliminates the need for separate
transmit-empty and receive-full status bits. A single status bit (SPIF) is used to signify that the input/output
(I/O) operation has been completed.
S
M
INTERNAL
MCU CLOCK
MSB
LSB
MISO
PD2
M
S
8-BIT SHIFT REG
MOSI
PD3
DIVIDER
÷2
÷4
÷ 16 ÷ 32
SELECT
S
CLOCK
LOGIC
M
SPR0
SPR1
CLOCK
SPI CLOCK
(MASTER)
PIN CONTROL LOGIC
READ DATA BUFF
SCK
PD4
SS
PD5
MSTR
SPR0
SPR1
CPOL
CPHA
MSTR
SPE
SPIE
SPE
MODF
WCOL
SPIF
SPI CONTROL
SPI CONTROL REGISTER
SPI STATUS REGISTER
INTERNAL
DATA BUS
SPI INTERRUPT
REQUEST
Figure 10-2. Serial Peripheral Interface Block Diagram
MC68HC05C8A • MC68HCL05C8A • MC68HSC05C8A Data Sheet, Rev. 5.1
Freescale Semiconductor
61
Serial Peripheral Interface (SPI)
The SPI data register (SPDR) is double buffered on read, but not on write. If a write is performed during
data transfer, the transfer occurs uninterrupted, and the write will be unsuccessful. This condition will
cause the write collision (WCOL) status bit in the SPSR to be set. After a data byte is shifted, the SPIF
flag of the SPSR is set.
In the master mode, the SCK pin is an output. It idles high or low, depending on the CPOL bit in the SPCR,
until data is written to the shift register, at which point eight clocks are generated to shift the eight bits of
data and then SCK goes idle again.
In a slave mode, the slave select start logic receives a logic low at the SS pin and a clock at the SCK pin.
Thus, the slave is synchronized with the master. Data from the master is received serially at the MOSI
line and loads the 8-bit shift register. After the 8-bit shift register is loaded, its data is parallel transferred
to the read buffer. During a write cycle, data is written into the shift register, then the slave waits for a clock
train from the master to shift the data out on the slave’s MISO line.
Figure 10-3 illustrates the MOSI, MISO, SCK, and SS master-slave interconnections.
PD3/MOSI
SPI SHIFT REGISTER
SPI SHIFT REGISTER
PD2/MISO
I/O PORT
PD5
SS
SPDR ($000C)
SPDR ($000C)
PD4/SCK
MASTER MCU
SLAVE MCU
Figure 10-3. Serial Peripheral Interface Master-Slave Interconnection
10.5 SPI Registers
This subsection describes the three registers in the SPI which provide control, status, and data storage
functions. These registers are:
• Serial peripheral control register (SPCR)
• Serial peripheral status register (SPSR)
• Serial peripheral data I/O register (SPDR)
MC68HC05C8A • MC68HCL05C8A • MC68HSC05C8A Data Sheet, Rev. 5.1
62
Freescale Semiconductor
SPI Registers
10.5.1 Serial Peripheral Control Register
Address: $000A
Read:
Write:
Reset
Bit 7
6
SPIE
SPE
0
0
5
0
= Unimplemented
4
3
2
1
Bit 0
MSTR
CPOL
CPHA
SPR1
SPR0
0
0
0
U
U
U = Unaffected
Figure 10-4. SPI Control Register (SPCR)
SPIE — Serial Peripheral Interrupt Enable Bit
0 = SPIF interrupts disabled
1 = SPI interrupt is enabled
SPE — Serial Peripheral System Enable Bit
0 = SPI system off
1 = SPI system on
MSTR — Master Mode Select Bit
0 = Slave mode
1 = Master mode
CPOL — Clock Polarity Bit
When the clock polarity bit is cleared and data is not being transferred, a steady state low value is
produced at the SCK pin of the master device. Conversely, if this bit is set, the SCK pin will idle high.
This bit also is used in conjunction with the clock phase control bit to produce the desired clock-data
relationship between master and slave. See Figure 10-1.
CPHA — Clock Phase Bit
The clock phase bit, in conjunction with the CPOL bit, controls the clock-data relationship between
master and slave. The CPOL bit can be thought of as simply inserting an inverter in series with the
SCK line. The CPHA bit selects one of two fundamentally different clocking protocols. When CPHA =
0, the shift clock is the OR of SCK with SS. As soon as SS goes low, the transaction begins and the
first edge on SCK invokes the first data sample. When CPHA = 1, the SS pin may be thought of as a
simple output enable control. See Figure 10-1.
SPR1 and SPR0 — SPI Clock Rate Select Bits
These two bits select one of four baud rates to be used as SCK if the device is a master; however, they
have no effect in the slave mode. See Table 10-1.
Table 10-1. Serial Peripheral Rate Selection
SPR1
SPR0
Bus Clock Divided By
0
0
2
0
1
4
1
0
16
1
1
32
MC68HC05C8A • MC68HCL05C8A • MC68HSC05C8A Data Sheet, Rev. 5.1
Freescale Semiconductor
63
Serial Peripheral Interface (SPI)
10.5.2 Serial Peripheral Status Register
Address: $000B
Read:
Write:
Reset
Bit 7
6
SPIF
WCOL
0
0
= Unimplemented
5
0
0
4
MODF
0
3
2
1
Bit 0
0
0
0
0
0
0
U
U
U = Unaffected
Figure 10-5. SPI Status Register (SPSR)
SPIF — SPI Transfer Complete Flag
The serial peripheral data transfer flag bit is set upon completion of data transfer between the
processor and external device. If SPIF goes high and if SPIE is set, a serial peripheral interrupt is
generated. Clearing the SPIF bit is accomplished by reading the SPSR (with SPIF set) followed by an
access of the SPDR. Unless SPSR is read (with SPIF set) first, attempts to write to SPDR are inhibited.
WCOL — Write Collision Bit
The write collision bit is set when an attempt is made to write to the serial peripheral data register while
data transfer is taking place. If CPHA is 0, a transfer is said to begin when SS goes low and the transfer
ends when SS goes high after eight clock cycles on SCK. When CPHA is 1, a transfer is said to begin
the first time SCK becomes active while SS is low. The transfer ends when the SPIF flag gets set.
Clearing the WCOL bit is accomplished by reading the SPSR (with WCOL set) followed by an access
to SPDR.
Bit 5 — Not implemented
This bit always reads as 0.
MODF — Mode Fault Flag
The mode fault flag indicates that there may have been a multi-master conflict for system control and
allows a proper exit from system operation to a reset or default system state. The MODF bit is normally
clear and is set only when the master device has its SS pin pulled low. Setting the MODF bit affects
the internal serial peripheral interface system in these ways:
• An SPI interrupt is generated if SPIE = 1.
• The SPE bit is cleared. This disables the SPI.
• The MSTR bit is cleared, thus forcing the device into the slave mode.
Clearing the MODF bit is accomplished by reading the SPSR (with MODF set), followed by a write to
the SPCR. Control bits SPE and MSTR may be restored by user software to their original state after
the MODF bit has been cleared.
Bits 3–0 — Not Implemented
These bits always reads as 0.
MC68HC05C8A • MC68HCL05C8A • MC68HSC05C8A Data Sheet, Rev. 5.1
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SPI Registers
10.5.3 Serial Peripheral Data I/O Register
Address: $000C
Read:
Write:
Reset
Bit 7
6
5
4
3
2
1
Bit 0
SPD7
SPD6
SPD5
SPD4
SPD3
SPD2
SPD1
SPD0
Unaffected by reset
Figure 10-6. SPI Data Register (SPSR)
The serial peripheral data I/O register is used to transmit and receive data on the serial bus. Only a write
to this register will initiate transmission/reception of another byte, and this will occur only in the master
device. At the completion of transmitting a byte of data, the SPIF status bit is set in both the master and
slave devices.
When the user reads the serial peripheral data I/O register, a buffer is actually being read. The first SPIF
must be cleared by the time a second transfer of the data from the shift register to the read buffer is
initiated or an overrun condition will exist. In cases of overrun, the byte which causes the overrun is lost.
A write to the serial peripheral data I/O register is not buffered and places data directly into the shift
register for transmission.
MC68HC05C8A • MC68HCL05C8A • MC68HSC05C8A Data Sheet, Rev. 5.1
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Serial Peripheral Interface (SPI)
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Freescale Semiconductor
Chapter 11
Operating Modes
11.1 Introduction
The microcontroller unit (MCU) has two modes of operation: user mode and self-check mode. Table 11-1
shows the conditions required to enter into each mode, where VTST = 2 x VDD.
Table 11-1. Operating Mode Conditions
RESET
IRQ
TCAP
Mode
VSS to VDD
VSS to VDD
User
VTST
VDD
Self-Check
11.2 User Mode
In user mode, the address and data buses are not available externally, but there are three 8-bit
input/output (I/O) ports and one 7-bit input-only port. This mode allows the MCU to function as a
self-contained microcontroller, with maximum use of the pins for on-chip peripheral functions. All address
and data activity occurs within the MCU. User mode is entered on the rising edge of RESET if the IRQ
pin is within normal operating range.
The user mode pinout is shown in Figure 11-1.
MC68HC05C8A • MC68HCL05C8A • MC68HSC05C8A Data Sheet, Rev. 5.1
Freescale Semiconductor
67
Operating Modes
RESET
1
40
VDD
IRQ
2
39
OSC1
NC
3
38
OSC2
PA7
4
37
TCAP
PA6
5
36
PD7
PA5
6
35
PD6/TCMP
PA4
7
34
PD5/SS
PA3
8
33
PD4/SCK
PA2
9
32
PD3/MOSI
PA1
10
31
PD2/MISO
PA0
11
30
PD1/TDO
PB0
12
29
PD0/RDI
PB1
13
28
PC0
PB2
14
27
PC1
PB3
15
26
PC2
PB4
16
25
PC3
PB5
17
24
PC4
PB6
18
23
PC5
PB7
19
22
PC6
VSS
20
21
PC7
Figure 11-1. User Mode Pinout
11.3 Self-Check Mode
Self-check mode is entered upon the rising edge of RESET if the IRQ pin is at VTST and the TCAP pin is
at logic 1.
11.3.1 Self-Check Tests
The self-check read-only memory (ROM) at mask ROM location $1F00–$1FEF determines if the MCU is
functioning properly.These tests are performed:
1. I/O — Functional test of ports A, B, and C
2. Random-access memory (RAM) — Counter test for each RAM byte
3. Timer — Test of counter register and OCF bit
4. Serial communications interface (SCI) — Transmission test checks for RDRF, TDRE, TC, and FE
flags
5. Read-only memory (ROM) — Exclusive OR with odd ones parity result
6. Serial peripheral interface (SPI) — Transmission test checks for SPIF and WCOL flags
The self-check circuit is shown in Figure 11-2.
MC68HC05C8A • MC68HCL05C8A • MC68HSC05C8A Data Sheet, Rev. 5.1
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Freescale Semiconductor
Self-Check Mode
VDD
VDD
10 V
1
40
VDD
IRQ
2
39
OSC1
NC
3
38
OSC2
PA7
4
37
TCAP
PA6
5
36
PD7
4 MHZ
V
PA5
6
35
TCMP
PA4
7
34
PD5/SS
PA3
8
33
PD4/SCK
PA2
9
32
PD3/MOSI
PA1
10
31
PD2/MISO
PA0
11
30
PD1/TDO
PB0
12
29
PD0/RDI
PB1
13
28
PC0
PB2
14
27
PC1
PB3
15
26
PC2
PB4
16
25
PC3
PB5
17
24
PC4
PB6
18
23
PC5
PB7
19
22
PC6
VSS
20
21
PC7
DD
10 MΩ
10 kΩ
20 pF
20 pF
1 MΩ
CMOS
BUFFER
330 Ω
330 Ω
(MC74HC125)
330 Ω
RESET
4.7 kΩ
VDD
MC68H05C8A
330 Ω
MC34064
V
DD
Notes:
1. VDD = 5.0 V
2. TCMP = NC
Figure 11-2. Self-Check Circuit Schematic
MC68HC05C8A • MC68HCL05C8A • MC68HSC05C8A Data Sheet, Rev. 5.1
Freescale Semiconductor
69
Operating Modes
11.3.2 Self-Check Results
Table 11-2 shows the light-emitting diode (LED) codes that indicate self-check test results.
Table 11-2. Self-Check Circuit LED Codes
PC3
PC2
PC1
PC0
Remarks
Off
On
On
Off
I/O failure
Off
On
Off
On
RAM failure
Off
On
Off
Off
Timer failure
Off
Off
On
On
SCI failure
Off
Off
On
Off
ROM failure
Off
Off
Off
On
SPI failure
Flashing
No failure
All others
Device failure
Perform these steps to activate the self-check tests:
1. Apply 10 V (2 x VDD) to the IRQ pin.
2. Apply a logic 1 to the TCAP pin.
3. Apply a logic 0 to the RESET pin.
The self-check tests begin on the rising edge of the RESET pin.
RESET must be held low for 4064 cycles after power-on reset (POR) or for a time, tRL, for any other reset.
For the tRL value, see 13.8 5.0-V Control Timing.
MC68HC05C8A • MC68HCL05C8A • MC68HSC05C8A Data Sheet, Rev. 5.1
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Freescale Semiconductor
Chapter 12
Instruction Set
12.1 Introduction
The microcontroller unit (MCU) instruction set has 62 instructions and uses eight addressing modes. The
instructions include all those of the M146805 CMOS (complementary metal oxide silicon) Family plus one
more: the unsigned multiply (MUL) instruction. The MUL instruction allows unsigned multiplication of the
contents of the accumulator (A) and the index register (X). The high-order product is stored in the index
register, and the low-order product is stored in the accumulator.
12.2 Addressing Modes
The central processor unit (CPU) uses eight addressing modes for flexibility in accessing data. The
addressing modes provide eight different ways for the CPU to find the data required to execute an
instruction. The eight addressing modes are:
• Inherent
• Immediate
• Direct
• Extended
• Indexed, no offset
• Indexed, 8-bit offset
• Indexed, 16-bit offset
• Relative
12.2.1 Inherent
Inherent instructions are those that have no operand, such as return from interrupt (RTI) and stop (STOP).
Some of the inherent instructions act on data in the CPU registers, such as set carry flag (SEC) and
increment accumulator (INCA). Inherent instructions require no operand address and are one byte long.
12.2.2 Immediate
Immediate instructions are those that contain a value to be used in an operation with the value in the
accumulator or index register. Immediate instructions require no operand address and are two bytes long.
The opcode is the first byte, and the immediate data value is the second byte.
12.2.3 Direct
Direct instructions can access any of the first 256 memory locations with two bytes. The first byte is the
opcode, and the second is the low byte of the operand address. In direct addressing, the CPU
automatically uses $00 as the high byte of the operand address.
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Instruction Set
12.2.4 Extended
Extended instructions use three bytes and can access any address in memory. The first byte is the
opcode; the second and third bytes are the high and low bytes of the operand address.
When using the Freescale assembler, the programmer does not need to specify whether an instruction is
direct or extended. The assembler automatically selects the shortest form of the instruction.
12.2.5 Indexed, No Offset
Indexed instructions with no offset are 1-byte instructions that can access data with variable addresses
within the first 256 memory locations. The index register contains the low byte of the effective address of
the operand. The CPU automatically uses $00 as the high byte, so these instructions can address
locations $0000–$00FF.
Indexed, no offset instructions are often used to move a pointer through a table or to hold the address of
a frequently used random-access memory (RAM) or input/output (I/O) location.
12.2.6 Indexed, 8-Bit Offset
Indexed, 8-bit offset instructions are 2-byte instructions that can access data with variable addresses
within the first 511 memory locations. The CPU adds the unsigned byte in the index register to the
unsigned byte following the opcode. The sum is the effective address of the operand. These instructions
can access locations $0000–$01FE.
Indexed 8-bit offset instructions are useful for selecting the kth element in an n-element table. The table
can begin anywhere within the first 256 memory locations and could extend as far as location 510
($01FE). The k value is typically in the index register, and the address of the beginning of the table is in
the byte following the opcode.
12.2.7 Indexed, 16-Bit Offset
Indexed, 16-bit offset instructions are 3-byte instructions that can access data with variable addresses at
any location in memory. The CPU adds the unsigned byte in the index register to the two unsigned bytes
following the opcode. The sum is the effective address of the operand. The first byte after the opcode is
the high byte of the 16-bit offset; the second byte is the low byte of the offset.
Indexed, 16-bit offset instructions are useful for selecting the kth element in an n-element table anywhere
in memory.
As with direct and extended addressing, the Freescale assembler determines the shortest form of
indexed addressing.
12.2.8 Relative
Relative addressing is only for branch instructions. If the branch condition is true, the CPU finds the
effective branch destination by adding the signed byte following the opcode to the contents of the program
counter. If the branch condition is not true, the CPU goes to the next instruction. The offset is a signed,
two’s complement byte that gives a branching range of –128 to +127 bytes from the address of the next
location after the branch instruction.
When using the Freescale assembler, the programmer does not need to calculate the offset, because the
assembler determines the proper offset and verifies that it is within the span of the branch.
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Instruction Types
12.3 Instruction Types
The MCU instructions fall into the following five categories:
• Register/Memory instructions
• Read-Modify-Write instructions
• Jump/Branch instructions
• Bit Manipulation instructions
• Control instructions
12.3.1 Register/Memory Instructions
These instructions operate on CPU registers and memory locations. Most of them use two operands. One
operand is in either the accumulator or the index register. The CPU finds the other operand in memory.
Table 12-1. Register/Memory Instructions
Instruction
Mnemonic
Add Memory Byte and Carry Bit to Accumulator
ADC
Add Memory Byte to Accumulator
ADD
AND Memory Byte with Accumulator
AND
Bit Test Accumulator
BIT
Compare Accumulator
CMP
Compare Index Register with Memory Byte
CPX
EXCLUSIVE OR Accumulator with Memory Byte
EOR
Load Accumulator with Memory Byte
LDA
Load Index Register with Memory Byte
LDX
Multiply
MUL
OR Accumulator with Memory Byte
ORA
Subtract Memory Byte and Carry Bit from Accumulator
SBC
Store Accumulator in Memory
STA
Store Index Register in Memory
STX
Subtract Memory Byte from Accumulator
SUB
MC68HC05C8A • MC68HCL05C8A • MC68HSC05C8A Data Sheet, Rev. 5.1
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73
Instruction Set
12.3.2 Read-Modify-Write Instructions
These instructions read a memory location or a register, modify its contents, and write the modified value
back to the memory location or to the register.
NOTE
Do not use read-modify-write operations on write-only registers.
Table 12-2. Read-Modify-Write Instructions
Instruction
Mnemonic
Arithmetic Shift Left (Same as LSL)
ASL
Arithmetic Shift Right
ASR
Bit Clear
BCLR(1)
Bit Set
BSET(1)
Clear Register
CLR
Complement (One’s Complement)
COM
Decrement
DEC
Increment
INC
Logical Shift Left (Same as ASL)
LSL
Logical Shift Right
LSR
Negate (Two’s Complement)
NEG
Rotate Left through Carry Bit
ROL
Rotate Right through Carry Bit
ROR
Test for Negative or Zero
TST(2)
1. Unlike other read-modify-write instructions, BCLR and
BSET use only direct addressing.
2. TST is an exception to the read-modify-write sequence
because it does not write a replacement value.
MC68HC05C8A • MC68HCL05C8A • MC68HSC05C8A Data Sheet, Rev. 5.1
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Freescale Semiconductor
Instruction Types
12.3.3 Jump/Branch Instructions
Jump instructions allow the CPU to interrupt the normal sequence of the program counter. The
unconditional jump instruction (JMP) and the jump-to-subroutine instruction (JSR) have no register
operand. Branch instructions allow the CPU to interrupt the normal sequence of the program counter
when a test condition is met. If the test condition is not met, the branch is not performed.
The BRCLR and BRSET instructions cause a branch based on the state of any readable bit in the first
256 memory locations. These 3-byte instructions use a combination of direct addressing and relative
addressing. The direct address of the byte to be tested is in the byte following the opcode. The third byte
is the signed offset byte. The CPU finds the effective branch destination by adding the third byte to the
program counter if the specified bit tests true. The bit to be tested and its condition (set or clear) is part of
the opcode. The span of branching is from –128 to +127 from the address of the next location after the
branch instruction. The CPU also transfers the tested bit to the carry/borrow bit of the condition code
register.
Table 12-3. Jump and Branch Instructions
Instruction
Mnemonic
Branch if Carry Bit Clear
BCC
Branch if Carry Bit Set
BCS
Branch if Equal
BEQ
Branch if Half-Carry Bit Clear
BHCC
Branch if Half-Carry Bit Set
BHCS
Branch if Higher
BHI
Branch if Higher or Same
BHS
Branch if IRQ Pin High
BIH
Branch if IRQ Pin Low
BIL
Branch if Lower
BLO
Branch if Lower or Same
BLS
Branch if Interrupt Mask Clear
BMC
Branch if Minus
BMI
Branch if Interrupt Mask Set
BMS
Branch if Not Equal
BNE
Branch if Plus
BPL
Branch Always
BRA
Branch if Bit Clear
Branch Never
Branch if Bit Set
BRCLR
BRN
BRSET
Branch to Subroutine
BSR
Unconditional Jump
JMP
Jump to Subroutine
JSR
MC68HC05C8A • MC68HCL05C8A • MC68HSC05C8A Data Sheet, Rev. 5.1
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Instruction Set
12.3.4 Bit Manipulation Instructions
The CPU can set or clear any writable bit in the first 256 bytes of memory, which includes I/O registers
and on-chip RAM locations. The CPU can also test and branch based on the state of any bit in any of the
first 256 memory locations.
Table 12-4. Bit Manipulation Instructions
Instruction
Bit Clear
Mnemonic
BCLR
Branch if Bit Clear
BRCLR
Branch if Bit Set
BRSET
Bit Set
BSET
12.3.5 Control Instructions
These instructions act on CPU registers and control CPU operation during program execution.
Table 12-5. Control Instructions
Instruction
Mnemonic
Clear Carry Bit
CLC
Clear Interrupt Mask
CLI
No Operation
NOP
Reset Stack Pointer
RSP
Return from Interrupt
RTI
Return from Subroutine
RTS
Set Carry Bit
SEC
Set Interrupt Mask
SEI
Stop Oscillator and Enable IRQ Pin
STOP
Software Interrupt
SWI
Transfer Accumulator to Index Register
TAX
Transfer Index Register to Accumulator
TXA
Stop CPU Clock and Enable Interrupts
WAIT
MC68HC05C8A • MC68HCL05C8A • MC68HSC05C8A Data Sheet, Rev. 5.1
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Freescale Semiconductor
Instruction Set Summary
12.4 Instruction Set Summary
ADD #opr
ADD opr
ADD opr
ADD opr,X
ADD opr,X
ADD ,X
AND #opr
AND opr
AND opr
AND opr,X
AND opr,X
AND ,X
ASL opr
ASLA
ASLX
ASL opr,X
ASL ,X
— IMM
DIR
EXT
IX2
IX1
IX
2
A9 ii
B9 dd 3
C9 hh ll 4
D9 ee ff 5
4
E9 ff
3
F9
— IMM
DIR
EXT
IX2
IX1
IX
2
AB ii
BB dd 3
CB hh ll 4
DB ee ff 5
4
EB ff
3
FB
— — —
IMM
DIR
EXT
IX2
IX1
IX
2
A4 ii
B4 dd 3
C4 hh ll 4
D4 ee ff 5
4
E4 ff
3
F4
38
48
58
68
78
dd
— — DIR
INH
INH
IX1
IX
DIR
INH
INH
IX1
IX
37
47
57
67
77
dd
REL
Effect
on CCR
Description
H I N Z C
A ← (A) + (M) + (C)
Add with Carry
A ← (A) + (M)
Add without Carry
A ← (A) ∧ (M)
Logical AND
Arithmetic Shift Left (Same as LSL)
C
0
b7
ASR opr
ASRA
ASRX
ASR opr,X
ASR ,X
Arithmetic Shift Right
BCC rel
Branch if Carry Bit Clear
b0
C
b7
— — b0
PC ← (PC) + 2 + rel ? C = 0
ff
5
3
3
6
5
5
3
3
6
5
24
rr
3
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
— — — — —
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
11
13
15
17
19
1B
1D
1F
dd
dd
dd
dd
dd
dd
dd
dd
5
5
5
5
5
5
5
5
PC ← (PC) + 2 + rel ? C = 1
— — — — —
REL
25
rr
3
Mn ← 0
— — — — —
ff
Cycles
Opcode
ADC #opr
ADC opr
ADC opr
ADC opr,X
ADC opr,X
ADC ,X
Operation
Address
Mode
Source
Form
Operand
Table 12-6. Instruction Set Summary (Sheet 1 of 6)
BCLR n opr
Clear Bit n
BCS rel
Branch if Carry Bit Set (Same as BLO)
BEQ rel
Branch if Equal
PC ← (PC) + 2 + rel ? Z = 1
— — — — —
REL
27
rr
3
BHCC rel
Branch if Half-Carry Bit Clear
PC ← (PC) + 2 + rel ? H = 0
— — — — —
REL
28
rr
3
BHCS rel
Branch if Half-Carry Bit Set
PC ← (PC) + 2 + rel ? H = 1
— — — — —
REL
29
rr
3
BHI rel
Branch if Higher
PC ← (PC) + 2 + rel ? C ∨ Z = 0 — — — — —
REL
22
rr
3
BHS rel
Branch if Higher or Same
PC ← (PC) + 2 + rel ? C = 0
— — — — —
REL
24
rr
3
BIH rel
Branch if IRQ Pin High
PC ← (PC) + 2 + rel ? IRQ = 1
— — — — —
REL
2F
rr
3
BIL rel
Branch if IRQ Pin Low
PC ← (PC) + 2 + rel ? IRQ = 0
— — — — —
REL
2E
rr
3
MC68HC05C8A • MC68HCL05C8A • MC68HSC05C8A Data Sheet, Rev. 5.1
Freescale Semiconductor
77
Instruction Set
H I N Z C
BIT #opr
BIT opr
BIT opr
BIT opr,X
BIT opr,X
BIT ,X
Bit Test Accumulator with Memory Byte
BLO rel
Branch if Lower (Same as BCS)
BLS rel
Branch if Lower or Same
IMM
DIR
EXT
IX2
IX1
IX
2
A5 ii
B5 dd 3
C5 hh ll 4
D5 ee ff 5
4
E5 ff
3
F5
Cycles
Description
Opcode
Operation
Effect
on CCR
Address
Mode
Source
Form
Operand
Table 12-6. Instruction Set Summary (Sheet 2 of 6)
(A) ∧ (M)
— — —
PC ← (PC) + 2 + rel ? C = 1
— — — — —
REL
25
rr
3
PC ← (PC) + 2 + rel ? C ∨ Z = 1 — — — — —
REL
23
rr
3
BMC rel
Branch if Interrupt Mask Clear
PC ← (PC) + 2 + rel ? I = 0
— — — — —
REL
2C
rr
3
BMI rel
Branch if Minus
PC ← (PC) + 2 + rel ? N = 1
— — — — —
REL
2B
rr
3
BMS rel
Branch if Interrupt Mask Set
PC ← (PC) + 2 + rel ? I = 1
— — — — —
REL
2D
rr
3
BNE rel
Branch if Not Equal
PC ← (PC) + 2 + rel ? Z = 0
— — — — —
REL
26
rr
3
BPL rel
Branch if Plus
PC ← (PC) + 2 + rel ? N = 0
— — — — —
REL
2A
rr
3
BRA rel
Branch Always
PC ← (PC) + 2 + rel ? 1 = 1
— — — — —
REL
20
rr
3
01
03
05
07
09
0B
0D
0F
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
5
5
5
5
5
5
5
5
BRCLR n opr rel Branch if Bit n Clear
BRN rel
Branch Never
BRSET n opr rel Branch if Bit n Set
BSET n opr
Set Bit n
PC ← (PC) + 2 + rel ? Mn = 0
PC ← (PC) + 2 + rel ? 1 = 0
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
— — — — DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
— — — — —
21
rr
3
PC ← (PC) + 2 + rel ? Mn = 1
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
— — — — DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
REL
00
02
04
06
08
0A
0C
0E
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
5
5
5
5
5
5
5
5
Mn ← 1
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
— — — — —
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
10
12
14
16
18
1A
1C
1E
dd
dd
dd
dd
dd
dd
dd
dd
5
5
5
5
5
5
5
5
PC ← (PC) + 2; push (PCL)
SP ← (SP) – 1; push (PCH)
SP ← (SP) – 1
PC ← (PC) + rel
— — — — —
REL
AD
rr
6
BSR rel
Branch to Subroutine
CLC
Clear Carry Bit
C←0
— — — — 0
INH
98
2
CLI
Clear Interrupt Mask
I←0
— 0 — — —
INH
9A
2
MC68HC05C8A • MC68HCL05C8A • MC68HSC05C8A Data Sheet, Rev. 5.1
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Freescale Semiconductor
Instruction Set Summary
CMP #opr
CMP opr
CMP opr
CMP opr,X
CMP opr,X
CMP ,X
COM opr
COMA
COMX
COM opr,X
COM ,X
CPX #opr
CPX opr
CPX opr
CPX opr,X
CPX opr,X
CPX ,X
DEC opr
DECA
DECX
DEC opr,X
DEC ,X
EOR #opr
EOR opr
EOR opr
EOR opr,X
EOR opr,X
EOR ,X
INC opr
INCA
INCX
INC opr,X
INC ,X
JMP opr
JMP opr
JMP opr,X
JMP opr,X
JMP ,X
JSR opr
JSR opr
JSR opr,X
JSR opr,X
JSR ,X
DIR
INH
INH
IX1
IX
3F
4F
5F
6F
7F
dd
— — IMM
DIR
EXT
IX2
IX1
IX
2
A1 ii
B1 dd 3
C1 hh ll 4
D1 ee ff 5
4
E1 ff
3
F1
— — 1
DIR
INH
INH
IX1
IX
33
43
53
63
73
— — IMM
DIR
EXT
IX2
IX1
IX
2
A3 ii
B3 dd 3
C3 hh ll 4
D3 ee ff 5
4
E3 ff
3
F3
— — —
DIR
INH
INH
IX1
IX
3A
4A
5A
6A
7A
— — —
IMM
DIR
EXT
IX2
IX1
IX
2
A8 ii
B8 dd 3
C8 hh ll 4
D8 ee ff 5
4
E8 ff
3
F8
— — —
DIR
INH
INH
IX1
IX
3C
4C
5C
6C
7C
— — — — —
DIR
EXT
IX2
IX1
IX
BC dd 2
CC hh ll 3
DC ee ff 4
EC ff
3
FC
2
— — — — —
DIR
EXT
IX2
IX1
IX
BD dd 5
CD hh ll 6
DD ee ff 7
6
ED ff
5
FD
Effect
on CCR
H I N Z C
Clear Byte
Compare Accumulator with Memory Byte
Complement Byte (One’s Complement)
Compare Index Register with Memory Byte
Decrement Byte
EXCLUSIVE OR Accumulator with Memory
Byte
Increment Byte
M ← $00
A ← $00
X ← $00
M ← $00
M ← $00
(A) – (M)
M ← (M) = $FF – (M)
A ← (A) = $FF – (A)
X ← (X) = $FF – (X)
M ← (M) = $FF – (M)
M ← (M) = $FF – (M)
(X) – (M)
M ← (M) – 1
A ← (A) – 1
X ← (X) – 1
M ← (M) – 1
M ← (M) – 1
A ← (A) ⊕ (M)
M ← (M) + 1
A ← (A) + 1
X ← (X) + 1
M ← (M) + 1
M ← (M) + 1
Unconditional Jump
PC ← Jump Address
Jump to Subroutine
PC ← (PC) + n (n = 1, 2, or 3)
Push (PCL); SP ← (SP) – 1
Push (PCH); SP ← (SP) – 1
PC ← Effective Address
— — 0 1 —
ff
dd
ff
dd
ff
dd
ff
Cycles
Description
Operand
CLR opr
CLRA
CLRX
CLR opr,X
CLR ,X
Operation
Opcode
Source
Form
Address
Mode
Table 12-6. Instruction Set Summary (Sheet 3 of 6)
5
3
3
6
5
5
3
3
6
5
5
3
3
6
5
5
3
3
6
5
MC68HC05C8A • MC68HCL05C8A • MC68HSC05C8A Data Sheet, Rev. 5.1
Freescale Semiconductor
79
Instruction Set
LDX #opr
LDX opr
LDX opr
LDX opr,X
LDX opr,X
LDX ,X
LSL opr
LSLA
LSLX
LSL opr,X
LSL ,X
2
A6 ii
B6 dd 3
C6 hh ll 4
D6 ee ff 5
4
E6 ff
3
F6
A ← (M)
— — —
IMM
DIR
EXT
IX2
IX1
IX
2
AE ii
BE dd 3
CE hh ll 4
DE ee ff 5
4
EE ff
3
FE
X ← (M)
Load Index Register with Memory Byte
38
48
58
68
78
dd
— — DIR
INH
INH
IX1
IX
Logical Shift Left (Same as ASL)
C
0
b7
DIR
INH
INH
IX1
IX
34
44
54
64
74
dd
MUL
Unsigned Multiply
0 — — — 0
INH
42
0
C
b7
NEG opr
NEGA
NEGX
NEG opr,X
NEG ,X
— — DIR
INH
INH
IX1
IX
30
40
50
60
70
Negate Byte (Two’s Complement)
NOP
No Operation
INH
9D
M ← –(M) = $00 – (M)
A ← –(A) = $00 – (A)
X ← –(X) = $00 – (X)
M ← –(M) = $00 – (M)
M ← –(M) = $00 – (M)
— — — — —
A ← (A) ∨ (M)
C
b7
ROR opr
RORA
RORX
ROR opr,X
ROR ,X
Rotate Byte Right through Carry Bit
RSP
Reset Stack Pointer
— — 0 b0
X : A ← (X) × (A)
Logical OR Accumulator with Memory
Rotate Byte Left through Carry Bit
b0
dd
ff
— — —
39
49
59
69
79
dd
— — DIR
INH
INH
IX1
IX
DIR
INH
INH
IX1
IX
36
46
56
66
76
dd
INH
9C
— — — — —
5
3
3
6
5
5
3
3
6
5
2
AA
BA
CA
DA
EA
FA
— — 5
3
3
6
5
1
1
IMM
DIR
EXT
IX2
IX1
IX
b0
SP ← $00FF
ff
ii
dd
hh ll
ee ff
ff
b0
C
b7
ff
Cycles
Description
Load Accumulator with Memory Byte
Logical Shift Right
ROL opr
ROLA
ROLX
ROL opr,X
ROL ,X
— — —
IMM
DIR
EXT
IX2
IX1
IX
Effect
on CCR
H I N Z C
LSR opr
LSRA
LSRX
LSR opr,X
LSR ,X
ORA #opr
ORA opr
ORA opr
ORA opr,X
ORA opr,X
ORA ,X
Opcode
LDA #opr
LDA opr
LDA opr
LDA opr,X
LDA opr,X
LDA ,X
Operation
Address
Mode
Source
Form
Operand
Table 12-6. Instruction Set Summary (Sheet 4 of 6)
ff
ff
2
3
4
5
4
3
5
3
3
6
5
5
3
3
6
5
2
MC68HC05C8A • MC68HCL05C8A • MC68HSC05C8A Data Sheet, Rev. 5.1
80
Freescale Semiconductor
Instruction Set Summary
INH
80
9
— — — — —
INH
81
6
A ← (A) – (M) – (C)
— — IMM
DIR
EXT
IX2
IX1
IX
2
A2 ii
B2 dd 3
C2 hh ll 4
D2 ee ff 5
4
E2 ff
3
F2
Description
RTI
Return from Interrupt
SP ← (SP) + 1; Pull (CCR)
SP ← (SP) + 1; Pull (A)
SP ← (SP) + 1; Pull (X)
SP ← (SP) + 1; Pull (PCH)
SP ← (SP) + 1; Pull (PCL)
RTS
Return from Subroutine
SP ← (SP) + 1; Pull (PCH)
SP ← (SP) + 1; Pull (PCL)
Effect
on CCR
SBC #opr
SBC opr
SBC opr
SBC opr,X
SBC opr,X
SBC ,X
Subtract Memory Byte and Carry Bit from
Accumulator
SEC
Set Carry Bit
C←1
— — — — 1
INH
99
SEI
Set Interrupt Mask
I←1
— 1 — — —
INH
9B
STA opr
STA opr
STA opr,X
STA opr,X
STA ,X
Store Accumulator in Memory
STOP
Stop Oscillator and Enable IRQ Pin
STX opr
STX opr
STX opr,X
STX opr,X
STX ,X
SUB #opr
SUB opr
SUB opr
SUB opr,X
SUB opr,X
SUB ,X
Store Index Register In Memory
Subtract Memory Byte from Accumulator
SWI
Software Interrupt
TAX
Transfer Accumulator to Index Register
TST opr
TSTA
TSTX
TST opr,X
TST ,X
Test Memory Byte for Negative or Zero
M ← (A)
— — —
DIR
EXT
IX2
IX1
IX
B7
C7
D7
E7
F7
— 0 — — —
INH
8E
Cycles
H I N Z C
Opcode
Operation
Address
Mode
Source
Form
Operand
Table 12-6. Instruction Set Summary (Sheet 5 of 6)
2
2
dd
hh ll
ee ff
ff
4
5
6
5
4
2
dd
hh ll
ee ff
ff
4
5
6
5
4
— — —
DIR
EXT
IX2
IX1
IX
BF
CF
DF
EF
FF
— — IMM
DIR
EXT
IX2
IX1
IX
2
A0 ii
B0 dd 3
C0 hh ll 4
D0 ee ff 5
4
E0 ff
3
F0
PC ← (PC) + 1; Push (PCL)
SP ← (SP) – 1; Push (PCH)
SP ← (SP) – 1; Push (X)
SP ← (SP) – 1; Push (A)
— 1 — — —
SP ← (SP) – 1; Push (CCR)
SP ← (SP) – 1; I ← 1
PCH ← Interrupt Vector High Byte
PCL ← Interrupt Vector Low Byte
INH
83
1
0
— — — — —
INH
97
2
— — —
DIR
INH
INH
IX1
IX
3D
4D
5D
6D
7D
M ← (X)
A ← (A) – (M)
X ← (A)
(M) – $00
dd
ff
4
3
3
5
4
MC68HC05C8A • MC68HCL05C8A • MC68HSC05C8A Data Sheet, Rev. 5.1
Freescale Semiconductor
81
Instruction Set
WAIT
A
C
CCR
dd
dd rr
DIR
ee ff
EXT
ff
H
hh ll
I
ii
IMM
INH
IX
IX1
IX2
M
N
n
Transfer Index Register to Accumulator
A ← (X)
Stop CPU Clock and Enable Interrupts
Accumulator
Carry/borrow flag
Condition code register
Direct address of operand
Direct address of operand and relative offset of branch instruction
Direct addressing mode
High and low bytes of offset in indexed, 16-bit offset addressing
Extended addressing mode
Offset byte in indexed, 8-bit offset addressing
Half-carry flag
High and low bytes of operand address in extended addressing
Interrupt mask
Immediate operand byte
Immediate addressing mode
Inherent addressing mode
Indexed, no offset addressing mode
Indexed, 8-bit offset addressing mode
Indexed, 16-bit offset addressing mode
Memory location
Negative flag
Any bit
opr
PC
PCH
PCL
REL
rel
rr
SP
X
Z
#
∧
∨
⊕
()
–( )
←
?
:
—
H I N Z C
— — — — —
INH
9F
2
— 0 — — —
INH
8F
2
Effect
on CCR
Cycles
Description
Opcode
TXA
Operation
Address
Mode
Source
Form
Operand
Table 12-6. Instruction Set Summary (Sheet 6 of 6)
Operand (one or two bytes)
Program counter
Program counter high byte
Program counter low byte
Relative addressing mode
Relative program counter offset byte
Relative program counter offset byte
Stack pointer
Index register
Zero flag
Immediate value
Logical AND
Logical OR
Logical EXCLUSIVE OR
Contents of
Negation (two’s complement)
Loaded with
If
Concatenated with
Set or cleared
Not affected
12.5 Opcode Map
See Table 12-7.
MC68HC05C8A • MC68HCL05C8A • MC68HSC05C8A Data Sheet, Rev. 5.1
82
Freescale Semiconductor
Bit Manipulation
DIR
DIR
MSB
LSB
0
MC68HC05C8A • MC68HCL05C8A • MC68HSC05C8A Data Sheet, Rev. 5.1
Freescale Semiconductor
Table 12-7. Opcode Map
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0
1
Branch
REL
DIR
2
3
Read-Modify-Write
INH
INH
IX1
4
5
6
IX
7
5
5
3
5
3
3
6
5
BRSET0
BSET0
BRA
NEG
NEGA
NEGX
NEG
NEG
3
DIR 2
DIR 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX 1
5
5
3
BRCLR0
BCLR0
BRN
3
DIR 2
DIR 2
REL
1
5
5
3
11
BRSET1
BSET1
BHI
MUL
3
DIR 2
DIR 2
REL
1
INH
5
5
3
5
3
3
6
5
BRCLR1
BCLR1
BLS
COM
COMA
COMX
COM
COM
3
DIR 2
DIR 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX 1
5
5
3
5
3
3
6
5
BRSET2
BSET2
BCC
LSR
LSRA
LSRX
LSR
LSR
3
DIR 2
DIR 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX
5
5
3
BRCLR2
BCLR2 BCS/BLO
3
DIR 2
DIR 2
REL
5
5
3
5
3
3
6
5
BRSET3
BSET3
BNE
ROR
RORA
RORX
ROR
ROR
3
DIR 2
DIR 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX
5
5
3
5
3
3
6
5
BRCLR3
BCLR3
BEQ
ASR
ASRA
ASRX
ASR
ASR
3
DIR 2
DIR 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX
5
5
3
5
3
3
6
5
BRSET4
BSET4
BHCC
ASL/LSL ASLA/LSLA ASLX/LSLX ASL/LSL ASL/LSL
3
DIR 2
DIR 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX
5
5
3
5
3
3
6
5
BRCLR4
BCLR4
BHCS
ROL
ROLA
ROLX
ROL
ROL
3
DIR 2
DIR 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX
5
5
3
5
3
3
6
5
BRSET5
BSET5
BPL
DEC
DECA
DECX
DEC
DEC
3
DIR 2
DIR 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX
5
5
3
BRCLR5
BCLR5
BMI
3
DIR 2
DIR 2
REL
5
5
3
5
3
3
6
5
BRSET6
BSET6
BMC
INC
INCA
INCX
INC
INC
3
DIR 2
DIR 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX
5
5
3
4
3
3
5
4
BRCLR6
BCLR6
BMS
TST
TSTA
TSTX
TST
TST
3
DIR 2
DIR 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX
5
5
3
BRSET7
BSET7
BIL
3
DIR 2
DIR 2
REL
1
5
5
3
5
3
3
6
5
BRCLR7
BCLR7
BIH
CLR
CLRA
CLRX
CLR
CLR
3
DIR 2
DIR 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX 1
REL = Relative
IX = Indexed, No Offset
IX1 = Indexed, 8-Bit Offset
IX2 = Indexed, 16-Bit Offset
8
9
9
RTI
INH
6
RTS
INH
2
2
2
10
SWI
INH
2
2
2
2
1
1
1
1
1
1
1
2
TAX
INH
2
CLC
INH 2
2
SEC
INH 2
2
CLI
INH 2
2
SEI
INH 2
2
RSP
INH
2
NOP
INH 2
2
STOP
INH
2
2
WAIT
TXA
INH 1
INH
IMM
DIR
A
B
2
SUB
IMM 2
2
CMP
IMM 2
2
SBC
IMM 2
2
CPX
IMM 2
2
AND
IMM 2
2
BIT
IMM 2
2
LDA
IMM 2
2
2
EOR
IMM 2
2
ADC
IMM 2
2
ORA
IMM 2
2
ADD
IMM 2
2
6
BSR
REL 2
2
LDX
2
IMM 2
2
MSB
LSB
LSB of Opcode in Hexadecimal
0
Register/Memory
EXT
IX2
3
SUB
DIR 3
3
CMP
DIR 3
3
SBC
DIR 3
3
CPX
DIR 3
3
AND
DIR 3
3
BIT
DIR 3
3
LDA
DIR 3
4
STA
DIR 3
3
EOR
DIR 3
3
ADC
DIR 3
3
ORA
DIR 3
3
ADD
DIR 3
2
JMP
DIR 3
5
JSR
DIR 3
3
LDX
DIR 3
4
STX
DIR 3
0
C
4
SUB
EXT 3
4
CMP
EXT 3
4
SBC
EXT 3
4
CPX
EXT 3
4
AND
EXT 3
4
BIT
EXT 3
4
LDA
EXT 3
5
STA
EXT 3
4
EOR
EXT 3
4
ADC
EXT 3
4
ORA
EXT 3
4
ADD
EXT 3
3
JMP
EXT 3
6
JSR
EXT 3
4
LDX
EXT 3
5
STX
EXT 3
D
5
SUB
IX2 2
5
CMP
IX2 2
5
SBC
IX2 2
5
CPX
IX2 2
5
AND
IX2 2
5
BIT
IX2 2
5
LDA
IX2 2
6
STA
IX2 2
5
EOR
IX2 2
5
ADC
IX2 2
5
ORA
IX2 2
5
ADD
IX2 2
4
JMP
IX2 2
7
JSR
IX2 2
5
LDX
IX2 2
6
STX
IX2 2
IX1
IX
E
F
4
SUB
IX1 1
4
CMP
IX1 1
4
SBC
IX1 1
4
CPX
IX1 1
4
AND
IX1 1
4
BIT
IX1 1
4
LDA
IX1 1
5
STA
IX1 1
4
EOR
IX1 1
4
ADC
IX1 1
4
ORA
IX1 1
4
ADD
IX1 1
3
JMP
IX1 1
6
JSR
IX1 1
4
LDX
IX1 1
5
STX
IX1 1
MSB
LSB
3
SUB
1
CMP
IX
3
SBC
IX
3
CPX
2
3
IX
3
4
AND
IX
3
BIT
5
IX
3
6
LDA
IX
4
7
STA
IX
3
EOR
8
IX
3
9
ADC
IX
3
A
ORA
IX
3
ADD
B
IX
2
C
JMP
IX
5
JSR
IX
3
LDX
D
E
IX
4
F
STX
IX
MSB of Opcode in Hexadecimal
5 Number of Cycles
BRSET0 Opcode Mnemonic
3
DIR Number of Bytes/Addressing Mode
0
IX
3
83
Opcode Map
INH = Inherent
IMM = Immediate
DIR = Direct
EXT = Extended
Control
INH
INH
Instruction Set
MC68HC05C8A • MC68HCL05C8A • MC68HSC05C8A Data Sheet, Rev. 5.1
84
Freescale Semiconductor
Chapter 13
Electrical Specifications
13.1 Introduction
This section contains the electrical and timing specifications.
13.2 Maximum Ratings
Maximum ratings are the extreme limits to which the microcontroller unit (MCU) can be exposed without
permanently damaging it.
The MCU contains circuitry to protect the inputs against damage from high static voltages; however, do
not apply voltages higher than those shown in the table below. Keep VIn and VOut within the range
VSS ≤ (VIn or VOut) ≤ VDD. Connect unused inputs to the appropriate voltage level, either VSS or VDD.
Rating
Symbol
Value
Unit
VDD
–0.3 to +7.0
V
I
25
mA
IRQ pin only
VIn
VSS –0.3 to
2 x VDD + 0.3
V
Storage temperature range
Tstg
–65 to +150
°C
Supply voltage
Current drain per pin excluding VDD and VSS
NOTE
This device is not guaranteed to operate properly at the maximum ratings.
Refer to 13.6 5.0-V DC Electrical Characteristics and
13.7 3.3-V DC Electrical Characteristics for guaranteed operating
conditions.
13.3 Operating Temperature Range
Characteristic
Operating temperature range(1)
MC68HC05C8AP, FN, B, FB
MC68HSC05C8CP, CFN, CB, CFB
MC68HC05C8AVP, VN, VB, VFB
MC68HC05C8AMP, MFN, MB, MFB
Symbol
Value
Unit
TL to TH
TA
0 to +70
–40 to +85
–40 to +105
–40 to +125
°C
1. P = Plastic dual in-line package (PDIP)
FN = Plastic-leaded chip carrier (PLCC)
B = Shrink dual in-line-package (SDIP)
FB = Quad flat pack (QFP)
MC68HC05C8A • MC68HCL05C8A • MC68HSC05C8A Data Sheet, Rev. 5.1
Freescale Semiconductor
85
Electrical Specifications
13.4 Thermal Characteristics
Characteristic
Symbol
Thermal resistance
Plastic dual in-line package
Plastic leaded chip carrier (PLCC)
Quad flat pack (QFP0)
Plastic shrink DIP (SDIP)
Value
60
70
95
60
θJA
Unit
°C/W
13.5 Power Considerations
The average chip-junction temperature, TJ, in °C, can be obtained from:
TJ = TA + (PD × θJA)
(1)
where:
TA = Ambient temperature, °C
θJA = Package thermal resistance, junction to ambient, °C/W.
PD = PINT + PI/O
PINT = IDD × VDD watts (chip internal power)
PI/O = Power dissipation on input and output pins (user-determined)
For most applications PI/O « PINT and can be neglected.
Following is an approximate relationship between PD and TJ (neglecting PI/O):
PD = K ÷ (TJ + 273 °C)
(2)
Solving equations (1) and (2) for K gives:
K = PD × (TA + 273 °C) + θJA × (PD)2
(3)
where K is a constant pertaining to the particular part. K can be determined from equation (3) by
measuring PD (at equilibrium) for a known TA. Using this value of K, the values of PD and TJ can be
obtained by solving equations (1) and (2) iteratively for any value of TA.
VDD = 4.5 V
VDD
Pins
R2
SEE TABLE
TEST
POINT
C
SEE
TABLE
PA7–PA0
PB7–PB0
PC7–PC0
PD5–PD0, PD7
R1
R2
3.26 Ω
2.38 Ω
R1
R2
C
50 pF
R1
SEE TABLE
VDD = 3.0 V
Pins
PA7–PA0
PB7–PB0
PC7–PC0
PD5–PD0, PD7
10.91 Ω
6.32 Ω
C
50 pF
Figure 13-1. Test Load
MC68HC05C8A • MC68HCL05C8A • MC68HSC05C8A Data Sheet, Rev. 5.1
86
Freescale Semiconductor
5.0-V DC Electrical Characteristics
13.6 5.0-V DC Electrical Characteristics
Characteristic(1)
Output voltage
ILoad = 10.0 µA
ILoad = –10.0 µA
Symbol
Min
Typ(2)
Max
Unit
VOL
VOH
—
VDD–0.1
—
—
0.1
—
V
VDD–0.8
VDD–0.8
VDD–0.8
—
—
—
—
—
—
Output high voltage
(ILoad = –0.8 mA) PA7–PA0, PB7–PB0, PC6–PC0, TCMP
(ILoad = –1.6 mA) PD4–PD1
(ILoad = –5.0 mA) PC7
VOH
Output low voltage
(ILoad = 1.6 mA) PA7–PA0, PB7–PB0, PC6–PC0,
PD4–PD1, TCMP
(ILoad = 10 mA) PC7
VOL
—
—
—
—
0.4
0.4
V
Input high voltage
PA7–PA0, PB7–PB0, PC7–PC0, PD7,
PD5–PD0, TCAP, IRQ, RESET, OSC1
VIH
0.7×VDD
—
VDD
V
Input low voltage
PA7–PA0, PB7–PB0, PC7–PC0, PD7,
PD5–PD0, TCAP, IRQ, RESET, OSC1
VIL
VSS
—
0.2×VDD
V
—
—
3.50
1.00
5.25
3.25
mA
mA
—
—
—
1
—
—
20
40
50
µA
µA
µA
V
Supply current (4.5–5.5 Vdc @ fBus = 2.1 MHz)
Run(3)
Wait(4)
Stop(5)
25°C
0°C to 70°C (standard)
–40°C to +125°C (standard)
IDD
I/O ports hi-z leakage current
PA7–PA0, PB7–PB0 (without pullup)
PC7–PC0, PD7, PD5–PD0
IOZ
—
—
±10
µA
Input current
RESET, IRQ, OSC1, TCAP, PD7, PD5–PD0
IIn
—
—
±1
µA
Input pullup current(6)
PB7–PB0 (with pullup)
IIn
175
385
750
µA
COut
CIn
—
—
—
—
12
8
pF
Capacitance
Ports (as input or output)
RESET, IRQ, OSC1, TCAP, PD7, PD5, PD0
1. VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = –40°C to +125°C, unless otherwise noted.
2. Typical values reflect measurements taken on average processed devices at the midpoint of voltage range, 25°C only.
3. Run (operating) IDD measured using external square wave clock source; all I/O pins configured as inputs, Port B = VDD, all
other inputs VIL = 0.2 V, VIH = VDD–0.2 V; no DC loads; less than 50 pF on all outputs; CL = 20 pF on OSC2.
4. Wait IDD measured using external square wave clock source; all I/O pins configured as inputs, Port B = VDD, all other inputs
VIL = 0.2 V, VIH = VDD–0.2 V; no DC loads; less than 50 pF on all outputs; CL = 20 pF on OSC2. Wait IDD is affected linearly
by the OSC2 capacitance.
5. Stop IDD measured with OSC1 = 0.2 V; all I/O pins configured as inputs, Port B = VDD, all other inputs VIL = 0.2 V,
VIH = VDD –0.2 V.
6. Input pullup current measured with VIL = 0.2 V.
MC68HC05C8A • MC68HCL05C8A • MC68HSC05C8A Data Sheet, Rev. 5.1
Freescale Semiconductor
87
Electrical Specifications
13.7 3.3-V DC Electrical Characteristics
Characteristic(1)
Output voltage
ILoad = 10.0 µA
ILoad = –10.0 µA
Symbol
Min
Typ(2)
Max
Unit
VOL
VOH
—
VDD–0.1
—
—
0.1
—
V
VDD–0.3
VDD–0.3
VDD–0.3
—
—
—
—
—
—
Output high voltage
(ILoad = –0.2 mA) PA7–PA0, PB7–PB0, PC6–PC0, TCMP
(ILoad = –0.4 mA) PD4–PD1
(ILoad = –1.5 mA) PC7
VOH
Output low voltage
(ILoad = 0.4 mA) PA7–PA0, PB7–PB0, PC6–PC0,
PD4–PD1, TCMP
(ILoad = 6 mA) PC7
VOL
—
—
—
—
0.3
0.3
V
Input high voltage
PA7–PA0, PB7–PB0, PC7–PC0, PD7,
PD5–PD0, TCAP, IRQ, RESET, OSC1
VIH
0.7×VDD
—
VDD
V
Input low voltage
PA7–PA0, PB7–PB0, PC7–PC0, PD7,
PD5–PD0, TCAP, IRQ, RESET, OSC1
VIL
VSS
—
0.2×VDD
V
—
—
1.00
500
1.60
900
mA
µA
—
—
—
1
—
—
8
16
20
µA
µA
µA
V
Supply current (3.0–3.6 Vdc @ fBus = 1.0 MHz)
Run(3)
Wait(4)
Stop(5)
25°C
0°C to +70°C (standard)
–40°C to +125°C (standard)
IDD
I/O ports hi-z leakage current
PA7–PA0, PB7–PB0 (without pullup)
PC7–PC0, PD7, PD5–PD0
IOZ
—
—
±10
µA
Input current
RESET, IRQ, OSC1, TCAP, PD7, PD5, PD0
IIn
—
—
±1
µA
Input pullup current(6)
PB7–PB0 (with pullup)
IIn
75
175
350
µA
COut
CIn
—
—
—
—
12
8
pF
Capacitance
Ports (as input or output)
RESET, IRQ, OSC1, TCAP, PD7, PD5, PD0
1. VDD = 3.3 Vdc ± 0.3 Vdc, VSS = 0 Vdc, TA = –40°C to +125°C, unless otherwise noted.
2. Typical values reflect measurements taken on average processed devices at the midpoint of voltage range, 25°C only.
3. Run (operating) IDD measured using external square wave clock source; all I/O pins configured as inputs, Port B = VDD, all
other inputs VIL = 0.2 V, VIH = VDD –0.2 V; no DC loads; less than 50 pF on all outputs; CL = 20 pF on OSC2.
4. Wait IDD measured using external square wave clock source; all I/O pins configured as inputs, Port B = VDD, all other inputs
VIL = 0.2 V, VIH = VDD –0.2 V; no DC loads; less than 50 pF on all outputs; CL = 20 pF on OSC2. Wait IDD is affected linearly
by the OSC2 capacitance.
5. Stop IDD measured with OSC1 = 0.2 V; all I/O pins configured as inputs, Port B = VDD, all other inputs VIL = 0.2 V,
VIH = VDD –0.2 V.
6. Input pullup current measured with VIL = 0.2 V.
MC68HC05C8A • MC68HCL05C8A • MC68HSC05C8A Data Sheet, Rev. 5.1
88
Freescale Semiconductor
3.3-V DC Electrical Characteristics
5.00 mA
SUPPLY CURRENT (IDD)
VDD = 5.5 V
T = –40°C TO 125°C
4.00 mA
N
RU
P
(O
G)
IN
T
A
ER
I DD
IT
WA
3.00 mA
I DD
2.00 mA
1.00 mA
50 µA
STOP IDD
(MHZ)
0.5 MHz
1.0 MHz
1.5 MHz
2.0 MHz
INTERNAL CLOCK FREQUENCY (XTAL ÷ 2)
Figure 13-2. Maximum Supply Current versus
Internal Clock Frequency, VDD = 5.5 V
ID
D
1.50 mA
N(
1.00 mA
RU
SUPPLY CURRENT (IDD)
OP
ER
A
T IN
G)
VDD = 3.6 V
T = –40°C TO 125°C
TID
AI
W
D
500 mA
STOP IDD
0.5 MHz
1.0 MHz
INTERNAL CLOCK FREQUENCY (XTAL ÷ 2)
Figure 13-3. Maximum Supply Current versus
Internal Clock Frequency, VDD = 3.6 V
MC68HC05C8A • MC68HCL05C8A • MC68HSC05C8A Data Sheet, Rev. 5.1
Freescale Semiconductor
89
Electrical Specifications
13.8 5.0-V Control Timing
Characteristic(1)
Symbol
Min
Max
Unit
Oscillator frequency
Crystal
External clock
fOSC
—
dc
4.2
4.2
MHz
Internal operating frequency
Crystal
External clock
fOP
—
dc
2.1
2.1
MHz
Internal clock cycle time
tCYC
480
—
ns
Crystal oscillator startup time
tOXOV
—
100
ms
Stop recovery startup time (crystal oscillator)
tILCH
—
100
ms
RESET pulse width
Timer
Resolution(2)
Input capture pulse width
Input capture pulse period
Interrupt pulse width low (edge-triggered)
Interrupt pulse period
OSC1 pulse width
tRL
1.5
—
tCYC
tRESL
tTH, tTL
tTLTL
4.0
125
Note(3)
—
—
—
tCYC
ns
tCYC
tilih
125
—
ns
tILIL
Note(4)
—
tCYC
toh, tol
90
—
ns
1. VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = –40°C to +125°C, unless otherwise noted.
2. Because a 2-bit prescaler in the timer must count four internal cycles (tCYC), this is the limiting minimum factor in determining the timer resolution.
3. The minimum period tTLTL should not be less than the number of cycle times it takes to execute the capture interrupt service
routine plus 24 tCYC.
4. The minimum tILIL should not be less than the number of cycle times it takes to execute the interrupt service routine plus
19 tCYc.
MC68HC05C8A • MC68HCL05C8A • MC68HSC05C8A Data Sheet, Rev. 5.1
90
Freescale Semiconductor
3.3-V Control Timing
13.9 3.3-V Control Timing
Characteristic(1)
Symbol
Min
Max
Unit
Oscillator frequency
Crystal
External clock
fOSC
—
dc
2.0
2.0
MHz
Internal operating frequency
Crystal
External clock
fOP
—
dc
1.00
1.00
MHz
Internal clock cycle time
tCYC
1000
—
ns
ms
Crystal oscillator startup time
tOXOV
100
Stop recovery startup time (crystal oscillator)
tILCH
100
ms
RESET pulse width
Timer
Resolution(2)
Input capture pulse width
Input capture pulse period
Interrupt pulse width low (edge-triggered)
Interrupt pulse period
OSC1 pulse width
tRL
1.5
—
tCYC
tRESL
tTH, tTL
tTLTL
4.0
250
Note(3)
—
—
—
tCYC
ns
tCYC
tilih
250
—
ns
tILIL
Note(4)
—
tCYC
toh, tol
200
—
ns
1. VDD = 3.3 Vdc ± 0.3 Vdc, VSS = 0 Vdc, TA = –40°C to +125°C, unless otherwise noted.
2. Because a 2-bit prescaler in the timer must count four internal cycles (tCYC), this is the limiting minimum factor in determining the timer resolution.
3. The minimum period tTLTL should not be less than the number of cycle times it takes to execute the capture interrupt service
routine plus 24 tCYC.
4. The minimum tILIL should not be less than the number of cycle times it takes to execute the interrupt service routine plus
19 tCYC.
tTLTL
tTH
tTL
TCAP PIN
Figure 13-4. TCAP Timing Relationships
MC68HC05C8A • MC68HCL05C8A • MC68HSC05C8A Data Sheet, Rev. 5.1
Freescale Semiconductor
91
Electrical Specifications
tILIL
tILIH
IRQ PIN
a. Edge-Sensitive Trigger Condition. The minimum pulse width (tILIH) is either 125 ns (fOP = 2.1 MHz)
or 250 ns (fOP = 1 MHz). The period tILIL should not be less than the number of tCYC cycles it takes to
execute the interrupt service routine plus 19 tCYC cycles.
tILIH
IRQ1
NORMALLY USED
WITH WIRED-OR
CONNECTION
.
.
.
IRQn
IRQ
(INTERNAL)
b. Level-Sensitive Trigger Condition. If after servicing an interrupt the IRQ remains low, the
next interrupt is recognized.
Figure 13-5. External Interrupt Timing
INTERNAL
CLOCK(1)
INTERNAL
ADDRESS BUS(1)
1FFE
1FFE
1FFE
NEW
PCH
INTERNAL
DATA BUS(1)
RESET(2)
1FFE
1FFF
NEW
PCL
NEW PC
OP
CODE
tRL
Notes:
1. Internal clock, internal address bus, and internal data bus are not available externally.
2. The next rising edge of the internal clock after the rising edge of RESET initiates the reset sequence.
Figure 13-6. External Reset Timing
MC68HC05C8A • MC68HCL05C8A • MC68HSC05C8A Data Sheet, Rev. 5.1
92
Freescale Semiconductor
3.3-V Control Timing
OSC(1)
tRL
RESET
tILIH
IRQ(2)
4064 tCYC
IRQ(3)
INTERNAL
CLOCK
INTERNAL
ADDRESS BUS
1FFE
1FFE
1FFE
1FFE
Notes:
1. Represents the internal clocking of the OSC1 pin
2. IRQ pin edge-sensitive mask option
3. IRQ pin level- and edge-sensitive mask option
4. RESET vector address shown for timing example
1FFE
1FFF(4)
RESET OR INTERRUPT
VECTOR FETCH
Figure 13-7. STOP Recovery Timing Diagram
(NOTE 1)
VDD
OSC1 PIN(2)
4064 tCYC
INTERNAL
CLOCK(3)
INTERNAL
ADDRESS BUS(3)
1FFE
1FFE
1FFE
1FFE
1FFE
INTERNAL
DATA BUS(3)
1FFE
NEW
PCH
1FFF
NEW
PCL
NOTES:
1. Power-on reset threshold is typically between 1 V and 2 V.
2. OSC1 line is meant to represent time only, not frequency.
3. Internal clock, internal address bus, and internal data bus are not available externally.
Figure 13-8. Power-On Reset Timing Diagram
MC68HC05C8A • MC68HCL05C8A • MC68HSC05C8A Data Sheet, Rev. 5.1
Freescale Semiconductor
93
Electrical Specifications
13.10 5.0-V Serial Peripheral Interface Timing
Characteristic(1)
Num
Symbol
Min
Max
Unit
Operating frequency
Master
Slave
fOP(M)
fOP(S)
dc
dc
0.5
2.1
fOP
MHz
1
Cycle time
Master
Slave
tCYC(M)
tCYC(S)
2.0
480
—
—
tCYC
ns
2
Enable lead time
Master
Slave
tLead(M)
tLead(S)
(2)
—
—
ns
240
Enable lag time
Master
Slave
tLag(M)
tLag(S)
—
—
ns
720
3
(2)
4
Clock (SCK) high time
Master
Slave
tW(SCKH)M
tW(SCKH)S
340
190
—
—
ns
5
Clock (SCK) low time
Master
Slave
tW(SCKL)M
tW(SCKL)S
340
190
—
—
ns
6
Data setup time (inputs)
Master
Slave
tSU(M)
tSU(S)
100
100
—
—
ns
7
Data hold time (inputs)
Master
Slave
tH(M)
tH(S)
100
100
—
—
ns
8
Slave access time (time-to-data active from high-impedance
state)
tA
0
120
ns
9
Slave disable time (hold time to high-impedance state)
tDIS
—
240
ns
10
Data valid
Master (before capture edge)
Slave (after enable edge)(3)
tV(M)
tV(S)
0.25
—
—
240
tCYC(M)
ns
11
Data hold time (outputs)
Master (after capture edge)
Slave (after enable edge)
tHO(M)
tHO(S)
0.25
0
—
—
tCYC(M)
ns
tRM
tRS
—
—
100
2.0
ns
µs
tFM
tFS
—
—
100
2.0
ns
µs
Rise time (20% VDD to 70% VDD, CL = 200 pF)
12
SPI outputs (SCK, MOSI, and MISO)
SPI inputs (SCK, MOSI, MISO, and SS)
Fall time (70% VDD to 20% VDD, CL = 200 pF)
13
SPI outputs (SCK, MOSI, and MISO)
SPI inputs (SCK, MOSI, MISO, and SS)
1. VDD = 5.0 Vdc ± 10%; VSS = 0 Vdc, TA = TL to TH. Refer to Figure 13-9 and Figure 13-10 for timing diagrams.
2. Signal production depends on software.
3. Assumes 200 pF load on all SPI pins
MC68HC05C8A • MC68HCL05C8A • MC68HSC05C8A Data Sheet, Rev. 5.1
94
Freescale Semiconductor
3.3-V Serial Peripheral Interface Timing
13.11 3.3-V Serial Peripheral Interface Timing
Characteristic(1)
Num
Symbol
Min
Max
Unit
Operating frequency
Master
Slave
fOP(M)
fOP(S)
dc
dc
0.5
1.0
fOP
MHz
1
Cycle time
Master
Slave
tCYC(M)
tCYC(S)
2.0
1.0
—
—
tCYC
µs
2
Enable lead time
Master
Slave
tLead(M)
tLead(S)
(2)
—
—
ns
500
Enable lag time
Master
Slave
tLag(M)
tLag(S)
1.5
—
—
ns
µs
3
(2)
4
Clock (SCK) high time
Master
Slave
tW(SCKH)M
tW(SCKH)S
720
400
—
—
ns
5
Clock (SCK) low time
Master
Slave
tW(SCKL)M
tW(SCKL)S
720
400
—
—
ns
6
Data setup time (inputs)
Master
Slave
tSU(M)
tSU(S)
200
200
—
—
ns
7
Data hold time (inputs)
Master
Slave
tH(M)
tH(S)
200
200
—
—
ns
8
Slave access time (time to data active from high-impedance state)
tA
0
250
ns
9
Slave disable time (hold time to high-impedance state)
tDIS
—
500
ns
10
Data valid
Master (before capture edge)
Slave (after enable edge)(3)
tV(M)
tV(S)
0.25
—
—
500
tCYC(M)
ns
11
Data hold time (outputs)
Master (after capture edge)
Slave (after enable edge)
tHO(M)
tHO(S)
0.25
0
—
—
tCYC(M)
ns
12
Rise time (20% VDD to 70% VDD, CL = 200 pF)
SPI outputs (SCK, MOSI, and MISO)
SPI Inputs (SCK, MOSI, MISO, and SS)
tRM
tRS
—
—
200
2.0
ns
µs
13
Fall time (70% VDD to 20% VDD, CL = 200 pF)
SPI outputs (SCK, MOSI, and MISO)
SPI inputs (SCK, MOSI, MISO, and SS)
tFM
tFS
—
—
200
2.0
ns
µs
1. VDD = 3.3 Vdc ± 0.3 Vdc; VSS = 0 Vdc, TA = TL to TH. Refer to Figure 13-9 and Figure 13-10 for timing diagrams.
2. Signal production depends on software.
3. Assumes 200 pF load on all SPI pins
MC68HC05C8A • MC68HCL05C8A • MC68HSC05C8A Data Sheet, Rev. 5.1
Freescale Semiconductor
95
Electrical Specifications
SS
(INPUT)
SS PIN OF MASTER HELD HIGH.
12
1
SCK (CPOL = 0)
(OUTPUT)
13
12
5
NOTE
4
12
SCK (CPOL = 1)
(OUTPUT)
13
5
NOTE
4
6
MISO
(INPUT)
MSB IN
BITS 6–1
10 (REF)
LSB IN
11
MOSI
(OUTPUT)
7
10
MASTER MSB OUT
11 (REF)
BITS 6–1
MASTER LSB OUT
13
12
Note: This first clock edge is generated internally, but is not seen at the SCK pin.
a) SPI Master Timing (CPHA = 0)
SS
(INPUT)
SS PIN OF MASTER HELD HIGH.
1
SCK (CPOL = 0)
(OUTPUT)
13
12
5
NOTE
4
12
SCK (CPOL = 1)
(OUTPUT)
13
5
NOTE
4
6
MISO
(INPUT)
MSB IN
10 (REF)
BITS 6–1
11
MOSI
(OUTPUT)
MASTER MSB OUT
7
LSB IN
10
BITS 6–1
11
MASTER LSB OUT
13
12
Note: This last clock edge is generated internally, but is not seen at the SCK pin.
b) SPI Master Timing (CPHA = 1)
Figure 13-9. SPI Master Timing Diagram
MC68HC05C8A • MC68HCL05C8A • MC68HSC05C8A Data Sheet, Rev. 5.1
96
Freescale Semiconductor
3.3-V Serial Peripheral Interface Timing
SS
(INPUT)
1
SCK (CPOL = 0)
(INPUT)
13
12
12
13
3
5
4
2
SCK (CPOL = 1)
(INPUT)
5
4
8
MISO
(INPUT)
SLAVE
MSB OUT
6
MOSI
(OUTPUT)
BITS 6–1
10
7
MSB IN
9
SLAVE LSB OUT
11
NOTE
11
BITS 6–1
LSB IN
Note: Not defined but normally MSB of character just received.
a) SPI Slave Timing (CPHA = 0)
SS
(INPUT)
13
1
SCK (CPOL = 0)
(INPUT)
12
5
4
2
3
SCK (CPOL = 1)
(INPUT)
5
4
10
8
MISO
(OUTPUT)
NOTE
MOSI
(INPUT)
12
SLAVE
MSB OUT
6
7
13
BITS 6–1
10
MSB IN
9
SLAVE LSB OUT
11
BITS 6–1
LSB IN
Note: Not defined but normally LSB of character previously transmitted.
b) SPI Slave Timing (CPHA = 1)
Figure 13-10. SPI Slave Timing Diagram
MC68HC05C8A • MC68HCL05C8A • MC68HSC05C8A Data Sheet, Rev. 5.1
Freescale Semiconductor
97
Electrical Specifications
MC68HC05C8A • MC68HCL05C8A • MC68HSC05C8A Data Sheet, Rev. 5.1
98
Freescale Semiconductor
Chapter 14
Mechanical Specifications
14.1 Introduction
This section describes the dimensions of the:
• Dual in-line package (DIP)
• Plastic shrink dual in-line package (SDIP)
• Plastic leaded chip carrier (PLCC)
• Quad flat pack (QFP) MCU packages
14.2 40-Pin Plastic Dual In-Line (DIP) Package (Case 711-03)
40
NOTES:
1. POSITION TOLERANCE OF LEADS (D), SHALL
BEWITHIN 0.25 (0.010) AT MAXIMUM MATERIAL
CONDITIONS, IN RELATION TO SEATING PLANE
AND EACH OTHER.
2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
3. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
21
B
1
20
L
A
C
N
J
H
G
F
D
K
SEATING
PLANE
M
DIM
A
B
C
D
F
G
H
J
K
L
M
N
MILLIMETERS
MIN
MAX
51.69
52.45
13.72
14.22
3.94
5.08
0.36
0.56
1.02
1.52
2.54 BSC
1.65
2.16
0.20
0.38
2.92
3.43
15.24 BSC
0°
1°
0.51
1.02
INCHES
MIN
MAX
2.035
2.065
0.540
0.560
0.155
0.200
0.014
0.022
0.040
0.060
0.100 BSC
0.065
0.085
0.008
0.015
0.115
0.135
0.600 BSC
0°
1°
0.020
0.040
MC68HC05C8A • MC68HCL05C8A • MC68HSC05C8A Data Sheet, Rev. 5.1
Freescale Semiconductor
99
Mechanical Specifications
14.3 42-Pin Plastic Shrink Dual In-Line (SDIP) Package (Case 858-01)
-A42
NOTES:
1. DIMENSIONS AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSIONS A AND B DO NOT INCLUDE MOLD
FLASH. MAXIMUM MOLD FLASH 0.25 (0.010).
22
-B1
21
L
DIM
A
B
C
D
F
G
H
J
K
L
M
N
H
C
-TSEATING
PLANE
0.25 (0.010)
N
G
F
D 42 PL
K
M
T A
S
M
J 42 PL
0.25 (0.010)
M
T B
INCHES
MIN
MAX
1.435 1.465
0.540 0.560
0.155 0.200
0.014 0.022
0.032 0.046
0.070 BSC
0.300 BSC
0.008 0.015
0.115 0.135
0.600 BSC
15°
0°
0.020 0.040
MILLIMETERS
MIN
MAX
36.45 37.21
13.72 14.22
3.94
5.08
0.36
0.56
0.81
1.17
1.778 BSC
7.62 BSC
0.20
0.38
2.92
3.43
15.24 BSC
0°
15°
0.51
1.02
S
MC68HC05C8A • MC68HCL05C8A • MC68HSC05C8A Data Sheet, Rev. 5.1
100
Freescale Semiconductor
44-Lead Plastic Leaded Chip Carrier (PLCC) (Case 777-02)
14.4 44-Lead Plastic Leaded Chip Carrier (PLCC) (Case 777-02)
-N-
Y BRK
0.007(0.180) M T
B
D
L-M S N S
0.007(0.180) M T
U
L-M S N S
Z
-M-
-L-
V
44
W
1
X
D
G1
0.010 (0.25) S T
VIEW D-D
A
0.007(0.180) M T
L-M S N S
R
0.007(0.180) M T
L-M S N S
0.007(0.180) M T
H
L-M S N S
L-M S N S
Z
J
K1
E
C
0.004 (0.10)
G
-TG1
0.010 (0.25) S T
L-M S N S
K
SEATING
PLANE
F
0.007(0.180)M T
VIEW S
L-M S N S
VIEW S
NOTES:
1. DATUMS -L-, -M-, AND -N- ARE DETERMINED
WHERE TOP OF LEAD SHOLDERS EXITS
PLASTIC BODY AT MOLD PARTING LINE.
2. DIMENSION G1, TRUE POSITION TO BE
MEASURED AT DATUM -T-, SEATING PLANE.
3. DIMENSION R AND U DO NOT INCLUDE MOLD
FLASH. ALLOWABLE MOLD FLASH IS 0.010
(0.25) PER SIDE.
4. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
5. CONTROLLING DIMENSION: INCH.
6. THE PACKAGE TOP MAY BE SMALLER THAN
THE PACKAGE BOTTOM BY UP TO 0.012
(0.300). DIMENSIONS R AND U ARE DETERMINED
AT THE OUTERMOST EXTREMES OF THE
PLASTIC BODY EXCLUSIVE OF THE MOLD
FLASH, TIE BAR BURRS, GATE BURRS AND
INTERLEAD FLASH, BUT INCLUDING ANY
MISMATCH BETWEEN THE TOP AND BOTTOM
OF THE PLASTIC BODY.
7. DIMINSION H DOES NOT INCLUDE DAMBAR
PROTRUSION OR INTRUSION. THE DAMBAR
PROTUSION(S) SHALL NOT CAUSE THE H
DIMINSION TO BE GREATER THAN 0.037
(0.940102). THE DAMBAR INTRUSION(S) SHALL
NOT CAUSE THE H DIMINISION TO SMALLER
THAN 0.025 (0.635).
INCHES
DIM
A
B
C
E
F
G
H
J
K
R
U
V
W
X
Y
Z
G1
K1
MIN
MAX
0.685
0.695
0.685
0.695
0.165
0.180
0.090
0.110
0.013
0.019
0.050 BSC
0.026
0.032
0.020
0.025
0.650
0.656
0.650
0.656
0.042
0.048
0.042
0.048
0.042
0.056
0.020
2°
10°
0.610
0.630
0.040
MILLIMETERS
MIN
MAX
17.40
17.65
17.40
17.65
4.20
4.57
2.29
2.79
0.33
0.48
1.27 BSC
0.66
0.81
0.51
0.64
16.51
16.66
16.51
16.66
1.07
1.21
1.07
1.21
1.07
1.42
0.50
2°
10°
15.50
16.00
1.02
MC68HC05C8A • MC68HCL05C8A • MC68HSC05C8A Data Sheet, Rev. 5.1
Freescale Semiconductor
101
Mechanical Specifications
14.5 44-Lead Quad Flat Pack (QFP) (Case 824A-01)
L
33
23
B
DETAIL A
S
S
D
D
S
V
H A-B
L
-A,B,DB
M
-B-
B
0.20 (0.008)
-A-
S
22
0.20 (0.008) M C A-B
0.05 (0.002) A-B
34
DETAIL A
44
12
1
11
F
-DA
0.20 (0.008) M C A-B
0.05 (0.002) A-B
S
0.20 (0.008) M H A-B
BASE METAL
S
D
S
S
D
S
J
N
D
M
DETAIL C
0.20 (0.008)
M
C A-B
S
D
S
SECTION B–B
C E
-H-
0.01 (0.004)
-CSEATING
PLANE
H
M
G
M
T
DATUM
PLANE
DATUM
PLANE
-H-
R
K
W
X
DETAIL C
Q
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DATUM PLANE ĆHĆ IS LOCATED AT BOTTOM OF
LEAD AND IS COINCIDENT WITH THE LEAD WHERE
THE LEAD EXITS THE PLASTIC BODY AT THE
BOTTOM OF THE PARTING LINE.
4. DATUMS ĆAĆ, ĆBĆ AND ĆDĆ TO BE DETERMINED AT
DATUM PLANE ĆHĆ.
5. DIMENSIONS S AND V TO BE DETERMINED AT
SEATING PLANE ĆCĆ.
6. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS 0.25
(0.010) PER SIDE. DIMENSIONS A AND B DO
INCLUDE MOLD MISMATCH AND ARE DETERMINED
AT DATUM PLANE ĆHĆ.
7. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT.
DIM
A
B
C
D
E
F
G
H
J
K
L
M
N
Q
R
S
T
U
V
W
X
MILLIMETERS
MIN
MAX
9.90 10.10
9.90 10.10
2.45
2.10
0.45
0.30
2.10
2.00
0.40
0.30
0.80 BSC
0.25
Ċ
0.23
0.13
0.95
0.65
8.00 REF
10°
5°
0.17
0.13
7°
0°
0.30
0.13
12.95 13.45
Ċ
0.13
Ċ
0°
12.95 13.45
Ċ
0.40
1.6 REF
INCHES
MIN
MAX
0.390 0.398
0.390 0.398
0.083 0.096
0.012 0.018
0.079 0.083
0.012 0.016
0.031 BSC
0.010
Ċ
0.005 0.009
0.026 0.037
0.315 REF
10°
5°
0.005 0.007
7°
0°
0.005 0.012
0.510 0.530
Ċ
0.005
Ċ
0°
0.510 0.530
Ċ
0.016
0.063 REF
MC68HC05C8A • MC68HCL05C8A • MC68HSC05C8A Data Sheet, Rev. 5.1
102
Freescale Semiconductor
Chapter 15
Ordering Information
15.1 Introduction
This section contains instructions for ordering custom-masked read-only memory (ROM) microcontroller
units (MCU).
15.2 MCU Ordering Forms
To initiate an order for a ROM-based MCU, first obtain the current ordering form for the MCU from a
Freescale representative. Submit these items when ordering MCUs:
• A current MCU ordering form that is completely filled out (Contact your Freescale sales office for
assistance.)
• A copy of the customer specification if the customer specification deviates from the Freescale
specification for the MCU.
• Customer’s application program on one of the media listed in 15.3 Application Program Media.
15.3 Application Program Media
Please deliver the application program to Freescale in one of these media:
• Macintosh®(1) 3-1/2-inch diskette (double-sided 800 K or double-sided high-density 1.4 M)
• MS-DOS®(2) or PC-DOSTM(3) 3-1/2-inch diskette (double-sided 720 K or double-sided high-density
1.44 M)
• MS-DOS® or PC-DOSTM 5-1/4-inch diskette (double-sided double-density 360 K or double-sided
high-density 1.2 M)
Use positive logic for data and addresses.
When submitting the application program on a diskette, clearly label the diskette with this information:
• Customer name
• Customer part number
• Project or product name
• File name of object code
• Date
• Name of operating system that formatted diskette
• Formatted capacity of diskette
1. Macintosh is a registered trademark of Apple Computer, Inc.
2. MS-DOS is a registered trademark of Microsoft Corporation.
3. PC-DOS is a trademark of International Business Machines Corporation.
MC68HC05C8A • MC68HCL05C8A • MC68HSC05C8A Data Sheet, Rev. 5.1
Freescale Semiconductor
103
Ordering Information
On diskettes, the application program must be in Freescale’s S-record format (S1 and S9 records), a
character-based object file format generated by M6805 cross assemblers and linkers.
Begin the application program at the first user ROM location. Program addresses must correspond
exactly to the available on-chip user ROM addresses as shown in the memory map. Write $00 in all
non-user ROM locations or leave all non-user ROM locations blank. Refer to the current MCU ordering
form for additional requirements. Freescale may request pattern re-submission if non-user areas contain
any non-zero code.
If the memory map has two user ROM areas with the same addresses, then write the two areas in
separate files on the diskette. Label the diskette with both filenames.
In addition to the object code, a file containing the source code can be included. Freescale keeps this
code confidential and uses it only to expedite ROM pattern generation in case of any difficulty with the
object code. Label the diskette with the filename of the source code.
15.4 ROM Program Verification
The primary use for the on-chip ROM is to hold the customer’s application program. The customer
develops and debugs the application program and then submits the MCU order along with the application
program.
Freescale inputs the customer’s application program code into a computer program that generates a
listing verify file. The listing verify file represents the memory map of the MCU. The listing verify file
contains the user ROM code and may also contain non-user ROM code, such as self-check code.
Freescale sends the customer a computer printout of the listing verify file along with a listing verify form.
To aid the customer in checking the listing verify file, Freescale will program the listing verify file into
customer-supplied blank preformatted Macintosh or DOS disks. All original pattern media are filed for
contractual purposes and are not returned.
Check the listing verify file thoroughly, then complete and sign the listing verify form and return the listing
verify form to Freescale. The signed listing verify form constitutes the contractual agreement for the
creation of the custom mask.
15.5 ROM Verification Units (RVUs)
After receiving the signed listing verify form, Freescale manufactures a custom photographic mask. The
mask contains the customer’s application program and is used to process silicon wafers. The application
program cannot be changed after the manufacture of the mask begins. Freescale then produces 10
MCUs, called RVUs, and sends the RVUs to the customer. RVUs are usually packaged in unmarked
ceramic and tested to 5 Vdc at room temperature. RVUs are not tested to environmental extremes
because their sole purpose is to demonstrate that the customer’s user ROM pattern was properly
implemented. The 10 RVUs are free of charge with the minimum order quantity. These units are not to be
used for qualification or production. RVUs are not guaranteed by Freescale Quality Assurance.
MC68HC05C8A • MC68HCL05C8A • MC68HSC05C8A Data Sheet, Rev. 5.1
104
Freescale Semiconductor
Appendix A
MC68HCL05C8A
A.1 Introduction
This appendix introduces the MC68HCL05C8A, a low-power version of the MC68HC05C8A. The
technical data applying to the MC68HC05C8A applies to the MC68HCL05C8A with the exceptions given
here.
A.2 Low-Power Operating Temperature Range
The follow data replaces the corresponding data found in 13.3 Operating Temperature Range.
Rating
Symbol
Value
Unit
TA
TL to TH
0 to +70
°C
Operating temperature range(1)
MC68HCL05C8AP, FN, B, FB
1. P = Plastic dual in-line package (PDIP)
FN = Plastic-leaded chip carrier (PLCC)
B = Shrink dual in-line package (SDIP)
FB = Quad flat pack (QFP)
A.3 2.5-V to 3.6-V DC Electrical Characteristics
Characteristic
Output high voltage
(ILoad = –0.2 mA) PA7–PA0, PB7–PB0, PC6–PC0, TCMP
(ILoad = –0.4 mA) PD4–PD1
(ILoad = –1.5 mA) PC7
Output low voltage
(ILoad = 0.4 mA) PA7–PA0, PB7–PB0, PC6–PC0,
PD4–PD1, TCMP
(ILoad = 5.0 mA) PC7
Input pullup current
PB7–PB0 (with pullup)
Symbol
Min(1)
Typ
Max
VOH
VDD – 0.3
VDD – 0.3
VDD – 0.3
—
—
—
—
—
—
VOL
—
—
—
—
0.3
0.3
Iin
40
160
300
Unit
V
V
µA
1. VDD = 2.5–3.6 Vdc
MC68HC05C8A • MC68HCL05C8A • MC68HSC05C8A Data Sheet, Rev. 5.1
Freescale Semiconductor
105
A.4 1.8-V to 2.4-V DC Electrical Characteristics
Characteristic
Output high voltage
(ILoad = –0.1 mA) PA7–PA0, PB7–PB0, PC6–PC0, TCMP
(ILoad = –0.2 mA) PD4–PD1
(ILoad = –0.75 mA) PC7
Output low voltage
(ILoad = 0.2 mA) PA7–PA0, PB7–PB0, PC6–PC0,
PD4–PD1, TCMP
(ILoad = 2.0 mA) PC7
Input pullup current
PB7–PB0 (with pullup)
Symbol
Min(1)
Typ
Max
VOH
VDD – 0.3
VDD – 0.3
VDD – 0.3
—
—
—
—
—
—
VOL
—
—
—
—
0.3
0.3
IIn
15
110
200
Unit
V
V
µA
1. VDD = 2.5–3.6 Vdc
A.5 Low-Power Supply Current
Characteristic(1)
Symbol
Min
Typ(1)
Max
Unit
—
—
3.50
1.6
4.25
2.25
mA
mA
—
—
1
—
15
25
µA
µA
—
—
1.00
0.7
1.4
1.0
mA
mA
—
—
1
—
5
10
µA
µA
—
—
500
300
750
500
µA
µA
—
—
1
—
5
10
µA
µA
—
—
300
250
600
400
µA
µA
—
—
1
—
2
5
µA
µA
Supply current (4.5–5.5 Vdc @ fBus = 2.1 MHz)
Run(2)
Wait(3)
Stop(4)
25°C
0°C to +70°C (standard)
IDD
Supply current (2.4–3.6 Vdc @ fBus = 1.0 MHz)
Run(2)
Wait(3)
Stop(4)
25°C
0°C to +70° C (standard)
IDD
Supply current (2.5–3.6 Vdc @ fBus = 500 kHz)
Run(2)
Wait(3)
Stop(4)
25°C
0°C to +70°C (standard)
IDD
Supply current (1.8–2.4 Vdc @ fBus = 500 kHz)
Run(2)
Wait(3)
Stop(4)
25°C
0°C to +70°C (standard)
IDD
1. Typical values reflect measurements taken on average processed devices at the midpoint of voltage range, 25°C only.
2. Run (operating) IDD measured using external square wave clock source; all I/O pins configured as inputs,
Port B = VDD, all other inputs VIL = 0.2 V, VIH = VDD –0.2 V; no DC loads; less than 50 pF on all outputs;
CL = 20 pF on OSC2
3. Wait IDD measured using external square wave clock source; all I/O pins configured as inputs, Port B = VDD, all other inputs
VIL = 0.2 V, VIH = VDD –0.2 V; no DC loads; less than 50 pF on all outputs; CL = 20 pF on OSC2. Wait IDD is affected linearly
by the OSC2 capacitance.
4. Stop IDD measured with OSC1 = 0.2 V; all I/O pins configured as inputs, Port B = VDD, all other inputs VIL = 0.2 V,
VIH = VDD –0.2 V
MC68HC05C8A • MC68HCL05C8A • MC68HSC05C8A Data Sheet, Rev. 5.1
106
Freescale Semiconductor
Appendix B
MC68HSC05C8A
B.1 Introduction
This appendix introduces the MC68HSC05C8A, a high-speed version of the MC68HC05C8A. The
technical data applying to the MC68HC05C8A applies to the MC68HSC05C8A with the exceptions given
here.
B.2 High-Speed Operating Temperature Range
The follow data replaces the corresponding data found in 13.3 Operating Temperature Range.
Rating
Operating temperature range(1)
MC68HSC05C8AP, FN, B, FB
MC68HSC05C8CP, CFN, CB, CFB
Symbol
Value
Unit
TA
TL to TH
0 to +70
–40 to +85
°C
1. P = Plastic dual in-line package (PDIP)
FN = Plastic-leaded chip carrier (PLCC)
B = Shrink dual in-line package (SDIP)
FB = Quad flat pack (QFP)
MC68HC05C8A • MC68HCL05C8A • MC68HSC05C8A Data Sheet, Rev. 5.1
Freescale Semiconductor
107
B.3 DC Electrical Characteristics
The data in 13.6 5.0-V DC Electrical Characteristics and 13.7 3.3-V DC Electrical Characteristics applies
to the MC68HSC05C8A with the exceptions given here.
Characteristic(1)
Symbol
Min
Typ
Max
Unit
—
—
7.00
2.00
11.0
6.50
mA
mA
—
—
—
1
—
—
20
40
50
µA
µA
µA
—
—
2.50
1.00
4.00
2.00
mA
mA
—
—
—
1
—
—
8
16
20
µA
µA
µA
Supply current (4.5–5.5 Vdc @ fBUS = 4.0 MHz)
Run(2)
Wait(3)
Stop(4)
25°C
0°C to 70°C (Standard)
–40°C to 125°C (Standard)
IDD
Supply Current (2.4–3.6 Vdc @ fBUS = 2.0 MHz)
Run(2)
Wait(3)
Stop(4)
25°C
0°C to 70°C (standard)
–40°C to 125°C (standard)
IDD
Input pullup current (VDD = 4.5–5.5 V)
PB7–PB0 (with pullup)
IIn
175
385
750
µA
Input pullup current (VDD = 2.4–3.6 V)
PB7–PB0 (with pullup)
IIn
50
160
350
µA
1. Typical values reflect measurements taken on average processed devices at the midpoint of voltage range, 25°C only.
2. Run (operating) IDD measured using external square wave clock source; all I/O pins configured as inputs, Port B = VDD,
all other inputs VIL = 0.2 V, VIH = VDD–0.2 V; no DC loads; less than 50 pF on all outputs;
CL = 20 pF on OSC2
3. Wait IDD measured using external square wave clock source; all I/O pins configured as inputs,
Port B = VDD, all other inputs VIL = 0.2 V, VIH = VDD –0.2 V; no DC loads; less than 50 pF on all outputs;
CL = 20 pF on OSC2. Wait IDD is affected linearly by the OSC2 capacitance.
4. Stop IDD measured with OSC1 = 0.2 V; all I/O pins configured as inputs, Port B = VDD, all other inputs
VIL = 0.2 V, VIH = VDD –0.2 V
MC68HC05C8A • MC68HCL05C8A • MC68HSC05C8A Data Sheet, Rev. 5.1
108
Freescale Semiconductor
B.4 4.5-V to 5.5-V Control Timing
The data in 13.8 5.0-V Control Timing applies to the MC68HSC05C8A with the exceptions given here.
Characteristic
Symbol
Min
Max
Unit
Oscillator frequency
Crystal
External Clock
fOSC
—
dc
8.2
8.2
MHz
Internal operating frequency (fOSC ÷ 2)
Crystal
External clock
fOP
—
dc
4.1
4.1
MHz
Cycle time
tCYC
244
—
ns
Crystal oscillator startup time
tOXOV
100
ms
Stop recovery startup time
tILCH
100
ms
tRL
1.5
—
tCYC
tRESL
tTH or tTL
tTHTL
4.0
64
(2)
—
—
—
tCYC
ns
tCYC
Interrupt pulse width low (edge-triggered)
tILIH
64
—
ns
Interrupt pulse period
tILIL
(3)
—
tCYC
tOH or tOL
50
—
ns
RESET pulse width
Timer
Resolution(1)
Input capture pulse width
Input capture pulse width
OSC1 pulse width
1. Because a 2-bit prescaler in the timer must count four internal cycles (tCYC), this is the limiting minimum factor in
determining the timer resolution.
2. The minimum period tTLTL should not be less than the number of cycle times it takes to execute the capture interrupt service
routine plus 24 tCYC.
3. The minimum tILIL should not be less than the number of cycle times it takes to execute the interrupt service routine plus
19 tCYC.
MC68HC05C8A • MC68HCL05C8A • MC68HSC05C8A Data Sheet, Rev. 5.1
Freescale Semiconductor
109
B.5 2.4-V to 3.6-V Control Timing
The data in 13.9 3.3-V Control Timing applies to the MC68HSC05C8A with the exceptions given here.
Characteristic
Symbol
Min
Max
Unit
Oscillator frequency
Crystal
External clock
fOSC
—
dc
4.2
4.2
MHz
Internal operating frequency (fOSC ÷ 2)
Crystal
External clock
fOP
—
dc
2.1
2.1
MHz
Cycle time
tCYC
480
—
ns
Crystal oscillator startup time
tOXOV
100
ms
Stop recovery startup time
tILCH
100
ms
tRL
1.5
—
tCYC
tRESL
tTH or tTL
tTHTL
4.0
125
(2)
—
—
—
tCYC
ns
tCYC
Interrupt pulse width low (edge-triggered)
tILIH
125
—
ns
Interrupt pulse period
tILIL
(3)
—
tCYC
tOH or tOL
90
—
ns
RESET pulse width
Timer
Resolution(1)
Input capture pulse width
Input capture pulse width
OSC1 pulse width
1. Because a 2-bit prescaler in the timer must count four internal cycles (tCYC), this is the limiting minimum factor in
determining the timer resolution.
2. The minimum period tTLTL should not be less than the number of cycle times it takes to execute the capture interrupt service
routine plus 24 tCYC.
3. The minimum tILIL should not be less than the number of cycle times it takes to execute the interrupt service routine plus
19 tCYC.
MC68HC05C8A • MC68HCL05C8A • MC68HSC05C8A Data Sheet, Rev. 5.1
110
Freescale Semiconductor
B.6 4.5-V to 5.5-V High-Speed SPI Timing
The data in 13.10 5.0-V Serial Peripheral Interface Timing applies to the MC68HSC05C8A with the
exceptions given here.
Num
Symbol
Min
Max
Unit
Operating frequency
Master
Slave
fOP(M)
fOP(S)
dc
dc
0.5
4.1
fOP
MHz
1
Cycle time
Master
Slave
tCYC(M)
tCYC(S)
2.0
244
—
—
tCYC
ns
2
Enable lead time
Master
Slave
tLead(M)
tLead(S)
(1)
122
—
—
ns
ns
Enable lag time
Master
Slave
tLag(M)
tLag(S)
366
—
—
ns
ns
3
Characteristic
(1)
4
Clock (SCK) high time
Master
Slave
tW(SCKH)M
tW(SCKH)S
166
93
—
—
ns
ns
5
Clock (SCK) low time
Master
Slave
tW(SCKL)M
tW(SCKL)S
166
93
—
—
ns
ns
6
Data setup time (inputs)
Master
Slave
tSU(M)
tSU(S)
49
49
—
—
ns
ns
7
Data hold time (inputs)
Master
Slave
tH(M)
tH(S)
49
49
—
—
ns
ns
8
Slave access time (time to data active from high-impedance state)
tA
0
61
ns
9
Slave disable time (hold time to high-impedance state)
tDIS
—
122
ns
10
Data valid
Master (before capture edge)
Slave (after enable edge)(2)
tV(M)
tV(S)
0.25
—
—
122
tCYC(M)
ns
11
Data hold time (outputs)
Master (after capture edge)
Slave (After Enable Edge)
tHO(M)
tHO(S)
0.25
0
—
—
tCYC(M)
ns
12
Rise time (20% VDD to 70% VDD, CL = 200 pF)
SPI outputs (SCK, MOSI, and MISO)
SPI inputs (SCK, MOSI, MISO, and SS)
tRM
tRS
—
—
50
1.0
ns
µs
13
Fall time (70% VDD to 20% VDD, CL = 200 pF)
SPI outputs (SCK, MOSI, and MISO)
SPI inputs (SCK, MOSI, MISO, and SS)
tFM
tFS
—
—
50
1.0
ns
µs
1. Signal production depends on software.
2. Assumes 200 pF load on all SPI pins.
MC68HC05C8A • MC68HCL05C8A • MC68HSC05C8A Data Sheet, Rev. 5.1
Freescale Semiconductor
111
B.7 2.4-V to 3.6-V High-Speed SPI Timing
The data in 13.11 3.3-V Serial Peripheral Interface Timing applies to the MC68HSC05C8A with the
exceptions given in the following table.
Num
Symbol
Min
Max
Unit
Operating frequency
Master
Slave
fOP(M)
fOP(S)
dc
dc
0.5
2.1
fOP
MHz
1
Cycle time
Master
Slave
tCYC(M)
tCYC(S)
2.0
480
—
—
tCYC
ns
2
Enable lead time
Master
Slave
tLead(M)
tLead(S)
(1)
240
—
—
ns
ns
Enable lag time
Master
Slave
tLag(M)
tLag(S)
720
—
—
ns
ns
3
Characteristic
(1)
4
Clock (SCK) High Time
Master
Slave
tW(SCKH)M
tW(SCKH)S
340
190
—
—
ns
ns
5
Clock (SCK) low time
Master
Slave
tW(SCKL)M
tW(SCKL)S
340
190
—
—
ns
ns
6
Data setup time (Inputs)
Master
Slave
tSU(M)
tSU(S)
100
100
—
—
ns
ns
7
Data hold time (Inputs)
Master
Slave
tH(M)
tH(S)
100
100
—
—
ns
ns
8
Slave access time (time to data active from high-impedance state)
tA
0
120
ns
9
Slave disable time (hold time to high-impedance state)
tDIS
—
240
ns
10
Data
Master (before capture edge)
Slave (after enable edge)(2)
tV(M)
tV(S)
0.25
—
—
240
tCYC(M)
ns
11
Data Hold Time (outputs)
Master (after capture edge)
Slave (after enable edge)
tHO(M)
tHO(S)
0.25
0
—
—
tCYC(M)
ns
12
Rise time (20% VDD to 70% VDD, CL = 200 pF)
SPI outputs (SCK, MOSI, and MISO)
SPI inputs (SCK, MOSI, MISO, and SS)
tRM
tRS
—
—
100
2.0
ns
µs
13
Fall time (70% VDD to 20% VDD, CL = 200 pF)
SPI outputs (SCK, MOSI, and MISO)
SPI inputs (SCK, MOSI, MISO, and SS)
tFM
tFS
—
—
100
2.0
ns
µs
1. Signal production depends on software.
2. Assumes 20 pF load on all SPI pins.
MC68HC05C8A • MC68HCL05C8A • MC68HSC05C8A Data Sheet, Rev. 5.1
112
Freescale Semiconductor
Appendix C
M68HC05Cx Family Feature Comparisons
Refer to Table C-1 for a comparison of the features for all the M68HC05C Family members.
MC68HC05C8A • MC68HCL05C8A • MC68HSC05C8A Data Sheet, Rev. 5.1
Freescale Semiconductor
113
114
Table C-1. M68HC05Cx Feature Comparison
C4
C4A
705C4A
C8
C8A
705C8
705C8A
C12
C12A
C9
C9A
705C9
705C9A
USER ROM
4160
4160
—
7744
7744
—
—
12,096
12,096
15,760–15,936
15,760–15,936
—
—
USER EPROM
—
—
4160
—
—
7596–7740
7596–7740
—
—
—
—
15,760–15,936
12,096–15,936
CODE
SECURITY
NO
YES
YES
NO
YES
YES
YES
NO
YES
NO
YES
NO
YES
Freescale Semiconductor
MC68HC05C8A • MC68HCL05C8A • MC68HSC05C8A Data Sheet, Rev. 5.1
RAM
176
176
176
176
176
176–304
176–304
176
176
176–352
176–352
176–352
176–352
OPTION
REGISTER
(IRQ/RAM/
SEC)
NO
NO
$1FDF
(IRQ/SEC)
NO
NO
$1FDF
(IRQ/RAM/
SEC)
$1FDF
(IRQ/RAM/SEC)
NO
NO
$3FDF
(IRQ/RAM)
$3FDF
(IRQ/RAM)
$3FDF
(IRQ/RAM)
$3FDF
(IRQ/RAM)
MASK OPTION
REGISTER(S)
NO
NO
$1FF0–1
NO
NO
NO
$1FF0–1
NO
NO
NO
NO
NO
$3FF0–1
PORTB
KEYSCAN
(PULLUP/
INTERRUPT)
NO
YES
MASK
OPTION
YES
MOR SELECTABLE
NO
YES
MASK
OPTION
NO
YES
MOR
SELECTABLE
YES
MASK
OPTION
YES
MASK
OPTION
NO
YES
MASK
OPTION
NO
YES
MOR
SELECTABLE
PC7 DRIVE
STANDARD
HIGH
CURRENT
HIGH
CURRENT
STANDARD
HIGH
CURRENT
STANDARD
HIGH
CURRENT
HIGH
CURRENT
HIGH
CURRENT
STANDARD
HIGH
CURRENT
STANDARD
HIGH
CURRENT
PD7, 5–0
INPUT ONLY
PD7, 5–0
INPUT ONLY
PD7, 5–0
INPUT ONLY
PD7, 5–0
INPUT ONLY
PD7, 5–0
INPUT ONLY
PD7, 5–0
BIDIRECTIONAL
PD7, 5–0
BIDIRECTIONAL
PD7, 5–0
BIDIRECTIONAL
PD7, 5–0
BIDIRECTIONAL
NO
YES
YES
TWO TYPES
YES
YES
YES
YES
YES
TWO TYPES
SOFTWARE
SOFTWARE+
MOR
MASK
OPTION
MASK
OPTION
SOFTWARE
SOFTWARE
SOFTWARE
SOFTWARE+
MOR
SOFTWARE
SELECTABLE
SOFTWARE
SELECTABLE
SOFTWARE
SELECTABLE
SOFTWARE+
MOR
SELECTABLE
PORT D
COP
PD7, 5–0
PD7, 5–0
PD7, 5–0
PD7, 5–0
INPUT ONLY INPUT ONLY INPUT ONLY INPUT ONLY
NO
YES
COP ENABLE
—
MASK
OPTION
YES
MOR
—
MASK
OPTION
COP TIMEOUT
—
64 ms
(@4 MHz
osc)
64 ms
(@4 MHz osc)
—
64 ms
(@4 MHz osc)
SOFTWARE
SELECTABLE
SOFTWARE+
MOR
SELECTABLE
64 ms
(@4 MHz osc)
64 ms
(@4MHz osc)
COP CLEAR
—
CLR $1FF0
CLR $1FF0
—
CLR $1FF0
WRITE $55/$AA
TO $001D
WRITE $55/$AA
TO $001D
OR
CLR $1FF0
CLR $3FF0
CLR $3FF0
CLOCK
MONITOR
NO
NO
NO
NO
NO
YES
YES
NO
NO
ACTIVE
RESET
NO
NO
NO
NO
NO
COP/CLOCK
MONITOR
PROGRAMMABLE
COP/CLOCK
MONITOR
NO
STOP DISABLE
NO
MASK
OPTION
NO
NO
MASK
OPTION
NO
NO
MASK
OPTION
WRITE $55/$AA WRITE $55/$AA WRITE $55/$AA
TO $001D
TO $001D
TO $001D
WRITE $55/$AA
TO $001D
OR
CLR $3FF0
YES
YES
YES
YES
(C9A MODE)
NO
POR/COP/
CLOCK
MONITOR
POR/COP/
CLOCK
MONITOR
POR/COP/
CLOCK
MONITOR
POR/C9A COP/
CLOCK
MONITOR
MASK
OPTION
NO
NO
NO
MOR
SELECTABLE
(C12A MODE)
NOTES:
1. The expanded RAM map (from $30–$4F and $100–$15F) available on the OTP devices MC68HC705C8 and MC68HC705C8A is not available on the ROM devices MC68HC05C8 and
MC68HC05C8A.
2. The programmable COP available on the MC68HC705C8 and MC68HC705C8A is not available on the MC68HC05C8A. For ROM compatibility, use the non-programmable COP.
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MC68HC05C8A
Rev. 5.1, 08/2005
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