LM5051 www.ti.com SNVS702D – OCTOBER 2011 – REVISED MARCH 2013 LM5051 Low Side OR-ing FET Controller Check for Samples: LM5051 FEATURES DESCRIPTION • The LM5051 Low Side OR-ing FET Controller operates in conjunction with an external MOSFET as an ideal diode rectifier when connected in series with a power source. This OR-ing controller allows MOSFETs to replace diode rectifiers in power distribution networks thus reducing both power loss and voltage drops. 1 2 • • • • • • Wide operating input voltage range: -6V to 100V -100V Transient Capability Gate drive for external N-Channel MOSFET MOSFET diagnostic test mode Fast 50ns response to current reversal 2A peak gate turn-off current Package: 8-Lead SOIC The LM5051 controller provides gate drive for an external N-Channel MOSFET and a fast response comparator to turn off the FET when current flows in the reverse direction. The LM5051 can connect power supplies ranging from -6V to -100V and can withstand transients up to -100V. APPLICATIONS • Active OR-ing of Redundant (N+1) Power Supplies The LM5051 also provides a FET test diagnostic mode which allows the system controller to test for shorted MOSFETs. Typical Application Circuits GND GND LINE Shutdown VCC OFF + LOAD - LM5051 Status nFGD INN GATE INP/VSS -VOUT -48V Figure 1. Full Application with MOSFET Diagnostic 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2011–2013, Texas Instruments Incorporated LM5051 SNVS702D – OCTOBER 2011 – REVISED MARCH 2013 www.ti.com LINE VCC LM5051 PS1 INN GATE INP/VSS D S LINE VCC RLOAD LM5051 PS2 INN GATE D INP/VSS S Figure 2. Typical Redundant Supply Configuration Connection Diagram Top View LINE 1 OFF 3 LM5051 MA VCC 2 8 GATE 7 INP/VSS 6 INN 5 INP/VSS nFGD 4 Device Pin 5 (INP) is internally connected to Device Pin 7 (VSS) Figure 3. LM5051MA 8-Lead SOIC D Package PIN DESCRIPTIONS Pin # Function 1 LINE Power supply pin to bias the internal 12V zener shunt regulator at the VCC pin through an internal 50 kΩ (typical) series resistor. See the APPLICATION INFORMATION section. 2 VCC Connection to the internal 12V zener shunt voltage regulator. Bypass this pin with minimum 0.1μF capacitor to the VSS pin. This pin can be biased via an external resistor rather than via the internal resistor from the LINE pin (pin 1). See the APPLICATION INFORMATION section. 3 OFF FET Test Mode control input. Logic low or open state at the OFF pin will deactivate the FET Test Mode and allow normal operation. A logic high state at the OFF pin will pull the GATE pin low and turn off the external MOSFET. If the body diode forward voltage of the MOSFET (from source to drain) is greater than 260mV the nFGD pin will indicate that the MOSFET is not shorted by pulling to the active low state. 4 nFGD Open drain output for the FET Test circuit. An active low state on nFGD indicates that the forward voltage (from source to drain) of the external MOSFET is greater than 260 mV typical. The nFGD pin requires an external pull-up resistor to a voltage not higher than VSS + 5.5V. 5 INP/VSS 6 INN 7 2 Name INP/VSS See device Pin 7. Voltage sense connection to the external MOSFET Drain pin Internally connected to device Pin 5. Negative supply voltage connection and MOSFET voltage sense connected to the external MOSFET common source connection. All device voltages and currents are referenced to this pin, unless otherwise stated. See the INP/VSS PINS section. Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LM5051 LM5051 www.ti.com SNVS702D – OCTOBER 2011 – REVISED MARCH 2013 PIN DESCRIPTIONS (continued) Pin # Name 8 GATE Function Connection to the external MOSFET Gate. These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings (1) LINE Pin to INP/VSS -0.3V to 103V INN Pin to INP/VSS -2V to 103V OFF Pin to INP/VSS -0.3V to 7V VCC Pin Sink to INP/VSS -0.1mA to 20mA nFGD Pin to INP/VSS (Off) -0.3V to 7V −65°C to 150°C Storage Temperature Range ESD (HBM) (2) Peak Reflow Temperature (1) (2) (3) ±2 kV (3) 260°C, 30sec Absolute Maximum Ratings indicate limits beyond which damage to the device may occur, including in-operability and degradation of device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in the Recommended Operating Conditions is not implied. Operating Range conditions indicate the conditions at which the device is functional and the device should not be operated beyond such conditions. For ensured specifications and conditions, see Electrical Characteristics. The Human Body Model (HBM) is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin. Applicable test standard is JESD-22-A114-C. For soldering specifications see the LM5051 Product Folder at www.national.com, general information at www.national.com/analog/packaging/, and reflow information at www.national.com/ms/MS/MS-SOLDERING.pdf . Operating Ratings (1) Relative to VSS pin LINE Pin Voltage 36V to 100V INN Pin Voltage -1V to 100V VCC Pin Current 1 mA to 10 mA OFF Pin Voltage 0.0V to 5.0V nFGD Voltage (Off) 0.0V to 5.0V nFGD Sink Current (On) 0 mA to 2 mA −40°C to +125°C Junction Temperature Range (TJ) (1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur, including in-operability and degradation of device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in the Recommended Operating Conditions is not implied. Operating Range conditions indicate the conditions at which the device is functional and the device should not be operated beyond such conditions. For ensured specifications and conditions, see Electrical Characteristics. Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LM5051 3 LM5051 SNVS702D – OCTOBER 2011 – REVISED MARCH 2013 www.ti.com Electrical Characteristics Limits in standard type are for TJ = 25°C only; limits in boldface type apply over the operating junction temperature (TJ) range of -40°C to +125°C. Minimum and Maximum limits are ensured through test, design, or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated all conditions and measurements are referenced to device pin 7 (INP/VSS), and the following conditions apply: VLINE= 48.0V, VINN= -150 mV, VOFF= 0.0V, CGATE= 47 nF, CVCC= 0.1 µF, and TJ= 25°C. Symbol Parameter Conditions Min Typ Max Unit 690 780 μA V LINE Pin ILINE LINE Pin current VLINE = 48.0V VCC Pin = Open - Operating Voltage Range LINE Pin = Open 4.50 - VZ IVCC = 2 mA 11.9 13.0 14.3 IVCC = 10 mA 12.5 13.5 14.5 IVCC = 2 mA to 10 mA - 0.50 1.11 VVCC = VZ - 100mV - 1.0 1.50 VVCC = 5.0V - 0.4 1.10 VINN = 0.0V - 3.1 - VINN = 90V - 0.04 - VCC Pin VCC VZ ΔVZ IVCC VCC Shunt Zener Voltage Shunt Zener Regulation Supply Current V V mA INN Pin IINN INN Pin Current μA GATE GATE Charge Current VGATE = 5.5V VINN = -150mV 0.28 0.66 0.95 mA GATE Discharge Current VGATE = 5.5V VINN = -150 mV to +300 mV t ≤ 10 ms 2.4 3.5 - A IGATE VLINE = 48.0V VGATE VSD(REV) ΔVSD(REV) VSD(REG) GATE Pin High Voltage Reverse Threshold Reverse Threshold Hysteresis - 13.0 - VVCC = 10.25V, LINE = Open 9.98 10.2 - VVCC = 5.0V, LINE= Open V 4.70 4.95 - VINN going negative until Gate Drive Turns ON -112.2 -45 +11.4 mV VINN going positive from VSD(REV) Threshold until Gate Drive Turns OFF - 50 - mV -10.8 12 30.8 mV 50 Regulated VINP/VSS to VINN Threshold - 34 CGATE = 10 nF (1) - 60 - CGATE = 47 nF (1) - 90 230 Gate Capacitance Discharge Time at OFF pin Low to High Transition See Figure 7 CGATE = 47 nF (2) - 120 - VOFF(IH) OFF Input High Threshold Voltage VINN = -400 mV VOFF Rising until Gate is Low 1.28 1.50 1.65 VOFF(IL) OFF Input Low Threshold Voltage VINN = -400 mV VOFF Falling until Gate is High - 1.48 - ΔVOFF OFF Threshold Voltage Hysteresis VOFF(IH) - VOFF(IL) - 20 - mV IOFF(IH) OFF Pin Internal Pull-down VOFF = 5.0V - 4.6 6.00 µA VOFF = 0.0V - -0.03 - µA tGATE(REV) tGATE(OFF) Gate Capacitance Discharge Time at Forward to Reverse Transition See Figure 6 CGATE = 0 (1) ns ns OFF Pin IOFF(IL) (1) (2) 4 V Time from VINN voltage transition from -200 mV to +500 mV until Gate pin voltage falls to ≤ 1.00V. See Figure 6 Time from VOFF voltage transition from 0.0V to 5.0V until GATE pin voltage falls to ≤ 1.0V. See Figure 7 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LM5051 LM5051 www.ti.com SNVS702D – OCTOBER 2011 – REVISED MARCH 2013 Electrical Characteristics (continued) Limits in standard type are for TJ = 25°C only; limits in boldface type apply over the operating junction temperature (TJ) range of -40°C to +125°C. Minimum and Maximum limits are ensured through test, design, or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated all conditions and measurements are referenced to device pin 7 (INP/VSS), and the following conditions apply: VLINE= 48.0V, VINN= -150 mV, VOFF= 0.0V, CGATE= 47 nF, CVCC= 0.1 µF, and TJ= 25°C. Symbol Parameter Conditions Min Typ Max Unit FET Test Threshold Voltage VINP - VINN VOFF = 5.0V VINN/VSS going negative from VINP until nFGD pin goes Hi-Z -360 -260 -183 mV FET Test Threshold Voltage Hysteresis VOFF = 5.0V VINN going positve from VSDT(ST) until nFGD pin goes Lo-Z - 6.5 - mV nFGDVOL nFGD Output Low Voltage nFGD Output = On VOFF = 5V InFGD = 1mA Sinking - 285 450 mV nFGDIOL nFGD Output Leakage Current nFGD Output = Off VOFF = 0V VnFGD = 5.0V - 0.01 0.7 µA FET Test Comparator VSD(TST) ΔVSD(TST) nFGD Pin VINN VSD(REG) 0.0 mV ûVSD(REV) VGATE VSD(REV) VGATE 0.0V Figure 4. VSD(REV) Threshold Definitions 0.0 mV VINN ûVSD(TST) VSD(TST) VnFGD VnFGD 0.0V Figure 5. VSD(TST) Threshold Definitions Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LM5051 5 LM5051 SNVS702D – OCTOBER 2011 – REVISED MARCH 2013 www.ti.com VINN +500 mV ûVSD(REV) 0 mV VSD(REV) -200 mV tGATE(REV) VGATE VGATE 1.0V 0.0V Figure 6. Gate Off Timing for VSD(REV) Transition VOFF 5.0V ûVOFF VOFF(IH) VOFF(IL) 0.0V tGATE(OFF) VGATE VGATE 1.0V 0.0V Figure 7. Gate Off Timing for VOFF Transition 6 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LM5051 LM5051 www.ti.com SNVS702D – OCTOBER 2011 – REVISED MARCH 2013 Typical Performance Characteristics Unless otherwise stated: All conditions and measurements are referenced to device pin 7 (INP/VSS), VLINE = 48V, VOFF = 0.0V, VINN = -150 mV, CVCC = 0.1 µF, CGATE = 47 nF, and TJ = 25°C Gate Charge Time, CGATE = 47 nF 14 GATE Discharge Time, tGATE(REV), CGATE = 47 nF 14 INN INP/VSS GATE 12 10 VOLTS (V) VOLTS (V) 10 8 6 4 2 6 4 0 0 -2 -2 0 1 2 TIME (ms) 3 4 -50 0 50 100 150 TIME (ns) 200 Figure 8. Figure 9. IGATE Discharge Current vs Temperature, VGATE = 5.5V Gate Discharge Time vs Temperature 5.0 200 4.5 180 GATE DISCHARGE TIME (ns) GATE DISCHARGE CURRENT (A) 8 2 -1 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 250 Cgate = 47 nF Cgate = 10 nF 160 140 120 100 80 60 40 20 0 -50 200 -25 0 25 50 75 TEMPERATURE (°C) 100 125 -50 -25 0 25 50 75 TEMPERATURE (°C) 100 125 Figure 10. Figure 11. Gate Discharge Time vs CGATE IGATE Charge Current vs Temperature, VGATE = 5.5V 1.0 GATE CHARGE CURRENT (mA) +125°C +25°C -40°C 180 GATE CHARGE TIME (ns) INN INP/VSS GATE 12 160 140 120 100 80 60 40 20 0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 0 10 20 30 40 GATE CAPACITANCE, CGATE(nF) 50 Figure 12. -50 -25 0 25 50 75 TEMPERATURE (°C) 100 125 Figure 13. Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LM5051 7 LM5051 SNVS702D – OCTOBER 2011 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) Unless otherwise stated: All conditions and measurements are referenced to device pin 7 (INP/VSS), VLINE = 48V, VOFF = 0.0V, VINN = -150 mV, CVCC = 0.1 µF, CGATE = 47 nF, and TJ = 25°C Gate Charge Time vs Temperature, VGATE= 0.0V to 5.5V 0 Cgate = 47 nF Cgate = 10 nF VSD(TST)THRESHOLD (mV) GATE CHARGE TIME (ms) 0.6 VSD(TST) Thresholds vs Temperature 0.5 0.4 0.3 0.2 0.1 0.0 -25 0 25 50 75 TEMPERATURE (°C) 100 125 -150 -200 -250 -300 -350 -50 -25 0 25 50 75 TEMPERATURE (°C) 100 125 Figure 14. Figure 15. OFF Thresholds vs Temperature VZ vs Temperature, VINN= –100 mV 15.0 Voff Falling Voff Rising 14.5 Ivcc = 10 mA Ivcc = 2mA 14.0 1.55 13.5 1.50 VZ(V) VOFFTHRESHOLDS (V) 1.60 1.45 13.0 12.5 12.0 1.40 11.5 1.35 11.0 1.30 10.5 1.25 -50 10.0 -25 0 25 50 75 TEMPERATURE (°C) 100 125 -50 -25 0 25 50 75 TEMPERATURE (°C) Figure 16. Figure 17. VZ vs VLINE, VINN= –100 mV ILINE vs VLINE 14 2.0 13 1.8 +125°C +25°C -40°C 12 100 125 -40°C +25°C +125°C 1.6 1.4 ILINE(mA) 11 VZ(V) -100 -400 -50 10 9 8 1.2 1.0 0.8 7 0.6 6 0.4 5 0.2 4 0.0 20 30 40 50 60 70 VLINE(V) 80 90 100 Figure 18. 8 Vsd(tst) Rising Threshold Vsd(tst) Falling Threshold -50 20 30 40 50 60 70 80 90 100 VLINE(V) Figure 19. Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LM5051 LM5051 www.ti.com SNVS702D – OCTOBER 2011 – REVISED MARCH 2013 Typical Performance Characteristics (continued) Unless otherwise stated: All conditions and measurements are referenced to device pin 7 (INP/VSS), VLINE = 48V, VOFF = 0.0V, VINN = -150 mV, CVCC = 0.1 µF, CGATE = 47 nF, and TJ = 25°C IGATE Charge Current vs VLINE , VGATE = 0.0V 1.4 VGATE vs VLINE 15 -40°C +25°C +125°C 1.2 -40°C +25°C +125°C 14 13 12 VGATE(V) IGATE(mA) 1.0 0.8 0.6 11 10 9 8 0.4 7 0.2 6 0.0 5 0.5 30 40 50 60 70 VLINE(V) 80 90 100 NFGDVOL(V) 30 40 90 100 nFGDVOL vs Temperature VSD(REV) Thresholds vs Temperature 40 1 mA 0.2 0.1 0.0 Vsd(rev) + ûVsd(rev) Vsd(rev) 20 0 -20 -40 -60 -80 -100 -25 0 25 50 75 TEMPERATURE (°C) 100 125 -50 -25 0 25 50 75 TEMPERATURE (°C) Figure 22. 100 125 Figure 23. IINN vs VINN IINN(mA) 80 Figure 21. 0.3 0.4 50 60 70 VLINE(V) Figure 20. 0.4 -50 20 VSD(REV) THRESHOLDS(mV) 20 VOFF VGATE vs , VINN = -100mV 15 +25°C +125°C 0.2 13 0.0 11 VGATE 9 -0.2 7 -0.4 VOFF 5 -0.6 3 -0.8 1 -1.0 -1.0 -1 -0.8 -0.6 -0.4 VINN(V) -0.2 0.0 Figure 24. -2 -1 0 1 TIME ( s) 2 3 Figure 25. Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LM5051 9 LM5051 SNVS702D – OCTOBER 2011 – REVISED MARCH 2013 www.ti.com BLOCK DIAGRAM LOAD (+) LM5051 VCC 50 k: 1 2 VZ 13V LINE 0.1 µF Bias Circuitry 4 3 nFGD OFF - 5 µA + 1.5V Forward Comparator - + 260 mV INP VSS 45 mV + Reverse Comparator 6 INN 8 GATE D 5 G INP/VSS S LOAD (-) -48V 10 7 INP/VSS Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LM5051 LM5051 www.ti.com SNVS702D – OCTOBER 2011 – REVISED MARCH 2013 APPLICATION INFORMATION FUNCTIONAL DESCRIPTION Systems that require high availability often use multiple, parallel-connected redundant power supplies to improve reliability. Schottky OR-ing diodes are typically used to connect these redundant power supplies to a common point at the load. The disadvantage of using OR-ing diodes is the forward voltage drop, which reduces the available voltage, and the associated power losses as load currents increase. Using an N-channel MOSFET to replace the OR-ing diode requires a small increase in the level of complexity, but reduces, or eliminates, the need for diode heat sinks or large thermal copper area in circuit board layouts for high power applications. PS1 RLOAD PS2 Figure 26. Traditional OR-ing with Diodes The LM5051 is a negative voltage (i.e. low-side) OR-ing controller that will drive an external N-channel MOSFET to replace an OR-ing diode. The voltage across the MOSFET source and drain pins is monitored by the LM5051 at the IN and OUT pins, while the GATE pin drives the MOSFET to control its operation based on the monitored source-drain voltage. The resulting behavior is that of an ideal rectifier with source and drain pins of the MOSFET acting as the anode and cathode pins of a diode respectively. LINE VCC LM5051 PS1 INN GATE INP/VSS RLOAD LINE VCC LM5051 PS2 INN GATE INP/VSS Figure 27. OR-ing with MOSFETs INP/VSS PINS The INP input is internally connected to the both device pin 5 and 7. Typical applications will use device pin 7 only, with a single common connection to the source connection of the N-Channel MOSFET array. If pins 5 and 7 are both used, it is recommended that the two pins be externally connected together at the package, with a single common connection routed to the source connection of the N-Channel MOSFET array. Current should not be allowed flow through the internal connection between pin 5 and pin 7. INN and GATE PINS When power is initially applied, the load current will flow from source to drain through the body diode of the MOSFET. The resulting voltage across the body diode will be detected across the LM5051 INN and INP/VSS pins which then begins charging the MOSFET gate through a 0.66 mA (typical) current source. Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LM5051 11 LM5051 SNVS702D – OCTOBER 2011 – REVISED MARCH 2013 www.ti.com The LM5051 is designed to regulate the MOSFET gate to source voltage if the voltage across the MOSFET source and drain pins falls below the VSD(REG) voltage of 20 mV (typical). If the MOSFET current decreases to the point that the voltage across the MOSFET falls below the VSD(REG) voltage regulation point of 12 mV (typical), the GATE pin voltage will be decreased until the voltage across the MOSFET is regulated at 12 mV (typical). If the drain to source voltage is greater thanVSD(REG) voltage the gate voltage will increase. 160 16 Q1 = IRF7495PDF 140 VGATE 14 12 VSD 100 10 80 8 60 6 40 4 VGATE(V) VSD(mV) 120 2 20 VSD(REG) 0 0 0 1 2 3 ISD(A) 4 5 Figure 28. VSD and VGATE vs ILOAD with IRF7495PDF When the power supply voltages are within a few milli-volts of each other, this regulation method ensures that the load current transitions between them without any abrupt on and off oscillations. The current flowing through the MOSFET in each OR-ing circuit depends on the RDS(ON) of the MOSFETs, how close the power supply voltages are set, and the load regulation of the supplies. If the MOSFET current reverses, possibly due to failure of the input supply, such that the voltage across the LM5051 INN pin is 5 mV (typical) more positive than INP/VSS pin (VSD(REV) + ΔVSD(REV)) the LM5051 will quickly discharge the MOSFET gate through a strong GATE pin to INP/VSS pin discharge path. A reverse current though the MOSFET is required to turn the gate drive off. If a single operating supply is removed from the ORing array, the gate drive will not be discharged since there is no reverse current through the MOSFET to trip the reverse comparator. If the input supply fails abruptly, as would occur if the supply was shorted directly to ground, a reverse current will temporarily flow through the MOSFET until the gate can be fully discharged. This reverse current is sourced from the load capacitance and from the parallel connected supplies. The LM5051 responds to a voltage reversal condition typically within 34 ns. The actual time required to turn off the MOSFET will depend on the charge held by gate capacitance of the MOSFET being used. A MOSFET with 47 nF of effective gate capacitance can be turned off in typically 90 ns. This fast turn-off time minimizes voltage disturbances at the output, as well as the current transients from the redundant supplies. OFF PIN The OFF pin is used to disable the active OR-ing control circuitry, and to discharge the MOSFET Gate. The OFF pin has an internal pull-down (4.6 μA typical) which will, by default, keep the active OR-ing control circuitry enabled. If the OFF pin function is not needed, this pin can be left open or connected to the INP/VSS pin. Pulling the OFF pin above the VOFF(IH) threshold of 1.50V (typical) will disable the active OR-ing control circuitry and discharge the MOSFET Gate. The VOFF threshold has a typical hysteresis of 20mV. It is recommended that the OFF pin be pulled cleanly, and promptly, through the VOFF(IH) threshold region to prevent any aberrant behavior. The OFF pin must not be pulled higher than 5.5V above the INP/VSS pin. nFGD PIN The nFGD pin is an open Drain output pin and is controlled by status of the Forward comparator. When the voltage on INN pin is more negative than the VSD(TST) threshold voltage (285 mV typical) the nFGD pin will conduct current to the INP/VSS pin. During normal Active OR-ing, when the MOSFET is ON, the INN pin voltage should be less than approximately -100mV and the nFGD pin will be logic high. When the MOSFET is OFF and current is flowing through the body diode of the MOSFET, the INN pin voltage will be approximately -600 mV and the nFGD pin will be logic low. 12 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LM5051 LM5051 www.ti.com SNVS702D – OCTOBER 2011 – REVISED MARCH 2013 Several factors can prevent the nFGD pin from indicating that the external MOSFET is operating normally. If the LM5051 is used to connect parallel, redundant power supplies, one of the connected supplies may hold the INP/VSS pin voltage close enough to the LM5051 INN pin voltage that the VSD(TST) threshold is not exceeded. Additionally, operating with a high output capacitance value and low output load current may require a significant amount of time before the output load capacitance is discharged to the point where the VSD(TST) threshold is crossed and the nFGD pin switches. The status of the nFGD pin does not depend on the status of the OFF pin. The status of the nFGD pin depends only on the voltage at the INN pin relative to the INP/VSS pin being above, or below, the VSD(TST) threshold voltage. The nFGD output pin requires pull-up to an external voltage source, and must not be pulled higher than 5.5V above the INP/VSS pin. It is recommended that the nFGD pin is not required to sink more than 2mA. VCC PIN The VCC pin is connected to the cathode of the internal shunt (zener) voltage regulator. The anode of the shunt regulator is connected to the INP/VSS pin. The VCC pin provides bias for internal circuitry, as well as gate drive to the external MOSFET. The VCC pin should always be bypassed with a 0.1 μF ceramic capacitor to the INP/VSS pin. Typically, the VCC pin is biased from the LINE pin, through the internal 50 kΩ series resistor, when the available VLINE voltage is not less than the 36V minimum operating voltage. If the available LINE voltage is less than less than the 36V minimum operating voltage the VCC pin can be biased through the use of an external resistor to an appropriate bias supply that is referenced to the INP/VSS pin. A minimum VCC pin bias current of 1 mA is recommended, with a recommended 10 mA maximum. A design example for calculating the external resistor where the VCC pin will be biased from an 18V to 36V supply (relative to the INP/VSS pin): RBIAS = (VBIAS(MIN) - VZ) / IBIAS(MIN) RBIAS = (18V - 13V) / 1 mA RBIAS = 5.0 kΩ (1) (2) (3) Next, using the calculated RBIAS resistor value, verify that the VCC pin current will be no more than 10mA at the maximum VBIAS voltage: ICC = (VBIAS(MAX) - 13V) / RBIAS ICC = (36V - 13V) / 5.0 kΩ ICC = 4.6 mA (4) (5) (6) Since the calculated 4.6 mA is less than the 10 mA maximum, the 5 kΩ value for RBIAS is acceptable. RBIAS LINE VCC LM5051 INN GATE INP/VSS 0.1 F Figure 29. Using an External Resistor to Bias the VCC Pin Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LM5051 13 LM5051 SNVS702D – OCTOBER 2011 – REVISED MARCH 2013 www.ti.com Alternately, an external bias supply can be connected directly to the VCC pin, as long as the applied voltage is below the minimum VZ breakdown voltage (11.9V) and above the minimum VCC operating voltage (4.50V). In this case, it is important to pay close attention to the VGS rating of the external MOSFET as the gate drive voltage will be affected by the lower voltage on the VCC pin. RBIAS LINE VCC LM5051 INN GATE INP/VSS Figure 30. Using an External Zener to Bias the VCC Pin In the case where the OFF pin is high (i.e. OR-ing is disabled, and the Gate is discharged) and the voltage at the INN pin is more negative than the VSD(REV) threshold voltage the internal current increases, and the voltage on the VCC pin may drop.. Since the LM5051 is in the OFF state, this voltage drop does not affect any operation. However, when the OFF pin is taken low to resume normal operation, the initial Gate charge time may be extended slightly if the capacitor on the VCC pin has not had adequate time to fully recharge through either the external RBIAS resistor, or through the internal 50 kΩ resistor. 15 VCCAND VGATE(V) 13 VVCC 11 9 VOFF 7 5 3 VGATE 1 -1 -2 0 2 4 6 8 TIME (ms) 10 12 14 Figure 31. VCC and VGATE vs VOFF, VINN = –100 mV HIGH SIDE OR-ing Because the INP and VSS functions are internally connected, the LM5051 cannot be configured as a High-Side (i.e. Positive) OR-ing controller. Please refer to the LM5050-1 and LM5050-2 High-Side OR-ing controllers. MOSFET FAILURE Typically, the INN pin maximum negative voltage will be defined by the body diode of the external MOSFET. In the even that the external MOSFET has a catastrophic failure that results in an open body diode, the voltage between the INP/VSS pin and the INN pin may cause current through the LM5051 substrate diode at the INN pin. The voltage at the INN pin must be limited to a safe level ( -1V) to prevent damage to the LM5051. The voltage on the INN pin can be limited with the use of a Schottky diode and a current limiting resistor. Note that the power dissipation of the current limiting resistor should allow for any anticipated worst case condition. See Figure 32. 14 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LM5051 LM5051 www.ti.com SNVS702D – OCTOBER 2011 – REVISED MARCH 2013 LINE VCC LM5051 INN GATE INP/VSS 1k Figure 32. Protecting the INN Pin SHORT CIRCUIT FAILURE OF AN INPUT SUPPLY An abrupt zero ohm short circuit across the input supply will cause the highest possible reverse current to flow while the internal LM5051 control circuitry discharges the gate of the MOSFET. During this time, the reverse current is limited only by the RDS(ON) of the MOSFET, along with parasitic wiring resistances and inductances. Worst case instantaneous reverse current would be limited to: ID(REV) = (VOUT - VIN) / RDS(ON) (7) The internal Reverse Comparator will react, and will start the process of discharging the Gate, when the reverse current reaches: ID(REV) = VSD(REV) / RDS(ON) (8) When the MOSFET is finally switched off, the energy stored in the parasitic wiring inductances will be transferred to the rest of the circuit. LINE LM5051 VCC Shorted Input Parasitic Inductance INN GATE INP/VSS COUT CLOAD Parasitic Inductance Figure 33. Input Supply Fault Transients MOSFET SELECTION The important MOSFET electrical parameters are the maximum continuous Drain current ID, the maximum Source current (i.e. body diode), the maximum drain-to-source voltage VDS(MAX), the gate-to-source threshold voltage VGS(TH), the drain-to-source reverse breakdown voltage V(BR)DSS, and the drain-to-source On resistance RDS(ON). The maximum continuous drain current, ID, rating must be exceed the maximum continuous load current. The rating for the maximum current through the body diode, IS, is typically rated the same as, or slightly higher than the drain current, but body diode current only flows while the MOSFET gate is being charged to VGS(TH): Gate Charge Time = Qg / IGATE(ON) (9) The maximum drain-to-source voltage, VDS(MAX), must be high enough to withstand the highest differential voltage seen in the application. This would include any anticipated fault conditions. The drain-to-source reverse breakdown voltage, V(BR)DSS, may provide some transient protection to the OUT pin in low voltage applications by allowing conduction back to the IN pin during positive transients at the OUT pin. The gate-to-source threshold voltage, VGS(TH), should be compatible with the LM5051 gate drive capabilities. Logic level MOSFETs are recommended, but sub-Logic level MOSFETs can also be used. Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LM5051 15 LM5051 SNVS702D – OCTOBER 2011 – REVISED MARCH 2013 www.ti.com The dominate MOSFET loss for the LM5051 active OR-ing controller is conduction loss due to source-to-drain current to the output load, and the RDS(ON) of the MOSFET. This conduction loss could be reduced by using a MOSFET with the lowest possible RDS(ON). However, contrary to popular belief, arbitrarily selecting a MOSFET based solely on having low RDS(ON) may not always give desirable results for several reasons: 1) Reverse transition detection. Higher RDS(ON) will provide increased voltage information to the LM5051 Reverse Comparator at a lower reverse current level. This will give an earlier MOSFET turn-off condition should the input voltage become shorted to ground. This will minimize any disturbance of the redundant bus. 2) Reverse current leakage. In cases where multiple input supplies are closely matched it may be possible for some small current to flow continuously through the MOSFET drain to source (i.e. reverse) without activating the LM5051 Reverse Comparator. Higher RDS(ON) will reduce this reverse current level. 3) Cost. Generally, as the RDS(ON) rating goes lower, the cost of the MOSFET goes higher. Selecting a MOSFET with an RDS(ON) that is too large will result in excessive power dissipation. As a guideline, it is suggest that RDS(ON) be selected to provide at least 20 mV, and no more than 100 mV, at the nominal load current. (20 mV / ID) ≤ RDS(ON) ≤ (100mV / ID) (10) The thermal resistance of the MOSFET package should also be considered against the anticipated dissipation in the MOSFET in order to ensure that the junction temperature (TJ) is reasonably well controlled, since the RDS(ON) of the MOSFET increases as the junction temperature increases. PDISS = ID2 x (RDS(ON)) (11) Operating with a maximum ambient temperature (TA(MAX)) of 35°C, a load current of 10A, and an RDS(ON) of 10 mΩ, and desiring to keep the junction temperature under 100°C, the maximum junction-to-ambient thermal resistance rating (θJA) would need to be: θJA≤ (TJ(MAX) - TA(MAX))/(ID2 x RDS(ON)) θJA≤ (100°C - 35°C)/(10A x 10A x 0.01Ω) θJA≤ 65°C/W 16 (12) (13) (14) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LM5051 LM5051 www.ti.com SNVS702D – OCTOBER 2011 – REVISED MARCH 2013 TYPICAL APPLICATIONS GND 0V GND LINE LM5051 INN GATE VCC INP/VSS CVCC 0.1 PF G -VIN -48V D -VOUT S Q1 IRF7495PDF Figure 34. Basic Application GND 0V GND LINE CIN 1 PF 100V X7R D1 SS16T3 1A/60V LM5051 INN R1 1 k: -VIN -48V D Q1 IRF7495PDF GATE G + VCC INP/VSS D3 SS16T3 COUT 22 PF 100V D2 SMB5945 68V/3W CVCC 0.1 PF 25V X7R -VOUT S Typical –48V Application with Input and Output Transient Protection and Open MOSFET Protection Figure 35. Typical –48V Application Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LM5051 17 LM5051 SNVS702D – OCTOBER 2011 – REVISED MARCH 2013 www.ti.com REVISION HISTORY Changes from Revision C (March 2013) to Revision D • 18 Page Changed layout of National Data Sheet to TI format .......................................................................................................... 17 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LM5051 PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) (4) LM5051MA/NOPB ACTIVE SOIC D 8 95 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 L5051 MA LM5051MAE/NOPB ACTIVE SOIC D 8 250 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 L5051 MA LM5051MAX/NOPB ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 L5051 MA (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. 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Addendum-Page 1 Samples PACKAGE MATERIALS INFORMATION www.ti.com 11-Oct-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant LM5051MAE/NOPB SOIC D 8 250 178.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 LM5051MAX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 11-Oct-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM5051MAE/NOPB SOIC D LM5051MAX/NOPB SOIC D 8 250 210.0 185.0 35.0 8 2500 367.0 367.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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